Digital Electronic Systems Unit 5

Integrated Circuit TechnologyThis unit describes the performance characteristics and parameters of various gates that are available commercially as integrated circuits (ICs). There are three digital integrated circuit (IC) technologies used to make the basic logic gates – CMOS, TTL and ECL. CMOS and TTL are the most common technologies.

CMOS (Complementary metal oxide semiconductor)

Most large scale IC’s and microprocessors are implemented using CMOS technology to construct the gates at chip level. This technology uses Field Effect Transistors. Advantages – low power dissipation, improving switching speed (due to ever reducing transistor size), fully restored logic levels, very high levels of integration and performance.

TTL (Transistor transistor logic)

This technology uses Bipolar Junction Transistors to construct the gates at chip level. Advantage – not as sensitive to electrostatic discharge as CMOS – therefore no handling precautions. Fast switching speed, but uses more power than CMOS.

ECL (Emitter-coupled logic)

This is also a bipolar technology. Advantage – much faster than TTL, but uses much more power than TTL also. This technology is not very commonly used.

Basic Operational Characteristics and parameters

When working with digital electronics, one should be familiar, not only with the logical operation of Integrated Circuits (I.C.), but also with such operational properties as voltage levels, noise immunity, propagation delays, fanout and loading. In this section the practical aspects of these properties are discussed briefly.

DC supply voltage

The nominal supply voltage of the dc supply for CMOS and TTL devices is +5 Volts (though 3.3V CMOS is also available). This supply must be connected if the logic functions are to work. It should be noted that this is usually omitted from the logic diagram for simplicity. Shown below is what the gate would look like with the power supply attached.

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Logic Level

So far we have talked about binary 1’s and 0’s or logic HIGH’s and logic LOW’s but we have never put a figure on it. Ideally the logic level HIGH would be represented by +5 volts and the logic level LOW represented by 0 Volts. These two levels hold true for both TTL and CMOS devices. However because of small fluctuations in the dc power supply and from surrounding noise, it is necessary to have a tolerance on these voltage levels so that they do not have to be so precise. The tolerance level also depends on whether the logic level is being used as an input or an output. Examples of logic tolerances are shown below.

It can be seen that the CMOS gate fully restores the logic levels to typically within 0.1V of the supply levels.

Noise Immunity

Noise is unwanted voltage that is induced in the electrical circuits and can present a threat to the proper operation of the circuit. Wires and other conductors within a system pick us stray high-frequency electromagnetic radiation from adjacent conductors or from any other external source. Note that power-line voltage fluctuation is a source of low frequency noise.

In order to avoid getting incorrect logic levels at the output of any circuit, the circuitry must have a certain noise immunity. This is the ability to tolerate a certain amount of noise. It relies on the fact that there is some small tolerance on the input of the waveform. Shown below is a sample of what can happen if the noise becomes too great, causing the input signal to go below or above the circuit’s noise immunity level.

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Propagation Delay

When a signal propagates through a circuit there is a delay caused by how long it takes to go from the input to the output. There are two propagation delays specific to logic gates:

tPHL : the time between a designated point on the input pulse and the corresponding point on the output pulse when the output is changing from HIGH to LOW.

tPLH : the time between a designated point on the input pulse and the corresponding point on the output pulse when the output is changing from LOW to HIGH.

The propagation delay limits the frequency that the circuit can work at. The greater the propagation delay then the lower the maximum frequency. Thus, a higher-speed circuit has a smaller propagation delay.

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Fan-out and Loading

The fan-out of a logic gate is the maximum number of inputs that can be connected to a gate’s output, while still maintaining the output voltage levels within the specified limits. Fan-out is specified in terms of unit loads. A unit load for a logic gate equals one input to a like circuit.

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Types of fixed-function logic gates

All of the basic logic operations (NOT, AND, OR, NAND, NOR, XOR) are available in some or all of the integrated circuit technologies. Logic gates are recognised by the use of the prefix 74 or 54 in front of the device number. The prefix 54 is generally for military use and 74 prefix for commercial use. The integrated circuit technologies are designated prefixes as follows:

5V CMOS Category Prefix Designation74HC High speed CMOS (74 indicates commercial grade)

74HCT High speed CMOS (T indicates TTL compatibility)74AC Advanced CMOS

74ACT Advanced CMOS (TTL compatible)74AHC Advanced High-speed CMOS

74AHCT Advanced High-speed CMOS (TTL compatible)3.3V CMOS Category Prefix Designation

74LV Low voltage CMOS74LVC Low voltage CMOS

74ALVC Advance Low-voltage CMOSBiCMOS Category Prefix Designation

74BCT BiCMOS (Combines both CMOS and TTL)74ABT Advance BiCMOS74LVT Low voltage BiCMOS74ALB Advanced low voltage BiCMOS

TTL Category Prefix Designation74 Standard TTL (no letter)

74S Schottky TTL74AS Advanced Schottky TTL74LS Low Power Schottky TTL

74ALS Advanced Low Power Schottky TTL74F Fast TTL

Prefix designation for the various integrated circuit technologies

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Common logic gate configurations and their standard identifier digits are as follows:

Gate Configuration Identifier DigitsQuad 2-input NAND 00Quad 2-input NOR 02

Hex inverter 04Quad 2-input AND 08

Triple 3-input NAND 10Triple 3-input AND 11Dual 4-input NAND 20Dual 2-input AND 21Triple 3-input NOR 27

Single 8-input NAND 30Quad 2-input OR 32

Quad 2-input XOR 86

Identifier Digits for standard gate configurations

Note that in the gate configuration descriptions, a single means 1 gate per IC, a dual means 2 gates per IC, a treble means 3 gates per IC, a quad means 4 gates per IC and a hex means 6 gates per IC.

Therefore, for example, a 74LV02 is a 3.3V CMOS quad 2-input NOR gate integrated circuit.

Example:

74LS00 Integrated Circuit (IC) is a TTL QUAD 2-input NAND IC. It has 14 pins:

74LS00 Quad 2-Input NAND IC

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Example:

Data Sheet for 74LS00 Chip [page 1]

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Data Sheet for 74LS00 Chip [page 2]

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Explanation of Data Sheet Parameters

VC C The dc voltage that supplies power to the device. Below the specified minimum, reliable operation can not be guaranteed and above the specified maximum, damage may occur to the device.

IO H The output current that the gate provides (sources) to a load when the output is at the HIGH level. By convention, the current out of a terminal is assigned a negative value.

IO L The output current that the gate sinks when the output is at the LOW level. By convention, the current into a terminal is assigned a positive value.

VI H The value of the input voltage that can be accepted as a HIGH level by the gate. This parameter and the next three are relevant to Noise immunity.

VI L The value of the input voltage that can be accepted as a LOW level by the gate.

VO H The value of HIGH level output voltage that the gate produces.

VO L The value of LOW level output voltage that the gate produces.

II H The value of input current for a HIGH level input voltage.

II L The value of input current for a LOW level input voltage.

IO S The output current when the gate is shorted to ground and with input conditions that would establish a HIGH level on the output.

IC C H The total current from the VC C supply when all gate outputs are at the HIGH level.

IC C L The total current from the VC C supply when all gate outputs are at the LOW level.

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