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UNITED STATES PATENT AND TRADEMARK OFFICE

______________

BEFORE THE PATENT TRIAL AND APPEAL BOARD

______________

CRESTRON ELECTRONICS, INC.

Petitioner

v.

VESPER TECHNOLOGY RESEARCH, LLC

Patent Owner

U. S. PATENT NO. 6,611,247

Case No. IPR2017-00497

PETITION FOR INTER PARTES REVIEW OF

U. S. PATENT NO. 6,611,247

UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. §§ 42.1-42.80 & 42.100-42.123

Petition for Inter Partes Review of

U.S.US Patent No. 6,611,247

Page i

TABLE OF CONTENTS

I. EXHIBIT LIST UNDER 37 C.F.R. § 42. 63(e) ......................................... iii

II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(a)(1) ....................... 1

A. Real Party in Interest under 37 C.F.R. § 42.8(b)(1) ............................ 1

B. Related Matters under 37 C.F.R. § 42.8(b)(2) ..................................... 1

C. Lead and Backup Counsel and Service Information (37

C.F.R. § 42.8(b)(3)-(4)). ..................................................................... 3

D. Service Information Under 37 C.F.R. § 42.8(b)(4) ............................. 3

Mailing address ....................................................................................... 3

Electronic Mail address .......................................................................... 3

E. Payment of Fees Under 37 C.F.R. § 42.103 and 37

C.F.R. § 42.15(a) ................................................................................ 3

III. REQUIREMENTS for IPR UNDER 37 C.F.R. § 42.104 ............................ 4

A. Grounds for Standing Under 37 C.F.R. § 42.104(a) ............................ 4

B. Citation of Prior Art ............................................................................. 4

Ex. 1003 – U.S. Patent No. 6,339,622, to Kuy Tae Kim (”Kim”) ......... 4

Ex. 1004 - U. S. Patent No. 6,320,590 to Yong-Suk Go (“Go”) ........... 4

Ex. 1005 - U. S. Patent No. 5,761,246 to Cao et al. (“Cao”) ................. 5

Ex. 1009 - U. S. Patent No. 5,684,833 to Hirofumi Watanabe

("Watanabe") .................................................................................... 5

C. Claims and Statutory Grounds under 37 C.F.R.

§§42.104(b)(1) & (b)(2) ...................................................................... 5

IV. The ‘247 Patent ............................................................................................. 6

A. Background .......................................................................................... 6

B. Summary of the ‘247 Patent ................................................................ 7

C. The Admitted Prior Art ........................................................................ 8

Active matrix LCD’s were known ......................................................... 9

Data transfer systems for LCD’s were known ..................................... 11

Digital timing controllers for LCD’s were known ............................... 11

Digital input data drivers for a LCD’s were known ............................. 11

D. Level of Ordinary Skill in the Art ...................................................... 12

E. Claim Construction under 37 C.F.R. § 42. 104(b)(3) ........................ 12

The term “Multi-level” ......................................................................... 13

V. the claims are unpatentable Pursuant to 37 C.F.R. § 42. 104(b)(4) ............ 15

A. GROUND 1 - Claims 1-3, 5 are anticipated under 35

U.S.C. § 102(e) by Kim. ................................................................... 15

Claim 1.................................................................................................. 15



Page ii

Claim 2.................................................................................................. 23

Independent Claim 3 ............................................................................. 23

Claim 5.................................................................................................. 27

B. GROUND 2 - Claims 1-7 are Obvious under 35 U.S.C.

§ 103 (a) over Kim in combination with APA. ................................ 28

Claim 1.................................................................................................. 28

Claim 2.................................................................................................. 35

Claim 3.................................................................................................. 35

Claim 4.................................................................................................. 39

Claim 5.................................................................................................. 41

Claim 6.................................................................................................. 41

Claim 7.................................................................................................. 47

C. GROUND 3 - Claim 8-10 are Obvious under 35 U.S.C.

§ 103 (a) over Kim and APA in view of Watanabe. ......................... 49

Claim 8.................................................................................................. 49

Claim 9.................................................................................................. 49

Claim 10................................................................................................ 49

D. GROUND 4 - Claims 1-7 are Obvious under 35 U.S.C.

§ 103 (a) over Go in view of the APA of the ‘247

Patent. ................................................................................................ 53

Claim 1.................................................................................................. 53

Claim 2.................................................................................................. 59

Claim 3.................................................................................................. 60

Claim 4.................................................................................................. 62

Claim 5.................................................................................................. 62

Claim 6.................................................................................................. 64

Claim 7.................................................................................................. 70

E. GROUND 5 - Claim 8-10 are Obvious under 35 U.S.C.

§ 103 (a) over Go and APA in view of Cao. .................................... 71

Claim 8: ................................................................................................ 71

Claim 9: ................................................................................................ 71

Claim 10: .............................................................................................. 71

F. Supporting Evidence § 42. 104(b)(5) ................................................ 73

VI. CONCLUSION ........................................................................................... 74

VII. CERTIFICATE OF SERVICE (37 C.F.R. §§ 42. 6(e) and 42.

105(a)) ......................................................................................................... 75

VIII. CERTIFICATE OF COMPLIANCE (37 C.F.R. §§ 42. 6(e) and 42.

105(a)) ......................................................................................................... 76



Page iii

I. EXHIBIT LIST UNDER 37 C.F.R. § 42. 63(E)

Exhibit Description

Ex. 1001 U. S. Patent No. US 6,611,247 (“the ‘247 Patent”)

Ex. 1002 Declaration of Dr. Peter M. Corcoran (“Corcoran”)

Ex. 1003 U. S. Patent No. 6,339,622 to Kuy Tae Kim (“Kim”)

Ex. 1004 U. S. Patent No. 6,320,590 to Yong-Suk Go (“Go”)

Ex. 1005 U. S. Patent No. 5,761,246 to Cao et al. (“Cao”)

Ex. 1006 U. S. Patent No. 5,844,538 to Shiraki et al. (“Shiraki ”)

Ex. 1007 U. S. Patent No. 4,606,046 to John J. Ludwick (“Ludwick”)

Ex. 1008 U. S. Patent No. 4,908,710 to Wakai et al. (“Wakai”)

Ex. 1009 U. S. Patent No. 5,684,833 to Hirofumi Watanabe (“Watanabe”)

Ex. 1010 Liquid Crystal Flat Panel Displays: Manufacturing Science &

Technology by William C. O’Mara, 1993. (“O’Mara1993”)

Ex. 1011 McGraw-Hill Dictionary of Scientific and Technical Terms (4th

Edition, 1989)

Ex. 1012 Prosecution History of U.S. Patent No. 6,611,247

Ex. 1013 Curriculum Vitae of Dr. Peter M. Corcoran



Page 1

II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(A)(1)

A. Real Party in Interest under 37 C.F.R. § 42.8(b)(1)

The real parties-in-interest are Vesper Technology Research, LLC. and

Crestron Electronics, Inc (“Crestron”).

B. Related Matters under 37 C.F.R. § 42.8(b)(2)

The ‘247 Patent is asserted in the following pending cases in the District of

Texas (“the Texas Actions”):

Docket No. Caption Filing Date

2:16-cv-01236 Vesper Technology Research, LLC v.

Atlona, Inc.

November 7,

2016


ATEN International Co., Ltd. et al

November 8,

2016


Samsung Electronics Co., Ltd. et al

November 8,

2016


Sharp Electronics Corp.

November 8,

2016


Pioneer Electronics (USA) Inc. et al

November 9,

2016



Page 2

Docket No. Caption Filing Date


AMX, LLC et al

November 10,

2016

2:16-cv-01259 Vesper Technology Research, LLC v. LG

Display Co., Ltd. et al

November 10,

2016


Crestron Electronics, Inc.

November 15,

2016


RGB Systems, Inc. d/b/a Extron

Electronics et al.

November 15,

2016


Kramer Electronics Ltd. et al

November 15,

2016


IDK America Inc. et al

November 16,

2016


Panasonic Corporation of North

America

November 16,

2016

There are no known related administrative proceedings.



Page 3

C. Lead and Backup Counsel and Service Information (37 C.F.R. §

42.8(b)(3)-(4)).

Petitioner designates Samir Termanini (No. 56,591) as lead counsel and

Philip Kirkpatrick (No. 46,015) as back-up counsel, all of Crestron Electronics,

Inc., 15 Volvo Drive, Rockleigh, NJ 07647; telephone: (201) 767-3400 Ext. 12516;

facsimile: (201) 768-7289.

D. Service Information Under 37 C.F.R. § 42.8(b)(4)

Mailing address

Please address all correspondence and service to counsel at: Crestron

Electronics, Inc., 15 Volvo Drive, Rockleigh, NJ 07647.

Electronic Mail address

Crestron consents to electronic service by email at: Patents@crestron. com.

E. Payment of Fees Under 37 C.F.R. § 42.103 and 37 C.F.R. §

42.15(a)

The undersigned authorizes the Office to charge $23,000 ($9,000 request fee

and $14,000 post-institution fee) to Deposit Account No 50-5234 for the fees set

forth in 37 C.F.R. §42. 15(a) for this Petition for Inter Partes Review. The

undersigned further authorizes payment for any additional fees that might be due in

connection with this Petition to be charged to the above-referenced Deposit

Account.

mailto:[email protected]



Page 4

III. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104

A. Grounds for Standing Under 37 C.F.R. § 42.104(a)

Petitioner certifies that the ‘247 Patent’s claims for which review is sought

are available for inter partes review and that Petitioner is not barred or estopped

from requesting an inter partes review challenging the ‘247 Patent on the grounds

identified in this petition.

B. Citation of Prior Art

Ex. 1003 – U.S. Patent No. 6,339,622, to Kuy Tae Kim (”Kim”)

Kim is a U.S. patent, filed on Sept. 4, 1998. Kim was filed prior to ‘the 247

Patent and has a different inventive entity than that of the ‘247 Patent. Therefore,

Kim is prior art to the ’247 Patent under at least 35 U.S.C. § 102(e). Kim was not

cited during the prosecution of the ’247 Patent.

Ex. 1004 - U. S. Patent No. 6,320,590 to Yong-Suk Go (“Go”)

Go is a U.S. patent, filed on Oct. 13, 1998. Go was filed prior to ‘the 247

Patent and has a different inventive entity then the ‘247 Patent. Therefore, Go is

prior art to the ’247 Patent under at least 35 U.S.C. § 102(e). Go was not cited

during the prosecution of the ’247 Patent.



Page 5

Ex. 1005 - U. S. Patent No. 5,761,246 to Cao et al. (“Cao”)

Cao is a U.S. patent that issued on Jun. 2, 1998, more than one year prior to

the ‘247 Patent. Therefore, Cao is prior art to the ’247 Patent under at least 35

U.S.C. § 102(b). Cao was not cited during the prosecution of the ’247 Patent.

Ex. 1009 - U. S. Patent No. 5,684,833 to Hirofumi Watanabe

("Watanabe")

Watanabe is a U.S. patent that issued on Nov. 4, 1997, more than one year

prior to the ‘247 Patent. Therefore, Watanabe is prior art to the ’247 Patent under

at least 35 U.S.C. § 102(b). Watanabe was not cited during the prosecution of the

’247 Patent.

C. Claims and Statutory Grounds under 37 C.F.R. §§42.104(b)(1) &

(b)(2)

The relief requested by Petitioner is that Claims 1-10 of the ‘247 Patent be

found unpatentable and cancelled from the ‘247 Patent on the following grounds:

Ground Claims Basis

1 1-3, 5

Anticipated under §102(e) by U. S. Patent No. 6,339,622

to Kuy Tae Kim (“Kim”)

2 1-7

Obvious under §103(a) over Kim taken in view of the

Admitted Prior Art (“APA”) of the ‘247 Patent



Page 6

3 8-10

Obvious under §103(a) over Kim taken in view of APA

and U. S. Patent No. 5,684,833 to Hirofumi Watanabe

(“Watanabe”)

4 1-7

Obvious under §103(a) over U. S. Patent No. 6,320,590

to Yong-Suk Go (“Go”) in view of APA

5 8-10

Obvious under §103(a) over Go and APA in view of U.

S. Patent No. 5,761,246 to Cao et al. (“Cao”)

The unpatentability grounds set forth in this Petition are further supported by

the Expert Declaration of Dr. Peter M. Corcoran (Ex. 1002), which includes his

curriculum vitae (Ex. 1013).

IV. THE ‘247 PATENT

A. Background

The ‘247 Patent (Ex. 1001) is entitled “DATA TRANSFER SYSTEM AND

METHOD FOR MULTI-LEVEL SIGNAL OF MATRIX DISPLAY.” The patent

issued on August 26, 2003 from U. S. Patent Application No. 09/345,962 (“the

‘247 Application”), filed on July 1, 1999. The ‘247 Patent does not claim priority

to any earlier domestic or foreign patent application. Thus, its earliest effective

priority date is July 1, 1999. The claims addressed in this petition, Claims 1-10, are



Page 7

directed to driving a matrix liquid crystal display (“LCD”) using a multi-level

signal. Claims 1, 3 and 6 are independent claims.

B. Summary of the ‘247 Patent

The ‘247 Patent (Ex. 1001) describes the invention as a display data transfer

system and method for a matrix display in which multi-level signaling is used for

transferring display data needed for image display on a display panel. Ex. 1001,

1:8-11).

According to the ’247 Patent, the display data required for displaying images

on a matrix LCD is generated by a digital timing controller and sent to a digital

input data driver via a digital bus. Id., 1:39-43). However, as space resolution and

luminescence resolution of an image are increased, the number of the data lines is

remarkably increased. Id., 1:52-54). The ’247 Patent states that by increasing the

transfer speed of interface signal or operating speed of the system, the transfer

frequency of the digital bus can be improved. Id. 1:66-2:1). However, increasing

the transfer frequency creates large amounts of electromagnetic interference

(“EMI”). (Id. 2:14-15).

The ’247 Patent purports to solve these (frequency/EMI) problem by

utilizing a multi-level signal to transfer display data over a multi-level bus where

each data line of the bus can be in one of multiple states. Id. at 5:48-51. An



Page 8

encoder is inserted at the end of the signal bus by the LCD controller and a decoder

provided at the other end of the signal bus by the source data driver. Id. at 5:51-54.

Fig. 5 of the ‘247 Patent (reproduced highlighted below) with the system

described above, constitutes the claimed invention of the ‘247 Patent, highlighted.

The gray portions of Fig. 5 below constitute the admitted prior art referenced in the

‘247 Patent, and is discussed in detail below.

The ‘247 Patent, Fig. 5 (annotations added in color)

C. The Admitted Prior Art

To better understand what is claimed in the ’247 Patent, a discussion of the

admitted prior art (“APA”) is helpful, as the inventors of the ’247 Patent admitted

prior art at length at 1:19-2:37 and by Figs. 1-4; See also the ‘247 Patent at 3:9-16.



Page 9

Active matrix LCD’s were known

The ‘247 Patent admits that at the time of its invention active matrix LCD’s

were known in the art. Ex. 1001 at 1:19-2:37 (Background of the Invention). The

‘247 Patent further admits that FIG. 1 is a block diagram showing a conventional

active matrix LCD. Ex. 1001 at 1:27-28, 3:9-10, and Fig. 1, reproduced below.

The ‘247 Patent, Fig. 1

According to the ‘247 Patent, it is suggested that an “LCD panel 100

comprises a plurality of data bus lines Xl, X2,. . ., Xm, [and] plurality of scan bus

lines Yl,Y2,. . ., Yn, and a plurality of pixels disposed between the data bus lines

and scan bus lines.” Ex. 1001, 1:28-31.

The ‘247 Patent further discloses that it was known to those skilled in the art

that “[a] scan driver 10 selects one of the TFTs in a LCD panel 100 and a digital

input data driver 20 provides a data driving signal.” Ex. 1001, 1:36-38.



Page 10

The ‘247 Patent, 3

As described in the ‘247 Patent, with detail shown at Fig. 3 above, “a display data

required for image display passes through a digital timing controller 40 through an

input interface 50, and is sent to the digital input data driver 20 via a digital bus

60.” Ex. 1001, 1:35-43; Corcoran Ex. 1002 at ¶¶ 56-61.

According to the ‘247 it is admitted that “…in a prior art digital input data

driver 20 shown in FIG. 4, data from FIG. 3 passes through an input data register

22, an internal processing logic 24 and a digital-to-analog converter (DAC) to

become an analog signal output, which is a data driving signal.” Ex. 1001 at 4:28-

32.

Rather than disclosing anything new with regard to analog signal output

from a data driver, the ’247 Patent adopts the well-known admitted prior art



Page 11

concept of a DAC within a digital input data driver. Ex. 1001 at 4:28-32. Corcoran

Ex. 1002 at ¶ 83.

Data transfer systems for LCD’s were known

The ‘247 Patent admits at the time of its invention data transfer systems for

a LCD’s were known in the art. Ex. 1001 at 1:19-2:37 (Background of the

Invention). The ‘247 Patent further admits that FIG. 2 is a schematic view of a

conventional data transfer system. Ex. 1001 at 3:11-12, and Fig. 2.

Digital timing controllers for LCD’s were known

The ‘247 Patent admits that at the time of its invention digital timing

controllers for LCD’s were known in the art. Ex. 1001 at 1:19-2:37 (Background of

the Invention), 4:15-20, and 4:28-32. The ‘247 Patent further admits that Fig. 3 is a

“prior art” schematic view of a conventional digital timing controller of a LCD.

Ex. 1001 at 4:15-20, 3:13-14, and Fig. 3.

Digital input data drivers for a LCD’s were known

The ‘247 Patent admits that at the time of its invention digital input data

drivers for a LCD’s were known in the art. Ex. 1001 at 1:19-2:37 (Background of

the Invention). The ‘247 Patent admits that Fig. 4 is a “prior art” schematic view of

a conventional digital input data driver of a LCD. Ex. 1001 at 3:15-16, 4:28-32,

and Fig. 4.



Page 12

D. Level of Ordinary Skill in the Art

A person of ordinary skill in the art at the time of the effective filing date for

the claims of the ’247 Patent would have a Bachelor’s degree in electrical

engineering or physics, or equivalent, and at least a year of relevant experience

relating to digital logic circuits. Corcoran Ex. 1002 at ¶ 28. (Absent a formal

degree, a person of ordinary skill in the art would have additional years of work

experience). Id.

E. Claim Construction under 37 C.F.R. § 42. 104(b)(3)

In an inter partes review, claim terms in an unexpired patent are interpreted

according to their broadest reasonable interpretation (“BRI”) in view of the

specification in which they appear. See 37 C.F.R. § 42. 100(b); See also Cuozzo

Speed Techs., LLC v. Lee, 136 No. 15-446, 579 U. S. Ct. 2131 (2016).

Throughout this Petition, as required by the rules governing it, Crestron

applies the BRI of claim terms appropriate for these proceedings. However, the

claim interpretations presented in this Petition do not necessarily reflect the claim

constructions that Crestron believes should be adopted by a district court under

Phillips v. AWH Corp., 415 F. 3d 1303 (Fed. Cir. 2005), under rules which are

different from those applicable in this proceeding.



Page 13

The term “Multi-level”

The ‘247 Patent does not offer an “explicit” definition of the term “Multi-

level” (i.e., no lexicographical definition is present). However, during prosecution,

Applicant expressly admitted that “multilevel digital signals and multilevel

transmission are well understood by those of ordinary skill in the art”1 (See e.g. Ex.

1012 at pg. 99 (6/25/2002 - Amendment), pg. 115 (6/25/2002 - After final

amendment), pg. 136 (3/12/2003 - Appeal Brief)), in order to overcome a series of

35 U.S.C. § 112 First paragraph rejections (See E.g. Ex. 1012 at pgs. 87 and 106).

1 “The PTO should [] consult the patent’s prosecution history in proceedings

in which the patent has been brought back to the agency for a second review.”

Microsoft Corp. v. Proxyconn, Inc., 789 F.3d 1292, 1298 (Fed. Cir. 2015) (citing

Tempo Lighting Inc. v. Tivoli LLC, 742 F.3d 973, 977 (Fed. Cir. 2014)).



Page 14

Petitioner proposes the same dictionary definition Applicant offered during

prosecution to overcome §112 rejections and get the ‘247 Patent allowed.2. See Ex.

1011 at pg. 6; Ex. 1012 at pg. 136 (3/12/2003 - Appeal Brief).

Accordingly, under the broadest reasonable interpretation in light of the

specification, “Multi-level” should be construed to mean “having more than two

possible meaningful levels.”

2 At the time of allowance, the examiner did not inform the record of any

reasoning for withdrawing the §112 first paragraph rejection. Ex. 1012 at pg. 184

(5/19/2003 Notice of allowance). It would be reasonable to infer that Applicant

finally convinced the examiner of how well known multi-level signaling was to the

ordinarily skilled artisan.



Page 15

V. THE CLAIMS ARE UNPATENTABLE PURSUANT TO 37 C.F.R. §

42. 104(B)(4)

A. GROUND 1 - Claims 1-3, 5 are anticipated under 35 U.S.C. §

102(e) by Kim.

Claim 1

1. A data transfer system for a multi-level signal for

providing a display data to a matrix display panel,

comprising:…

Kim teaches a data transfer system for a multi-level signal for providing a

display data as one of its objectives: “[a]n object of the present invention is to

provide a data transmission device for a liquid crystal display device which

improves a data transmission efficiency by converting a binary data to a ternary

data.” Ex. 1003 at 2:59-62 (emphasis added); See Corcoran Ex. 1002 at ¶¶ 39-44.

It appears the body of claim 1 describes a structurally complete invention

such that deletion of the preamble phrase “…for providing a display data to a

matrix display panel…” does not affect the structure of the claimed invention.



Page 16

However, if the Board determines that the above limitation in claim 1 is limiting3

Kim is further cited for teaching their LCD panel to be a matrix panel, “…the LCD

device includes an LCD panel 41, a plurality of source drivers 43, a plurality of

gate drivers 45, and an LCD controller 47. The source drivers 43 and the gate

drivers 45 are disposed around the LCD panel 41.” (Emphasis added) Ex. 1003 at

2:20-23. One of ordinarily skill in the art would necessarily know that Kim’s LCD

panel is a “matrix” panel because it is described with terminology specific only to

matrix LCD’s. See Corcoran Ex. 1002 at ¶¶ 61, 77.

3 A preamble is generally not limiting when the claim body describes a

structurally complete invention such that deleting the preamble phrase does not

affect the structure or steps of the claimed invention. “A preamble limits the

invention if it recites essential structure or steps or if it is ‘necessary to give life

meaning, and vitality’ to the claim.” Catalina Mktg. Int’l, Inc. v. Coolsavings.com,

Inc., 289 F.3d 801, 808 (Fed. Cir. 2002) (quoting Pitney Bowes, Inc. v. Hewlett-

Packard Co., 182 F.3d 1298, 1305 (Fed. Cir. 1999)).



Page 17

…a multi-level timing controller for receiving a digital data

input …

Kim teaches a multi-level timing controller as element 47. See also Corcoran

Ex. 1002 ¶¶63-65 and 113. Kim’s explains, “The LCD controller 47 controls the

source drivers 43 and the gate drivers 45.” (Emphasis added) Kim at 2:23-25;

.1002 ¶¶ 63-65 and 113. Kim’s multilevel timing controller receives a digital data

input and converts it into a multi-level signal display data output. See “Digital data

input” on Kim’s annotated Fig. 10; below. See also Corcoran Ex. 1002 at ¶¶ 110-

111.



Page 18

and converting it into a multi-level signal display data output;

Kim teaches converting into a multi-level signal display data output.

Corcoran Ex. 1002 ¶ 110–111; See also Ex. 1003, Fig. 12. Furthermore, Kim

teaches the data to be multilevel, describing the display data, “converting a binary

data to a ternary data, a ternary data generator for generating three logic levels

…” Ex. 1003 at 3:5-11 (emphasis added); See Corcoran Ex. 1002 at ¶¶ 41-44, 85,

and 110-111. Kim’s data is display data, “….8 bit data per each of R, G, B image

signals to the source drivers 43” (emphasis added) Ex. 1003 at 2:26-29. Kim

shows the several levels of the multilevel signal at Fig. 6 (annotated) below.



Page 19

…a multi-level signal bus having a plurality of data lines,

connected to said multi-level timing controller,…

Kim illustrates a multi-level signal bus having a plurality of data lines,

connected to said multi-level timing controller. See, e.g., Fig. 12, reproduced

below.



Page 20

…for transferring said multi-level signal display data from

said multi-level timing controller; and…

Kim teaches the claimed, “...transmission lines for a data transmission to

the source drivers 43 from the controller 47…” (Emphasis added). Ex. 1003 at

6:19-20; See Corcoran Ex. 1002 at ¶¶ 64, and 114.

…a multi-level input data driver connected to said multi-level

signal bus…

Kim illustrates the claimed multi-level input data driver connected to a

multi-level signal bus, see annotated figure below. As can be seen in Fig. 12

below, Kim further taught is a multi-level input data driver (or “source driver”) 43

connected to the multi-level signal bus, which connects it to the LCD controller 47.

Fig. 12 of Kim (Annotated)



Page 21

See also Corcoran Ex. 1002 at ¶ 77 (explaining that a “data driver” is also

known as a “source driver”) (citing Ex. 1006 at 3:39-41); See also, Applicant’s

admission that a “data driver” is also known as a “source driver”; See also Ex.

1012 (2002-01-14 Amendment at page 6, lines 1-6) and Corcoran Ex. 1002 ¶ 101.

…for receiving said multi-level signal display data input and

converting it into a data driving signal to be outputted to said

matrix display panel.

Kim further describes receiving said multi-level signal display data input as,

“…data transmission to the source drivers…” (Ex. 1003 at 6:19-20) and converting

it into a data driving signal: “[t]he encoder 57 converts the ternary data outputted

from the ternary data detector 55 back to the binary data.” Ex. 1003 4:22-34; See

also Corcoran Ex. 1002 ¶¶ 41-44, 85, and 109-112. See also Figs. 7 and 11 of Kim,

below.



Page 22



Page 23

Claim 2

2. The system according to claim 1, wherein said multi-

level timing controller comprises a multi-level encoder for

encoding said digital data input and …

Kim teaches the claimed multi-level encoder, “. . . decoder for converting a

binary data to a ternary data, a ternary data generator for generating three logic

levels …” See Ex. 1003 at 3:5-11 (emphasis added); See Corcoran Ex. 1002 at ¶¶

41-44, 85, and 110-111.

…said multi-level input data driver comprises a multi-level

decoder for decoding said multi-level signal display data.

Kim teaches the claimed multi-level decoder: “…a data detector for

converting the three logic levels from the ternary data generator to pairs of binary

data, and an encoder for restoring the pairs of binary data to binary data.” Ex.

1003 at 3:10-12 (emphasis added); See Corcoran Ex. 1002 at ¶¶ 43-44, 85, and

110-111.

Independent Claim 3

3. A data transfer method for a multi-level signal for

providing a display data to a matrix display panel, said

method comprising the steps of:

As discussed above, with respect to claim 1, Kim teaches, “An object of the

present invention is to provide a data transmission device for a liquid crystal



Page 24

display device which improves a data transmission efficiency by converting a

binary data to a ternary data.” Ex. 1003 at 2:59-62 (emphasis added); See also

discussion below.

(a) converting a first digital data signal into a multi-level

signal display data output by a multi-level timing controller;

Kim teaches converting digital data signal into a multi-level signal: “[t]he

decoder 51 converts three binary data to generate a ternary data to the ternary

data generator 53. The ternary data generator 53 generates ternary data H, L, and

C…” Ex. 1003 at 5:56-59; See Corcoran Ex. 1002 at ¶¶ 41-44, 85, and 110-111.

See also Fig 6.

Kim’s multilevel timing controller receives a digital data input and converts

it into a multi-level signal display data output. See Kim at Fig. 10, below.



Page 25

(b) transferring said multi-level signal display data by a multi-

level signal bus comprising a plurality of data lines; and

Kim teaches transferring said multi-level signal display data from said multi-

level timing controller: “transmission lines for a data transmission [i.e.

transferring] to the source drivers 43 from the controller 47.” (emphasis added)

Ex. 1003 at 6:19-20. Corcoran Ex.1002 ¶64. See also, Fig. 12 of Kim:



Page 26

(c) converting said multi-level signal display data input into a

second digital data signal by a multi-level input data driver.

Kim teaches converting said multi-level signal display data input into a

second digital data signal by a multi-level input data driver: “[t]he ternary data

detector 55 is to detect the ternary data and output the same to OUTt11, OUTt12,

OUTt21, and OUTt22. The encoder 57 converts the ternary data outputted from

the ternary data detector 55 back to the binary data.” (emphasis added) Kim at

4:20-25; See Corcoran Ex. 1002 at ¶¶ 43, 85, and 110.



Page 27

Claim 5

5. The method according to claim 3, wherein step (a)

comprises encoding said first digital data signal by a multi-

level encoder, and

The limitations of claim 3, from which this claim depends, are addressed in

the treatment of claim 3, above. Kim further teaches, encoding said first digital

data signal by a multi-level encoder: “[s]pecifically, the decoder 51 is for

outputting data tlL, tlC and tlH, and t2L, t2C and t2H from three input data A, B,

and C to form ternary data. The ternary data generator 53 generates ternary

data from the output signals from the decoder 51.” Ex. 1003 at 4:16-21

(emphasis added); Kim at 4:16-21. See Corcoran Ex. 1002 at ¶¶ 41-44, 85, and

110-111

…step (c) comprises decoding said multi-level signal display

data by a multi-level decoder.

Kim also teaches, decoding said multi-level signal display data by a multi-

level decoder: “[t]he encoder 57 converts the ternary data outputted from the

ternary data detector 55 back to the binary data.” 1003 at 4:23-24 (emphasis

added);) Kim at 4:23-24. See Corcoran Ex. 1002 at ¶¶ 43, 85, and 110. .



Page 28

B. GROUND 2 - Claims 1-7 are Obvious under 35 U.S.C. § 103 (a)

over Kim in combination with APA.

Claim 1

A data transfer system for a multi-level signal for providing a

display data to a matrix display panel, comprising:

Kim teaches a data transfer system for a multi-level signal for providing a

display data as one of its objectives: “[a]n object of the present invention is to



data.” Ex. 1003 at 2:59-62 (emphasis added)..

Kim also describes their LCD panel to be a matrix panel “…the LCD device

includes an LCD panel 41, a plurality of source drivers 43, a plurality of gate

drivers 45, and an LCD controller 47. The source drivers 43 and the gate drivers 45

are disposed around the LCD panel 41.” (emphasis added) Ex. 1003 at 2:20-23

(emphasis added); Corcoran Ex. 1002 at ¶¶ 77 and 101.


input …

Kim teaches a multi-level timing controller as element 47. See also Corcoran

Ex. 1002 ¶116. Kim’s explains, “The LCD controller 47 controls the source drivers

43 and the gate drivers 45.” Kim Ex. 1003 at 2:23-25; Ex. 1002 ¶ 63-65 and 113.

Kim’s multilevel timing controller receives a digital data input and converts it into



Page 29

a multi-level signal display data output. See Kim Ex. 1003 at Fig. 10 and Corcoran

Ex. 1002 at ¶¶ 77, 101, and 109-111,

See also, Kim Ex. 1003 at Fig. 12:



Page 30

and converting it into a multi-level signal display data output;

Kim’s data transmission is for data display, “…the LCD controller 47

transmits a control signal to the gate drivers 45 and respective 6 or 8 bit data per

each of R, G, B image signals to the source drivers 43” Ex. 1003 at 2:26-29

(emphasis added); See also, Ex. 1003 Fig. 12. Furthermore, Kim teaches the

multilevel display data, explaining, “converting a binary data to a ternary data, a

ternary data generator for generating three logic levels …” Ex. 1003 at 3:5-

11(emphasis added); Corcoran Ex. 1002 at ¶¶ 39-44. Kim shows the several levels

of the multilevel signal at Fig. 6 below.



Page 31

…a multi-level signal bus having a plurality of data lines,

connected to said multi-level timing controller,…

Kim illustrates, a multi-level signal bus having a plurality of data lines,

connected to said multi-level timing controller. See, e.g., Fig. 12, reproduced

below.



Page 32

…for transferring said multi-level signal display data from

said multi-level timing controller; and…

Kim teaches the claimed, “…transmission lines for a data transmission [i.e.

transferring] to the source drivers 43 from the controller 47” Ex. 1003 at 6:19-20

(emphasis added); See Corcoran Ex. 1002 at ¶¶ 64, and 114.


signal bus…

As can be seen in the figure below, Kim’s multi-level input data driver (or

“source driver”) is connected to a multi-level signal bus. See Corcoran Ex. 1002 at

¶77, explaining a “data driver” is also known as a “source driver.” See also

Applicant’s admission that a “data driver” is also known as a “source driver.” Ex.

1012 (2002-01-14 Amendment at page 6, lines 1-6). See also Corcoran Ex. 1002

¶101.



Page 33

…for receiving said multi-level signal display data input and

converting it into a data driving signal to be outputted to said

matrix display panel.

Kim further describes receiving said multi-level signal display data input as,

“ … data transmission to the source drivers…” (Ex. 1003 at 6:19-20) and

converting it into a data driving signal: “[t]he encoder 57 converts the ternary data

outputted from the ternary data detector 55 back to the binary data.” Kim Ex. 1003

at 4:22-34 (emphasis added); See also Corcoran Ex. 1002 at ¶¶ 41-44, 85, and

110; See also Fig. 7 and Fig. 11 of Kim, below.



Page 34



Page 35

Claim 2

The system according to claim 1, wherein said multi-level

timing controller comprises a multi-level encoder for

encoding said digital data input and …

Kim teaches the claimed multi-level encoder, “. . . decoder for converting a

binary data to a ternary data, a ternary data generator for generating three logic

levels …” Ex. 1003 at 3:5-11 (emphasis added); See Corcoran Ex. 1002 at ¶¶ 41-

44, 85, and 110.

…said multi-level input data driver comprises a multi-level


Kim teaches the claimed multi-level decoder: “…a data detector for

converting the three logic levels from the ternary data generator to pairs of binary

data, and an encoder for restoring the pairs of binary data to binary data.” Ex.

1003 at 3:10-12 (emphasis added); See Corcoran Ex. 1002 at ¶¶ 41-44, 85 and 110.

Claim 3




As discussed above, Kim states, “An object of the present invention is to




Page 36


data.” Ex. 1003 at 2:59-62 (emphasis added); See also discussion above.



Kim teaches converting digital data signal into a multi-level signal: “[t]he

decoder 51 converts three binary data to generate a ternary data to the ternary

data generator 53. The ternary data generator 53 generates ternary data H, L, and

C…” Ex. 1003 at 5:54-59; See Corcoran Ex. 1002 at ¶¶ 41-44, 85, and 110-111.See

also Fig 6.

Kim’s multilevel timing controller receives a digital data input and converts

it into a multi-level signal display data output. See Kim at Fig. 10, below.



Page 37



Kim teaches transferring said multi-level signal display data from said multi-

level timing controller: “transmission lines for a data transmission [i.e.

transferring] to the source drivers 43 from the controller 47.” Ex. 1003 at 6:19-20

(emphasis added); See Corcoran Ex. 1002 at ¶¶ 64, and 114. See also, Fig. 12 of

Kim:



Page 38



Kim teaches converting said multi-level signal display data input into a

second digital data signal by a multi-level input data driver: “[t]he ternary data

detector 55 is to detect the ternary data and output the same to OUTt11, OUTt12,

OUTt21 and OUTt22. The encoder 57 converts the ternary data outputted from

the ternary data detector 55 back to the binary data.” Kim at 4:20-25; See

Corcoran Ex. 1002 at ¶¶63-64, 85, and Fig. 11 of Kim.



Page 39

Claim 4

4. The method according to claim 3, further comprising

converting said second digital data signal into an analog

signal.

While Kim does not explicitly state converting said second digital data

signal into an analog signal, one of ordinary skill would have known that an analog

signal was typically applied to pixels via corresponding data lines. See Corcoran

Ex. 1002 at ¶¶ 61, 70-71.

According to the ‘247 it is admitted that in “…a prior art digital input data

driver 20 shown in FIG. 4, data from FIG. 3 passes through an input data register


become an analog signal output, which is a data driving signal.” Ex. 1001 at 4:28-

32.

Rather than disclosing anything new with regard to analog signal output

from a data driver, the ’247 Patent simply adopts the well-known admitted prior art

concept of converting a digital data signal into an analog signal with a DAC of a

digital input data driver. See Ex. 1001 at 4:28-32 and Corcoran Ex. 1002 at ¶ 61-

63. For example:



Page 40

(Annotations added in color). The ‘247 Patent admits as follows, “[o]n the other

hand, in a prior art digital input data driver 20 shown in FIG. 4, data from FIG.

3 passes through an input data register 22, an internal processing logic 24 and a

digital-to-analog converter (DAC) to become an analog signal output, which is a

data driving signal.” Ex. 1001 at 4:28-32.

Accordingly, the APA evidences that it was well known to those of ordinary

skill in the art that drivers like Kim’s convert said second digital data signals into

analog signals. Corcoran Ex. 1002 at ¶ 63. Therefore, it would have been obvious

to a person of ordinary skill in the art that Kim’s did exactly that, because it was

specifically admitted by the ’247 Patent.



Page 41

Claim 5



level encoder, and

The limitations of claim 3, from which this claim depends, are addressed in

the treatment of claim 3, above. Kim further teaches, encoding said first digital

data signal by a multi-level encoder: “[s]pecifically, the decoder 51 is for

outputting data tlL, tlC and tlH, and t2L, t2C and t2H from three input data A, B,

and C to form ternary data. The ternary data generator 53 generates ternary

data from the output signals from the decoder 51.” See Kim Ex. 1003 at 4:16-21.

…step (c) comprises decoding said multi-level signal display


Kim also teaches, decoding said multi-level signal display data by a multi-

level decoder: “[t]he encoder 57 converts the ternary data outputted from the

ternary data detector 55 back to the binary data.” Kim Ex. 1003 at 4:23-24

(emphasis added); See) Kim at 4:23-24. Corcoran Ex. 1002 at ¶¶ 63-64, 85, 110.¶¶

87, 112.

Claim 6

A liquid crystal display device, comprising:

As discussed above, Kim teaches a Liquid Crystal Display device, “the

LCD panel 41.” Ex. 1003 at 2:20-23; See also Corcoran 1002 at ¶ 63.



Page 42

a matrix liquid crystal display panel;

Kim also describes their LCD panel to be a matrix panel “…the LCD device

includes an LCD panel 41, a plurality of source drivers 43, a plurality of gate

drivers 45, and an LCD controller 47. The source drivers 43 and the gate drivers 45

are disposed around the LCD panel 41.”(emphasis added) Ex. 1003 at 2:20-23;

See. Corcoran Ex. 1002 at ¶ 63.¶¶ 77 and 101.

a scan driver for providing a scan voltage signal to said liquid

crystal display panel by a plurality of scan bus lines; and

The ‘247 Patent admits that a person having ordinary skill in the art would

have understood that “[a] scan driver 10 selects one of the TFTs in a LCD panel

100….” Ex. 1001, 1:35-43. The ‘247 Patent further admits, by way of APA, that it

was known that a prior art matrix “LCD panel 100 comprises a plurality of scan

bus lines Yl, Y2, . . ., Yn….” Ex. 1001, 1:28-31.

a display data transfer system for providing a data driving

signal to said liquid crystal display panel by a plurality of data

bus lines, said display data transfer system comprising:

According to APA of the ‘247 Patent, it is suggested that an “LCD panel 100

comprises a plurality of data bus lines Xl, X2,. . ., Xm, [and] a plurality of scan bus

lines Yl,Y2,. . ., Yn, and a plurality of pixels disposed between the data bus lines

and scan bus lines.” Ex. 1001, 1:28-31. The ‘247 Patent further discloses that it



Page 43

was known to those skilled in the art that “[a] scan driver 10 selects one of the

TFTs in a LCD panel 100 and a digital input data driver 20 provides a data driving

signal. A display data required for image display is generated by a digital timing

controller 40 through an input interface 50, and is sent to the digital input data

driver 20 via a digital bus 60.” Ex. 1001, 1:35-43.

a multi-level timing controller for receiving a digital data

input and converting it into a multi-level signal display data

output;

As discussed above, Kim teaches a multi-level timing controller as element

47. Kim’s explains, “The LCD controller 47 controls the source drivers 43 and the

gate drivers 45.” Kim Ex. 1003 at 2:23-25; See Corcoran Ex. 1002 ¶ 63-65 and¶

¶77, 113. Kim’s multilevel timing controller receives a digital data input and

converts it into a multi-level signal display data output. See Kim at Fig. 10.



Page 44

a multi-level signal bus having a plurality of data lines,

connected to said multi-level timing controller,

As discussed above, Kim teaches a multi-level signal bus having a plurality

of data lines, connected to said multi-level timing controller: See also Fig. 12 of

Kim:



Page 45

for transferring said multi-level signal display data from said

multi-level timing controller; and

As previously discussed, Kim teaches the plurality of data lines for

transferring said multi-level signal display data from said multi-level timing

controller, “transmission lines for a data transmission [i.e. transferring] to the

source drivers 43 from the controller 47” Ex. 1003 at 6:19-20 (emphasis added)..

See Corcoran Ex. 1002 at ¶¶ 64, and 114.



Page 46


signal bus,…

Kim teaches a multi-level input data driver (or “source driver”) connected to

said multi-level signal bus. Corcoran Ex. 1002 at ¶ 77. See Fig. 12 of Kim (excerpt,

annotated); see also Corcoran Ex. 1002 at ¶ 77.).

… for receiving said multi-level signal display data input and

converting it into said data driving signal.

Kim teaches the claimed receiving said multi-level signal display data input,

“… data transmission to the source drivers…” (Ex. 1003 at 6:19-20). See

Corcoran Ex. 1002 at ¶¶ 64, and 114. Kim further teaches converting it into a data

driving signal: “[t]he encoder 57 converts the ternary data outputted from the

ternary data detector 55 back to the binary data.” Ex. 1003 at 4:22-34; See also



Page 47

Corcoran Ex. 1002 at ¶¶41-44, 85, and 109-12;110. See also Fig. 7 and Fig. 11 of

Kim, below.

Claim 7

7. The device according to claim 6, wherein said multi-level


encoding said digital data input and

As discussed above, Kim taught the limitations of claim 6. Kim further

teaches the multi-level encoder, “…decoder for converting a binary data to a



Page 48

ternary data, a ternary data generator for generating three logic levels …” Ex.

1003 at 3:5-11 (emphasis added); See Corcoran Ex. 1002 at ¶ 109-11.112.

said multi-level input data driver comprises a multi-level


Kim further teaches multi-level decoder, “…a data detector for converting

the three logic levels from the ternary data generator to pairs of binary data, and an

encoder for restoring the pairs of binary data to binary data.” Ex. 1003 at

3:10-12 (emphasis added); See Corcoran Ex. 1002 at ¶110.112.



Page 49

C. GROUND 3 - Claim 8-10 are Obvious under 35 U.S.C. § 103 (a)

over Kim and APA in view of Watanabe.

Claim 8

8. The system according to claim 1, wherein said multi-level

signal display data is in the form of digital signals with

amplitudes equal to one of eight values.

Claim 9

9. The method according to claim 3, wherein said multi-level



Claim 10




Claim 8, 9 and 10 are identical except that they depend from independent

Claim 1, 3 and 6, respectively. Kim in view of APA taught the limitations of

independent claims 1, 3, and 6, addressed in detail above. Kim in combination with

the APA does not disclose:

…wherein said multi-level signal display data is in the form of

digital signals with amplitudes equal to one of eight values.

The above limitations are identically required of claims 8, 9, and 10.

However, Watanabe (Ex. 1009) teaches multi-level data in the form of digital



Page 50

signals with amplitudes equal to one of eight values. See Ex. 1009, at Fig. 5B,

reproduced below:

As can been seen in Fig. 5B the “data series” (i.e., multi-level signal display

data) is one of 8 amplitude levels, namely. Namley: 0, 1, 2, 3, 4, 5, 6, and 7. The B-

level above is not used to represent “multi-level signal display data.” Watanabe is

clear on this point by designating, “…8 as the value of m…” Ex. 1009 at 7:35-40.

Corcoran Ex. 1002 ¶ 121.

When Kim in view of APA and Watanabe are combined together, they teach

the use of multi-level signal display data in the form of digital signals with

amplitudes equal to one of eight values. This natural combination of these

complementary references meets all of the limitations recited in claims 8-10



Page 51

(including their parent claims, from which they depend) and renders them

unpatentable for the following reasons.

It would have been obvious to combine the teachings of Watanabe with Kim

(including it APA) for several good reasons. First, these two complementary

references are from the same field of endeavor — data transmission. More

particularly, Watanabe and Kim both are concerned with the specific problem of

the conversion of binary data to multilevel data in connection with data

transmission. For example, Kim states, “An object of the present invention is to


improves a data transmission efficiency by converting a binary data to a

ternary data.” Kim Ex. 1003 at 2:59-62 (emphasis added).) Kim at 2:59-62. In a

complementary manner, Watanabe explains, “[t]he present invention relates to a

method of converting binary data and a multilevel signal, mutually and a

communication method employing the mutual conversion.” Watanabe Ex. 1009

at 1:8-10.

Second, Kim explains “when the data transmission device of the present

invention is applied to the LCD device, the number of the data transmission lines

between the LCD controller and the source driver is much reduced…” Ex. 1003 at

6:42-47.



Page 52

Watanabe teaches this solution to further improve accuracy in the

conversion from between binary data and a multilevel signal. For example, “it is

an object of the present invention to obtain level and timing standards accurately

from a received signal in mutual conversion between binary data and a

multilevel signal.” Ex. 1009 at 1:43-46 (emphasis added).. It would have been

obvious to a person of ordinary skill in the art to use one of eight amplitude levels

taught by Watanabe to represent display data in the form of digital signals, because

a person of ordinary skill in the art would have recognized that increasing the

number of levels improves data transmission efficiency. See Corcoran Ex. 1002 ¶¶

37-38.

For the above reasons, this combination of Watanabe and Kim in the manner

claimed in claims 8, 9, and 10 of the ‘247 Patent, including each claim depended

from) amounts to the use of a known technique (using eight levels) to improve

similar devices (that use multi-level transmission) in the same way (to improve

data transmission efficiency). KSR Int'l Co. v. Teleflex Inc., 550 U. S. 398, 417

(2007). A system designer of ordinary skill wishing to improve data transmission

efficiency would have seen a benefit of implementing Kim using the eight levels

suggested in Watanabe. See Corcoran Ex. 1002 at ¶¶ 109-114, 117, and 121. This

is especially true given the 3-bit solution Watanabe proposes. See to Kim’s 3-bit

requirement. Corcoran Ex. 1002 at ¶¶ 111, and 119-122



Page 53

Finally, as noted above, should Patent Owner contend that either Watanabe

or Kim lack sufficient disclosure of some claim element, it is respectfully

submitted that the PTAB should compare the reference’s disclosure of that element

to that of the specification of the ‘247 Patent. See In re Epstein, 32 F. 3d 1559,

1568 (Fed. Cir. 1994); In re Fox, 471 F. 2d 1405, 1407 (CCPA 1973).

D. GROUND 4 - Claims 1-7 are Obvious under 35 U.S.C. § 103 (a)

over Go in view of the APA of the ‘247 Patent.

Claim 1

1. A data transfer system for a multi-level signal for

providing a display data to a matrix display panel,

comprising:…

The ‘247 Patent describes a matrix display panel including a data transfer

system for providing display data to a matrix display panel as being known in the

prior art. See Ex. 1001, Fig. 1 and Col. 1:27-43 (“FIG. 1 is a block diagram

showing a conventional active matrix LCD … LCD panel 100 comprises … a

plurality of pixels … [e]ach of the pixels consists of a … thin film transistor (TFT)

… connected between the liquid crystal cell and one of the data bus lines … a

digital input data driver 20 provides a data driving signal. A display data required

for image display is generated by a digital timing controller 40 through an input

interface 50, and is sent to the digital input data driver 20 via a digital bus 60.”).



Page 54

Go teaches a data transfer system for a multi-level signal for providing a

display data to a matrix display panel. See Ex. 1004 at Fig. 1, Col. 3:39-48, and

Col. 3:39-62 (“The video data generated by the video card 32 include red(R),

green(G), and blue(B) data for each pixel. Each one of the R, G, and B data has a

6-bit length, and hence the video data has a 18-bit length for each pixel. … The

video data VD comprising 18 bit lines are supplied, via a first bus line 31, to the

bus compressor 34. … The bus compressor 34 compresses the 18-bit video data

VD from the first data bus 31 to 9-analog signals. … The 9-analog signals AMS

generated by the bus compressor 34 in this manner are transferred to the LCD 40

over the FPC cable 36. … [T]he 18 bit video data are compressed into the 9-analog

signals to reduce the number of lines in the FPC cable 36.”).



output;…

The ‘247 Patent describes such a multi-level timing controller as comprising

of a prior art digital timing controller with an additional multi-level encoder

element. Compare Ex. 1001, Fig. 3 with Fig. 7 and see Col. 4:16-25 (“As shown in

FIG. 3, according to the prior art, a digital timing controller 40 comprises a timing

generator . . . [a]ccording to the present invention, as shown in FIG. 7, in addition



Page 55

to a timing generator 72, a multi-level timing controller 70 further comprises a

multi-level encoder …).

Go describes a multilevel controller that accepts 18-bit RGB video and

provides a multi-level output. See Ex. 1004 at Col. 3:50-51 (“The bus compressor

34 compresses the 18-bit video data VD from the first data bus 31 to 9-analog

signals.”).

The ‘encoding’ aspect of the ‘247 Patent Claim 1 “multilevel timing

controller” is described, below.

The ‘247 Patent describes a prior art timing controller used in a 6-bit XGA

notebook computer. See Ex. 1001 at Col. 2:22-28 (“The transceiver receives a

digital input signal and then outputs it to a digital timing controller 40 where it is

converted into a digital display data signal …”).


provides a multi-level signal display data output. See Ex. 1004 at Col. 3:50-58

(“The bus compressor 34 compresses the 18-bit video data VD from the first data

bus 31 to 9-analog signals. … Specifically, the bus compressor 34 modulates 2 bit

data from two bit lines of the first data bus 31 to a single analog signal having a

different amplitude signal AMS in accordance with logical values of the 2 bit data.

To this end, the bus compressor 34 includes 9-bus compression cells connected to

two separate bit lines among the 18 bit lines of the first data bus 31.”).



Page 56


connected to said multi-level timing controller, for

transferring said multi-level signal display data from said


Go describes a multi-level signal bus having a plurality of data lines. See Ex.

1004 at Col. 3:50-58 (“The bus compressor 34 compresses the 18-bit video data



over the FPC cable 36.”).

a multi-level input data driver connected to said multi-level

signal bus, for receiving said multi-level signal display data

input and converting it into a data driving signal to be

outputted to said matrix display panel.

The ‘247 Patent describes such a multi-level input data driver as comprising

of a prior art digital input data driver with an additional multi-level decoder

element. Compare Fig. 4 with Fig. 8 and see Col. 4:28-39 (“[I]n a prior art digital

input data driver 20 shown in FIG. 4, data … passes through an input data register


become an analog signal output…According to the present invention, as shown in

FIG. 8, the multi-level data … is inputted to a multi-level input data driver 80 and

then is decoded by a multi-level decoder 82. After that, it passes through an input



Page 57

data register 84, an internal processing logic 86 and a DAC 88 to become an

analog signal output …”).

The ‘247 Patent describes a prior art data driver that receives a signal display

data input and converts this input into a data driving signal. See Ex. 1001, Fig. 4

and Col. 2:28-32 (“[I]n a prior art digital input data driver 20 shown in FIG. 4, data

… passes through an input data register 22, an internal processing logic 24 and a

digital-to-analog converter (DAC) to become an analog signal output …”).

Go teaches that each data driver can be configured to receive a multi-level

signal bus. See Ex. 1004, Fig. 1 element 44, and Col. 3:63-4:4, and Col. 6:46-51

(“The LCD 40 includes a number of D-ICs 44 for divisionally and selectively

driving the pixels in the liquid crystal panel 42, a bus decompressor 46 for

receiving the 9-analog signals AMS … The bus decompressor 46 quantizes and

codes the 9-analog signals AMS … to substantially reconstruct 18-bit video. …

Moreover, in the LCD according to the present invention, the bus decompressor

can be mounted in each D-IC and the data transmission line is commonly

connected to the D-ICs, thereby further simplifying the wiring structure and

reducing the liquid crystal panel dimension.”).

Go describes an input data driver that that accepts a multi-level signal

display data input and provides a data driving signal. See Ex. 1004 at Col. 4:1-34

(“The bus decompressor 46 includes 9-bus decompression cells (not shown)



Page 58

responsive and corresponding to the 9-analog signals AMS. The reconstructed

video data VD are commonly supplied, via a second data bus 41 comprising 18-bit

lines, to the D-ICs 44. … The video data VD for one pixel line are distributively

and simultaneously inputted to each D-IC 44 the output of which are supplied to

the liquid crystal panel 42 to drive the pixels for one line. … [I]f the bus

decompressor 46 are located within each D-ICs 44 … then the EMI generated in

the video data … can be minimized and the wiring structure … can be simplified. )

The ‘247 Patent describes such as data driving signal being output to the

matrix display panel. See Ex. 1001, Fig. 1 and Col. 1:19-39 (“[T]hin or flat

displays have been developed, including liquid crystal displays … such a display

comprises a plurality of picture element circuits arranged as a matrix. Each of the

picture element circuits is controlled to turn on/off to determine display state of its

corresponding pixel. … Each of the pixels consists of a liquid crystal cell and a

switching element … the switching element is a thin film transistor (TFT). The

TFT is connected between the liquid crystal cell and one of the data bus lines, and

it has a gate connected to one of the scan bus lines. A scan driver 10 selects one of

the TFTs in a LCD panel 100 and a digital input data driver 20 provides a data

driving signal.”).



Page 59

Claim 2



encoding said digital data input and said multi-level input

data driver comprises a multi-level decoder for decoding said

multi-level signal display data.

As discussed above, the prior art teaches and/or suggests the limitations of

independent claim 1. Go describes a multilevel encoder that accepts 18-bit RGB

video and provides a multi-level output. See Ex. 1004Col. 3:50-51 (“The bus

compressor 34 compresses the 18-bit video data VD from the first data bus 31 to 9-

analog signals.”).


signal bus. See Ex. 1004, Fig. 7, Col. 4:1-4, and Col. 6:46-51 (“The bus

decompressor 46 quantizes and codes the 9-analog signals AMS … to substantially

reconstruct 18-bit video. … Moreover, in the LCD according to the present

invention, the bus decompressor can be mounted in each D-IC and the data

transmission line is commonly connected to the D-ICs, thereby further simplifying

the wiring structure and reducing the liquid crystal panel dimension.”).



Page 60

Claim 3




Go teaches a data transfer method for a multi-level signal for providing a

display data to a matrix display panel. See Ex. 1004, Fig. 1, Col. 3:39-48, and Col.

3:39-62 (“The video data generated by the video card 32 include red(R), green(G),

and blue(B) data for each pixel. Each one of the R, G, and B data has a 6-bit

length, and hence the video data has a 18-bit length for each pixel. … The video

data VD comprising 18 bit lines are supplied, via a first bus line 31, to the bus

compressor 34. … The bus compressor 34 compresses the 18-bit video data VD

from the first data bus 31 to 9-analog signals. … The 9-analog signals AMS



signals to reduce the number of lines in the FPC cable 36.”)




provides a multi-level output. See Ex. 1004 Col. 3:50-51 (“The bus compressor 34

compresses the 18-bit video data VD from the first data bus 31 to 9-analog

signals.”).



Page 61




1004 Col. 3:50-58 (“The bus compressor 34 compresses the 18-bit video data VD

from the first data bus 31 to 9-analog signals. … The 9-analog signals AMS






display data input and provides a data driving signal according to a first scheme.

See Ex. 1004 Col. 4:1-9 (“The bus decompressor 46 includes 9-bus decompression

cells (not shown) responsive and corresponding to the 9-analog signals AMS. The

reconstructed video data VD are commonly supplied, via a second data bus 41

comprising 18-bit lines, to the D-ICs 44.”).



Page 62

Claim 4

4. The method according to claim 3, further comprising

converting said second digital data signal into an analog

signal.


independent claim 3. The ‘247 Patent describes a prior art data driver that receives

a signal display data input and converts this input into a data driving signal. See

Ex. 1001 at Fig. 4 and Col. 2:28-32 (“[I]n a prior art digital input data driver 20

shown in FIG. 4, data … passes through an input data register 22, an internal

processing logic 24 and a digital-to-analog converter (DAC) to become an analog

signal output …”).

Claim 5



level encoder, and


independent claim 3. The ‘247 Patent describes such a multi-level timing controller

as comprising of a prior art digital timing controller with an additional multi-level

encoder element. Compare Ex. 1001 Fig. 3 with Fig. 7 and see Col. 4:16-25 (“As

shown in FIG. 3, according to the prior art, a digital timing controller 40 comprises

a timing generator . . . [a]ccording to the present invention, as shown in FIG. 7, in



Page 63

addition to a timing generator 72, a multi-level timing controller 70 further

comprises a multi-level encoder …).




signals … Specifically, the bus compressor 34 modulates 2 bit data from two bit

lines of the first data bus 31 to a single analog signal having a different amplitude

signal AMS in accordance with logical values of the 2 bit data. To this end, the bus

compressor 34 includes 9-bus compression cells connected to two separate bit lines

among the 18 bit lines of the first data bus 31.”).

step (c) comprises decoding said multi-level signal display


Go describes an input data driver that that includes a multi-level decoder.

See Ex. 1004 at Col. 4:1-34 (“The bus decompressor 46 includes 9-bus

decompression cells (not shown) responsive and corresponding to the 9-analog

signals AMS. The reconstructed video data VD are commonly supplied, via a

second data bus 41 comprising 18-bit lines, to the D-ICs 44. … The video data VD

for one pixel line are distributively and simultaneously inputted to each D-IC 44

the output of which are supplied to the liquid crystal panel 42 to drive the pixels

for one line. … [I]f the bus decompressor 46 are located within each D-ICs 44 …



Page 64

then the EMI generated in the video data … can be minimized and the wiring

structure … can be simplified.

Claim 6

6. A liquid crystal display device, comprising: a matrix liquid

crystal display panel; a scan driver for providing a scan

voltage signal to said liquid crystal display panel by a plurality

of scan bus lines; and a display data transfer system for

providing a data driving signal to said liquid crystal display

panel by a plurality of data bus lines, said display data

transfer system comprising:

The ‘247 Patent describes a matrix display panel including a data transfer

system for providing display data to a matrix display panel as being known in the

prior art. See Ex. 1001 at Fig. 1 and Col. 1:27-43 (“FIG. 1 is a block diagram

showing a conventional active matrix LCD … LCD panel 100 comprises … a

plurality of pixels … [e]ach of the pixels consists of a … thin film transistor (TFT)

… connected between the liquid crystal cell and one of the data bus lines … a

digital input data driver 20 provides a data driving signal. A display data required

for image display is generated by a digital timing controller 40 through an input

interface 50, and is sent to the digital input data driver 20 via a digital bus 60.”).

Go teaches a data transfer system for a multi-level signal for providing a

display data to a matrix display panel. See Ex. 1004 at Fig. 1, Col. 3:39-48, and



Page 65

Col. 3:39-62 (“The video data generated by the video card 32 include red(R),

green(G), and blue(B) data for each pixel. Each one of the R, G, and B data has a

6-bit length, and hence the video data has a 18-bit length for each pixel. … The

video data VD comprising 18 bit lines are supplied, via a first bus line 31, to the

bus compressor 34. … The bus compressor 34 compresses the 18-bit video data




signals to reduce the number of lines in the FPC cable 36.”).

a multi-level timing controller for receiving a digital data


output;




signals.”). The ‘encoding’ aspect of the ‘247 Claim 6 “multilevel timing

controller” is described below.



Page 66

The ‘247 Patent describes a prior art timing controller used in a 6-bit XGA

notebook computer. See Ex. 1001 at Col. 2:22-28 (“The transceiver receives a

digital input signal and then outputs it to a digital timing controller 40 where it is

converted into a digital display data signal …”).


provides a multi-level signal display data output according to a first scheme. See

Ex. 1004 at Col. 3:50-58 (“The bus compressor 34 compresses the 18-bit video

data VD from the first data bus 31 to 9-analog signals. … Specifically, the bus

compressor 34 modulates 2 bit data from two bit lines of the first data bus 31 to a

single analog signal having a different amplitude signal AMS in accordance with

logical values of the 2 bit data. To this end, the bus compressor 34 includes 9-bus

compression cells connected to two separate bit lines among the 18 bit lines of the

first data bus 31.”).


connected to said multi-level timing controller, for

transferring said multi-level signal display data from said



1004 at Col. 3:50-58 (“The bus compressor 34 compresses the 18-bit video data




Page 67



a multi-level input data driver connected to said multi-level

signal bus, for receiving said multi-level signal display data

input and converting it into said data driving signal.

The ‘247 Patent describes such a multi-level input data driver as comprising

of a prior art digital input data driver with an additional multi-level decoder

element. Compare Ex. 1001 Fig. 4 with Fig. 8 and see Fig. 4 with Fig. 8 and see

Col. 4:28-39 (“[I]n a prior art digital input data driver 20 shown in FIG. 4, data …

passes through an input data register 22, an internal processing logic 24 and a

digital-to-analog converter (DAC) to become an analog signal output . . .

According to the present invention, as shown in FIG. 8, the multi-level data … is

inputted to a multi-level input data driver 80 and then is decoded by a multi-level

decoder 82. After that, it passes through an input data register 84, an internal

processing logic 86 and a DAC 88 to become an analog signal output …”).

The ‘decoding’ aspect of this “multilevel input data driver” is described in

claim element 6i, below.

The ‘247 Patent describes a prior art data driver that receives a signal display

data input and converts this input into a data driving signal. See Ex. 1001 Fig. 4



Page 68

and Col. 2:28-32 (“[I]n a prior art digital input data driver 20 shown in FIG. 4, data

… passes through an input data register 22, an internal processing logic 24 and a

digital-to-analog converter (DAC) to become an analog signal output …”).


signal bus. See Ex. 1004 at Fig. 7, Col. 3:63 – 4:4, and Col. 6:46-51 (“The LCD 40

includes a number of D-ICs 44 for divisionally and selectively driving the pixels in

the liquid crystal panel 42, a bus decompressor 46 for receiving the 9-analog

signals AMS … The bus decompressor 46 quantizes and codes the 9-analog

signals AMS … to substantially reconstruct 18-bit video. … Moreover, in the LCD

according to the present invention, the bus decompressor can be mounted in each

D-IC and the data transmission line is commonly connected to the D-ICs, thereby

further simplifying the wiring structure and reducing the liquid crystal panel

dimension.”).


display data input and provides a data driving signal according to a first scheme.

See Ex. 1004 at Col. 4:1-34 (“The bus decompressor 46 includes 9-bus

decompression cells (not shown) responsive and corresponding to the 9-analog

signals AMS. The reconstructed video data VD are commonly supplied, via a

second data bus 41 comprising 18-bit lines, to the D-ICs 44. … The video data VD

for one pixel line are distributively and simultaneously inputted to each D-IC 44



Page 69

the output of which are supplied to the liquid crystal panel 42 to drive the pixels

for one line. … [I]f the bus decompressor 46 are located within each D-ICs 44 …

then the EMI generated in the video data … can be minimized and the wiring

structure … can be simplified.”).

The ‘247 patent describes such as data driving signal being output to the

matrix display panel. See Ex. 1001 at Fig. 1 and Col. 1:19-39 (“[T]hin or flat

displays have been developed, including liquid crystal displays … such a display

comprises a plurality of picture element circuits arranged as a matrix. Each of the

picture element circuits is controlled to turn on/off to determine display state of its

corresponding pixel. … Each of the pixels consists of a liquid crystal cell and a

switching element … the switching element is a thin film transistor (TFT). The

TFT is connected between the liquid crystal cell and one of the data bus lines, and

it has a gate connected to one of the scan bus lines. A scan driver 10 selects one of

the TFTs in a LCD panel 100 and a digital input data driver 20 provides a data

driving signal.”).



Page 70

Claim 7



encoding said digital data input and said multi-level input

data driver comprises a multi-level decoder for decoding said

multi-level signal display data.


independent claim 6.

Go describes a multilevel encoder that accepts 18-bit RGB video and



signals.”).


signal bus. See Ex. 1004 at Fig. 7, Col. 4:1-4, and Col. 6:46-51 (“The bus

decompressor 46 quantizes and codes the 9-analog signals AMS … to substantially

reconstruct 18-bit video. … Moreover, in the LCD according to the present

invention, the bus decompressor can be mounted in each D-IC and the data

transmission line is commonly connected to the D-ICs, thereby further simplifying

the wiring structure and reducing the liquid crystal panel dimension.”).



Page 71

E. GROUND 5 - Claim 8-10 are Obvious under 35 U.S.C. § 103 (a)

over Go and APA in view of Cao.

Claim 8:




Claim 9:

9. The method according to claim 3, wherein said multi-level



Claim 10:




Claim 8, 9 and 10 depend from independent Claims 1, 3 and 6, respectively.

Kim in view of APA taught the limitations of independent claims 1, 3 and 6,

addressed in detail above. However, Kim in combination with APA does not

disclose:

wherein said multi-level signal display data is in the form of

digital signals with amplitudes equal to one of eight values.

The above limitation is identically required of claims 8, 9 and 10. Cao is

cited for teaching the transmission of multi-level signal display data in the form of

digital signals with amplitudes equal to one of eight values. Specifically,



Page 72

“Referring to the table below, …the resistor values Ra, Rb, and Re are selected so

that predetermined voltages are 5 transmitted from output pin 104 along

transmission line 103 to chip 102 as a function of the logical levels of digital

signals A, B and C.” Cao Ex. 1005 at 4:3-7(emphasis added).

As can be seen above, the eight levels are 0, 0. 355, 0. 71, 1. 06, 1. 43, 1. 79,

2. 143, and 2. 5. Cao further explains, “The table shows that a unique voltage level

is transmitted along transmission line 103 from chip 101 to chip 102 for each of the

eight possible values (3 binary bits)…” Ex. 1005 at 4:35-37 (emphasis added).)

Cao at 4:35-37.

A person of ordinary skill would have been motivated to combine Cao with

Go because both references: (1) Identify a common problem, reducing wiring

complexity; (2) Specifically propose solutions to the common problem using

multi-level transmission; and (3) share the common goal of reducing the number of

transmission lines in order to simplify wiring structure. For example, Go states,



Page 73

“Another object of the present invention is to provide an interfacing unit that is

suitable for reducing the number of transmission lines.” Go Ex. 1004 at 2:20-

22(emphasis added).) Go at 2:20-22.1002 at ¶¶ 115-16. Go further states, “Still

another object of the present invention is to provide a liquid crystal display

wherein the wiring structure and circuit configuration thereof are simplified.”

Id. 2:23-2625.

Cao, in sharing the same goal, explains that,

“Naturally, to implement time division multiplexing, additional

complex circuitry is required. As a result, traditional system designs

have had to settle for implementing separate transmission lines in order

to support data communications in a simultaneous manner. However, it

is generally desired when designing circuitry (for example, for

computer systems) that the circuitry be simplified as much as

possible. Therefore, it is desired to reduce the number of

transmission lines between chips, along with the corresponding

connection circuitry (e.g., driver, receiver, chip pins and signal pads).”).

Cao Ex. 1005 at 1:34-45.

F. Supporting Evidence § 42. 104(b)(5)

The supporting evidence relied upon and the relevance of the evidence to the

challenges raised, including identification of specific portions of the evidence that

support the challenge, are provided herein. An Exhibit List identifying the exhibits

is included above. In further support of the proposed grounds of rejection, this



Page 74

Petition is accompanied by the declaration of Dr. Peter M. Corcoran, (“Corcoran”),

Ex. 1002.

VI. CONCLUSION

Petitioner has established a reasonable likelihood that the challenged claims

of the ‘247 Patent will be found unpatentable. Petitioner therefore respectfully

requests that inter partes review of the ‘247 Patent be granted, and that Claims 1-

10 be held unpatentable.

Respectfully submitted,

Dated: January 20, 2017


/Samir Termanini/

Samir Termanini, Reg. No. 56,591


15 Volvo Drive

Rockleigh, NJ 07647-2507

T: 201-767-3400 Ext. 12516

F: 201-768-7289

patents@crestron. com



Page 75

VII. CERTIFICATE OF SERVICE (37 C.F.R. §§ 42. 6(E) AND 42. 105(A))

The undersigned hereby certifies that the above-captioned “PETITION FOR

INTER PARTES REVIEW OF U. S. PATENT NO. 6,611,247” and true copies of

Exhibit Nos. 1001 to 1013 were served on Patent Owner on January 20, 2017, via

UPS, tracking number 1Z2FY5730192166332, at the official correspondence

address for the attorney of record for the ʼ247 patent as shown in USPTO PAIR via

UPS:

STEVEN M RABIN

RABIN & BERDO PC

1101 14TH STREET NW SUITE 500

WASHINGTON DC 20005




/Samir Termanini/



15 Volvo Drive


T: 201-767-3400 Ext. 12516

F: 201-768-7289




Page 76

VIII. CERTIFICATE OF COMPLIANCE (37 C.F.R. §§ 42. 6(E) AND 42.

105(A))

In accordance with 37 C.F.R. § 42. 24, as amended, the undersigned certifies

that this Petition complies with the applicable type-volume limitations of 37 CFR

42. 24(a)(i). Exclusive of the portions exempted by 37 CFR 42. 24(a), this Petition

contains 12,668 words as measured by the combined count of (1) the word

processing program used for its preparation (Microsoft Word 2016) and (2) a

manual count of the words that appear in the figures relied-upon herein.




/Samir Termanini/



15 Volvo Drive


T: 201-767-3400 Ext. 12516

F: 201-768-7289


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