unitedsic ujn1205k 1200v sic jfet - system plus consulting · this jfet is marketed as the ideal...

©2018 by System Plus Consulting | USCi UJN1205K 1

22 bd Benoni Goullin44200 NANTES - FRANCE +33 2 40 18 09 16 [email protected] www.systemplus.fr

USCi UJN1205K1200V SiC JFETPower report by Elena BARBARINI & Amine ALLOUCHEJune 2018 – version 1

REVERSE COSTING® – STRUCTURAL, PROCESS & COST REPORT


Table of Contents

Introduction 4

o Executive Summary

o Reverse Costing Methodology

o Glossary

o SiC Power Device Market

Company Profile 10

o UnitedSiC

o Portfolio

o Supply Chain

Physical Analysis 15

o Summary of the Physical Analysis

o Package analysis

Package Opening

Package Cross-section

o JFET Die

JFET Die View & Dimensions

JFET Delayering & main Blocs

JFET Die Process

JFET Die Cross-Section

JFET Die Process Characteristic

Manufacturing Process 43

o JFET Die Front-End Process

o JFET Fabrication Unit

o Packaging Process & Fabrication unit

Cost Analysis 51

o Summary of the cost analysis

o Yields Explanation & Hypotheses

o JFET die

JFET Die Front-End Cost

JFET Die Probe Test, Thinning & Dicing

JFET Die Wafer Cost

JFET Die Cost

o Complete Device

Assembled Components Cost

Summary of the assembling

Component Cost

Selling Price 62

Comparison between UnitedSiC’s and Semisouth’s SiC JFET 65

Company services 70


Overview / Introductiono Executive Summaryo Reverse Costing

Methodologyo Glossary

Company Profile & Supply Chain

Physical Analysis

Manufacturing Process Flow

Cost Analysis

Selling Price Analysis

Comparison

Feedbacks

About System Plus

Executive Summary

Silicon carbide-based device penetration is expanding in industrial applications. JFET is one of them.

UnitedSiC offers two types of medium-voltage (1200V) SiC JFETs, with the UJN1205K achieving the highest current (38A).

This JFET is marketed as the ideal solution for circuit protection because of its ability to handle peak temperatures and limit current by a rapid decrease due to self-heating.

The device also offers a low on-resistance of 45mΩ, but a very high current density of 4.08 A/mm2 at 25°C, thanks in large part to its trench structure with special openings for contacts.

UnitedSiC employs in its JFET structure a unique angled implantation process to improve threshold voltage control, and a silicide for both gate and source contact to boost contact resistance.

Owing to its design, the device’s cost is very competitive regarding its special steps. , Also, the packaging is optimized for cost-savings.

This report presents a deep technology analysis of the UJN1205K device, assembled in a TO247 package.

Also included is a production cost analysis, and comparisons with its JFET counterpart from SemiSouth. This comparison highlights the differences in the design technology choices and the electrical/geometrical parameters.


Overview / Introductiono Executive Summaryo Reverse Costing

Methodologyo Glossary


Physical Analysis


Cost Analysis


Comparison

Feedbacks

About System Plus

SiC Power Device market - Projection


Overview / Introduction

Company Profile & Supply Chain o UnitedSiCo SiC Portfolioo Supply Chain

Physical Analysis


Cost Analysis


Comparison

Feedbacks

About System Plus

UnitedSiC (USCi) : Company Profile

UnitedSiC is a fabless company that designs SiC semiconductors devices.

2016 UnitedSiC Financial Highlights:

o Sales revenues: $xx Million

o Estimated gross margin: xx%

General Information:

o Date of Establishment

xx

o Headquarter:

Monmouth Junction, New Jersey, USA

xx employees.

Source: «SiC Cascodes and its advantages in power electronic applications», Christopher Rocneanu, WBG Power Conference, 5th December 2017

Company History:



Company Profile & Supply Chain o UnitedSiCo SiC Portfolioo Supply Chain

Physical Analysis


Cost Analysis


Comparison

Feedbacks

About System Plus

SiC Portfolio

UnitedSiC JFETs portfolio proposes 2 types of SiC JFET at 1200V (two packaged and two bare dies)




Physical Analysis o Synthesiso Packageo Die designo Die Cross section


Cost Analysis


Comparison

Feedbacks

About System Plus

Datasheet






Cost Analysis


Comparison

Feedbacks

About System Plus

o The package type is a TO-247-3

o Package size : xxmm x xxmm x xxmm

o Pin pitch : xxmm

o The package markings include the following markings :

UJN1205K

USCi Logo

P1740 577

Package Views & Dimensions

Package Front view Package Back view

Reference of component

Lot code*Assembly & Date code*

*Source: TO-247-3L JFET OUTLINE, MARK AND TUBE, USCi






Cost Analysis


Comparison

Feedbacks

About System Plus

Package opening

Gate Wire Bonding:

o 1 Al wire.

o Diameter: xx µm.

o Medium length: xx mm

Source Wire Bonding:

o 2 Al wire.

o Diameter: xx µm.

o Medium length: xx mm

Package

xxxx

Package opening

xxx

xxx

xxxx

Wire bonding






Cost Analysis


Comparison

Feedbacks

About System Plus

Package Cross-Section

Package cross section

The packaging is standard plastic molding.






Cost Analysis


Comparison

Feedbacks

About System Plus

Package Cross-Section

Package cross section






Cost Analysis


Comparison

Feedbacks

About System Plus

Die process – Ring

• Distance between the active area and the die edge: xx µm

241 µm

Transistor process – Optical View

Active area

xx µm

Transistor process – Optical View

Sourcecontact






Cost Analysis


Comparison

Feedbacks

About System Plus

Die cross section

Epitaxy xx µm

Die cross section: SEM view

• SiC epitaxy layer thickness: xx µm

Silicon carbide substrate

Polyimide






Cost Analysis


Comparison

Feedbacks

About System Plus

Die cross section : Source trenches

Cross-Section SEM view

• Transistor pitch: xx µm

xx µm




Physical Analysis

Manufacturing Process Flowo Process flowo Front End Fab Unito Back End Fab Unit

Cost Analysis


Comparison

Feedbacks

About System Plus

JFET Process Flow (1/4)

Epitaxy

•N- Epitaxy

P++ Implantation

•TEOS oxide deposition

•Pattern SiO2

•P++ well implantation

Trench & P+ Implantation

• SiN deposition

•Pattern SiN

•Trench patterning

•P+ well tilted implantation

N- Drift Region Epitaxy

SiC Substrate N+

Drawings not to Scale

SiC Substrate N+

0

00 00

0




Physical Analysis


Cost Analysiso Synthesiso JFET Wafer Costo JFET Die Costo Packaging Costo Component Cost


Comparison

Feedbacks

About System Plus

JFET Front-End Cost

The front-end cost ranges from $xx to $xx according toyield variations.

The main part of the wafer cost is due to xx (xx%). Theepitaxy steps represent a large part of consumable andequipment cost (see details in the following pages).




Physical Analysis




Comparison

Feedbacks

About System Plus

JFET Wafer Cost per process steps




Physical Analysis




Comparison

Feedbacks

About System Plus

JFET Die Cost

The JFET die cost ranges from $xx to $xx according toyield variations.

The Front end manufacturing represents xx% of thecomponent cost, medium yield.

Probe test, dicing and scrap account for xx% of thecomponent cost.



Company Profile & SupplyChain

Physical Analysis


Cost Analysis


Comparisono UnitedSiC’s and

Semisouth’s SiC JFETAbout System Plus

Comparison between UnitedSiC’s and Semisouth’s SiC JFET

UJN1205K

SJEP170R550




Physical Analysis


Cost Analysis


Comparison

Feedbacks

About System Pluso Company serviceso Related reportso Contacto Legal

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