untethered lowrisc, memory mapped io and...
TRANSCRIPT
Untethered lowRISC, Memory Mapped IO and TileLink/AXI
Wei Song 27/07/2015
Time Line
2
Nov. 2014
Rocket-Chip release from Berkeley
Apr. 2015
First lowRISC release.
Initial tagged memory support.
Now
Memeory Mapped IO.
Oct. 2015
Untethered lowRISC release.
· Added tags in L1 D$, L2.· Added a tag cache.· Added 2 instructions to load/
store tag.· A tutorial about Rocket-chip.
· Untethered SoC.· Support Kintex KC705.· Support MMIO.· Support SD, UART, DDRAM.· Open simulation environment.
expected
Rocket-Chip Release (Berkeley)
3
Rocket Core
L2 & Coherence Manager
L2 & Coherence Manager
TileLink
I$ D$
Rocket Tile
TileLinkTileLink
L2 & Coherence Manager
TileLinkTileLinkTileLink
Rocket Core
I$ D$
Rocket Tile
Rocket Core
I$ D$
Rocket Tile
Arbiter
Memory Controller
MemIO Converter
Host Interface
ARM
UART
SD
EtherNet
lowRISC Release (tagged memory)
4
Rocket Core
L2 & Coherence Manager
L2 & Coherence Manager
TileLink
Allocator
I$ D$
Rocket Tile
TileLinkTileLink
L2 & Coherence Manager
TileLinkTileLinkTileLink
Rocket Core
I$ D$
Rocket Tile
Rocket Core
I$ D$
Rocket Tile
Tracker & Converter
DataArray
Tracker & Converter
MetaDataArray
Arbiter
Memory Controller
Tag Cache
Host Interface
ARM
UART
SD
EtherNet
Tag in L1 D$, L2 $ Tag Cache LTAG/STAG instructions
Latest Rocket-Chip (Berkeley)
5
Rocket Core
L2 & Coherence Manager
L2 & Coherence Manager
I$ D$
Rocket Tile
L2 & Coherence Manager
Rocket Core
I$ D$
Rocket Tile
Rocket Core
I$ D$
Rocket Tile
Arbiter
Memory Controller
Host Interface
TileLink/AXI
AXI/MemIO
AXI Bus
ARM
UART
SD
EtherNet
Cached TileLink
Uncached TileLink
AXI
MemIO
L2 Bus
Multi-beat TileLink Standardize TileLink transactions Possible coherence support of L3 Code refactoring AXI/AXI interface (NASTI)
Untethered lowRISC SoC (First Version)
6
Rocket Core
L2 & Coherence Manager
L2 & Coherence Manager
I$ D$
Rocket Tile
L2 & Coherence Manager
Rocket Core
I$ D$
Rocket Tile
Rocket Core
I$ D$
Rocket Tile
Arbiter
Memory Controller
TileLink/AXIAXI Bus
Cached TileLink
Uncached TileLink
AXI
L2 Cache Bus
Tag Cache
On-FPGABoot Ram
L2 IO Bus
AXI-Lite
UART SD EtherNet
TileLink/AXI-LiteDMA
DMA
coherent
incoherent
Boot Minion
Current Status
7
Rocket Core
L2 & Coherence Manager
L2 & Coherence Manager
I$ D$
Rocket Tile
L2 & Coherence Manager
Rocket Core
I$ D$
Rocket Tile
Rocket Core
I$ D$
Rocket Tile
Arbiter
Memory Controller
TileLink/AXIAXI Bus
Cached TileLink
Uncached TileLink
AXI
L2 Cache Bus
Tag Cache
On-FPGABoot Ram
L2 IO Bus
AXI-Lite
UART SD EtherNet
TileLink/AXI-LiteDMA
DMA
coherent
incoherent
Boot Minion
Memory Mapped IO
• Target
– IO load/write (B/HW/W/DW)
– In-order uncached load/store
– Side effect
• None for all write in units of byte
• None for all read in units of word (32-bit AXI-Lite)
– No change in current L2 coherent manager
8
Untethered lowRISC SoC (First Version)
9
Rocket Core
L2 & Coherence Manager
L2 & Coherence Manager
I$ D$
Rocket Tile
L2 & Coherence Manager
Rocket Core
I$ D$
Rocket Tile
Rocket Core
I$ D$
Rocket Tile
Arbiter
Memory Controller
TileLink/AXIAXI Bus
Cached TileLink
Uncached TileLink
AXI
L2 Cache Bus
Tag Cache
On-FPGABoot Ram
L2 IO Bus
AXI-Lite
UART SD EtherNet
TileLink/AXI-Lite
AXI/AXI-Lite
DMA
DMA
coherent
incoherent
Boot Minion
L1 Data Cache
10
data[DataArray
rocket/nbdcache.scala]
meta[MetadataArray
uncore/cache.scala]
mshrs[MSHRFile;rocket/nbdcache.scala]
mshr[MSHR
rocket/nbdcache.scala]
data[DataArray
rocket/nbdcache.scala]
meta[MetadataArray
uncore/cache.scala]
wb[WriteBack;rocket/nbdcache.scala]prober
[ProbeUnit;rocket/nbdcache.scala]
dtlb[TLB
rocket/tlb.scala]
Arb
iter
01234
Arb
iter
01
23
mshrs.replay
Arb
iter
01234
s1_req
s1_req.addr
====
s1_tag_eq_way code[DecodeLogic
rocket/decode.scala]
s1_addr
read
read
resp
resp
s2_req
s2_data(uncorrected)
amoalu[AMOALU
rocket/nbdcache.scala]
s3_req
s2_hit
s2_d
ata (corrected
)
Arb
Arb
0
1
0
1 write
write
mshrs.request
mshrs.meta_write
mem.req mem.grant
Arb
0
1meta/data read
meta/data read
wb
.meta/d
ata_readp
rob
er.meta/d
ata_read
req
Arb
0
1
releaserepwb_req
data_resp
s2_data(corrected)
prober.releasemshrs.wb_req
meta_write
prober.meta_write
line_state
req
mem.probemem.finish
mem
.release
cpu.resp.validcpu.resp.bits.data
cpu
.reqcp
u.p
tw
dtlb.ptw
Stage 1 Stage 2 Stage 3 Stage 4
s2_recycles1_recycled
s2_d
ata_correctab
le
vpn
ppn
correctable
correctin out
rhs
lhsout
s1_data
s2_tag_eq_way
s2_data
s2_h
it
L1 Data Cache (simplified)
11
data
meta
mshrs mshr
data
meta
dtlb
Arb
iterA
rbiter
mshrs.replay
Arb
iter
s1_req
s1_req.addr
====
s1_tag_eq_way
s1_addrread
read
resp
resp
s2_req
amoalu
s2_hit
write
write
mshrs.request
mshrs.meta_write
mem.req mem.grant
cpu
.req
Stage 1 Stage 2 Stage 3 Stage 4
vpn
ppn
rhs
lhs
out
s1_datas2_data
s2_h
it
cpu.resp
Arb
s1_ad
dr
L1 Data Cache with IO Handler
12
data
meta
mshrs mshr
data
meta
dtlb
Arb
iterA
rbiter
mshrs.replay
Arb
iter
s1_req
s1_req.addr
====
s1_tag_eq_way
s1_addrread
read
resp
resp
s2_req
amoaluwrite
write
mshrs.request
mshrs.meta_write
io.req io.grant
cpu
.req
Stage 1 Stage 2 Stage 3 Stage 4
vpn
ppn
rhs
lhs
out
s1_datas2_data
s2_h
it
cpu.resp
Arb
s1_ad
dr
ioaddr
s2_req.addr
addr io
iomshr
request
iomshr.replay
io_data s1_io_data
s2_io
_data
s2_io
_replay
io_datareplay
mem.req mem.grant
TileLink Channels
• Manager/Client – Manager: Coherent manager or next level cache/device – Client: upper level cache
• 5 Channels – Acquire: [C -> M]
• Read, uncached write (write-through, IO), permission update
– Grant: [M -> C] • Ack to Acquire (with data when read)
– Finish: [C -> M] • Finish a transaction
– Probe: [M -> C] • Coherence probe (snoop, invalidate)
– Release: [C -> M] • Write-back (replace or invalidate)
13
Untethered lowRISC SoC (First Version)
14
Rocket Core
L2 & Coherence Manager
L2 & Coherence Manager
I$ D$
Rocket Tile
L2 & Coherence Manager
Rocket Core
I$ D$
Rocket Tile
Rocket Core
I$ D$
Rocket Tile
Arbiter
Memory Controller
TileLink/AXIAXI Bus
Cached TileLink
Uncached TileLink
AXI
L2 Cache Bus
Tag Cache
On-FPGABoot Ram
L2 IO Bus
AXI-Lite
UART SD EtherNet
TileLink/AXI-Lite
AXI/AXI-Lite
DMA
DMA
coherent
incoherent
Boot Minion
TileLink Corssbar
15
AcquireGrant
FinishProbe
Release
AcquireGrant
FinishProbe
Release
AcquireGrantFinishProbeRelease
AcquireGrantFinishProbeRelease
L1 $
L1 $L2
Bank
L2 Bank
client ManagerTileLink Corssbar
Shared TileLink Corssbar
16
AcquireGrant
FinishProbe
Release
AcquireGrant
FinishProbe
Release
AcquireGrantFinishProbeRelease
AcquireGrantFinishProbeRelease
L1 $
L1 $L2
Bank
L2 Bank
client ManagerShared TileLink Corssbar
Use a SuperChannel to store all types of TileLink channels.
Current Status of TileLink/AXI
• TileLink/AXI (Berkeley, Rocket-chip) – only a whole cache line
• TileLink/AXI-Lite (lowRISC) – 1,2,4,8 byte write; 4,8 byte read
• AHB/APB (Berkeley, Z-Scale)
• Still needed: – AXI/AXI-Lite compatible, auto width SerDes switch
• The AXI-Node from PULP • May be in Chisel for its parameterization capability
– AXI/Wishbone, TileLink/Wishbone
17
Remain Issues
• Interrupt controller • Open Sourced, License compatible IPs
– UART (Flexpret, BSD) – SD host controller – Ethernet controller (Xilinx IP for now) – Memory controller (difficult to get)
• Open Source EDA tools – Current environment:
• VCS (DRAMSim, Front-end server, DirectC) • Vivado+SDK (SDK not available for Kintex)
– Target environment: • Verilator (SystemVerilog 2009, SystemC, VPI, DPI) • Vivado only
18
After the Untethered SoC
• Implementing the hierarchical tag cache (hardware)
• Debug interface
• Integrating minions (PULP)
• Tag support in Rocket cores (Lucas)
19