updated chapter 8

8/3/2019 Updated Chapter 8

1/65

Central Processing Unit

1


2/65

Contents Introduction

General Register Organization

Stack Organization Instruction Formats

Addressing Mode

Data Transfer and Manipulation Program Control

Reduced Instruction Set Computer (RISC)

2


3/65

Introduction

3


4/65

Major components of CPU

4

Control

Register set

Arithmeticlogic unit(ALU)


5/65

General Register Organization

5


6/65

Register set with common ALU

6

Arithmeticlogic unit

(ALU)

SELA SELB

OPR

OutputSELD

3X8decoder

MUX MUX

Abus Bbus

R7

R6

R5R4

R3

R2

R1

Load

(7 lines)

Clock Input

(a) Block diagram


7/657


8/658


9/65

Examples of microoperations for the CPU

9

Microoperation

Symbolic designation

Control wordSELA SELB SELD OPR

R1 R2 R3R4 R4 V R5R6 R6 + 1R7 R1Output R2

Output InputR4 shl R4R5 0

R2 R3 R1 SUBR4 R5 R4 ORR6 R6 INCAR1 R7 TSFAR2 None TSFA

Input None TSFAR4 R4 SHLAR5 R5 R5 XOR

010 011 001 00101100 101 100 01010110 000 110 00001001 000 111 00000010 000 000 00000

000 000 000 00000100 000 100 11000101 101 101 01100


10/65

Stack Organization

10


11/6511


12/6512


13/65

Reverse polish Notation for stack

13


14/65

Conversion RPN

Infix expression (A+B)*[C*(D+E)+F]

First perform the arithmetic inside the parenthesis.

Next calculate the expression between the squarebrackets.

The Multiplication must be done before in thisC*(D+E)+F ,since multiplication has higher

precedence over addition

RPN= AB+ DE+C*F+*

14


15/65

Instruction Formats

15


16/65

Instruction Format

16


17/65

17


18/65

18


19/65

Addressing Mode

19


20/65

20

ADDRESSING MODES


21/65

Implied Addressing mode:

In this mode the operands are specified implicitly in the definition of

the instruction.

E.g. CMA ,CME because the operand in the accumulator register isimplied in the definition of the instruction.

Opcode Mode Address

21


22/65

Immediate Addressing Operand is part of instruction

Operand = address field

e.g. ADD 5

Add 5 to contents of accumulator 5 is operand

No memory reference to fetch data

Fast

Limited range

OperandOpcode

Instruction


23/65

Direct Addressing Address field contains address of operand

Effective address (EA) = address field (A)

e.g. ADD A

Add contents of cell A to accumulator Look in memory at address A for operand

Single memory reference to access data

No additional calculations to work out effective address


24/65

Direct Addressing Diagram

Address AOpcode

Instruction

Memory

Operand


25/65

Indirect Addressing Memory cell pointed to by address field contains the address of

(pointer to) the operand .

EA = (A)

Look in A, find address (A) and look there for operand e.g. ADD (A)

Add contents of cell pointed to by contents of A to accumulator

Multiple memory accesses to find operand

Hence slower


26/65

Indirect Addressing Diagram

Address AOpcode

Instruction

Memory

Operand

Pointer to operand


27/65

Register Addressing Operand is held in register named in address filed

EA = R

Limited number of registers

Very small address field needed Shorter instructions

Faster instruction fetch

No memory access


28/65

Register Addressing Diagram

Register Address ROpcode

Instruction

Registers

Operand


29/65

Register Indirect Addressing

The instruction specifies the register which give the address of theoperand in the memory.

The selected register contain the address of the operand rather thenthe operand itself.

The advantage of RIA mode is that the address field if the instructionuses fewer bit to select the register then would have been required to

specify the memory address directly.


30/65

Register Indirect Addressing Diagram

Register Address ROpcode

Instruction

Memory

OperandPointer to Operand

Registers


31/65

Auto increment or Auto decrement Mode:

This mode is similar to register indirect mode exceptthe register is incremented or decremented after (orbefore)its vale is accessed from the memory.

31


32/65

Relative Addressing Mode:

In this mode the content of Program Counter (PC) is added to the address

part of the instruction in order to obtain the effective Address.

E.g. Assume the PC=825

Address part of the Instruction contain 24

Then the instruction location 825 is read from memory during fetch phaseand PC is incremented by 1.

PC=825+1=826

Effective address=826+24=850

This mode is largely used in branch type instructions.

It result in shorter address field in the instruction format since the relative

address can be specified with the smaller no. of bits as compare to entire

memory address.

32


33/65

Indexed Addressing Mode:

In this mode the content of index register is added toaddress part of the instruction to obtain the effectiveAddress.

Index register is a CPU register contain the indexvalue.

The address field of the instruction defines thebeginning address of the data array in the memory.

Each operand in the array is stored in the memoryrelative to the beginning address.

33


34/65

Base Register Address Mode:

The content of a base register is added to the addresspart of the instruction to obtain the effective address.

This is similar to index register mode except the registeris base register.

34


35/65

35

Numerical example for addressing modes


36/65

PROGRAM CONTROL

Instruction are stored in successive memory locations. When processed in

the CPU, the instructions are fetched from the memory place .

Program control types of instructions , when executed, may change the

address value of the program counter and causes the flow of instructionaltered.

This change in program counter value result in execution of a program

control instruction causing break in sequence of instruction execution.

This is also known as Branching capability of digital system into various

segment of the program.

36


37/65

Program Control

37


38/65

Processor status word register

Status register is where the status bit condition can be

stored for further analysis.

Status bits are also called condition code bit or flag bit.

Common flags in PSW

C, Carry is set to 1 if carry out of ALU is 1

S, Sign set to 1 if MSB bit is 1

Z ,zero is set to 1,if all the bits of output are 0s.

V, Overflow set to 1,XOR of last two bits is equals to 1.

38


39/65

Status register bits

39

8-bit ALU

F7~F0

Check for zero output

Output F

V Z S C

F7

A B

8

88

C7

C8


40/65

CONDITIONAL BRANCH INSTRUCTIONS

40


41/65

Reduced Instruction Set Computer(RISC)

41


42/65

Introduction The trend into computer hardware complexity was

influenced by various factors: Upgrading existing models to provide more customer applications

Adding instructions that facilitate the translation from high-level language

into machine language programs Striving to develop machines that move functions from software

implementation into hardware implementation

A computer with a large number of instructions isclassified as a complex instruction set computer(CISC).

A computer use fewer instructions with simple constructsso they can be executed much faster within the CPU

without having to use memory as often. It is classified as areduced instruction set computer(RISC).

42


43/65

Introduction(cont.) One reason for the trend to provide a complex instruction

set is the desire to simplify the compilation and improvethe overall computer performance.

The essential goal of a CISC architecture is to attempt toprovide a single machine insruction for each statementthat is written in a high-level language.

Example of CISC architecture are the DEC VAX computer

and the IBM 37 0computer.

43


44/65

CISC characteristics The major characteristics of CISC architecture are:

A large number of instructions typically from 100 to 250 instructions

Some instructions that perform specialized tasks and are used

infrequently

A large variety of addressing modestypically from 5 to 20 differentmodes

Variable-length instruction formats

Instructions that manipulate operands in memory

44


45/65

RISC characteristics The major characteristics of a RISC processor are:

Relatively few instructions

Relatively few addressing modes

Memory access limited to load and store instructions All operations done within the registers of the CPU

Fixed-length, easily decoded instruction format

Single-cycle instruction execution

Hardwired rather than microprogrammed control

45


46/65

RISC characteristics(cont.) Other characteristics attributed to RISC architecture are:

A relatively large number of registers in the processor unit

Use of overlapped register windows to speed-up procedure call and return

Efficient instruction pipeline

Compiler support for efficient translation of high-level language programsinto machine language programs

Studies that show improved performance for RISCarchitecture do not differentiate between the effects of thereduced instruction set and the effects of a large register file. A large number of registers in the processing unit are sometimes associated

with RISC processors.

46


47/65

Overlapped register windows Some computers provide multiple-register banks, and each procedure

is allocated its own bank of registers. This eliminates the need forsaving and restoring register values.

Some computers use the memory stack to store the parameters that areneeded by the procedure, but this required a memory access every timethe stack is accessed.

A characteristics of some RISC processors is their use of overlappedregister windows to provide the passing of parameters and avoid theneed for saving and restoring register values.

The concept of overlapped register windows is illustrated in Fig. 8-9.

47


48/65

Overlapped register windows(cont.)

In general, the organization of register windows will havethe following relationships:

number of global registers = G

number of local registers in each window = L

number of registers common to two windows = C

number of windows = W

The number of registers available for each window iscalculated as followed:

window size = L + 2C + G

The total number of registers needed in the processor isregister file = (L + C)W + G

The example of Fig. 8-9:

48


49/65

Overlapped register windows

49

R15

R10

R73

R64R63

R58

R57

R48

R47

R42

R41

R32R31

R26R25

R16

R15

R10

R9

R0

Common to allprocedures

Globalregisters

Common to D and A

Common to A and D

Common to A and B

Common to B and C

Common to C and D

Local to D

Local to C

Local to B

Local to A

Proc D

Proc C

Proc B

Proc A


50/65

Berkeley RISC I The Berkeley RISC I is a 32-bit integrated circuit CPU.

It supports 32-bit address and either 8-, 16-, or 32-bit data.

It has a 32-bit instruction format and a total of 31 instructions.

There are three basic addressing modes: Register addressing, immediate operand, and relative to PC addressing

for branch instructions.

It has a register file of 138 registers

10 global register and 8 windows of 32registers in each

The 32 registers in each window have an organization similar to theone shown in Fig. 8-9.

50


51/65

Berkeley RISC I(cont.) Fig. 8-10 shows the 32-bit instruction formats used for

register-to-register instructions and memory accessinstructions.

Seven of the bits in the operation code specify anoperation, and the eighth bit indicates whether to updatethe status bits after an ALU operation.

For register-to-register instructions : The 5-bit Rd field select one of the 32 rgisters as a destination for the

result of the operation The operation is performed with the data specified in fields Rs and S2.

Thus the instruction has a three-address format, but the second sourcemay be either a register or an immediate operand.

51


52/65

Berkeley RISC I(cont.) For memory access instructions:

Rs to specify a 32-bit address in a register

S2 to specify an offset

Register R0 contains all 0s, so it can be used in any field to specify a zero

quantity

The third instruction format combines the last three fieldsto form a 19-bit relative address Y and is used primarily

with the jump and call instructions. The COND fieldreplaces the Rd field for jump instructions and is used to

specify one of16 possible branch conditions.

52


53/65

Berkeley RISC I instruction formats

53

(a) Register mode: (S2 specifies a register)

(b) Register-immediate mode: (S2 specifies an operand )

(c) PC relative mode:

31 24 23 19 18 14 13 12 5 4 0

Opcode Rd Rs Not used S20

88 1 555

31 24 23 19 18 14 13 12 0

Opcode Rd Rs S21

138 155

31 24 23 19 18 0

Opcode COND

198 5

Y


54/65

Instruction set of berkeley RISC I The 31 instructions of RISC I are listed in Table8-12.

They have been grouped into three categories: The data manipulation instructions:

Perform arithmetic, logic, and shift operations. An immediate operandis symbolized by the number sign #.

54

ADD R22, R21, R23 R23 R22 + R21ADD R22, #150, R23 R23 R22 + 150

ADD R0, R21, R22 R22 R21 (Move)ADD R0, #150, R22 R22 150 (Load immediate)ADD R22, #1, R22 R22 R22 + 1 (Increment)


55/65

Instruction set of berkeley RISC I The data transfer instructions:

Consist of six load instructions, three store instructions, and two instructionsthat transfer the program status word PSW.

PSW contains the status of the CPU and includes the program counter, the status

bits from the ALU, pointers used in conjunction with the register windows, andother info. That determine the state of the CPU.

The program control instructions: Operate with the program counter PC to control the program sequence One uses an index plus displacement addressing

The second uses a relative to PC mode with the 19-bit Y value as the relativeaddress

55

LDL (R22)#150, R5 R5 M[R22] + 150LDL (R22)#0, R5 R5 M[R22]LDL (R0)#500, R5 R5 M[500]


56/65

Instruction set of berkeley RISC I

56

Opcode Operands Register transfer Description

Data manipulation instructions

ADD Rs,S2,Rd Rd Rs + S2 Integer addADDC Rs,S2,Rd Rd Rs + S2 + carry Add with carrySUB Rs,S2,Rd Rd Rs - S2 Integer subtractSUBC Rs,S2,Rd Rd Rs - S2 - carry Subtract with carrySUBR Rs,S2,Rd Rd S2 Rs Subtract reverseSUBCR Rs,S2,Rd Rd S2 Rs carry Subtract with carryAND Rs,S2,Rd Rd Rs S2 ANDOR Rs,S2,Rd Rd Rs V S2 OR

XOR Rs,S2,Rd Rd Rs S2 Exclusive-ORSLL Rs,S2,Rd Rd Rs shifted by S2 Shift-leftSRL Rs,S2,Rd Rd Rs shifted by S2 Shift-right logicalSRA Rs,S2,Rd Rd Rs shifted by S2 Shift-right arithmetic


57/65

Instruction set of berkeley RISC I(cont.)

57


Data transfer instructions

LDL (Rs)s2,Rd Rd M[Rs + S2] Load longLDSU (Rs)s2,Rd Rd M[Rs + S2] Load short unsignedLDSS (Rs)s2,Rd Rd M[Rs + S2] Load short signedLDBU (Rs)s2,Rd Rd M[Rs + S2] Load byte unsignedLDBS (Rs)s2,Rd Rd M[Rs + S2] Load byte signedLDHI Rd,Y Rd Y Load immediate highSTL Rd,(Rs)S2 M[Rs + S2] Rd Store longSTS Rd,(Rs)S2 M[Rs + S2] Rd Store short

STB Rd,(Rs)S2 M[Rs + S2] Rd Store byteGETPSW Rd Rd PSW Load status wordPUTPSW Rd PSW Rd Set status word


58/65

Instruction set of berkeley RISC I(cont.)

58


Program control instructions

JMP COND,S2(Rs) PC Rs + S2 Conditional jump

JMPR COND,Y PC

PC + Y Jump relativeCALL Rd,S2(Rs) Rd PC Call subroutinePC Rs + S2 andCWP CWP 1 change window

CALLR Rd,Y Rd PC Call relativePC PC + Y andCWP CWP 1 change window

RET Rd,S2 PC Rd + S2 Return and

CWP CWP + 1 change windowCALLINT Rd Rd PC Disable interrupts

CWP CWP 1RETINT Rd,S2 PC Rd + S2 Enable interrupt

CWP CWP + 1GTLPC Rd Rd PC Get last PC


59/65

Homework # 4 Q8-36, Q8-37, Q8-39

59


60/65

Data Transfer and Manipulation

60


61/65

Typical data transfer instructions

61

Name Mnemonic

Load LDStore STMove MOVExchange XCHInput INOutput OUT

Push PUSHPop POP


62/65

Eight addressing modes for the load

instruction

62

ModeAssemblyConvention Register transfer

Direct address LD ADR AC M[ADR]Indirect address LD @ADR AC M[M[ADR]]Relative address LD $ADR AC M[PC + ADR]Immediate operand LD #NBR AC NBRIndex addressing LD ADR(X) AC M[ADR + XR]Register LD R1 AC R1

Register indirect LD (R1) AC

M[R1]Autoincrement LD (R1)+ AC M[R1], R1 R1 + 1


63/65

Typical arithmetic instructions

63

Name Mnemonic

Increment INCDecrement DECAdd ADDSubtract SUBMultiply MULDivide DIV

Add with carryADDCSubtract with borrow SUBBNegate (2s complement) NEG


64/65

Typical logical and bit manipulation

instructions

64

Name Mnemonic

Clear CLRComplement COMAND ANDOR ORExclusive-OR XORClear carry CLRC

Set carry SETCComplement carry COMCEnable interrupt EIDisable interrupt DI


65/65

Typical shift instructions

Name Mnemonic

Logical shift right SHRLogical shift left SHLArithmetic shift right SHRAArithmetic shift left SHLARotate right RORRotate left ROL

Rotate right through carry RORCRotate left through carry ROLC

updated chapter 8

Documents