user/peterj/designs/./mrod x v2 wd/channel in/schematic ...peterj/mrod-x/mrod_x... · u2 u3 u4 u5...
TRANSCRIPT
H
I
9
15 16 17
C
14
I
J
G
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1
Name
Size
Dim
K
L
3
Date
Time
of
4
10u Tantalum
AVX TAJB106K010R
J
13
13
10
D
62 107 8
5 15 16 17
C
11 12
D
14
B
11 12
NIKHEF
7 863 4
Page
E
F
E
F
A
H
18
G
V2
7 Feb 2006
1:50:33 pm
tonvr
A3 4 1 4 A
420 x 297 mm
1 6
GOL_MOD_DEF and GOL_TX_Fault
Signal Pull-ups in one
arc242 package
1098 SJ AMSTERDAM NEDERLANDET-Nikhef Amsterdam
B
5
Rev
c
K
1 2
L
A
9
Proj: Proj.No:
18
GND
channel_in
GOL Input
MROD-X 38405
Peter Jansweijer [email protected]
2
2
3
5
4
10u
C1002
R1002180
R1001180
IC1002
NC7SZ00
1
2
3
5
4
GND
C1007
22n
GND
GND4GND4
GND5GND5
GND6GND6
GND7GND7
GND8
GND8
GND9
GND9
GND
IC1003
NC7SZ00
1
GND12
GND13GND13
GND14GND14
GND15GND15
GND16GND16
GND17GND17
GND18
GND18
GND19
GND19
GND2GND2
GND20
GND20
GND3GND3
C1001
SFPT_cage
IC1001
GND1GND1
GND10
GND10
GND11GND11
GND12
4K7
GND
GND
GND
100n
1u
L1002
R1004
D1A
k_r
a_r
GND GND
L1001
1u
100n
C1004
D1A
Fr_LED_Gn
k_g
a_g
Fr_LED_Rd
GND
GND
22n
C1006
C1003
100n
4K7
4K7
R1003R1003
4K7
20
mod_def06
mod_def15
mod_def24
4K7
R1003R1003
Tx_disable3
Tx_fault2
VccR
15
VccT
16
VeeR1
9
VeeR2
10
VeeR3
11
14
VeeR4
VeeT1
1
VeeT2
17
VeeT3
IC1001
HFBR5720
LOS8
RD_n12 S
RD_p13 S
Rate_Sel7
TD_n19 T
TD_p18 T
GOL_XClk GOL_XClk
3V3
3V3
GOL_TX_Fault
GOL_MOD_DEF2
GOL_MOD_DEF1
GOL_MOD_DEF0
3V3
10u
C1005
GOL_RX_LOS
GOL_RXNGOL_LVDSGOL_LVDS
GOL_RXPGOL_LVDSGOL_LVDS
GOL_RATE_SEL
GOL_TXPGOL_LVDSGOL_LVDS
GOL_TX_Disable
ErrLED
UpLED
GOL_TXNGOL_LVDSGOL_LVDS
10 11 12 13
G
H
3 4
G
II
J
Date
2
VCCO_# (3V3) 10 pins each
12
Proj: Proj.No:
Rev
Size
A
Dim
1 3 6 7
7
NIKHEF
1
C
D
Input FPGA Power pins:
c ET-Nikhef Amsterdam
2
16
L
J
K
14
9
Page
A
B
C
K
6 18
E
F
KRUISLAAN 409, 020-592 2000
1715
VCCAUX (2V5) 16 pins
VCCINT (1V5) 32 pins
D
of
15
Time
Name
H
5
E
tonvr
1:50:53 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
Input FPGA
channel_in
8 9 16
8 14 18
11
1098 SJ AMSTERDAM NEDERLAND
L
B
10 13
4 5
F
17
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
GND 124 pins
62
420 x 297 mm
4 1 4 AA3
Y6 Y7 Y8 Y9 Y23 Y24 Y25 Y26 Y27 Y28 Y29Y3 Y30Y4 Y5 Y13 Y14 Y15 Y16 Y17 Y18 Y19Y2 Y20 Y21 Y22
W4 W5 W6 W7 W8 W9
Y1 Y10 Y11 Y12
W21 W22 W23 W24 W25 W26 W27 W28 W29W3 W30W11 W12 W13 W14 W15 W16 W17 W18 W19W2 W20
V3 V30V4 V5 V6 V7 V8 V9
W1 W10
V2 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29V1 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19
U28 U29U3 U30U4 U5 U6 U7 U8 U9 U18 U19U2 U20 U21 U22 U23 U24 U25 U26 U27
T8 T9
U1 U10 U11 U12 U13 U14 U15 U16 U17
T26 T27 T28 T29T3 T30T4 T5 T6 T7 T16 T17 T18 T19T2 T20 T21 T22 T23 T24 T25
R6 R7 R8 R9
T1 T10 T11 T12 T13 T14 T15
R24 R25 R26 R27 R28 R29R3 R30R4 R5 R14 R15 R16 R17 R18 R19R2 R20 R21 R22 R23
P4 P5 P6 P7 P8 P9
R1 R10 R11 R12 R13
P22 P23 P24 P25 P26 P27 P28 P29P3 P30P12 P13 P14 P15 P16 P17 P18 P19P2 P20 P21
N3 N30N4 N5 N6 N7 N8 N9
P1 P10 P11
N20 N21 N22 N23 N24 N25 N26 N27 N28 N29N10 N11 N12 N13 N14 N15 N16 N17 N18 N19N2
M28 M29M3 M30M4 M5 M6 M7 M8 M9
N1
M19M2 M20 M21 M22 M23 M24 M25 M26 M27
L9
M1 M10 M11 M12 M13 M14 M15 M16 M17 M18
L26 L27 L28 L29L3 L30L4 L5 L6 L7 L8 L17 L18 L19L2 L20 L21 L22 L23 L24 L25
K7 K8 K9
L1 L10 L11 L12 L13 L14 L15 L16
K24 K25 K26 K27 K28 K29K3 K30K4 K5 K6 K15 K16 K17 K18 K19K2 K20 K21 K22 K23
J5 J6 J7 J8 J9
K1 K10 K11 K12 K13 K14
J22 J23 J24 J25 J26 J27 J28 J29J3 J30J4 J13 J14 J15 J16 J17 J18 J19J2 J20 J21
H30H4 H5 H6 H7 H8 H9
J1 J10 J11 J12
H20 H21 H22 H23 H24 H25 H26 H27 H28 H29H3 H11 H12 H13 H14 H15 H16 H17 H18 H19H2
G29G3 G30G4 G5 G6 G7 G8 G9
H1 H10
G19G2 G20 G21 G22 G23 G24 G25 G26 G27 G28G1 G10 G11 G12 G13 G14 G15 G16 G17 G18
F27 F28 F29F3 F30F4 F5 F6 F7 F8 F9 F17 F18 F19F2 F20 F21 F22 F23 F24 F25 F26
E8 E9
F1 F10 F11 F12 F13 F14 F15 F16
E25 E26 E27 E28 E29E3 E30E4 E5 E6 E7 E15 E16 E17 E18 E19E2 E20 E21 E22 E23 E24
D6 D7 D8 D9
E1 E10 E11 E12 E13 E14
D23 D24 D25 D26 D27 D28 D29D3 D30D4 D5 D13 D14 D15 D16 D17 D18 D19D2 D20 D21 D22
C4 C5 C6 C7 C8 C9
D1 D10 D11 D12
C21 C22 C23 C24 C25 C26 C27 C28 C29C3 C30C11 C12 C13 C14 C15 C16 C17 C18 C19C2 C20
B3 B30B4 B5 B6 B7 B8 B9
C1 C10
B2 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29B1 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19
AK27 AK28 AK29AK3 AK4 AK5 AK6 AK7 AK8 AK9
T
AK18
T
AK19
S
AK2 AK20
S
AK21 AK22 AK23 AK24 AK25 AK26
AJ8 AJ9
AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17
AJ25 AJ26 AJ27 AJ28 AJ29AJ3 AJ30AJ4 AJ5 AJ6 AJ7 AJ15 AJ16 AJ17 AJ18 AJ19AJ2 AJ20 AJ21 AJ22 AJ23 AJ24
AH6 AH7 AH8 AH9
AJ1 AJ10 AJ11 AJ12 AJ13 AJ14
AH23 AH24 AH25 AH26 AH27 AH28 AH29AH3 AH30AH4 AH5 AH13 AH14 AH15 AH16 AH17 AH18 AH19AH2 AH20 AH21 AH22
AG4 AG5 AG6 AG7 AG8 AG9
AH1 AH10 AH11 AH12
AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29AG3 AG30AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19AG2 AG20
AF3 AF30AF4 AF5 AF6 AF7 AF8 AF9
AG1 AG10
AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29AF1 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19
AE28 AE29AE3 AE30AE4 AE5 AE6 AE7 AE8 AE9 AE18 AE19AE2 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27
AD8 AD9
AE1 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17
AD26 AD27 AD28 AD29AD3 AD30AD4 AD5 AD6 AD7 AD16 AD17 AD18 AD19AD2 AD20 AD21 AD22 AD23 AD24 AD25
AC6 AC7 AC8 AC9
AD1 AD10 AD11 AD12 AD13 AD14 AD15
AC24 AC25 AC26 AC27 AC28 AC29AC3 AC30AC4 AC5 AC14 AC15 AC16 AC17 AC18 AC19AC2 AC20 AC21 AC22 AC23
AB4 AB5 AB6 AB7 AB8 AB9
AC1 AC10 AC11 AC12 AC13
AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29AB3 AB30AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19AB2 AB20 AB21
AA3 AA30AA4 AA5 AA6 AA7 AA8 AA9
AB1 AB10 AB11
AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19AA2
A27 A28 A29A3 A4 A5 A6 A7 A8 A9
AA1
T
A19
S
A2 A20
S
A21 A22 A23 A24 A25 A26
XC2VP7FF896
IC1004
A10 A11 A12 A13 A14 A15 A16 A17
T
A18
DP_GOL_RX1A
GOL_RXNVRP_2VCCAUX
DMAR_n
BufR_W_n
BufA(18)
SMBClkSMBDataT_Alert_n
Rst_n
GOL_LVDS
GOL_LVDS
DP_GOL_TX1A
GOL_TXN
GOL_LVDS
GOL_LVDS
DP_GOL_TX1A
GOL_TXP
GOL_LVDS
GOL_LVDS
DP_GOL_RX1A
GOL_RXP
GOL_LVDSGOL_LVDS
SDRAM_A(4)SDRAM_A(5)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(16)Adr(15)Adr(14)Adr(13)Adr(12)Adr(11)
VCCAUXVRP_7LEDs(0)GNDVCCAUXVCCAUXGND
Adr(6)Adr(5)Adr(4)GND
SDRAM_A(6)SDRAM_A(7)SDRAM_A(8)SDRAM_A(9)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5IRQ2_nData(3)VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(10)Adr(9)Adr(8)Adr(7)
SDRAM_DQ(30)SDRAM_DQ(31)SDRAM_DQM(3)SDRAM_A(3)
Data(10)Data(15)D1PWRDWN_BAdr(3)Adr(2)
GNDSDRAM_CKESDRAM_A(12)SDRAM_DQM(1)M1M2D7TestCon(10)TestCon(9)TestCon(8)IRQ1_nData(2)Data(9)Data(11)Data(16)D0DONECCLK
Data(19)Data(23)INIT_BGND
GNDGNDEmptyData(0)Data(6)GNDData(14)Data(20)Data(24)Data(25)GND
SDRAM_DQ(8)SDRAM_DQ(9)M0D6TestCon(13)TestCon(12)TestCon(11)IRQ0_nData(1)Data(7)Data(8)
VRN_5GNDTTC_n(5)GNDChaBusyLHC_ClkSharcWr_nData(4)GNDData(12)GNDVRP_4D2DOUTAdr(1)GNDAdr(0)Data(31)Data(30)
GNDRDWR_BTTC_n(4)TTC_n(6)TTC_n(7)SDRAM_CLKSDRAM_CLKinData(5)Data(13)
GNDGNDA21D4VRP_5TTC_n(3)GNDA19GNDClkSharcRd_nGNDGNDA18Data(18)VRN_4D3GNDA16Data(29)Data(28)GNDData(27)Data(26)
SDRAM_DQ(10)SDRAM_DQ(11)SDRAM_DQ(12)GNDSDRAM_DQ(13)CS_BD5
AVCCAUXTX19VTRXPAD19AVCCAUXRX19Clkx2Rocket_XClkVTTXPAD18AVCCAUXTX18VTRXPAD18AVCCAUXRX18Data(17)Data(22)VTTXPAD16AVCCAUXTX16VTRXPAD16AVCCAUXRX16VRP_3GNDVCCAUX
SDRAM_DQ(14)SDRAM_DQ(15)
GND
ROCKET_LVDS
Rocket_TXN
ROCKET_LVDS
Rocket_TXP
ROCKET_LVDS
Rocket_RXP
ROCKET_LVDS
Rocket_RXNVCCAUXVCCAUXGNDData(21)VRN_3VCCAUX
VCCAUXGNDVRP_6VTTXPAD21AVCCAUXTX21VTRXPAD21AVCCAUXRX21TTC_n(1)TTC_n(2)VTTXPAD19
VTTXPAD6AVCCAUXTX6VTRXPAD6AVCCAUXRX6GOL_XClkVTTXPAD7AVCCAUXTX7VTRXPAD7AVCCAUXRX7VTTXPAD9AVCCAUXTX9VTRXPAD9AVCCAUXRX9VRN_2GNDVCCAUX
VCCAUXVRN_6TTC_n(0)
BufCE_nGNDBufA(7)BufA(6)GNDA4LEDs(3)LEDs(2)GNDA6UpLEDGNDGNDGNDA7GNDA9GND
VCCAUXGNDVRN_7VTTXPAD4AVCCAUXTX4VTRXPAD4AVCCAUXRX4LEDs(1)
GOL_TX_FaultVRP_1VRN_1GND
BufD(33)GNDBufD(16)DXNChaID(0)ChaID(1)GNDGOL_MOD_DEF0GOL_MOD_DEF1GNDErrLEDGOL_TX_DisableGOL_RX_LOSGNDGNDGND
BufA(19)
PROG_BTestCon(2)TestCon(3)TestCon(4)TestCon(5)TestCon(6)TCK
TDIGNDTestCon(0)TestCon(1)GNDGNDGNDTDO
GNDVRP_0VRN_0ChaID(2)GOL_RATE_SELGOL_MOD_DEF2
BufD(25)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2TestCon(14)
GNDBufD(19)DXPHSWAP_ENTestCon(7)TestCon(15)TMSVBATTGND
BufD(17)BufD(18)
BufD(26)BufD(27)BufD(28)BufD(29)BufD(30)BufD(31)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2
BufD(20)BufD(21)BufD(22)BufD(23)BufD(24)
GNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufD(32)BufA(5)GNDBufA(4)BufA(3)GNDVCCO_7VCCO_7GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_2VCCO_2GNDGND
VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufA(2)BufA(1)BufA(0)BufA(10)BufA(11)BufA(12)BufA(13)BufA(14)VCCO_7VCCO_7VCCINTGNDGNDGND
BufD(11)BufD(12)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2GND
BufA(15)BufA(16)BufD(35)BufD(0)BufD(1)BufD(2)BufD(3)BufD(4)VCCO_7VCCO_7
BufA(9)BufA(8)BufA(17)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCAUX
BufD(5)BufD(6)BufD(7)BufD(8)BufD(9)GNDBufD(10)
SDRAM_DQ(4)SDRAM_DQ(5)SDRAM_DQ(6)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3Spare(0)Spare(1)Spare(2)Spare(3)Spare(4)VCCAUX
VCCAUXBufD(13)BufD(14)BufD(15)BufD(34)
SDRAM_RAS_nGNDSDRAM_CS_nSDRAM_A(11)SDRAM_BA(0)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3GND
VCCAUXSDRAM_DQ(0)SDRAM_DQ(1)SDRAM_DQ(2)SDRAM_DQ(3)
SDRAM_A(0)SDRAM_A(1)SDRAM_A(2)SDRAM_DQM(2)SDRAM_DQ(16)SDRAM_DQ(17)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3A21_Select
SDRAM_DQ(7)SDRAM_DQM(0)SDRAM_WE_nSDRAM_CAS_n
SDRAM_DQ(21)SDRAM_DQ(22)SDRAM_DQ(23)SDRAM_DQ(24)SDRAM_DQ(25)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3MS3_nMS2_nMS1_nMS0_nAdr(21)
SDRAM_BA(1)SDRAM_A(10)
SDRAM_DQ(26)SDRAM_DQ(27)GNDSDRAM_DQ(28)SDRAM_DQ(29)GNDVCCO_6VCCO_6GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_3VCCO_3GNDAdr(20)Adr(19)GNDAdr(18)Adr(17)
SDRAM_DQ(18)SDRAM_DQ(19)SDRAM_DQ(20)
XC2VP7/20 VCCINT Decoupling Capacitors
FYSICA EN HOGE ENERGIE-FYSICA
IccINT = 600 mA
Dim
A
B
C
18
A
173
K
13
Date
15 16 17 18
AVX TAJB476K010R
11
IccAUX = 250 mA (min)
ET-Nikhef Amsterdam
VCCAUX and VCCO can ramp up at any rate
3
Proj.No:
1
4
AVX TAJB476K010R
2
D
Rev
L
E
F
For Xilinx Virtex-II Pro, power supplies
can be turned on in any sequence.
8
Proj:
7
6 7
VCCINT Ramp rate 200 us min. and 50 ms max.
NIKHEFof
G
14
Pagec
K
L
Min. Power-On Current XC2VP20
Min. Power-On Current XC2VP20
G
H
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Name
Size
9 10 11 12 13
14
I
J
10
B
E
5
16
XC2VP7/20 VCCAUX Decoupling Capacitors
NATIONAAL INSTITUUT VOOR KERN-
Power Inputs
1:51:34 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
3 6
9 12
4
1
15
AVX TAJB476K010R
AVX TAJB476K010R
8
F
2
C
D
All GND nets on the FPGA need
to be connected to golbal GROUND.
6
5
Time
J
I
H
22n
C1046
GND
channel_in
Input FPGA Power Supply Decoupling
MROD-X 38405
Peter Jansweijer [email protected]
2V2
7 Feb 2006
680p
C1040
GND
47u
C1097
GND
680p
C1009
GND
GND
C1045
22n
GND
C1096
47u
22n
C1083
GND
C1084
22n
GND
C1050
22n 22n
C1052
GND
C1090
100n
GND
100n
C1095
GND
GND
680p
C1067
GND
GND
680p
C1044
GNDC1082
680p
680p
22n
C1079
GND
680p680p
C1071
GND
GND
C1008
GND
680p
C1087
C1072
GND
C1014
680p
C1041
680p
22n
C1047
22n
C1059
GND
C1039
680p
GND
GND
C1053
100n
C1055
47u
GND
GND
GND
GND
C1018
680p
680p
C1061
GND
GND
22n
C1024
22n
C1069
GND
GND
C1062
680p
GND
GND
GND
C1025
22n
C1043
680p
GND
C1051
22n
GNDGND
C1048
22n
C1023
22n
GND
680p
C1077
GND
GND GND
GND
C1022
22n
47u
C1035
C1016
680p
GND
C1019
22n
GND
680p
C1081
GND
100n
C1075
GND
GND
C1033
C1086
680p
C1068
22n
22n
C1049
C1092
680p
GND
100n
GND
GND
C1076
680p
GND
GND
680p
C1042
C1078
22n
GND
C1036
47u
C1030
100n
680p
C1017
GND
C1066
680p
GND
GND
GND
22n
C1073
GND
C1064
22n
GND
C1094
22n
GND
C1037
680p
C1028
22n
GND
GND
680p
C1015
22n
C1020
C1070
100n
680p
C1013
680p
C1091
GND
GND
100n
C1054
GND
100n
C1085
C1080
100n
680p
C1038
GNDGND
C1060
100n
GND
22n
C1021
C1058
22n
GND
100n
C1065
GND
C1012
680p
GND
GND
GND
GND
C1074
22n
C1056
680p
22n
C1093
GND
C1010
680p
22n
C1063
680p
C1057
GND
GND
C1088
22n
GND
680p
C1011
GND
GND
GND
GND
22n
C1089
C1034
100n
GND
100n
C1029
GND
GND
C1031
100n
GND
100n
C1032
22n
C1026
GND
22n
C1027
GND
1V5POWER_NET_TYPE
VCCINT
VCCINT
2V5POWER_NET_TYPE
VCCAUX
VCCAUX
POWER_NET_TYPE
3V33V3
3V3
POWER_NET_TYPE
GND
GND
GND
GND
VCCO_0
VCCO_1
VCCO_2
VCCO_4
VCCO_5
VCCO_6
VCCO_7
VCCO_3
2V5 @ 1,5A
Proj:
97
c ET-Nikhef Amsterdam
142
Buffer Memory interface
L
AVX TAJB476K010R
=> MGT Power (estimated 31 + 49 = 80 mA)
G
K
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
10
Series Termination for
3 5 131210
NIKHEF
Name
Series Termination for
Date
H
2 15
KRUISLAAN 409, 020-592 2000
16
Not (yet) used
H
General purpose
1
Size
PAD6 connected to GOL
PAD19 connected to MROD-Out FPGA
DC coupled
4
Not (yet) used
Series Termination for
L
1
AC coupled
Note: VT1V8_MGT is common to all MROD-Ins
11 14
General purpose
G
9
17 18
A
15
of
E
F
4
=> MGT TX (RX) Termination (estimated 11 mA)
1098 SJ AMSTERDAM NEDERLAND
Sharc Databus
Time
18
B
C C
J
I
Proj.No:
Series Termination for
3
D
6
6
13
SDRAM interface
B
K
Series Termination for
A
D
Series Termination for
I
J
Series Termination for
E
16
11 12
7
Sharc Addressbus
Series Termination for
17
Rev
8
channel_in
Input FPGA MGT Pwr Decoupling, Termination
MROD-X 38405
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:01 pm
tonvr
A3 4 1 4 A
420 x 297 mm
4 6
AVX TAJB476K010R
5
F
Page
Dim
8
GND
R1028
1M
1u
L1004
GND
L1018
1u
R1011
47
47
R1009
GND
L1019
1u
L1033
1u
GND GND
L1014
1u
C1100
100n
GND
2%
100 R1006
1u
L1021
GND
GND
GND
GND
GNDGND
GND
GND
L1022
1u
GND
GND
GND
220n
C1111
L1029
1u
C1101
47u
C1113
220n
GND
GND
GND GND
GND
R1009
47
GNDGND
GND
GND
C1115
220n
GND
GND
GND
GND2TAB
2IN OUT
4
5S_A
1_SHDN
47
R1009
0E01u
L1012
LT1963A_DD
IC1005
3GND1
GND
R1011
47
R1029
R1011
47
C1131
220n
GND
220n
C1104
C1129
220n
GND
GND
GND
C1133
220n
GND
GND
GND
GND
GND GND
L1025
1u
L1027
1u
C1118
GND
GND
L1009
1u
R1007
95E3
2%
220n
R1009
47
L1017
1u
GND GND
GND
C1108
220n
GND
1u
L1007
R1010
47
C1105
220n
C1123
220n
R1005
4K7
L1031
1u
1u
220n
C1116
C1107
220n
C1125
220n
C1124
220n
GND
L1026
L1010
1u
220n
C1120
GND
C1110
220n
C1103
220n
GND
C1109
220n
220n
C1102
GND
220n
C1112
C1127
220n
GND
47
R1008
C1098
47u
GND
R1008
47
C1119
220n
GND
C1117
220n
L1024
1u
L1020
1u
L1016
1u
L1015
1u1u
L1013
C1106
220n
R1008
47
1u
L1023
1u
GND
1u
L1011
C1121
220n
L1005
1u
L1030
C1099
100n
R1010
47
R1008
47
L1006
1u
C1126
220n
1u
L1003
L1032
1u1u
C1122
220n
R1011
47
L1034
1u
L1008
1u
L1028
R1010
47
47
R1010
C1114
220n
C1128
220n
GND
C1132
220n
VTRXPAD7VTRXPAD6VTRXPAD4
VT2V5_MGT
VT2V5_MGT
VT1V8_MGT
AVCCAUXTX4
VTTXPAD4
VRN_7
VRP_7
C1130
220n
VRN_4
3V3
VRP_4
VRN_5
3V3
VRP_5
VRN_6
3V3
VRP_6
3V3
VCCA_MGTPOWER_NET_TYPE
3V3
VTRXPAD9
VTRXPAD19 VTRXPAD18 VTRXPAD16
VRN_0
3V3
VRP_0
VRN_1
3V3
VRP_1
VRN_2
3V3
VRP_2
VRN_3
3V3
VRP_3
AVCCAUXTX18 AVCCAUXTX16
AVCCAUXRX16AVCCAUXRX18AVCCAUXRX19AVCCAUXRX21
VTTXPAD21 VTTXPAD19 VTTXPAD18 VTTXPAD16
VTRXPAD21
AVCCAUXTX9
AVCCAUXRX9AVCCAUXRX7AVCCAUXRX6AVCCAUXRX4
VTTXPAD6 VTTXPAD7 VTTXPAD9
AVCCAUXTX21 AVCCAUXTX19
POWER_NET_TYPE
VT2V5_MGT
VCCA_MGT
VCCA_MGT
GNDA4 GNDA6 GNDA7 GNDA9
GNDA21 GNDA19 GNDA18 GNDA16
AVCCAUXTX6 AVCCAUXTX7
18
E
5
F
B
C
7
c ET-Nikhef Amsterdam
Proj.No:
Date
Time
9
H
6
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
7 17
SDRAM_A(12) is not connected
L
1
J
11
A
of
G
NIKHEF
8
Proj:
K
8
2
16
I
163 5 14
Rev
E
17
9
18
1 10
H
4
Size
15
15
C
D
J
K
L
A
G
4
D
12
I
10
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:29 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
5 6
11 12
KRUISLAAN 409, 020-592 2000
13
2
1098 SJ AMSTERDAM NEDERLAND
6
F
Dim
Page
B
3
Name
13 14
8
GND
GND
channel_in
Buffer Memory (ZBT and SDRAM)
MROD-X 38405
9
21
22
32
GND
GND
4 1
GND
GND
8
C1142
22n
4K7
R1012
4K7
R1012
C1159
22n
4K7
R1012
C1141
22n
R1012
4K7
31
8
9
10
C1146
100n
13
GND
GND
GND
0
GND
GND
25
GND
C1144
22n
GND
6
3
GND
0
23
GND
GND
16
18
GNDGND
1
GND
2
13
15
GND GND
GND
29
30
20
9
GND
15
5
28
GND
6
7
C1162
100n
3
4
GND
30
11
GND
C1148
100n
GND
GND
GND
3 2
14
15
GND
14
19
12
GND
24
GND
GND
3
26
GND
9
16
33
7
2
GND
GND
GND
GND
GND
GND
GND
0
GND
7
16
GND
25
GND
11
10
11
0
12
4
31
27
24
19
GND
GND
35
GND
2
3
GND
17
18
VssQ438
VssQ546
VssQ652
78VssQ7
VssQ884
18_CAS
20_CS
_RAS19
17_WE
C1134
22n
49
VddQ655
VddQ775
81VddQ8
Vss144
Vss258
Vss372
86Vss4
VssQ16
VssQ212
32VssQ3
NC570
NC673
Vdd11
Vdd215
Vdd329
Vdd443
VddQ13
VddQ29
VddQ335
VddQ441
VddQ5
DQ713
DQ874
DQ976
DQM016 71
DQM1
DQM228
DQM359
NC114
NC230
NC357
69NC4
47
DQ2648
DQ2750
DQ2851
53DQ29
DQ37
DQ3054
56DQ31
DQ48
DQ510
11DQ6
85
DQ1631
DQ1733
DQ1834
DQ1936
DQ25
DQ2037
DQ2139
DQ2240
DQ2342
DQ2445
DQ25
23BA1
CKE67
CLK68
DQ02
4DQ1
DQ1077
DQ1179
80DQ12
DQ1382
DQ1483
DQ15
24
A1121
A227
A360
A461
A562
A663
A764
A865
A966
BA022
100n
27
28
MT48LC8M32B2
IC1007
A025
A126
A1010
5
6
7
C1152
22n
C1147
C1135
22n
1
2
GND
GND
GND
1
C1157
22n
GND
14
17
10
1
11
C1165
100n
C1156
22n
0
13
100n
C1164
C1161
22n
_BW4
_CE1
98
92
_CE2
_CEN
87
31
_LBO
_OE
86
C1158
22n
12
21VSS4
26VSS5
40
VSS6
55VSS7
VSS860
67VSS9
64ZZ
_BW1
93
94
_BW2
_BW3
95
96
16VDD5
20VDD6
27VDD7
VDD8
41
54VDD9
5VSS1
VSS1071
76VSS11
90
VSS12
VSS210
VSS317
VDD14
61VDD10
VDD1165
66VDD12
VDD1370
VDD1477
VDD15
91
11VDD2
VDD314
15VDD4
68IO8
69IO9
IOp151
IOp280
IOp31
IOp430
R_W
88
TCK
43
39
TDI
42
TDO
TMS
38
22
IO2723
24IO28
IO2925
57IO3
28IO30
29IO31
IO458
59IO5
IO662
IO763
IO16
IO173
6IO18
IO197
IO256
IO208
9IO21
12IO22
IO2313
18IO24
19IO25
IO2697
CE2
CLK
89
52IO0
IO153
72IO10
IO1173
74IO12
IO1375
78IO14
79IO15
2
83
84
A18
A2
35
A3
34
33
A4
32
A5
A6
100
99
A7
82
A8
81
A9
85
ADV_LD
IDT71V65603S100PF
IC1006
A0
37
36
A1
A10
44
A11
45
A12
46
A13
47
48
A14
A15
49
50
A16
A17
22n 22n
C1154
26
8
C1140
22n 22n
C1145
GND
C1138C1137
22n
5
22n
C1136
C1149
100n
GND
C1160
22n
C1143
C1153
22n
20
21
C1163
100n
22
0
4
5
22n
19
34
17
GND
6
GND
GND
GND
29
GND
23
18
22n
1
GND
22n 22n
C1155C1139
22n
C1150
BufCE_n SDRAM_CLKZ50_NET_TYPE
Z50_NET_TYPE
SDRAM_CLKin
SDRAM_WE_n
SDRAM_RAS_n
SDRAM_CAS_n
C1151
3V3
Clkx2
BufR_W_n
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
SDRAM_CS_n
SDRAM_DQ(31:0)
SDRAM_DQM(3:0)
SDRAM_BA(1:0)
SDRAM_A(12:0)
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
BufD(35:0)
BufA(19:0)
3V3
3V3
3V3
3V3
3V3
SDRAM_CKE
c
3
7
7
Answer Record #18562
14
Input Channel ID bits
10 17
K
GND
E
H
5
configuration. See Xilinx PROM Errata,
Testpoints force Spare
lines to be accessible.I
18
arc242 package
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
L
FPGA JTAG Signals
12
Temperature sensing diode
6
0 1 1 Master SelectMAP
12
0
It may be necessary to use Master SelectMap
3
I
HSWAP_EN = ’0’ => User IOs have pull-up
A
E
CLK
FPGA Configuration Signals
2
Default configuration mode will be Slave SelectMAP.
17
16
Connector
1
J J
Page
NATIONAAL INSTITUUT VOOR KERN-
H
PWRDWN_B is unsupported (should be pulled high)
Optinal Test
G
8
Clock Signals
16
chains where the same bitstream is loaded into multiple devices.
11
1098 SJ AMSTERDAM NEDERLAND
1
F
is no possibility for readback (RDWR_B = ’0’)
8 Input channels are loaded in parallel so there
Time
Dim
2
Proj:
9
to Master SelectMap and all other MROD-In FPGAs
to Slave SelectMap.
B
Size
Rocket IO Signals
15
Proj.No:
Rev
1 0 1 Boundary scan
’On’ = ’1’, ’Off’ = ’0’
13 18
Note: FCC_SelectMAP = 50 MHz so CCLK < 50 MHz!
M2 M1 M0
1 1 0 Slave SelectMAP (default)
6
D
14
-> Slave SlectMAP programming Mode -> BUSY.
15
13
Date
Name
See "Virtex-II Pro FPGA User Guide", Chapter 4 -> Configuration
F
FPGA Control signals
Cand each CS_B = ’0’
A
of
154
8
C
9
11
In this case set MROD-Out FPGA and one MROD-In FPGA
TTC Signals
NIKHEF
Pull-Ups
3
resistors during configuration
ET-Nikhef Amsterdam
K
5
4
B
2
1
D
L
G
10
66
420 x 297 mm
4 1 4 AA3
Ton van Reen
1:53:04 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405 MROD-X
Input FPGA Auxiliary Connections
channel_in
VBATT is decriptor key memory backup supply
Sharc Signals Frontend to Backend
DOUT is BUSY in SelectMAP mode and BUSY should NOT be used for parallel
1
0
6
GND
15
9
Fiducial1002
22n
C1168
NC7SZ08
IC1012
1
2
3
5
4
2n2
C1171
J1A 2
GND
2
U3_1A
U2_1A
1
2
3
5
4
0E0
R1026
NC7SZ00
IC1009
1
2
3
5
4
NC7SZ00
IC1011
C1166
22n
R1027
1K0
Fiducial1001
J1A 12
GND
Sw1A
17
180
R1013
GND
3
2
0
J1A 15
12
J1A
NC7SZ00
IC1010
1
2
3
5
4
SMD_LED_Red
D1002
J1A 16
GND
J1A 5
GND
GND
13
4
3
0
J1A 4
J1A 18
J1A 19
1K0
R1019
3
GND
GND
5
20
R10231K0
U1_1A
J1A
J1A 13
GND
1
2
J1A
R1015
J1A 8
4K7
R1025
180
R1024
D1004
SMD_LED_Green
180
R1025
Sw1A
D1001
SMD_LED_Red
ADD12
4DXN
5DXP
GND
3
SMBCLK8
SMBDATA9
VCC
6
10_ALERT
_STBY7
4K7
6
100n
C1172
GND
IC1013
MAX1618
1ADD0
11R1025
4K7
J1A
R10181K0
J1A 10
J1A
J1A 1
GND
SMD_LED_Green
D1003
Sw1A
J1A 7
R1020
NC7SZ00
IC1008
1
2
3
5
4
U4_1A
14
1K0
7
GND
10
4
R10224K7
6
5
GND
180
R1016 8
1
14
U0_1A
C1170
22n
R1021
180
R1014
J1A
GND
1K0
22n
C1167
7
GND
11GND
3
1K0
R1017
GND
GND
4
Spare(4:0)
J1A 9
22n
C1169
GND
CS_B
VCCAUXPWRDWN_B
CCLKCCLK
HSWAP_EN
PROG_BPROG_B
DXP
DXN
SMBClk
3V3
M2 M1
VCCAUX
M0
Spare(4:0)
Clk
TestCon(15:0)
3V3
3V3
3V3
3V3
T_Alert_n
SMBData
DOUT
INIT_BINIT_B
DONEDONE
D7
D6
D5
D4
D3
D2
D1
D0 D(7:0)
RDWR_B
3V3
ChaBusy ChaBusy
TTC_n(7:0)TTC_n(7:0)
ChaID(2:0)ChaID(2:0)
TCK
TDO
FPGA_TCK
FPGA_TMS
TDI FPGA_TDI
FPGA_TDO
Clk Clk
Clkx2Clkx2
LHC_ClkLHC_Clk
Rocket_XClk Rocket_XClk
Adr(21:0)Adr(21:0)
IRQ1_n IRQ1_n
IRQ2_n IRQ2_n
Empty Empty
DMAR_n DMAR_n
Rocket_RXPRocket_RXP
Rocket_RXN Rocket_RXN
Rocket_TXPRocket_TXP
Rocket_TXNRocket_TXN
A21_SelectA21_Select
TMS
3V3
LEDs(0)
LEDs(1)
LEDs(2)
LEDs(3)
General_Rst_n
Channel_Rst_n
Rst_n
VBATT
IRQ0_n IRQ0_n
Data(31:0) Data(31:0)
MS0_n MS0_n
MS1_nMS1_n
MS2_n MS2_n
MS3_nMS3_n
SharcRd_nSharcRd_n
SharcWr_n SharcWr_n
H
I
9
15 16 17
C
14
I
J
G
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1
Name
Size
Dim
K
L
3
Date
Time
of
4
10u Tantalum
AVX TAJB106K010R
J
13
13
10
D
62 107 8
5 15 16 17
C
11 12
D
14
B
11 12
NIKHEF
7 863 4
Page
E
F
E
F
A
H
18
G
V2
7 Feb 2006
1:50:33 pm
tonvr
A3 4 1 4 A
420 x 297 mm
1 6
GOL_MOD_DEF and GOL_TX_Fault
Signal Pull-ups in one
arc242 package
1098 SJ AMSTERDAM NEDERLANDET-Nikhef Amsterdam
B
5
Rev
c
K
1 2
L
A
9
Proj: Proj.No:
18
GND
channel_in
GOL Input
MROD-X 38405
Peter Jansweijer [email protected]
2
2
3
5
4
10u
C2002
R2002180
R2001180
IC2002
NC7SZ00
1
2
3
5
4
GND
C2007
22n
GND
GND4GND4
GND5GND5
GND6GND6
GND7GND7
GND8
GND8
GND9
GND9
GND
IC2003
NC7SZ00
1
GND12
GND13GND13
GND14GND14
GND15GND15
GND16GND16
GND17GND17
GND18
GND18
GND19
GND19
GND2GND2
GND20
GND20
GND3GND3
C2001
SFPT_cage
IC2001
GND1GND1
GND10
GND10
GND11GND11
GND12
4K7
GND
GND
GND
100n
1u
L2002
R2004
D1B
k_r
a_r
GND GND
L2001
1u
100n
C2004
D1B
Fr_LED_Gn
k_g
a_g
Fr_LED_Rd
GND
GND
22n
C2006
C2003
100n
4K7
4K7
R2003R2003
4K7
20
mod_def06
mod_def15
mod_def24
4K7
R2003R2003
Tx_disable3
Tx_fault2
VccR
15
VccT
16
VeeR1
9
VeeR2
10
VeeR3
11
14
VeeR4
VeeT1
1
VeeT2
17
VeeT3
IC2001
HFBR5720
LOS8
RD_n12 S
RD_p13 S
Rate_Sel7
TD_n19 T
TD_p18 T
GOL_XClk GOL_XClk
3V3
3V3
GOL_TX_Fault
GOL_MOD_DEF2
GOL_MOD_DEF1
GOL_MOD_DEF0
3V3
10u
C2005
GOL_RX_LOS
GOL_RXNGOL_LVDSGOL_LVDS
GOL_RXPGOL_LVDSGOL_LVDS
GOL_RATE_SEL
GOL_TXPGOL_LVDSGOL_LVDS
GOL_TX_Disable
ErrLED
UpLED
GOL_TXNGOL_LVDSGOL_LVDS
10 11 12 13
G
H
3 4
G
II
J
Date
2
VCCO_# (3V3) 10 pins each
12
Proj: Proj.No:
Rev
Size
A
Dim
1 3 6 7
7
NIKHEF
1
C
D
Input FPGA Power pins:
c ET-Nikhef Amsterdam
2
16
L
J
K
14
9
Page
A
B
C
K
6 18
E
F
KRUISLAAN 409, 020-592 2000
1715
VCCAUX (2V5) 16 pins
VCCINT (1V5) 32 pins
D
of
15
Time
Name
H
5
E
tonvr
1:50:53 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
Input FPGA
channel_in
8 9 16
8 14 18
11
1098 SJ AMSTERDAM NEDERLAND
L
B
10 13
4 5
F
17
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
GND 124 pins
62
420 x 297 mm
4 1 4 AA3
Y6 Y7 Y8 Y9 Y23 Y24 Y25 Y26 Y27 Y28 Y29Y3 Y30Y4 Y5 Y13 Y14 Y15 Y16 Y17 Y18 Y19Y2 Y20 Y21 Y22
W4 W5 W6 W7 W8 W9
Y1 Y10 Y11 Y12
W21 W22 W23 W24 W25 W26 W27 W28 W29W3 W30W11 W12 W13 W14 W15 W16 W17 W18 W19W2 W20
V3 V30V4 V5 V6 V7 V8 V9
W1 W10
V2 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29V1 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19
U28 U29U3 U30U4 U5 U6 U7 U8 U9 U18 U19U2 U20 U21 U22 U23 U24 U25 U26 U27
T8 T9
U1 U10 U11 U12 U13 U14 U15 U16 U17
T26 T27 T28 T29T3 T30T4 T5 T6 T7 T16 T17 T18 T19T2 T20 T21 T22 T23 T24 T25
R6 R7 R8 R9
T1 T10 T11 T12 T13 T14 T15
R24 R25 R26 R27 R28 R29R3 R30R4 R5 R14 R15 R16 R17 R18 R19R2 R20 R21 R22 R23
P4 P5 P6 P7 P8 P9
R1 R10 R11 R12 R13
P22 P23 P24 P25 P26 P27 P28 P29P3 P30P12 P13 P14 P15 P16 P17 P18 P19P2 P20 P21
N3 N30N4 N5 N6 N7 N8 N9
P1 P10 P11
N20 N21 N22 N23 N24 N25 N26 N27 N28 N29N10 N11 N12 N13 N14 N15 N16 N17 N18 N19N2
M28 M29M3 M30M4 M5 M6 M7 M8 M9
N1
M19M2 M20 M21 M22 M23 M24 M25 M26 M27
L9
M1 M10 M11 M12 M13 M14 M15 M16 M17 M18
L26 L27 L28 L29L3 L30L4 L5 L6 L7 L8 L17 L18 L19L2 L20 L21 L22 L23 L24 L25
K7 K8 K9
L1 L10 L11 L12 L13 L14 L15 L16
K24 K25 K26 K27 K28 K29K3 K30K4 K5 K6 K15 K16 K17 K18 K19K2 K20 K21 K22 K23
J5 J6 J7 J8 J9
K1 K10 K11 K12 K13 K14
J22 J23 J24 J25 J26 J27 J28 J29J3 J30J4 J13 J14 J15 J16 J17 J18 J19J2 J20 J21
H30H4 H5 H6 H7 H8 H9
J1 J10 J11 J12
H20 H21 H22 H23 H24 H25 H26 H27 H28 H29H3 H11 H12 H13 H14 H15 H16 H17 H18 H19H2
G29G3 G30G4 G5 G6 G7 G8 G9
H1 H10
G19G2 G20 G21 G22 G23 G24 G25 G26 G27 G28G1 G10 G11 G12 G13 G14 G15 G16 G17 G18
F27 F28 F29F3 F30F4 F5 F6 F7 F8 F9 F17 F18 F19F2 F20 F21 F22 F23 F24 F25 F26
E8 E9
F1 F10 F11 F12 F13 F14 F15 F16
E25 E26 E27 E28 E29E3 E30E4 E5 E6 E7 E15 E16 E17 E18 E19E2 E20 E21 E22 E23 E24
D6 D7 D8 D9
E1 E10 E11 E12 E13 E14
D23 D24 D25 D26 D27 D28 D29D3 D30D4 D5 D13 D14 D15 D16 D17 D18 D19D2 D20 D21 D22
C4 C5 C6 C7 C8 C9
D1 D10 D11 D12
C21 C22 C23 C24 C25 C26 C27 C28 C29C3 C30C11 C12 C13 C14 C15 C16 C17 C18 C19C2 C20
B3 B30B4 B5 B6 B7 B8 B9
C1 C10
B2 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29B1 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19
AK27 AK28 AK29AK3 AK4 AK5 AK6 AK7 AK8 AK9
T
AK18
T
AK19
S
AK2 AK20
S
AK21 AK22 AK23 AK24 AK25 AK26
AJ8 AJ9
AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17
AJ25 AJ26 AJ27 AJ28 AJ29AJ3 AJ30AJ4 AJ5 AJ6 AJ7 AJ15 AJ16 AJ17 AJ18 AJ19AJ2 AJ20 AJ21 AJ22 AJ23 AJ24
AH6 AH7 AH8 AH9
AJ1 AJ10 AJ11 AJ12 AJ13 AJ14
AH23 AH24 AH25 AH26 AH27 AH28 AH29AH3 AH30AH4 AH5 AH13 AH14 AH15 AH16 AH17 AH18 AH19AH2 AH20 AH21 AH22
AG4 AG5 AG6 AG7 AG8 AG9
AH1 AH10 AH11 AH12
AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29AG3 AG30AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19AG2 AG20
AF3 AF30AF4 AF5 AF6 AF7 AF8 AF9
AG1 AG10
AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29AF1 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19
AE28 AE29AE3 AE30AE4 AE5 AE6 AE7 AE8 AE9 AE18 AE19AE2 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27
AD8 AD9
AE1 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17
AD26 AD27 AD28 AD29AD3 AD30AD4 AD5 AD6 AD7 AD16 AD17 AD18 AD19AD2 AD20 AD21 AD22 AD23 AD24 AD25
AC6 AC7 AC8 AC9
AD1 AD10 AD11 AD12 AD13 AD14 AD15
AC24 AC25 AC26 AC27 AC28 AC29AC3 AC30AC4 AC5 AC14 AC15 AC16 AC17 AC18 AC19AC2 AC20 AC21 AC22 AC23
AB4 AB5 AB6 AB7 AB8 AB9
AC1 AC10 AC11 AC12 AC13
AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29AB3 AB30AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19AB2 AB20 AB21
AA3 AA30AA4 AA5 AA6 AA7 AA8 AA9
AB1 AB10 AB11
AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19AA2
A27 A28 A29A3 A4 A5 A6 A7 A8 A9
AA1
T
A19
S
A2 A20
S
A21 A22 A23 A24 A25 A26
XC2VP7FF896
IC2004
A10 A11 A12 A13 A14 A15 A16 A17
T
A18
DP_GOL_RX1B
GOL_RXNVRP_2VCCAUX
DMAR_n
BufR_W_n
BufA(18)
SMBClkSMBDataT_Alert_n
Rst_n
GOL_LVDS
GOL_LVDS
DP_GOL_TX1B
GOL_TXN
GOL_LVDS
GOL_LVDS
DP_GOL_TX1B
GOL_TXP
GOL_LVDS
GOL_LVDS
DP_GOL_RX1B
GOL_RXP
GOL_LVDSGOL_LVDS
SDRAM_A(4)SDRAM_A(5)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(16)Adr(15)Adr(14)Adr(13)Adr(12)Adr(11)
VCCAUXVRP_7LEDs(0)GNDVCCAUXVCCAUXGND
Adr(6)Adr(5)Adr(4)GND
SDRAM_A(6)SDRAM_A(7)SDRAM_A(8)SDRAM_A(9)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5IRQ2_nData(3)VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(10)Adr(9)Adr(8)Adr(7)
SDRAM_DQ(30)SDRAM_DQ(31)SDRAM_DQM(3)SDRAM_A(3)
Data(10)Data(15)D1PWRDWN_BAdr(3)Adr(2)
GNDSDRAM_CKESDRAM_A(12)SDRAM_DQM(1)M1M2D7TestCon(10)TestCon(9)TestCon(8)IRQ1_nData(2)Data(9)Data(11)Data(16)D0DONECCLK
Data(19)Data(23)INIT_BGND
GNDGNDEmptyData(0)Data(6)GNDData(14)Data(20)Data(24)Data(25)GND
SDRAM_DQ(8)SDRAM_DQ(9)M0D6TestCon(13)TestCon(12)TestCon(11)IRQ0_nData(1)Data(7)Data(8)
VRN_5GNDTTC_n(5)GNDChaBusyLHC_ClkSharcWr_nData(4)GNDData(12)GNDVRP_4D2DOUTAdr(1)GNDAdr(0)Data(31)Data(30)
GNDRDWR_BTTC_n(4)TTC_n(6)TTC_n(7)SDRAM_CLKSDRAM_CLKinData(5)Data(13)
GNDGNDA21D4VRP_5TTC_n(3)GNDA19GNDClkSharcRd_nGNDGNDA18Data(18)VRN_4D3GNDA16Data(29)Data(28)GNDData(27)Data(26)
SDRAM_DQ(10)SDRAM_DQ(11)SDRAM_DQ(12)GNDSDRAM_DQ(13)CS_BD5
AVCCAUXTX19VTRXPAD19AVCCAUXRX19Clkx2Rocket_XClkVTTXPAD18AVCCAUXTX18VTRXPAD18AVCCAUXRX18Data(17)Data(22)VTTXPAD16AVCCAUXTX16VTRXPAD16AVCCAUXRX16VRP_3GNDVCCAUX
SDRAM_DQ(14)SDRAM_DQ(15)
GND
ROCKET_LVDS
Rocket_TXN
ROCKET_LVDS
Rocket_TXP
ROCKET_LVDS
Rocket_RXP
ROCKET_LVDS
Rocket_RXNVCCAUXVCCAUXGNDData(21)VRN_3VCCAUX
VCCAUXGNDVRP_6VTTXPAD21AVCCAUXTX21VTRXPAD21AVCCAUXRX21TTC_n(1)TTC_n(2)VTTXPAD19
VTTXPAD6AVCCAUXTX6VTRXPAD6AVCCAUXRX6GOL_XClkVTTXPAD7AVCCAUXTX7VTRXPAD7AVCCAUXRX7VTTXPAD9AVCCAUXTX9VTRXPAD9AVCCAUXRX9VRN_2GNDVCCAUX
VCCAUXVRN_6TTC_n(0)
BufCE_nGNDBufA(7)BufA(6)GNDA4LEDs(3)LEDs(2)GNDA6UpLEDGNDGNDGNDA7GNDA9GND
VCCAUXGNDVRN_7VTTXPAD4AVCCAUXTX4VTRXPAD4AVCCAUXRX4LEDs(1)
GOL_TX_FaultVRP_1VRN_1GND
BufD(33)GNDBufD(16)DXNChaID(0)ChaID(1)GNDGOL_MOD_DEF0GOL_MOD_DEF1GNDErrLEDGOL_TX_DisableGOL_RX_LOSGNDGNDGND
BufA(19)
PROG_BTestCon(2)TestCon(3)TestCon(4)TestCon(5)TestCon(6)TCK
TDIGNDTestCon(0)TestCon(1)GNDGNDGNDTDO
GNDVRP_0VRN_0ChaID(2)GOL_RATE_SELGOL_MOD_DEF2
BufD(25)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2TestCon(14)
GNDBufD(19)DXPHSWAP_ENTestCon(7)TestCon(15)TMSVBATTGND
BufD(17)BufD(18)
BufD(26)BufD(27)BufD(28)BufD(29)BufD(30)BufD(31)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2
BufD(20)BufD(21)BufD(22)BufD(23)BufD(24)
GNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufD(32)BufA(5)GNDBufA(4)BufA(3)GNDVCCO_7VCCO_7GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_2VCCO_2GNDGND
VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufA(2)BufA(1)BufA(0)BufA(10)BufA(11)BufA(12)BufA(13)BufA(14)VCCO_7VCCO_7VCCINTGNDGNDGND
BufD(11)BufD(12)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2GND
BufA(15)BufA(16)BufD(35)BufD(0)BufD(1)BufD(2)BufD(3)BufD(4)VCCO_7VCCO_7
BufA(9)BufA(8)BufA(17)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCAUX
BufD(5)BufD(6)BufD(7)BufD(8)BufD(9)GNDBufD(10)
SDRAM_DQ(4)SDRAM_DQ(5)SDRAM_DQ(6)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3Spare(0)Spare(1)Spare(2)Spare(3)Spare(4)VCCAUX
VCCAUXBufD(13)BufD(14)BufD(15)BufD(34)
SDRAM_RAS_nGNDSDRAM_CS_nSDRAM_A(11)SDRAM_BA(0)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3GND
VCCAUXSDRAM_DQ(0)SDRAM_DQ(1)SDRAM_DQ(2)SDRAM_DQ(3)
SDRAM_A(0)SDRAM_A(1)SDRAM_A(2)SDRAM_DQM(2)SDRAM_DQ(16)SDRAM_DQ(17)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3A21_Select
SDRAM_DQ(7)SDRAM_DQM(0)SDRAM_WE_nSDRAM_CAS_n
SDRAM_DQ(21)SDRAM_DQ(22)SDRAM_DQ(23)SDRAM_DQ(24)SDRAM_DQ(25)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3MS3_nMS2_nMS1_nMS0_nAdr(21)
SDRAM_BA(1)SDRAM_A(10)
SDRAM_DQ(26)SDRAM_DQ(27)GNDSDRAM_DQ(28)SDRAM_DQ(29)GNDVCCO_6VCCO_6GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_3VCCO_3GNDAdr(20)Adr(19)GNDAdr(18)Adr(17)
SDRAM_DQ(18)SDRAM_DQ(19)SDRAM_DQ(20)
XC2VP7/20 VCCINT Decoupling Capacitors
FYSICA EN HOGE ENERGIE-FYSICA
IccINT = 600 mA
Dim
A
B
C
18
A
173
K
13
Date
15 16 17 18
AVX TAJB476K010R
11
IccAUX = 250 mA (min)
ET-Nikhef Amsterdam
VCCAUX and VCCO can ramp up at any rate
3
Proj.No:
1
4
AVX TAJB476K010R
2
D
Rev
L
E
F
For Xilinx Virtex-II Pro, power supplies
can be turned on in any sequence.
8
Proj:
7
6 7
VCCINT Ramp rate 200 us min. and 50 ms max.
NIKHEFof
G
14
Pagec
K
L
Min. Power-On Current XC2VP20
Min. Power-On Current XC2VP20
G
H
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Name
Size
9 10 11 12 13
14
I
J
10
B
E
5
16
XC2VP7/20 VCCAUX Decoupling Capacitors
NATIONAAL INSTITUUT VOOR KERN-
Power Inputs
1:51:34 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
3 6
9 12
4
1
15
AVX TAJB476K010R
AVX TAJB476K010R
8
F
2
C
D
All GND nets on the FPGA need
to be connected to golbal GROUND.
6
5
Time
J
I
H
22n
C2046
GND
channel_in
Input FPGA Power Supply Decoupling
MROD-X 38405
Peter Jansweijer [email protected]
2V2
7 Feb 2006
680p
C2040
GND
47u
C2097
GND
680p
C2009
GND
GND
C2045
22n
GND
C2096
47u
22n
C2083
GND
C2084
22n
GND
C2050
22n 22n
C2052
GND
C2090
100n
GND
100n
C2095
GND
GND
680p
C2067
GND
GND
680p
C2044
GNDC2082
680p
680p
22n
C2079
GND
680p680p
C2071
GND
GND
C2008
GND
680p
C2087
C2072
GND
C2014
680p
C2041
680p
22n
C2047
22n
C2059
GND
C2039
680p
GND
GND
C2053
100n
C2055
47u
GND
GND
GND
GND
C2018
680p
680p
C2061
GND
GND
22n
C2024
22n
C2069
GND
GND
C2062
680p
GND
GND
GND
C2025
22n
C2043
680p
GND
C2051
22n
GNDGND
C2048
22n
C2023
22n
GND
680p
C2077
GND
GND GND
GND
C2022
22n
47u
C2035
C2016
680p
GND
C2019
22n
GND
680p
C2081
GND
100n
C2075
GND
GND
C2033
C2086
680p
C2068
22n
22n
C2049
C2092
680p
GND
100n
GND
GND
C2076
680p
GND
GND
680p
C2042
C2078
22n
GND
C2036
47u
C2030
100n
680p
C2017
GND
C2066
680p
GND
GND
GND
22n
C2073
GND
C2064
22n
GND
C2094
22n
GND
C2037
680p
C2028
22n
GND
GND
680p
C2015
22n
C2020
C2070
100n
680p
C2013
680p
C2091
GND
GND
100n
C2054
GND
100n
C2085
C2080
100n
680p
C2038
GNDGND
C2060
100n
GND
22n
C2021
C2058
22n
GND
100n
C2065
GND
C2012
680p
GND
GND
GND
GND
C2074
22n
C2056
680p
22n
C2093
GND
C2010
680p
22n
C2063
680p
C2057
GND
GND
C2088
22n
GND
680p
C2011
GND
GND
GND
GND
22n
C2089
C2034
100n
GND
100n
C2029
GND
GND
C2031
100n
GND
100n
C2032
22n
C2026
GND
22n
C2027
GND
1V5POWER_NET_TYPE
VCCINT
VCCINT
2V5POWER_NET_TYPE
VCCAUX
VCCAUX
POWER_NET_TYPE
3V33V3
3V3
POWER_NET_TYPE
GND
GND
GND
GND
VCCO_0
VCCO_1
VCCO_2
VCCO_4
VCCO_5
VCCO_6
VCCO_7
VCCO_3
2V5 @ 1,5A
Proj:
97
c ET-Nikhef Amsterdam
142
Buffer Memory interface
L
AVX TAJB476K010R
=> MGT Power (estimated 31 + 49 = 80 mA)
G
K
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
10
Series Termination for
3 5 131210
NIKHEF
Name
Series Termination for
Date
H
2 15
KRUISLAAN 409, 020-592 2000
16
Not (yet) used
H
General purpose
1
Size
PAD6 connected to GOL
PAD19 connected to MROD-Out FPGA
DC coupled
4
Not (yet) used
Series Termination for
L
1
AC coupled
Note: VT1V8_MGT is common to all MROD-Ins
11 14
General purpose
G
9
17 18
A
15
of
E
F
4
=> MGT TX (RX) Termination (estimated 11 mA)
1098 SJ AMSTERDAM NEDERLAND
Sharc Databus
Time
18
B
C C
J
I
Proj.No:
Series Termination for
3
D
6
6
13
SDRAM interface
B
K
Series Termination for
A
D
Series Termination for
I
J
Series Termination for
E
16
11 12
7
Sharc Addressbus
Series Termination for
17
Rev
8
channel_in
Input FPGA MGT Pwr Decoupling, Termination
MROD-X 38405
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:01 pm
tonvr
A3 4 1 4 A
420 x 297 mm
4 6
AVX TAJB476K010R
5
F
Page
Dim
8
GND
R2028
1M
1u
L2004
GND
L2018
1u
R2011
47
47
R2009
GND
L2019
1u
L2033
1u
GND GND
L2014
1u
C2100
100n
GND
2%
100 R2006
1u
L2021
GND
GND
GND
GND
GNDGND
GND
GND
L2022
1u
GND
GND
GND
220n
C2111
L2029
1u
C2101
47u
C2113
220n
GND
GND
GND GND
GND
R2009
47
GNDGND
GND
GND
C2115
220n
GND
GND
GND
GND2TAB
2IN OUT
4
5S_A
1_SHDN
47
R2009
0E01u
L2012
LT1963A_DD
IC2005
3GND1
GND
R2011
47
R2029
R2011
47
C2131
220n
GND
220n
C2104
C2129
220n
GND
GND
GND
C2133
220n
GND
GND
GND
GND
GND GND
L2025
1u
L2027
1u
C2118
GND
GND
L2009
1u
R2007
95E3
2%
220n
R2009
47
L2017
1u
GND GND
GND
C2108
220n
GND
1u
L2007
R2010
47
C2105
220n
C2123
220n
R2005
4K7
L2031
1u
1u
220n
C2116
C2107
220n
C2125
220n
C2124
220n
GND
L2026
L2010
1u
220n
C2120
GND
C2110
220n
C2103
220n
GND
C2109
220n
220n
C2102
GND
220n
C2112
C2127
220n
GND
47
R2008
C2098
47u
GND
R2008
47
C2119
220n
GND
C2117
220n
L2024
1u
L2020
1u
L2016
1u
L2015
1u1u
L2013
C2106
220n
R2008
47
1u
L2023
1u
GND
1u
L2011
C2121
220n
L2005
1u
L2030
C2099
100n
R2010
47
R2008
47
L2006
1u
C2126
220n
1u
L2003
L2032
1u1u
C2122
220n
R2011
47
L2034
1u
L2008
1u
L2028
R2010
47
47
R2010
C2114
220n
C2128
220n
GND
C2132
220n
VTRXPAD7VTRXPAD6VTRXPAD4
VT2V5_MGT
VT2V5_MGT
VT1V8_MGT
AVCCAUXTX4
VTTXPAD4
VRN_7
VRP_7
C2130
220n
VRN_4
3V3
VRP_4
VRN_5
3V3
VRP_5
VRN_6
3V3
VRP_6
3V3
VCCA_MGTPOWER_NET_TYPE
3V3
VTRXPAD9
VTRXPAD19 VTRXPAD18 VTRXPAD16
VRN_0
3V3
VRP_0
VRN_1
3V3
VRP_1
VRN_2
3V3
VRP_2
VRN_3
3V3
VRP_3
AVCCAUXTX18 AVCCAUXTX16
AVCCAUXRX16AVCCAUXRX18AVCCAUXRX19AVCCAUXRX21
VTTXPAD21 VTTXPAD19 VTTXPAD18 VTTXPAD16
VTRXPAD21
AVCCAUXTX9
AVCCAUXRX9AVCCAUXRX7AVCCAUXRX6AVCCAUXRX4
VTTXPAD6 VTTXPAD7 VTTXPAD9
AVCCAUXTX21 AVCCAUXTX19
POWER_NET_TYPE
VT2V5_MGT
VCCA_MGT
VCCA_MGT
GNDA4 GNDA6 GNDA7 GNDA9
GNDA21 GNDA19 GNDA18 GNDA16
AVCCAUXTX6 AVCCAUXTX7
18
E
5
F
B
C
7
c ET-Nikhef Amsterdam
Proj.No:
Date
Time
9
H
6
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
7 17
SDRAM_A(12) is not connected
L
1
J
11
A
of
G
NIKHEF
8
Proj:
K
8
2
16
I
163 5 14
Rev
E
17
9
18
1 10
H
4
Size
15
15
C
D
J
K
L
A
G
4
D
12
I
10
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:29 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
5 6
11 12
KRUISLAAN 409, 020-592 2000
13
2
1098 SJ AMSTERDAM NEDERLAND
6
F
Dim
Page
B
3
Name
13 14
8
GND
GND
channel_in
Buffer Memory (ZBT and SDRAM)
MROD-X 38405
9
21
22
32
GND
GND
4 1
GND
GND
8
C2142
22n
4K7
R2012
4K7
R2012
C2159
22n
4K7
R2012
C2141
22n
R2012
4K7
31
8
9
10
C2146
100n
13
GND
GND
GND
0
GND
GND
25
GND
C2144
22n
GND
6
3
GND
0
23
GND
GND
16
18
GNDGND
1
GND
2
13
15
GND GND
GND
29
30
20
9
GND
15
5
28
GND
6
7
C2162
100n
3
4
GND
30
11
GND
C2148
100n
GND
GND
GND
3 2
14
15
GND
14
19
12
GND
24
GND
GND
3
26
GND
9
16
33
7
2
GND
GND
GND
GND
GND
GND
GND
0
GND
7
16
GND
25
GND
11
10
11
0
12
4
31
27
24
19
GND
GND
35
GND
2
3
GND
17
18
VssQ438
VssQ546
VssQ652
78VssQ7
VssQ884
18_CAS
20_CS
_RAS19
17_WE
C2134
22n
49
VddQ655
VddQ775
81VddQ8
Vss144
Vss258
Vss372
86Vss4
VssQ16
VssQ212
32VssQ3
NC570
NC673
Vdd11
Vdd215
Vdd329
Vdd443
VddQ13
VddQ29
VddQ335
VddQ441
VddQ5
DQ713
DQ874
DQ976
DQM016 71
DQM1
DQM228
DQM359
NC114
NC230
NC357
69NC4
47
DQ2648
DQ2750
DQ2851
53DQ29
DQ37
DQ3054
56DQ31
DQ48
DQ510
11DQ6
85
DQ1631
DQ1733
DQ1834
DQ1936
DQ25
DQ2037
DQ2139
DQ2240
DQ2342
DQ2445
DQ25
23BA1
CKE67
CLK68
DQ02
4DQ1
DQ1077
DQ1179
80DQ12
DQ1382
DQ1483
DQ15
24
A1121
A227
A360
A461
A562
A663
A764
A865
A966
BA022
100n
27
28
MT48LC8M32B2
IC2007
A025
A126
A1010
5
6
7
C2152
22n
C2147
C2135
22n
1
2
GND
GND
GND
1
C2157
22n
GND
14
17
10
1
11
C2165
100n
C2156
22n
0
13
100n
C2164
C2161
22n
_BW4
_CE1
98
92
_CE2
_CEN
87
31
_LBO
_OE
86
C2158
22n
12
21VSS4
26VSS5
40
VSS6
55VSS7
VSS860
67VSS9
64ZZ
_BW1
93
94
_BW2
_BW3
95
96
16VDD5
20VDD6
27VDD7
VDD8
41
54VDD9
5VSS1
VSS1071
76VSS11
90
VSS12
VSS210
VSS317
VDD14
61VDD10
VDD1165
66VDD12
VDD1370
VDD1477
VDD15
91
11VDD2
VDD314
15VDD4
68IO8
69IO9
IOp151
IOp280
IOp31
IOp430
R_W
88
TCK
43
39
TDI
42
TDO
TMS
38
22
IO2723
24IO28
IO2925
57IO3
28IO30
29IO31
IO458
59IO5
IO662
IO763
IO16
IO173
6IO18
IO197
IO256
IO208
9IO21
12IO22
IO2313
18IO24
19IO25
IO2697
CE2
CLK
89
52IO0
IO153
72IO10
IO1173
74IO12
IO1375
78IO14
79IO15
2
83
84
A18
A2
35
A3
34
33
A4
32
A5
A6
100
99
A7
82
A8
81
A9
85
ADV_LD
IDT71V65603S100PF
IC2006
A0
37
36
A1
A10
44
A11
45
A12
46
A13
47
48
A14
A15
49
50
A16
A17
22n 22n
C2154
26
8
C2140
22n 22n
C2145
GND
C2138C2137
22n
5
22n
C2136
C2149
100n
GND
C2160
22n
C2143
C2153
22n
20
21
C2163
100n
22
0
4
5
22n
19
34
17
GND
6
GND
GND
GND
29
GND
23
18
22n
1
GND
22n 22n
C2155C2139
22n
C2150
BufCE_n SDRAM_CLKZ50_NET_TYPE
Z50_NET_TYPE
SDRAM_CLKin
SDRAM_WE_n
SDRAM_RAS_n
SDRAM_CAS_n
C2151
3V3
Clkx2
BufR_W_n
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
SDRAM_CS_n
SDRAM_DQ(31:0)
SDRAM_DQM(3:0)
SDRAM_BA(1:0)
SDRAM_A(12:0)
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
BufD(35:0)
BufA(19:0)
3V3
3V3
3V3
3V3
3V3
SDRAM_CKE
c
3
7
7
Answer Record #18562
14
Input Channel ID bits
10 17
K
GND
E
H
5
configuration. See Xilinx PROM Errata,
Testpoints force Spare
lines to be accessible.I
18
arc242 package
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
L
FPGA JTAG Signals
12
Temperature sensing diode
6
0 1 1 Master SelectMAP
12
0
It may be necessary to use Master SelectMap
3
I
HSWAP_EN = ’0’ => User IOs have pull-up
A
E
CLK
FPGA Configuration Signals
2
Default configuration mode will be Slave SelectMAP.
17
16
Connector
1
J J
Page
NATIONAAL INSTITUUT VOOR KERN-
H
PWRDWN_B is unsupported (should be pulled high)
Optinal Test
G
8
Clock Signals
16
chains where the same bitstream is loaded into multiple devices.
11
1098 SJ AMSTERDAM NEDERLAND
1
F
is no possibility for readback (RDWR_B = ’0’)
8 Input channels are loaded in parallel so there
Time
Dim
2
Proj:
9
to Master SelectMap and all other MROD-In FPGAs
to Slave SelectMap.
B
Size
Rocket IO Signals
15
Proj.No:
Rev
1 0 1 Boundary scan
’On’ = ’1’, ’Off’ = ’0’
13 18
Note: FCC_SelectMAP = 50 MHz so CCLK < 50 MHz!
M2 M1 M0
1 1 0 Slave SelectMAP (default)
6
D
14
-> Slave SlectMAP programming Mode -> BUSY.
15
13
Date
Name
See "Virtex-II Pro FPGA User Guide", Chapter 4 -> Configuration
F
FPGA Control signals
Cand each CS_B = ’0’
A
of
154
8
C
9
11
In this case set MROD-Out FPGA and one MROD-In FPGA
TTC Signals
NIKHEF
Pull-Ups
3
resistors during configuration
ET-Nikhef Amsterdam
K
5
4
B
2
1
D
L
G
10
66
420 x 297 mm
4 1 4 AA3
Ton van Reen
1:53:04 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405 MROD-X
Input FPGA Auxiliary Connections
channel_in
VBATT is decriptor key memory backup supply
Sharc Signals Frontend to Backend
DOUT is BUSY in SelectMAP mode and BUSY should NOT be used for parallel
1
0
6
GND
15
9
Fiducial2002
22n
C2168
NC7SZ08
IC2012
1
2
3
5
4
2n2
C2171
J1B 2
GND
2
U3_1B
U2_1B
1
2
3
5
4
0E0
R2026
NC7SZ00
IC2009
1
2
3
5
4
NC7SZ00
IC2011
C2166
22n
R2027
1K0
Fiducial2001
J1B 12
GND
Sw1B
17
180
R2013
GND
3
2
0
J1B 15
12
J1B
NC7SZ00
IC2010
1
2
3
5
4
SMD_LED_Red
D2002
J1B 16
GND
J1B 5
GND
GND
13
4
3
0
J1B 4
J1B 18
J1B 19
1K0
R2019
3
GND
GND
5
20
R20231K0
U1_1B
J1B
J1B 13
GND
1
2
J1B
R2015
J1B 8
4K7
R2025
180
R2024
D2004
SMD_LED_Green
180
R2025
Sw1B
D2001
SMD_LED_Red
ADD12
4DXN
5DXP
GND
3
SMBCLK8
SMBDATA9
VCC
6
10_ALERT
_STBY7
4K7
6
100n
C2172
GND
IC2013
MAX1618
1ADD0
11R2025
4K7
J1B
R20181K0
J1B 10
J1B
J1B 1
GND
SMD_LED_Green
D2003
Sw1B
J1B 7
R2020
NC7SZ00
IC2008
1
2
3
5
4
U4_1B
14
1K0
7
GND
10
4
R20224K7
6
5
GND
180
R2016 8
1
14
U0_1B
C2170
22n
R2021
180
R2014
J1B
GND
1K0
22n
C2167
7
GND
11GND
3
1K0
R2017
GND
GND
4
Spare(4:0)
J1B 9
22n
C2169
GND
CS_B
VCCAUXPWRDWN_B
CCLKCCLK
HSWAP_EN
PROG_BPROG_B
DXP
DXN
SMBClk
3V3
M2 M1
VCCAUX
M0
Spare(4:0)
Clk
TestCon(15:0)
3V3
3V3
3V3
3V3
T_Alert_n
SMBData
DOUT
INIT_BINIT_B
DONEDONE
D7
D6
D5
D4
D3
D2
D1
D0 D(7:0)
RDWR_B
3V3
ChaBusy ChaBusy
TTC_n(7:0)TTC_n(7:0)
ChaID(2:0)ChaID(2:0)
TCK
TDO
FPGA_TCK
FPGA_TMS
TDI FPGA_TDI
FPGA_TDO
Clk Clk
Clkx2Clkx2
LHC_ClkLHC_Clk
Rocket_XClk Rocket_XClk
Adr(21:0)Adr(21:0)
IRQ1_n IRQ1_n
IRQ2_n IRQ2_n
Empty Empty
DMAR_n DMAR_n
Rocket_RXPRocket_RXP
Rocket_RXN Rocket_RXN
Rocket_TXPRocket_TXP
Rocket_TXNRocket_TXN
A21_SelectA21_Select
TMS
3V3
LEDs(0)
LEDs(1)
LEDs(2)
LEDs(3)
General_Rst_n
Channel_Rst_n
Rst_n
VBATT
IRQ0_n IRQ0_n
Data(31:0) Data(31:0)
MS0_n MS0_n
MS1_nMS1_n
MS2_n MS2_n
MS3_nMS3_n
SharcRd_nSharcRd_n
SharcWr_n SharcWr_n
H
I
9
15 16 17
C
14
I
J
G
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1
Name
Size
Dim
K
L
3
Date
Time
of
4
10u Tantalum
AVX TAJB106K010R
J
13
13
10
D
62 107 8
5 15 16 17
C
11 12
D
14
B
11 12
NIKHEF
7 863 4
Page
E
F
E
F
A
H
18
G
V2
7 Feb 2006
1:50:33 pm
tonvr
A3 4 1 4 A
420 x 297 mm
1 6
GOL_MOD_DEF and GOL_TX_Fault
Signal Pull-ups in one
arc242 package
1098 SJ AMSTERDAM NEDERLANDET-Nikhef Amsterdam
B
5
Rev
c
K
1 2
L
A
9
Proj: Proj.No:
18
GND
channel_in
GOL Input
MROD-X 38405
Peter Jansweijer [email protected]
2
2
3
5
4
10u
C3002
R3002180
R3001180
IC3002
NC7SZ00
1
2
3
5
4
GND
C3007
22n
GND
GND4GND4
GND5GND5
GND6GND6
GND7GND7
GND8
GND8
GND9
GND9
GND
IC3003
NC7SZ00
1
GND12
GND13GND13
GND14GND14
GND15GND15
GND16GND16
GND17GND17
GND18
GND18
GND19
GND19
GND2GND2
GND20
GND20
GND3GND3
C3001
SFPT_cage
IC3001
GND1GND1
GND10
GND10
GND11GND11
GND12
4K7
GND
GND
GND
100n
1u
L3002
R3004
D2A
k_r
a_r
GND GND
L3001
1u
100n
C3004
D2A
Fr_LED_Gn
k_g
a_g
Fr_LED_Rd
GND
GND
22n
C3006
C3003
100n
4K7
4K7
R3003R3003
4K7
20
mod_def06
mod_def15
mod_def24
4K7
R3003R3003
Tx_disable3
Tx_fault2
VccR
15
VccT
16
VeeR1
9
VeeR2
10
VeeR3
11
14
VeeR4
VeeT1
1
VeeT2
17
VeeT3
IC3001
HFBR5720
LOS8
RD_n12 S
RD_p13 S
Rate_Sel7
TD_n19 T
TD_p18 T
GOL_XClk GOL_XClk
3V3
3V3
GOL_TX_Fault
GOL_MOD_DEF2
GOL_MOD_DEF1
GOL_MOD_DEF0
3V3
10u
C3005
GOL_RX_LOS
GOL_RXNGOL_LVDSGOL_LVDS
GOL_RXPGOL_LVDSGOL_LVDS
GOL_RATE_SEL
GOL_TXPGOL_LVDSGOL_LVDS
GOL_TX_Disable
ErrLED
UpLED
GOL_TXNGOL_LVDSGOL_LVDS
10 11 12 13
G
H
3 4
G
II
J
Date
2
VCCO_# (3V3) 10 pins each
12
Proj: Proj.No:
Rev
Size
A
Dim
1 3 6 7
7
NIKHEF
1
C
D
Input FPGA Power pins:
c ET-Nikhef Amsterdam
2
16
L
J
K
14
9
Page
A
B
C
K
6 18
E
F
KRUISLAAN 409, 020-592 2000
1715
VCCAUX (2V5) 16 pins
VCCINT (1V5) 32 pins
D
of
15
Time
Name
H
5
E
tonvr
1:50:53 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
Input FPGA
channel_in
8 9 16
8 14 18
11
1098 SJ AMSTERDAM NEDERLAND
L
B
10 13
4 5
F
17
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
GND 124 pins
62
420 x 297 mm
4 1 4 AA3
Y6 Y7 Y8 Y9 Y23 Y24 Y25 Y26 Y27 Y28 Y29Y3 Y30Y4 Y5 Y13 Y14 Y15 Y16 Y17 Y18 Y19Y2 Y20 Y21 Y22
W4 W5 W6 W7 W8 W9
Y1 Y10 Y11 Y12
W21 W22 W23 W24 W25 W26 W27 W28 W29W3 W30W11 W12 W13 W14 W15 W16 W17 W18 W19W2 W20
V3 V30V4 V5 V6 V7 V8 V9
W1 W10
V2 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29V1 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19
U28 U29U3 U30U4 U5 U6 U7 U8 U9 U18 U19U2 U20 U21 U22 U23 U24 U25 U26 U27
T8 T9
U1 U10 U11 U12 U13 U14 U15 U16 U17
T26 T27 T28 T29T3 T30T4 T5 T6 T7 T16 T17 T18 T19T2 T20 T21 T22 T23 T24 T25
R6 R7 R8 R9
T1 T10 T11 T12 T13 T14 T15
R24 R25 R26 R27 R28 R29R3 R30R4 R5 R14 R15 R16 R17 R18 R19R2 R20 R21 R22 R23
P4 P5 P6 P7 P8 P9
R1 R10 R11 R12 R13
P22 P23 P24 P25 P26 P27 P28 P29P3 P30P12 P13 P14 P15 P16 P17 P18 P19P2 P20 P21
N3 N30N4 N5 N6 N7 N8 N9
P1 P10 P11
N20 N21 N22 N23 N24 N25 N26 N27 N28 N29N10 N11 N12 N13 N14 N15 N16 N17 N18 N19N2
M28 M29M3 M30M4 M5 M6 M7 M8 M9
N1
M19M2 M20 M21 M22 M23 M24 M25 M26 M27
L9
M1 M10 M11 M12 M13 M14 M15 M16 M17 M18
L26 L27 L28 L29L3 L30L4 L5 L6 L7 L8 L17 L18 L19L2 L20 L21 L22 L23 L24 L25
K7 K8 K9
L1 L10 L11 L12 L13 L14 L15 L16
K24 K25 K26 K27 K28 K29K3 K30K4 K5 K6 K15 K16 K17 K18 K19K2 K20 K21 K22 K23
J5 J6 J7 J8 J9
K1 K10 K11 K12 K13 K14
J22 J23 J24 J25 J26 J27 J28 J29J3 J30J4 J13 J14 J15 J16 J17 J18 J19J2 J20 J21
H30H4 H5 H6 H7 H8 H9
J1 J10 J11 J12
H20 H21 H22 H23 H24 H25 H26 H27 H28 H29H3 H11 H12 H13 H14 H15 H16 H17 H18 H19H2
G29G3 G30G4 G5 G6 G7 G8 G9
H1 H10
G19G2 G20 G21 G22 G23 G24 G25 G26 G27 G28G1 G10 G11 G12 G13 G14 G15 G16 G17 G18
F27 F28 F29F3 F30F4 F5 F6 F7 F8 F9 F17 F18 F19F2 F20 F21 F22 F23 F24 F25 F26
E8 E9
F1 F10 F11 F12 F13 F14 F15 F16
E25 E26 E27 E28 E29E3 E30E4 E5 E6 E7 E15 E16 E17 E18 E19E2 E20 E21 E22 E23 E24
D6 D7 D8 D9
E1 E10 E11 E12 E13 E14
D23 D24 D25 D26 D27 D28 D29D3 D30D4 D5 D13 D14 D15 D16 D17 D18 D19D2 D20 D21 D22
C4 C5 C6 C7 C8 C9
D1 D10 D11 D12
C21 C22 C23 C24 C25 C26 C27 C28 C29C3 C30C11 C12 C13 C14 C15 C16 C17 C18 C19C2 C20
B3 B30B4 B5 B6 B7 B8 B9
C1 C10
B2 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29B1 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19
AK27 AK28 AK29AK3 AK4 AK5 AK6 AK7 AK8 AK9
T
AK18
T
AK19
S
AK2 AK20
S
AK21 AK22 AK23 AK24 AK25 AK26
AJ8 AJ9
AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17
AJ25 AJ26 AJ27 AJ28 AJ29AJ3 AJ30AJ4 AJ5 AJ6 AJ7 AJ15 AJ16 AJ17 AJ18 AJ19AJ2 AJ20 AJ21 AJ22 AJ23 AJ24
AH6 AH7 AH8 AH9
AJ1 AJ10 AJ11 AJ12 AJ13 AJ14
AH23 AH24 AH25 AH26 AH27 AH28 AH29AH3 AH30AH4 AH5 AH13 AH14 AH15 AH16 AH17 AH18 AH19AH2 AH20 AH21 AH22
AG4 AG5 AG6 AG7 AG8 AG9
AH1 AH10 AH11 AH12
AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29AG3 AG30AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19AG2 AG20
AF3 AF30AF4 AF5 AF6 AF7 AF8 AF9
AG1 AG10
AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29AF1 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19
AE28 AE29AE3 AE30AE4 AE5 AE6 AE7 AE8 AE9 AE18 AE19AE2 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27
AD8 AD9
AE1 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17
AD26 AD27 AD28 AD29AD3 AD30AD4 AD5 AD6 AD7 AD16 AD17 AD18 AD19AD2 AD20 AD21 AD22 AD23 AD24 AD25
AC6 AC7 AC8 AC9
AD1 AD10 AD11 AD12 AD13 AD14 AD15
AC24 AC25 AC26 AC27 AC28 AC29AC3 AC30AC4 AC5 AC14 AC15 AC16 AC17 AC18 AC19AC2 AC20 AC21 AC22 AC23
AB4 AB5 AB6 AB7 AB8 AB9
AC1 AC10 AC11 AC12 AC13
AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29AB3 AB30AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19AB2 AB20 AB21
AA3 AA30AA4 AA5 AA6 AA7 AA8 AA9
AB1 AB10 AB11
AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19AA2
A27 A28 A29A3 A4 A5 A6 A7 A8 A9
AA1
T
A19
S
A2 A20
S
A21 A22 A23 A24 A25 A26
XC2VP7FF896
IC3004
A10 A11 A12 A13 A14 A15 A16 A17
T
A18
DP_GOL_RX2A
GOL_RXNVRP_2VCCAUX
DMAR_n
BufR_W_n
BufA(18)
SMBClkSMBDataT_Alert_n
Rst_n
GOL_LVDS
GOL_LVDS
DP_GOL_TX2A
GOL_TXN
GOL_LVDS
GOL_LVDS
DP_GOL_TX2A
GOL_TXP
GOL_LVDS
GOL_LVDS
DP_GOL_RX2A
GOL_RXP
GOL_LVDSGOL_LVDS
SDRAM_A(4)SDRAM_A(5)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(16)Adr(15)Adr(14)Adr(13)Adr(12)Adr(11)
VCCAUXVRP_7LEDs(0)GNDVCCAUXVCCAUXGND
Adr(6)Adr(5)Adr(4)GND
SDRAM_A(6)SDRAM_A(7)SDRAM_A(8)SDRAM_A(9)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5IRQ2_nData(3)VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(10)Adr(9)Adr(8)Adr(7)
SDRAM_DQ(30)SDRAM_DQ(31)SDRAM_DQM(3)SDRAM_A(3)
Data(10)Data(15)D1PWRDWN_BAdr(3)Adr(2)
GNDSDRAM_CKESDRAM_A(12)SDRAM_DQM(1)M1M2D7TestCon(10)TestCon(9)TestCon(8)IRQ1_nData(2)Data(9)Data(11)Data(16)D0DONECCLK
Data(19)Data(23)INIT_BGND
GNDGNDEmptyData(0)Data(6)GNDData(14)Data(20)Data(24)Data(25)GND
SDRAM_DQ(8)SDRAM_DQ(9)M0D6TestCon(13)TestCon(12)TestCon(11)IRQ0_nData(1)Data(7)Data(8)
VRN_5GNDTTC_n(5)GNDChaBusyLHC_ClkSharcWr_nData(4)GNDData(12)GNDVRP_4D2DOUTAdr(1)GNDAdr(0)Data(31)Data(30)
GNDRDWR_BTTC_n(4)TTC_n(6)TTC_n(7)SDRAM_CLKSDRAM_CLKinData(5)Data(13)
GNDGNDA21D4VRP_5TTC_n(3)GNDA19GNDClkSharcRd_nGNDGNDA18Data(18)VRN_4D3GNDA16Data(29)Data(28)GNDData(27)Data(26)
SDRAM_DQ(10)SDRAM_DQ(11)SDRAM_DQ(12)GNDSDRAM_DQ(13)CS_BD5
AVCCAUXTX19VTRXPAD19AVCCAUXRX19Clkx2Rocket_XClkVTTXPAD18AVCCAUXTX18VTRXPAD18AVCCAUXRX18Data(17)Data(22)VTTXPAD16AVCCAUXTX16VTRXPAD16AVCCAUXRX16VRP_3GNDVCCAUX
SDRAM_DQ(14)SDRAM_DQ(15)
GND
ROCKET_LVDS
Rocket_TXN
ROCKET_LVDS
Rocket_TXP
ROCKET_LVDS
Rocket_RXP
ROCKET_LVDS
Rocket_RXNVCCAUXVCCAUXGNDData(21)VRN_3VCCAUX
VCCAUXGNDVRP_6VTTXPAD21AVCCAUXTX21VTRXPAD21AVCCAUXRX21TTC_n(1)TTC_n(2)VTTXPAD19
VTTXPAD6AVCCAUXTX6VTRXPAD6AVCCAUXRX6GOL_XClkVTTXPAD7AVCCAUXTX7VTRXPAD7AVCCAUXRX7VTTXPAD9AVCCAUXTX9VTRXPAD9AVCCAUXRX9VRN_2GNDVCCAUX
VCCAUXVRN_6TTC_n(0)
BufCE_nGNDBufA(7)BufA(6)GNDA4LEDs(3)LEDs(2)GNDA6UpLEDGNDGNDGNDA7GNDA9GND
VCCAUXGNDVRN_7VTTXPAD4AVCCAUXTX4VTRXPAD4AVCCAUXRX4LEDs(1)
GOL_TX_FaultVRP_1VRN_1GND
BufD(33)GNDBufD(16)DXNChaID(0)ChaID(1)GNDGOL_MOD_DEF0GOL_MOD_DEF1GNDErrLEDGOL_TX_DisableGOL_RX_LOSGNDGNDGND
BufA(19)
PROG_BTestCon(2)TestCon(3)TestCon(4)TestCon(5)TestCon(6)TCK
TDIGNDTestCon(0)TestCon(1)GNDGNDGNDTDO
GNDVRP_0VRN_0ChaID(2)GOL_RATE_SELGOL_MOD_DEF2
BufD(25)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2TestCon(14)
GNDBufD(19)DXPHSWAP_ENTestCon(7)TestCon(15)TMSVBATTGND
BufD(17)BufD(18)
BufD(26)BufD(27)BufD(28)BufD(29)BufD(30)BufD(31)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2
BufD(20)BufD(21)BufD(22)BufD(23)BufD(24)
GNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufD(32)BufA(5)GNDBufA(4)BufA(3)GNDVCCO_7VCCO_7GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_2VCCO_2GNDGND
VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufA(2)BufA(1)BufA(0)BufA(10)BufA(11)BufA(12)BufA(13)BufA(14)VCCO_7VCCO_7VCCINTGNDGNDGND
BufD(11)BufD(12)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2GND
BufA(15)BufA(16)BufD(35)BufD(0)BufD(1)BufD(2)BufD(3)BufD(4)VCCO_7VCCO_7
BufA(9)BufA(8)BufA(17)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCAUX
BufD(5)BufD(6)BufD(7)BufD(8)BufD(9)GNDBufD(10)
SDRAM_DQ(4)SDRAM_DQ(5)SDRAM_DQ(6)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3Spare(0)Spare(1)Spare(2)Spare(3)Spare(4)VCCAUX
VCCAUXBufD(13)BufD(14)BufD(15)BufD(34)
SDRAM_RAS_nGNDSDRAM_CS_nSDRAM_A(11)SDRAM_BA(0)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3GND
VCCAUXSDRAM_DQ(0)SDRAM_DQ(1)SDRAM_DQ(2)SDRAM_DQ(3)
SDRAM_A(0)SDRAM_A(1)SDRAM_A(2)SDRAM_DQM(2)SDRAM_DQ(16)SDRAM_DQ(17)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3A21_Select
SDRAM_DQ(7)SDRAM_DQM(0)SDRAM_WE_nSDRAM_CAS_n
SDRAM_DQ(21)SDRAM_DQ(22)SDRAM_DQ(23)SDRAM_DQ(24)SDRAM_DQ(25)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3MS3_nMS2_nMS1_nMS0_nAdr(21)
SDRAM_BA(1)SDRAM_A(10)
SDRAM_DQ(26)SDRAM_DQ(27)GNDSDRAM_DQ(28)SDRAM_DQ(29)GNDVCCO_6VCCO_6GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_3VCCO_3GNDAdr(20)Adr(19)GNDAdr(18)Adr(17)
SDRAM_DQ(18)SDRAM_DQ(19)SDRAM_DQ(20)
XC2VP7/20 VCCINT Decoupling Capacitors
FYSICA EN HOGE ENERGIE-FYSICA
IccINT = 600 mA
Dim
A
B
C
18
A
173
K
13
Date
15 16 17 18
AVX TAJB476K010R
11
IccAUX = 250 mA (min)
ET-Nikhef Amsterdam
VCCAUX and VCCO can ramp up at any rate
3
Proj.No:
1
4
AVX TAJB476K010R
2
D
Rev
L
E
F
For Xilinx Virtex-II Pro, power supplies
can be turned on in any sequence.
8
Proj:
7
6 7
VCCINT Ramp rate 200 us min. and 50 ms max.
NIKHEFof
G
14
Pagec
K
L
Min. Power-On Current XC2VP20
Min. Power-On Current XC2VP20
G
H
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Name
Size
9 10 11 12 13
14
I
J
10
B
E
5
16
XC2VP7/20 VCCAUX Decoupling Capacitors
NATIONAAL INSTITUUT VOOR KERN-
Power Inputs
1:51:34 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
3 6
9 12
4
1
15
AVX TAJB476K010R
AVX TAJB476K010R
8
F
2
C
D
All GND nets on the FPGA need
to be connected to golbal GROUND.
6
5
Time
J
I
H
22n
C3046
GND
channel_in
Input FPGA Power Supply Decoupling
MROD-X 38405
Peter Jansweijer [email protected]
2V2
7 Feb 2006
680p
C3040
GND
47u
C3097
GND
680p
C3009
GND
GND
C3045
22n
GND
C3096
47u
22n
C3083
GND
C3084
22n
GND
C3050
22n 22n
C3052
GND
C3090
100n
GND
100n
C3095
GND
GND
680p
C3067
GND
GND
680p
C3044
GNDC3082
680p
680p
22n
C3079
GND
680p680p
C3071
GND
GND
C3008
GND
680p
C3087
C3072
GND
C3014
680p
C3041
680p
22n
C3047
22n
C3059
GND
C3039
680p
GND
GND
C3053
100n
C3055
47u
GND
GND
GND
GND
C3018
680p
680p
C3061
GND
GND
22n
C3024
22n
C3069
GND
GND
C3062
680p
GND
GND
GND
C3025
22n
C3043
680p
GND
C3051
22n
GNDGND
C3048
22n
C3023
22n
GND
680p
C3077
GND
GND GND
GND
C3022
22n
47u
C3035
C3016
680p
GND
C3019
22n
GND
680p
C3081
GND
100n
C3075
GND
GND
C3033
C3086
680p
C3068
22n
22n
C3049
C3092
680p
GND
100n
GND
GND
C3076
680p
GND
GND
680p
C3042
C3078
22n
GND
C3036
47u
C3030
100n
680p
C3017
GND
C3066
680p
GND
GND
GND
22n
C3073
GND
C3064
22n
GND
C3094
22n
GND
C3037
680p
C3028
22n
GND
GND
680p
C3015
22n
C3020
C3070
100n
680p
C3013
680p
C3091
GND
GND
100n
C3054
GND
100n
C3085
C3080
100n
680p
C3038
GNDGND
C3060
100n
GND
22n
C3021
C3058
22n
GND
100n
C3065
GND
C3012
680p
GND
GND
GND
GND
C3074
22n
C3056
680p
22n
C3093
GND
C3010
680p
22n
C3063
680p
C3057
GND
GND
C3088
22n
GND
680p
C3011
GND
GND
GND
GND
22n
C3089
C3034
100n
GND
100n
C3029
GND
GND
C3031
100n
GND
100n
C3032
22n
C3026
GND
22n
C3027
GND
1V5POWER_NET_TYPE
VCCINT
VCCINT
2V5POWER_NET_TYPE
VCCAUX
VCCAUX
POWER_NET_TYPE
3V33V3
3V3
POWER_NET_TYPE
GND
GND
GND
GND
VCCO_0
VCCO_1
VCCO_2
VCCO_4
VCCO_5
VCCO_6
VCCO_7
VCCO_3
2V5 @ 1,5A
Proj:
97
c ET-Nikhef Amsterdam
142
Buffer Memory interface
L
AVX TAJB476K010R
=> MGT Power (estimated 31 + 49 = 80 mA)
G
K
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
10
Series Termination for
3 5 131210
NIKHEF
Name
Series Termination for
Date
H
2 15
KRUISLAAN 409, 020-592 2000
16
Not (yet) used
H
General purpose
1
Size
PAD6 connected to GOL
PAD19 connected to MROD-Out FPGA
DC coupled
4
Not (yet) used
Series Termination for
L
1
AC coupled
Note: VT1V8_MGT is common to all MROD-Ins
11 14
General purpose
G
9
17 18
A
15
of
E
F
4
=> MGT TX (RX) Termination (estimated 11 mA)
1098 SJ AMSTERDAM NEDERLAND
Sharc Databus
Time
18
B
C C
J
I
Proj.No:
Series Termination for
3
D
6
6
13
SDRAM interface
B
K
Series Termination for
A
D
Series Termination for
I
J
Series Termination for
E
16
11 12
7
Sharc Addressbus
Series Termination for
17
Rev
8
channel_in
Input FPGA MGT Pwr Decoupling, Termination
MROD-X 38405
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:01 pm
tonvr
A3 4 1 4 A
420 x 297 mm
4 6
AVX TAJB476K010R
5
F
Page
Dim
8
GND
R3028
1M
1u
L3004
GND
L3018
1u
R3011
47
47
R3009
GND
L3019
1u
L3033
1u
GND GND
L3014
1u
C3100
100n
GND
2%
100 R3006
1u
L3021
GND
GND
GND
GND
GNDGND
GND
GND
L3022
1u
GND
GND
GND
220n
C3111
L3029
1u
C3101
47u
C3113
220n
GND
GND
GND GND
GND
R3009
47
GNDGND
GND
GND
C3115
220n
GND
GND
GND
GND2TAB
2IN OUT
4
5S_A
1_SHDN
47
R3009
0E01u
L3012
LT1963A_DD
IC3005
3GND1
GND
R3011
47
R3029
R3011
47
C3131
220n
GND
220n
C3104
C3129
220n
GND
GND
GND
C3133
220n
GND
GND
GND
GND
GND GND
L3025
1u
L3027
1u
C3118
GND
GND
L3009
1u
R3007
95E3
2%
220n
R3009
47
L3017
1u
GND GND
GND
C3108
220n
GND
1u
L3007
R3010
47
C3105
220n
C3123
220n
R3005
4K7
L3031
1u
1u
220n
C3116
C3107
220n
C3125
220n
C3124
220n
GND
L3026
L3010
1u
220n
C3120
GND
C3110
220n
C3103
220n
GND
C3109
220n
220n
C3102
GND
220n
C3112
C3127
220n
GND
47
R3008
C3098
47u
GND
R3008
47
C3119
220n
GND
C3117
220n
L3024
1u
L3020
1u
L3016
1u
L3015
1u1u
L3013
C3106
220n
R3008
47
1u
L3023
1u
GND
1u
L3011
C3121
220n
L3005
1u
L3030
C3099
100n
R3010
47
R3008
47
L3006
1u
C3126
220n
1u
L3003
L3032
1u1u
C3122
220n
R3011
47
L3034
1u
L3008
1u
L3028
R3010
47
47
R3010
C3114
220n
C3128
220n
GND
C3132
220n
VTRXPAD7VTRXPAD6VTRXPAD4
VT2V5_MGT
VT2V5_MGT
VT1V8_MGT
AVCCAUXTX4
VTTXPAD4
VRN_7
VRP_7
C3130
220n
VRN_4
3V3
VRP_4
VRN_5
3V3
VRP_5
VRN_6
3V3
VRP_6
3V3
VCCA_MGTPOWER_NET_TYPE
3V3
VTRXPAD9
VTRXPAD19 VTRXPAD18 VTRXPAD16
VRN_0
3V3
VRP_0
VRN_1
3V3
VRP_1
VRN_2
3V3
VRP_2
VRN_3
3V3
VRP_3
AVCCAUXTX18 AVCCAUXTX16
AVCCAUXRX16AVCCAUXRX18AVCCAUXRX19AVCCAUXRX21
VTTXPAD21 VTTXPAD19 VTTXPAD18 VTTXPAD16
VTRXPAD21
AVCCAUXTX9
AVCCAUXRX9AVCCAUXRX7AVCCAUXRX6AVCCAUXRX4
VTTXPAD6 VTTXPAD7 VTTXPAD9
AVCCAUXTX21 AVCCAUXTX19
POWER_NET_TYPE
VT2V5_MGT
VCCA_MGT
VCCA_MGT
GNDA4 GNDA6 GNDA7 GNDA9
GNDA21 GNDA19 GNDA18 GNDA16
AVCCAUXTX6 AVCCAUXTX7
18
E
5
F
B
C
7
c ET-Nikhef Amsterdam
Proj.No:
Date
Time
9
H
6
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
7 17
SDRAM_A(12) is not connected
L
1
J
11
A
of
G
NIKHEF
8
Proj:
K
8
2
16
I
163 5 14
Rev
E
17
9
18
1 10
H
4
Size
15
15
C
D
J
K
L
A
G
4
D
12
I
10
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:29 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
5 6
11 12
KRUISLAAN 409, 020-592 2000
13
2
1098 SJ AMSTERDAM NEDERLAND
6
F
Dim
Page
B
3
Name
13 14
8
GND
GND
channel_in
Buffer Memory (ZBT and SDRAM)
MROD-X 38405
9
21
22
32
GND
GND
4 1
GND
GND
8
C3142
22n
4K7
R3012
4K7
R3012
C3159
22n
4K7
R3012
C3141
22n
R3012
4K7
31
8
9
10
C3146
100n
13
GND
GND
GND
0
GND
GND
25
GND
C3144
22n
GND
6
3
GND
0
23
GND
GND
16
18
GNDGND
1
GND
2
13
15
GND GND
GND
29
30
20
9
GND
15
5
28
GND
6
7
C3162
100n
3
4
GND
30
11
GND
C3148
100n
GND
GND
GND
3 2
14
15
GND
14
19
12
GND
24
GND
GND
3
26
GND
9
16
33
7
2
GND
GND
GND
GND
GND
GND
GND
0
GND
7
16
GND
25
GND
11
10
11
0
12
4
31
27
24
19
GND
GND
35
GND
2
3
GND
17
18
VssQ438
VssQ546
VssQ652
78VssQ7
VssQ884
18_CAS
20_CS
_RAS19
17_WE
C3134
22n
49
VddQ655
VddQ775
81VddQ8
Vss144
Vss258
Vss372
86Vss4
VssQ16
VssQ212
32VssQ3
NC570
NC673
Vdd11
Vdd215
Vdd329
Vdd443
VddQ13
VddQ29
VddQ335
VddQ441
VddQ5
DQ713
DQ874
DQ976
DQM016 71
DQM1
DQM228
DQM359
NC114
NC230
NC357
69NC4
47
DQ2648
DQ2750
DQ2851
53DQ29
DQ37
DQ3054
56DQ31
DQ48
DQ510
11DQ6
85
DQ1631
DQ1733
DQ1834
DQ1936
DQ25
DQ2037
DQ2139
DQ2240
DQ2342
DQ2445
DQ25
23BA1
CKE67
CLK68
DQ02
4DQ1
DQ1077
DQ1179
80DQ12
DQ1382
DQ1483
DQ15
24
A1121
A227
A360
A461
A562
A663
A764
A865
A966
BA022
100n
27
28
MT48LC8M32B2
IC3007
A025
A126
A1010
5
6
7
C3152
22n
C3147
C3135
22n
1
2
GND
GND
GND
1
C3157
22n
GND
14
17
10
1
11
C3165
100n
C3156
22n
0
13
100n
C3164
C3161
22n
_BW4
_CE1
98
92
_CE2
_CEN
87
31
_LBO
_OE
86
C3158
22n
12
21VSS4
26VSS5
40
VSS6
55VSS7
VSS860
67VSS9
64ZZ
_BW1
93
94
_BW2
_BW3
95
96
16VDD5
20VDD6
27VDD7
VDD8
41
54VDD9
5VSS1
VSS1071
76VSS11
90
VSS12
VSS210
VSS317
VDD14
61VDD10
VDD1165
66VDD12
VDD1370
VDD1477
VDD15
91
11VDD2
VDD314
15VDD4
68IO8
69IO9
IOp151
IOp280
IOp31
IOp430
R_W
88
TCK
43
39
TDI
42
TDO
TMS
38
22
IO2723
24IO28
IO2925
57IO3
28IO30
29IO31
IO458
59IO5
IO662
IO763
IO16
IO173
6IO18
IO197
IO256
IO208
9IO21
12IO22
IO2313
18IO24
19IO25
IO2697
CE2
CLK
89
52IO0
IO153
72IO10
IO1173
74IO12
IO1375
78IO14
79IO15
2
83
84
A18
A2
35
A3
34
33
A4
32
A5
A6
100
99
A7
82
A8
81
A9
85
ADV_LD
IDT71V65603S100PF
IC3006
A0
37
36
A1
A10
44
A11
45
A12
46
A13
47
48
A14
A15
49
50
A16
A17
22n 22n
C3154
26
8
C3140
22n 22n
C3145
GND
C3138C3137
22n
5
22n
C3136
C3149
100n
GND
C3160
22n
C3143
C3153
22n
20
21
C3163
100n
22
0
4
5
22n
19
34
17
GND
6
GND
GND
GND
29
GND
23
18
22n
1
GND
22n 22n
C3155C3139
22n
C3150
BufCE_n SDRAM_CLKZ50_NET_TYPE
Z50_NET_TYPE
SDRAM_CLKin
SDRAM_WE_n
SDRAM_RAS_n
SDRAM_CAS_n
C3151
3V3
Clkx2
BufR_W_n
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
SDRAM_CS_n
SDRAM_DQ(31:0)
SDRAM_DQM(3:0)
SDRAM_BA(1:0)
SDRAM_A(12:0)
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
BufD(35:0)
BufA(19:0)
3V3
3V3
3V3
3V3
3V3
SDRAM_CKE
c
3
7
7
Answer Record #18562
14
Input Channel ID bits
10 17
K
GND
E
H
5
configuration. See Xilinx PROM Errata,
Testpoints force Spare
lines to be accessible.I
18
arc242 package
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
L
FPGA JTAG Signals
12
Temperature sensing diode
6
0 1 1 Master SelectMAP
12
0
It may be necessary to use Master SelectMap
3
I
HSWAP_EN = ’0’ => User IOs have pull-up
A
E
CLK
FPGA Configuration Signals
2
Default configuration mode will be Slave SelectMAP.
17
16
Connector
1
J J
Page
NATIONAAL INSTITUUT VOOR KERN-
H
PWRDWN_B is unsupported (should be pulled high)
Optinal Test
G
8
Clock Signals
16
chains where the same bitstream is loaded into multiple devices.
11
1098 SJ AMSTERDAM NEDERLAND
1
F
is no possibility for readback (RDWR_B = ’0’)
8 Input channels are loaded in parallel so there
Time
Dim
2
Proj:
9
to Master SelectMap and all other MROD-In FPGAs
to Slave SelectMap.
B
Size
Rocket IO Signals
15
Proj.No:
Rev
1 0 1 Boundary scan
’On’ = ’1’, ’Off’ = ’0’
13 18
Note: FCC_SelectMAP = 50 MHz so CCLK < 50 MHz!
M2 M1 M0
1 1 0 Slave SelectMAP (default)
6
D
14
-> Slave SlectMAP programming Mode -> BUSY.
15
13
Date
Name
See "Virtex-II Pro FPGA User Guide", Chapter 4 -> Configuration
F
FPGA Control signals
Cand each CS_B = ’0’
A
of
154
8
C
9
11
In this case set MROD-Out FPGA and one MROD-In FPGA
TTC Signals
NIKHEF
Pull-Ups
3
resistors during configuration
ET-Nikhef Amsterdam
K
5
4
B
2
1
D
L
G
10
66
420 x 297 mm
4 1 4 AA3
Ton van Reen
1:53:04 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405 MROD-X
Input FPGA Auxiliary Connections
channel_in
VBATT is decriptor key memory backup supply
Sharc Signals Frontend to Backend
DOUT is BUSY in SelectMAP mode and BUSY should NOT be used for parallel
1
0
6
GND
15
9
Fiducial3002
22n
C3168
NC7SZ08
IC3012
1
2
3
5
4
2n2
C3171
J2A 2
GND
2
U3_2A
U2_2A
1
2
3
5
4
0E0
R3026
NC7SZ00
IC3009
1
2
3
5
4
NC7SZ00
IC3011
C3166
22n
R3027
1K0
Fiducial3001
J2A 12
GND
Sw2A
17
180
R3013
GND
3
2
0
J2A 15
12
J2A
NC7SZ00
IC3010
1
2
3
5
4
SMD_LED_Red
D3002
J2A 16
GND
J2A 5
GND
GND
13
4
3
0
J2A 4
J2A 18
J2A 19
1K0
R3019
3
GND
GND
5
20
R30231K0
U1_2A
J2A
J2A 13
GND
1
2
J2A
R3015
J2A 8
4K7
R3025
180
R3024
D3004
SMD_LED_Green
180
R3025
Sw2A
D3001
SMD_LED_Red
ADD12
4DXN
5DXP
GND
3
SMBCLK8
SMBDATA9
VCC
6
10_ALERT
_STBY7
4K7
6
100n
C3172
GND
IC3013
MAX1618
1ADD0
11R3025
4K7
J2A
R30181K0
J2A 10
J2A
J2A 1
GND
SMD_LED_Green
D3003
Sw2A
J2A 7
R3020
NC7SZ00
IC3008
1
2
3
5
4
U4_2A
14
1K0
7
GND
10
4
R30224K7
6
5
GND
180
R3016 8
1
14
U0_2A
C3170
22n
R3021
180
R3014
J2A
GND
1K0
22n
C3167
7
GND
11GND
3
1K0
R3017
GND
GND
4
Spare(4:0)
J2A 9
22n
C3169
GND
CS_B
VCCAUXPWRDWN_B
CCLKCCLK
HSWAP_EN
PROG_BPROG_B
DXP
DXN
SMBClk
3V3
M2 M1
VCCAUX
M0
Spare(4:0)
Clk
TestCon(15:0)
3V3
3V3
3V3
3V3
T_Alert_n
SMBData
DOUT
INIT_BINIT_B
DONEDONE
D7
D6
D5
D4
D3
D2
D1
D0 D(7:0)
RDWR_B
3V3
ChaBusy ChaBusy
TTC_n(7:0)TTC_n(7:0)
ChaID(2:0)ChaID(2:0)
TCK
TDO
FPGA_TCK
FPGA_TMS
TDI FPGA_TDI
FPGA_TDO
Clk Clk
Clkx2Clkx2
LHC_ClkLHC_Clk
Rocket_XClk Rocket_XClk
Adr(21:0)Adr(21:0)
IRQ1_n IRQ1_n
IRQ2_n IRQ2_n
Empty Empty
DMAR_n DMAR_n
Rocket_RXPRocket_RXP
Rocket_RXN Rocket_RXN
Rocket_TXPRocket_TXP
Rocket_TXNRocket_TXN
A21_SelectA21_Select
TMS
3V3
LEDs(0)
LEDs(1)
LEDs(2)
LEDs(3)
General_Rst_n
Channel_Rst_n
Rst_n
VBATT
IRQ0_n IRQ0_n
Data(31:0) Data(31:0)
MS0_n MS0_n
MS1_nMS1_n
MS2_n MS2_n
MS3_nMS3_n
SharcRd_nSharcRd_n
SharcWr_n SharcWr_n
H
I
9
15 16 17
C
14
I
J
G
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1
Name
Size
Dim
K
L
3
Date
Time
of
4
10u Tantalum
AVX TAJB106K010R
J
13
13
10
D
62 107 8
5 15 16 17
C
11 12
D
14
B
11 12
NIKHEF
7 863 4
Page
E
F
E
F
A
H
18
G
V2
7 Feb 2006
1:50:33 pm
tonvr
A3 4 1 4 A
420 x 297 mm
1 6
GOL_MOD_DEF and GOL_TX_Fault
Signal Pull-ups in one
arc242 package
1098 SJ AMSTERDAM NEDERLANDET-Nikhef Amsterdam
B
5
Rev
c
K
1 2
L
A
9
Proj: Proj.No:
18
GND
channel_in
GOL Input
MROD-X 38405
Peter Jansweijer [email protected]
2
2
3
5
4
10u
C4002
R4002180
R4001180
IC4002
NC7SZ00
1
2
3
5
4
GND
C4007
22n
GND
GND4GND4
GND5GND5
GND6GND6
GND7GND7
GND8
GND8
GND9
GND9
GND
IC4003
NC7SZ00
1
GND12
GND13GND13
GND14GND14
GND15GND15
GND16GND16
GND17GND17
GND18
GND18
GND19
GND19
GND2GND2
GND20
GND20
GND3GND3
C4001
SFPT_cage
IC4001
GND1GND1
GND10
GND10
GND11GND11
GND12
4K7
GND
GND
GND
100n
1u
L4002
R4004
D2B
k_r
a_r
GND GND
L4001
1u
100n
C4004
D2B
Fr_LED_Gn
k_g
a_g
Fr_LED_Rd
GND
GND
22n
C4006
C4003
100n
4K7
4K7
R4003R4003
4K7
20
mod_def06
mod_def15
mod_def24
4K7
R4003R4003
Tx_disable3
Tx_fault2
VccR
15
VccT
16
VeeR1
9
VeeR2
10
VeeR3
11
14
VeeR4
VeeT1
1
VeeT2
17
VeeT3
IC4001
HFBR5720
LOS8
RD_n12 S
RD_p13 S
Rate_Sel7
TD_n19 T
TD_p18 T
GOL_XClk GOL_XClk
3V3
3V3
GOL_TX_Fault
GOL_MOD_DEF2
GOL_MOD_DEF1
GOL_MOD_DEF0
3V3
10u
C4005
GOL_RX_LOS
GOL_RXNGOL_LVDSGOL_LVDS
GOL_RXPGOL_LVDSGOL_LVDS
GOL_RATE_SEL
GOL_TXPGOL_LVDSGOL_LVDS
GOL_TX_Disable
ErrLED
UpLED
GOL_TXNGOL_LVDSGOL_LVDS
10 11 12 13
G
H
3 4
G
II
J
Date
2
VCCO_# (3V3) 10 pins each
12
Proj: Proj.No:
Rev
Size
A
Dim
1 3 6 7
7
NIKHEF
1
C
D
Input FPGA Power pins:
c ET-Nikhef Amsterdam
2
16
L
J
K
14
9
Page
A
B
C
K
6 18
E
F
KRUISLAAN 409, 020-592 2000
1715
VCCAUX (2V5) 16 pins
VCCINT (1V5) 32 pins
D
of
15
Time
Name
H
5
E
tonvr
1:50:53 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
Input FPGA
channel_in
8 9 16
8 14 18
11
1098 SJ AMSTERDAM NEDERLAND
L
B
10 13
4 5
F
17
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
GND 124 pins
62
420 x 297 mm
4 1 4 AA3
Y6 Y7 Y8 Y9 Y23 Y24 Y25 Y26 Y27 Y28 Y29Y3 Y30Y4 Y5 Y13 Y14 Y15 Y16 Y17 Y18 Y19Y2 Y20 Y21 Y22
W4 W5 W6 W7 W8 W9
Y1 Y10 Y11 Y12
W21 W22 W23 W24 W25 W26 W27 W28 W29W3 W30W11 W12 W13 W14 W15 W16 W17 W18 W19W2 W20
V3 V30V4 V5 V6 V7 V8 V9
W1 W10
V2 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29V1 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19
U28 U29U3 U30U4 U5 U6 U7 U8 U9 U18 U19U2 U20 U21 U22 U23 U24 U25 U26 U27
T8 T9
U1 U10 U11 U12 U13 U14 U15 U16 U17
T26 T27 T28 T29T3 T30T4 T5 T6 T7 T16 T17 T18 T19T2 T20 T21 T22 T23 T24 T25
R6 R7 R8 R9
T1 T10 T11 T12 T13 T14 T15
R24 R25 R26 R27 R28 R29R3 R30R4 R5 R14 R15 R16 R17 R18 R19R2 R20 R21 R22 R23
P4 P5 P6 P7 P8 P9
R1 R10 R11 R12 R13
P22 P23 P24 P25 P26 P27 P28 P29P3 P30P12 P13 P14 P15 P16 P17 P18 P19P2 P20 P21
N3 N30N4 N5 N6 N7 N8 N9
P1 P10 P11
N20 N21 N22 N23 N24 N25 N26 N27 N28 N29N10 N11 N12 N13 N14 N15 N16 N17 N18 N19N2
M28 M29M3 M30M4 M5 M6 M7 M8 M9
N1
M19M2 M20 M21 M22 M23 M24 M25 M26 M27
L9
M1 M10 M11 M12 M13 M14 M15 M16 M17 M18
L26 L27 L28 L29L3 L30L4 L5 L6 L7 L8 L17 L18 L19L2 L20 L21 L22 L23 L24 L25
K7 K8 K9
L1 L10 L11 L12 L13 L14 L15 L16
K24 K25 K26 K27 K28 K29K3 K30K4 K5 K6 K15 K16 K17 K18 K19K2 K20 K21 K22 K23
J5 J6 J7 J8 J9
K1 K10 K11 K12 K13 K14
J22 J23 J24 J25 J26 J27 J28 J29J3 J30J4 J13 J14 J15 J16 J17 J18 J19J2 J20 J21
H30H4 H5 H6 H7 H8 H9
J1 J10 J11 J12
H20 H21 H22 H23 H24 H25 H26 H27 H28 H29H3 H11 H12 H13 H14 H15 H16 H17 H18 H19H2
G29G3 G30G4 G5 G6 G7 G8 G9
H1 H10
G19G2 G20 G21 G22 G23 G24 G25 G26 G27 G28G1 G10 G11 G12 G13 G14 G15 G16 G17 G18
F27 F28 F29F3 F30F4 F5 F6 F7 F8 F9 F17 F18 F19F2 F20 F21 F22 F23 F24 F25 F26
E8 E9
F1 F10 F11 F12 F13 F14 F15 F16
E25 E26 E27 E28 E29E3 E30E4 E5 E6 E7 E15 E16 E17 E18 E19E2 E20 E21 E22 E23 E24
D6 D7 D8 D9
E1 E10 E11 E12 E13 E14
D23 D24 D25 D26 D27 D28 D29D3 D30D4 D5 D13 D14 D15 D16 D17 D18 D19D2 D20 D21 D22
C4 C5 C6 C7 C8 C9
D1 D10 D11 D12
C21 C22 C23 C24 C25 C26 C27 C28 C29C3 C30C11 C12 C13 C14 C15 C16 C17 C18 C19C2 C20
B3 B30B4 B5 B6 B7 B8 B9
C1 C10
B2 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29B1 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19
AK27 AK28 AK29AK3 AK4 AK5 AK6 AK7 AK8 AK9
T
AK18
T
AK19
S
AK2 AK20
S
AK21 AK22 AK23 AK24 AK25 AK26
AJ8 AJ9
AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17
AJ25 AJ26 AJ27 AJ28 AJ29AJ3 AJ30AJ4 AJ5 AJ6 AJ7 AJ15 AJ16 AJ17 AJ18 AJ19AJ2 AJ20 AJ21 AJ22 AJ23 AJ24
AH6 AH7 AH8 AH9
AJ1 AJ10 AJ11 AJ12 AJ13 AJ14
AH23 AH24 AH25 AH26 AH27 AH28 AH29AH3 AH30AH4 AH5 AH13 AH14 AH15 AH16 AH17 AH18 AH19AH2 AH20 AH21 AH22
AG4 AG5 AG6 AG7 AG8 AG9
AH1 AH10 AH11 AH12
AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29AG3 AG30AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19AG2 AG20
AF3 AF30AF4 AF5 AF6 AF7 AF8 AF9
AG1 AG10
AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29AF1 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19
AE28 AE29AE3 AE30AE4 AE5 AE6 AE7 AE8 AE9 AE18 AE19AE2 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27
AD8 AD9
AE1 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17
AD26 AD27 AD28 AD29AD3 AD30AD4 AD5 AD6 AD7 AD16 AD17 AD18 AD19AD2 AD20 AD21 AD22 AD23 AD24 AD25
AC6 AC7 AC8 AC9
AD1 AD10 AD11 AD12 AD13 AD14 AD15
AC24 AC25 AC26 AC27 AC28 AC29AC3 AC30AC4 AC5 AC14 AC15 AC16 AC17 AC18 AC19AC2 AC20 AC21 AC22 AC23
AB4 AB5 AB6 AB7 AB8 AB9
AC1 AC10 AC11 AC12 AC13
AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29AB3 AB30AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19AB2 AB20 AB21
AA3 AA30AA4 AA5 AA6 AA7 AA8 AA9
AB1 AB10 AB11
AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19AA2
A27 A28 A29A3 A4 A5 A6 A7 A8 A9
AA1
T
A19
S
A2 A20
S
A21 A22 A23 A24 A25 A26
XC2VP7FF896
IC4004
A10 A11 A12 A13 A14 A15 A16 A17
T
A18
DP_GOL_RX2B
GOL_RXNVRP_2VCCAUX
DMAR_n
BufR_W_n
BufA(18)
SMBClkSMBDataT_Alert_n
Rst_n
GOL_LVDS
GOL_LVDS
DP_GOL_TX2B
GOL_TXN
GOL_LVDS
GOL_LVDS
DP_GOL_TX2B
GOL_TXP
GOL_LVDS
GOL_LVDS
DP_GOL_RX2B
GOL_RXP
GOL_LVDSGOL_LVDS
SDRAM_A(4)SDRAM_A(5)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(16)Adr(15)Adr(14)Adr(13)Adr(12)Adr(11)
VCCAUXVRP_7LEDs(0)GNDVCCAUXVCCAUXGND
Adr(6)Adr(5)Adr(4)GND
SDRAM_A(6)SDRAM_A(7)SDRAM_A(8)SDRAM_A(9)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5IRQ2_nData(3)VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(10)Adr(9)Adr(8)Adr(7)
SDRAM_DQ(30)SDRAM_DQ(31)SDRAM_DQM(3)SDRAM_A(3)
Data(10)Data(15)D1PWRDWN_BAdr(3)Adr(2)
GNDSDRAM_CKESDRAM_A(12)SDRAM_DQM(1)M1M2D7TestCon(10)TestCon(9)TestCon(8)IRQ1_nData(2)Data(9)Data(11)Data(16)D0DONECCLK
Data(19)Data(23)INIT_BGND
GNDGNDEmptyData(0)Data(6)GNDData(14)Data(20)Data(24)Data(25)GND
SDRAM_DQ(8)SDRAM_DQ(9)M0D6TestCon(13)TestCon(12)TestCon(11)IRQ0_nData(1)Data(7)Data(8)
VRN_5GNDTTC_n(5)GNDChaBusyLHC_ClkSharcWr_nData(4)GNDData(12)GNDVRP_4D2DOUTAdr(1)GNDAdr(0)Data(31)Data(30)
GNDRDWR_BTTC_n(4)TTC_n(6)TTC_n(7)SDRAM_CLKSDRAM_CLKinData(5)Data(13)
GNDGNDA21D4VRP_5TTC_n(3)GNDA19GNDClkSharcRd_nGNDGNDA18Data(18)VRN_4D3GNDA16Data(29)Data(28)GNDData(27)Data(26)
SDRAM_DQ(10)SDRAM_DQ(11)SDRAM_DQ(12)GNDSDRAM_DQ(13)CS_BD5
AVCCAUXTX19VTRXPAD19AVCCAUXRX19Clkx2Rocket_XClkVTTXPAD18AVCCAUXTX18VTRXPAD18AVCCAUXRX18Data(17)Data(22)VTTXPAD16AVCCAUXTX16VTRXPAD16AVCCAUXRX16VRP_3GNDVCCAUX
SDRAM_DQ(14)SDRAM_DQ(15)
GND
ROCKET_LVDS
Rocket_TXN
ROCKET_LVDS
Rocket_TXP
ROCKET_LVDS
Rocket_RXP
ROCKET_LVDS
Rocket_RXNVCCAUXVCCAUXGNDData(21)VRN_3VCCAUX
VCCAUXGNDVRP_6VTTXPAD21AVCCAUXTX21VTRXPAD21AVCCAUXRX21TTC_n(1)TTC_n(2)VTTXPAD19
VTTXPAD6AVCCAUXTX6VTRXPAD6AVCCAUXRX6GOL_XClkVTTXPAD7AVCCAUXTX7VTRXPAD7AVCCAUXRX7VTTXPAD9AVCCAUXTX9VTRXPAD9AVCCAUXRX9VRN_2GNDVCCAUX
VCCAUXVRN_6TTC_n(0)
BufCE_nGNDBufA(7)BufA(6)GNDA4LEDs(3)LEDs(2)GNDA6UpLEDGNDGNDGNDA7GNDA9GND
VCCAUXGNDVRN_7VTTXPAD4AVCCAUXTX4VTRXPAD4AVCCAUXRX4LEDs(1)
GOL_TX_FaultVRP_1VRN_1GND
BufD(33)GNDBufD(16)DXNChaID(0)ChaID(1)GNDGOL_MOD_DEF0GOL_MOD_DEF1GNDErrLEDGOL_TX_DisableGOL_RX_LOSGNDGNDGND
BufA(19)
PROG_BTestCon(2)TestCon(3)TestCon(4)TestCon(5)TestCon(6)TCK
TDIGNDTestCon(0)TestCon(1)GNDGNDGNDTDO
GNDVRP_0VRN_0ChaID(2)GOL_RATE_SELGOL_MOD_DEF2
BufD(25)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2TestCon(14)
GNDBufD(19)DXPHSWAP_ENTestCon(7)TestCon(15)TMSVBATTGND
BufD(17)BufD(18)
BufD(26)BufD(27)BufD(28)BufD(29)BufD(30)BufD(31)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2
BufD(20)BufD(21)BufD(22)BufD(23)BufD(24)
GNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufD(32)BufA(5)GNDBufA(4)BufA(3)GNDVCCO_7VCCO_7GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_2VCCO_2GNDGND
VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufA(2)BufA(1)BufA(0)BufA(10)BufA(11)BufA(12)BufA(13)BufA(14)VCCO_7VCCO_7VCCINTGNDGNDGND
BufD(11)BufD(12)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2GND
BufA(15)BufA(16)BufD(35)BufD(0)BufD(1)BufD(2)BufD(3)BufD(4)VCCO_7VCCO_7
BufA(9)BufA(8)BufA(17)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCAUX
BufD(5)BufD(6)BufD(7)BufD(8)BufD(9)GNDBufD(10)
SDRAM_DQ(4)SDRAM_DQ(5)SDRAM_DQ(6)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3Spare(0)Spare(1)Spare(2)Spare(3)Spare(4)VCCAUX
VCCAUXBufD(13)BufD(14)BufD(15)BufD(34)
SDRAM_RAS_nGNDSDRAM_CS_nSDRAM_A(11)SDRAM_BA(0)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3GND
VCCAUXSDRAM_DQ(0)SDRAM_DQ(1)SDRAM_DQ(2)SDRAM_DQ(3)
SDRAM_A(0)SDRAM_A(1)SDRAM_A(2)SDRAM_DQM(2)SDRAM_DQ(16)SDRAM_DQ(17)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3A21_Select
SDRAM_DQ(7)SDRAM_DQM(0)SDRAM_WE_nSDRAM_CAS_n
SDRAM_DQ(21)SDRAM_DQ(22)SDRAM_DQ(23)SDRAM_DQ(24)SDRAM_DQ(25)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3MS3_nMS2_nMS1_nMS0_nAdr(21)
SDRAM_BA(1)SDRAM_A(10)
SDRAM_DQ(26)SDRAM_DQ(27)GNDSDRAM_DQ(28)SDRAM_DQ(29)GNDVCCO_6VCCO_6GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_3VCCO_3GNDAdr(20)Adr(19)GNDAdr(18)Adr(17)
SDRAM_DQ(18)SDRAM_DQ(19)SDRAM_DQ(20)
XC2VP7/20 VCCINT Decoupling Capacitors
FYSICA EN HOGE ENERGIE-FYSICA
IccINT = 600 mA
Dim
A
B
C
18
A
173
K
13
Date
15 16 17 18
AVX TAJB476K010R
11
IccAUX = 250 mA (min)
ET-Nikhef Amsterdam
VCCAUX and VCCO can ramp up at any rate
3
Proj.No:
1
4
AVX TAJB476K010R
2
D
Rev
L
E
F
For Xilinx Virtex-II Pro, power supplies
can be turned on in any sequence.
8
Proj:
7
6 7
VCCINT Ramp rate 200 us min. and 50 ms max.
NIKHEFof
G
14
Pagec
K
L
Min. Power-On Current XC2VP20
Min. Power-On Current XC2VP20
G
H
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Name
Size
9 10 11 12 13
14
I
J
10
B
E
5
16
XC2VP7/20 VCCAUX Decoupling Capacitors
NATIONAAL INSTITUUT VOOR KERN-
Power Inputs
1:51:34 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
3 6
9 12
4
1
15
AVX TAJB476K010R
AVX TAJB476K010R
8
F
2
C
D
All GND nets on the FPGA need
to be connected to golbal GROUND.
6
5
Time
J
I
H
22n
C4046
GND
channel_in
Input FPGA Power Supply Decoupling
MROD-X 38405
Peter Jansweijer [email protected]
2V2
7 Feb 2006
680p
C4040
GND
47u
C4097
GND
680p
C4009
GND
GND
C4045
22n
GND
C4096
47u
22n
C4083
GND
C4084
22n
GND
C4050
22n 22n
C4052
GND
C4090
100n
GND
100n
C4095
GND
GND
680p
C4067
GND
GND
680p
C4044
GNDC4082
680p
680p
22n
C4079
GND
680p680p
C4071
GND
GND
C4008
GND
680p
C4087
C4072
GND
C4014
680p
C4041
680p
22n
C4047
22n
C4059
GND
C4039
680p
GND
GND
C4053
100n
C4055
47u
GND
GND
GND
GND
C4018
680p
680p
C4061
GND
GND
22n
C4024
22n
C4069
GND
GND
C4062
680p
GND
GND
GND
C4025
22n
C4043
680p
GND
C4051
22n
GNDGND
C4048
22n
C4023
22n
GND
680p
C4077
GND
GND GND
GND
C4022
22n
47u
C4035
C4016
680p
GND
C4019
22n
GND
680p
C4081
GND
100n
C4075
GND
GND
C4033
C4086
680p
C4068
22n
22n
C4049
C4092
680p
GND
100n
GND
GND
C4076
680p
GND
GND
680p
C4042
C4078
22n
GND
C4036
47u
C4030
100n
680p
C4017
GND
C4066
680p
GND
GND
GND
22n
C4073
GND
C4064
22n
GND
C4094
22n
GND
C4037
680p
C4028
22n
GND
GND
680p
C4015
22n
C4020
C4070
100n
680p
C4013
680p
C4091
GND
GND
100n
C4054
GND
100n
C4085
C4080
100n
680p
C4038
GNDGND
C4060
100n
GND
22n
C4021
C4058
22n
GND
100n
C4065
GND
C4012
680p
GND
GND
GND
GND
C4074
22n
C4056
680p
22n
C4093
GND
C4010
680p
22n
C4063
680p
C4057
GND
GND
C4088
22n
GND
680p
C4011
GND
GND
GND
GND
22n
C4089
C4034
100n
GND
100n
C4029
GND
GND
C4031
100n
GND
100n
C4032
22n
C4026
GND
22n
C4027
GND
1V5POWER_NET_TYPE
VCCINT
VCCINT
2V5POWER_NET_TYPE
VCCAUX
VCCAUX
POWER_NET_TYPE
3V33V3
3V3
POWER_NET_TYPE
GND
GND
GND
GND
VCCO_0
VCCO_1
VCCO_2
VCCO_4
VCCO_5
VCCO_6
VCCO_7
VCCO_3
2V5 @ 1,5A
Proj:
97
c ET-Nikhef Amsterdam
142
Buffer Memory interface
L
AVX TAJB476K010R
=> MGT Power (estimated 31 + 49 = 80 mA)
G
K
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
10
Series Termination for
3 5 131210
NIKHEF
Name
Series Termination for
Date
H
2 15
KRUISLAAN 409, 020-592 2000
16
Not (yet) used
H
General purpose
1
Size
PAD6 connected to GOL
PAD19 connected to MROD-Out FPGA
DC coupled
4
Not (yet) used
Series Termination for
L
1
AC coupled
Note: VT1V8_MGT is common to all MROD-Ins
11 14
General purpose
G
9
17 18
A
15
of
E
F
4
=> MGT TX (RX) Termination (estimated 11 mA)
1098 SJ AMSTERDAM NEDERLAND
Sharc Databus
Time
18
B
C C
J
I
Proj.No:
Series Termination for
3
D
6
6
13
SDRAM interface
B
K
Series Termination for
A
D
Series Termination for
I
J
Series Termination for
E
16
11 12
7
Sharc Addressbus
Series Termination for
17
Rev
8
channel_in
Input FPGA MGT Pwr Decoupling, Termination
MROD-X 38405
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:01 pm
tonvr
A3 4 1 4 A
420 x 297 mm
4 6
AVX TAJB476K010R
5
F
Page
Dim
8
GND
R4028
1M
1u
L4004
GND
L4018
1u
R4011
47
47
R4009
GND
L4019
1u
L4033
1u
GND GND
L4014
1u
C4100
100n
GND
2%
100 R4006
1u
L4021
GND
GND
GND
GND
GNDGND
GND
GND
L4022
1u
GND
GND
GND
220n
C4111
L4029
1u
C4101
47u
C4113
220n
GND
GND
GND GND
GND
R4009
47
GNDGND
GND
GND
C4115
220n
GND
GND
GND
GND2TAB
2IN OUT
4
5S_A
1_SHDN
47
R4009
0E01u
L4012
LT1963A_DD
IC4005
3GND1
GND
R4011
47
R4029
R4011
47
C4131
220n
GND
220n
C4104
C4129
220n
GND
GND
GND
C4133
220n
GND
GND
GND
GND
GND GND
L4025
1u
L4027
1u
C4118
GND
GND
L4009
1u
R4007
95E3
2%
220n
R4009
47
L4017
1u
GND GND
GND
C4108
220n
GND
1u
L4007
R4010
47
C4105
220n
C4123
220n
R4005
4K7
L4031
1u
1u
220n
C4116
C4107
220n
C4125
220n
C4124
220n
GND
L4026
L4010
1u
220n
C4120
GND
C4110
220n
C4103
220n
GND
C4109
220n
220n
C4102
GND
220n
C4112
C4127
220n
GND
47
R4008
C4098
47u
GND
R4008
47
C4119
220n
GND
C4117
220n
L4024
1u
L4020
1u
L4016
1u
L4015
1u1u
L4013
C4106
220n
R4008
47
1u
L4023
1u
GND
1u
L4011
C4121
220n
L4005
1u
L4030
C4099
100n
R4010
47
R4008
47
L4006
1u
C4126
220n
1u
L4003
L4032
1u1u
C4122
220n
R4011
47
L4034
1u
L4008
1u
L4028
R4010
47
47
R4010
C4114
220n
C4128
220n
GND
C4132
220n
VTRXPAD7VTRXPAD6VTRXPAD4
VT2V5_MGT
VT2V5_MGT
VT1V8_MGT
AVCCAUXTX4
VTTXPAD4
VRN_7
VRP_7
C4130
220n
VRN_4
3V3
VRP_4
VRN_5
3V3
VRP_5
VRN_6
3V3
VRP_6
3V3
VCCA_MGTPOWER_NET_TYPE
3V3
VTRXPAD9
VTRXPAD19 VTRXPAD18 VTRXPAD16
VRN_0
3V3
VRP_0
VRN_1
3V3
VRP_1
VRN_2
3V3
VRP_2
VRN_3
3V3
VRP_3
AVCCAUXTX18 AVCCAUXTX16
AVCCAUXRX16AVCCAUXRX18AVCCAUXRX19AVCCAUXRX21
VTTXPAD21 VTTXPAD19 VTTXPAD18 VTTXPAD16
VTRXPAD21
AVCCAUXTX9
AVCCAUXRX9AVCCAUXRX7AVCCAUXRX6AVCCAUXRX4
VTTXPAD6 VTTXPAD7 VTTXPAD9
AVCCAUXTX21 AVCCAUXTX19
POWER_NET_TYPE
VT2V5_MGT
VCCA_MGT
VCCA_MGT
GNDA4 GNDA6 GNDA7 GNDA9
GNDA21 GNDA19 GNDA18 GNDA16
AVCCAUXTX6 AVCCAUXTX7
18
E
5
F
B
C
7
c ET-Nikhef Amsterdam
Proj.No:
Date
Time
9
H
6
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
7 17
SDRAM_A(12) is not connected
L
1
J
11
A
of
G
NIKHEF
8
Proj:
K
8
2
16
I
163 5 14
Rev
E
17
9
18
1 10
H
4
Size
15
15
C
D
J
K
L
A
G
4
D
12
I
10
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:29 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
5 6
11 12
KRUISLAAN 409, 020-592 2000
13
2
1098 SJ AMSTERDAM NEDERLAND
6
F
Dim
Page
B
3
Name
13 14
8
GND
GND
channel_in
Buffer Memory (ZBT and SDRAM)
MROD-X 38405
9
21
22
32
GND
GND
4 1
GND
GND
8
C4142
22n
4K7
R4012
4K7
R4012
C4159
22n
4K7
R4012
C4141
22n
R4012
4K7
31
8
9
10
C4146
100n
13
GND
GND
GND
0
GND
GND
25
GND
C4144
22n
GND
6
3
GND
0
23
GND
GND
16
18
GNDGND
1
GND
2
13
15
GND GND
GND
29
30
20
9
GND
15
5
28
GND
6
7
C4162
100n
3
4
GND
30
11
GND
C4148
100n
GND
GND
GND
3 2
14
15
GND
14
19
12
GND
24
GND
GND
3
26
GND
9
16
33
7
2
GND
GND
GND
GND
GND
GND
GND
0
GND
7
16
GND
25
GND
11
10
11
0
12
4
31
27
24
19
GND
GND
35
GND
2
3
GND
17
18
VssQ438
VssQ546
VssQ652
78VssQ7
VssQ884
18_CAS
20_CS
_RAS19
17_WE
C4134
22n
49
VddQ655
VddQ775
81VddQ8
Vss144
Vss258
Vss372
86Vss4
VssQ16
VssQ212
32VssQ3
NC570
NC673
Vdd11
Vdd215
Vdd329
Vdd443
VddQ13
VddQ29
VddQ335
VddQ441
VddQ5
DQ713
DQ874
DQ976
DQM016 71
DQM1
DQM228
DQM359
NC114
NC230
NC357
69NC4
47
DQ2648
DQ2750
DQ2851
53DQ29
DQ37
DQ3054
56DQ31
DQ48
DQ510
11DQ6
85
DQ1631
DQ1733
DQ1834
DQ1936
DQ25
DQ2037
DQ2139
DQ2240
DQ2342
DQ2445
DQ25
23BA1
CKE67
CLK68
DQ02
4DQ1
DQ1077
DQ1179
80DQ12
DQ1382
DQ1483
DQ15
24
A1121
A227
A360
A461
A562
A663
A764
A865
A966
BA022
100n
27
28
MT48LC8M32B2
IC4007
A025
A126
A1010
5
6
7
C4152
22n
C4147
C4135
22n
1
2
GND
GND
GND
1
C4157
22n
GND
14
17
10
1
11
C4165
100n
C4156
22n
0
13
100n
C4164
C4161
22n
_BW4
_CE1
98
92
_CE2
_CEN
87
31
_LBO
_OE
86
C4158
22n
12
21VSS4
26VSS5
40
VSS6
55VSS7
VSS860
67VSS9
64ZZ
_BW1
93
94
_BW2
_BW3
95
96
16VDD5
20VDD6
27VDD7
VDD8
41
54VDD9
5VSS1
VSS1071
76VSS11
90
VSS12
VSS210
VSS317
VDD14
61VDD10
VDD1165
66VDD12
VDD1370
VDD1477
VDD15
91
11VDD2
VDD314
15VDD4
68IO8
69IO9
IOp151
IOp280
IOp31
IOp430
R_W
88
TCK
43
39
TDI
42
TDO
TMS
38
22
IO2723
24IO28
IO2925
57IO3
28IO30
29IO31
IO458
59IO5
IO662
IO763
IO16
IO173
6IO18
IO197
IO256
IO208
9IO21
12IO22
IO2313
18IO24
19IO25
IO2697
CE2
CLK
89
52IO0
IO153
72IO10
IO1173
74IO12
IO1375
78IO14
79IO15
2
83
84
A18
A2
35
A3
34
33
A4
32
A5
A6
100
99
A7
82
A8
81
A9
85
ADV_LD
IDT71V65603S100PF
IC4006
A0
37
36
A1
A10
44
A11
45
A12
46
A13
47
48
A14
A15
49
50
A16
A17
22n 22n
C4154
26
8
C4140
22n 22n
C4145
GND
C4138C4137
22n
5
22n
C4136
C4149
100n
GND
C4160
22n
C4143
C4153
22n
20
21
C4163
100n
22
0
4
5
22n
19
34
17
GND
6
GND
GND
GND
29
GND
23
18
22n
1
GND
22n 22n
C4155C4139
22n
C4150
BufCE_n SDRAM_CLKZ50_NET_TYPE
Z50_NET_TYPE
SDRAM_CLKin
SDRAM_WE_n
SDRAM_RAS_n
SDRAM_CAS_n
C4151
3V3
Clkx2
BufR_W_n
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
SDRAM_CS_n
SDRAM_DQ(31:0)
SDRAM_DQM(3:0)
SDRAM_BA(1:0)
SDRAM_A(12:0)
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
BufD(35:0)
BufA(19:0)
3V3
3V3
3V3
3V3
3V3
SDRAM_CKE
c
3
7
7
Answer Record #18562
14
Input Channel ID bits
10 17
K
GND
E
H
5
configuration. See Xilinx PROM Errata,
Testpoints force Spare
lines to be accessible.I
18
arc242 package
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
L
FPGA JTAG Signals
12
Temperature sensing diode
6
0 1 1 Master SelectMAP
12
0
It may be necessary to use Master SelectMap
3
I
HSWAP_EN = ’0’ => User IOs have pull-up
A
E
CLK
FPGA Configuration Signals
2
Default configuration mode will be Slave SelectMAP.
17
16
Connector
1
J J
Page
NATIONAAL INSTITUUT VOOR KERN-
H
PWRDWN_B is unsupported (should be pulled high)
Optinal Test
G
8
Clock Signals
16
chains where the same bitstream is loaded into multiple devices.
11
1098 SJ AMSTERDAM NEDERLAND
1
F
is no possibility for readback (RDWR_B = ’0’)
8 Input channels are loaded in parallel so there
Time
Dim
2
Proj:
9
to Master SelectMap and all other MROD-In FPGAs
to Slave SelectMap.
B
Size
Rocket IO Signals
15
Proj.No:
Rev
1 0 1 Boundary scan
’On’ = ’1’, ’Off’ = ’0’
13 18
Note: FCC_SelectMAP = 50 MHz so CCLK < 50 MHz!
M2 M1 M0
1 1 0 Slave SelectMAP (default)
6
D
14
-> Slave SlectMAP programming Mode -> BUSY.
15
13
Date
Name
See "Virtex-II Pro FPGA User Guide", Chapter 4 -> Configuration
F
FPGA Control signals
Cand each CS_B = ’0’
A
of
154
8
C
9
11
In this case set MROD-Out FPGA and one MROD-In FPGA
TTC Signals
NIKHEF
Pull-Ups
3
resistors during configuration
ET-Nikhef Amsterdam
K
5
4
B
2
1
D
L
G
10
66
420 x 297 mm
4 1 4 AA3
Ton van Reen
1:53:04 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405 MROD-X
Input FPGA Auxiliary Connections
channel_in
VBATT is decriptor key memory backup supply
Sharc Signals Frontend to Backend
DOUT is BUSY in SelectMAP mode and BUSY should NOT be used for parallel
1
0
6
GND
15
9
Fiducial4002
22n
C4168
NC7SZ08
IC4012
1
2
3
5
4
2n2
C4171
J2B 2
GND
2
U3_2B
U2_2B
1
2
3
5
4
0E0
R4026
NC7SZ00
IC4009
1
2
3
5
4
NC7SZ00
IC4011
C4166
22n
R4027
1K0
Fiducial4001
J2B 12
GND
Sw2B
17
180
R4013
GND
3
2
0
J2B 15
12
J2B
NC7SZ00
IC4010
1
2
3
5
4
SMD_LED_Red
D4002
J2B 16
GND
J2B 5
GND
GND
13
4
3
0
J2B 4
J2B 18
J2B 19
1K0
R4019
3
GND
GND
5
20
R40231K0
U1_2B
J2B
J2B 13
GND
1
2
J2B
R4015
J2B 8
4K7
R4025
180
R4024
D4004
SMD_LED_Green
180
R4025
Sw2B
D4001
SMD_LED_Red
ADD12
4DXN
5DXP
GND
3
SMBCLK8
SMBDATA9
VCC
6
10_ALERT
_STBY7
4K7
6
100n
C4172
GND
IC4013
MAX1618
1ADD0
11R4025
4K7
J2B
R40181K0
J2B 10
J2B
J2B 1
GND
SMD_LED_Green
D4003
Sw2B
J2B 7
R4020
NC7SZ00
IC4008
1
2
3
5
4
U4_2B
14
1K0
7
GND
10
4
R40224K7
6
5
GND
180
R4016 8
1
14
U0_2B
C4170
22n
R4021
180
R4014
J2B
GND
1K0
22n
C4167
7
GND
11GND
3
1K0
R4017
GND
GND
4
Spare(4:0)
J2B 9
22n
C4169
GND
CS_B
VCCAUXPWRDWN_B
CCLKCCLK
HSWAP_EN
PROG_BPROG_B
DXP
DXN
SMBClk
3V3
M2 M1
VCCAUX
M0
Spare(4:0)
Clk
TestCon(15:0)
3V3
3V3
3V3
3V3
T_Alert_n
SMBData
DOUT
INIT_BINIT_B
DONEDONE
D7
D6
D5
D4
D3
D2
D1
D0 D(7:0)
RDWR_B
3V3
ChaBusy ChaBusy
TTC_n(7:0)TTC_n(7:0)
ChaID(2:0)ChaID(2:0)
TCK
TDO
FPGA_TCK
FPGA_TMS
TDI FPGA_TDI
FPGA_TDO
Clk Clk
Clkx2Clkx2
LHC_ClkLHC_Clk
Rocket_XClk Rocket_XClk
Adr(21:0)Adr(21:0)
IRQ1_n IRQ1_n
IRQ2_n IRQ2_n
Empty Empty
DMAR_n DMAR_n
Rocket_RXPRocket_RXP
Rocket_RXN Rocket_RXN
Rocket_TXPRocket_TXP
Rocket_TXNRocket_TXN
A21_SelectA21_Select
TMS
3V3
LEDs(0)
LEDs(1)
LEDs(2)
LEDs(3)
General_Rst_n
Channel_Rst_n
Rst_n
VBATT
IRQ0_n IRQ0_n
Data(31:0) Data(31:0)
MS0_n MS0_n
MS1_nMS1_n
MS2_n MS2_n
MS3_nMS3_n
SharcRd_nSharcRd_n
SharcWr_n SharcWr_n
H
I
9
15 16 17
C
14
I
J
G
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1
Name
Size
Dim
K
L
3
Date
Time
of
4
10u Tantalum
AVX TAJB106K010R
J
13
13
10
D
62 107 8
5 15 16 17
C
11 12
D
14
B
11 12
NIKHEF
7 863 4
Page
E
F
E
F
A
H
18
G
V2
7 Feb 2006
1:50:33 pm
tonvr
A3 4 1 4 A
420 x 297 mm
1 6
GOL_MOD_DEF and GOL_TX_Fault
Signal Pull-ups in one
arc242 package
1098 SJ AMSTERDAM NEDERLANDET-Nikhef Amsterdam
B
5
Rev
c
K
1 2
L
A
9
Proj: Proj.No:
18
GND
channel_in
GOL Input
MROD-X 38405
Peter Jansweijer [email protected]
2
2
3
5
4
10u
C5002
R5002180
R5001180
IC5002
NC7SZ00
1
2
3
5
4
GND
C5007
22n
GND
GND4GND4
GND5GND5
GND6GND6
GND7GND7
GND8
GND8
GND9
GND9
GND
IC5003
NC7SZ00
1
GND12
GND13GND13
GND14GND14
GND15GND15
GND16GND16
GND17GND17
GND18
GND18
GND19
GND19
GND2GND2
GND20
GND20
GND3GND3
C5001
SFPT_cage
IC5001
GND1GND1
GND10
GND10
GND11GND11
GND12
4K7
GND
GND
GND
100n
1u
L5002
R5004
D3A
k_r
a_r
GND GND
L5001
1u
100n
C5004
D3A
Fr_LED_Gn
k_g
a_g
Fr_LED_Rd
GND
GND
22n
C5006
C5003
100n
4K7
4K7
R5003R5003
4K7
20
mod_def06
mod_def15
mod_def24
4K7
R5003R5003
Tx_disable3
Tx_fault2
VccR
15
VccT
16
VeeR1
9
VeeR2
10
VeeR3
11
14
VeeR4
VeeT1
1
VeeT2
17
VeeT3
IC5001
HFBR5720
LOS8
RD_n12 S
RD_p13 S
Rate_Sel7
TD_n19 T
TD_p18 T
GOL_XClk GOL_XClk
3V3
3V3
GOL_TX_Fault
GOL_MOD_DEF2
GOL_MOD_DEF1
GOL_MOD_DEF0
3V3
10u
C5005
GOL_RX_LOS
GOL_RXNGOL_LVDSGOL_LVDS
GOL_RXPGOL_LVDSGOL_LVDS
GOL_RATE_SEL
GOL_TXPGOL_LVDSGOL_LVDS
GOL_TX_Disable
ErrLED
UpLED
GOL_TXNGOL_LVDSGOL_LVDS
10 11 12 13
G
H
3 4
G
II
J
Date
2
VCCO_# (3V3) 10 pins each
12
Proj: Proj.No:
Rev
Size
A
Dim
1 3 6 7
7
NIKHEF
1
C
D
Input FPGA Power pins:
c ET-Nikhef Amsterdam
2
16
L
J
K
14
9
Page
A
B
C
K
6 18
E
F
KRUISLAAN 409, 020-592 2000
1715
VCCAUX (2V5) 16 pins
VCCINT (1V5) 32 pins
D
of
15
Time
Name
H
5
E
tonvr
1:50:53 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
Input FPGA
channel_in
8 9 16
8 14 18
11
1098 SJ AMSTERDAM NEDERLAND
L
B
10 13
4 5
F
17
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
GND 124 pins
62
420 x 297 mm
4 1 4 AA3
Y6 Y7 Y8 Y9 Y23 Y24 Y25 Y26 Y27 Y28 Y29Y3 Y30Y4 Y5 Y13 Y14 Y15 Y16 Y17 Y18 Y19Y2 Y20 Y21 Y22
W4 W5 W6 W7 W8 W9
Y1 Y10 Y11 Y12
W21 W22 W23 W24 W25 W26 W27 W28 W29W3 W30W11 W12 W13 W14 W15 W16 W17 W18 W19W2 W20
V3 V30V4 V5 V6 V7 V8 V9
W1 W10
V2 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29V1 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19
U28 U29U3 U30U4 U5 U6 U7 U8 U9 U18 U19U2 U20 U21 U22 U23 U24 U25 U26 U27
T8 T9
U1 U10 U11 U12 U13 U14 U15 U16 U17
T26 T27 T28 T29T3 T30T4 T5 T6 T7 T16 T17 T18 T19T2 T20 T21 T22 T23 T24 T25
R6 R7 R8 R9
T1 T10 T11 T12 T13 T14 T15
R24 R25 R26 R27 R28 R29R3 R30R4 R5 R14 R15 R16 R17 R18 R19R2 R20 R21 R22 R23
P4 P5 P6 P7 P8 P9
R1 R10 R11 R12 R13
P22 P23 P24 P25 P26 P27 P28 P29P3 P30P12 P13 P14 P15 P16 P17 P18 P19P2 P20 P21
N3 N30N4 N5 N6 N7 N8 N9
P1 P10 P11
N20 N21 N22 N23 N24 N25 N26 N27 N28 N29N10 N11 N12 N13 N14 N15 N16 N17 N18 N19N2
M28 M29M3 M30M4 M5 M6 M7 M8 M9
N1
M19M2 M20 M21 M22 M23 M24 M25 M26 M27
L9
M1 M10 M11 M12 M13 M14 M15 M16 M17 M18
L26 L27 L28 L29L3 L30L4 L5 L6 L7 L8 L17 L18 L19L2 L20 L21 L22 L23 L24 L25
K7 K8 K9
L1 L10 L11 L12 L13 L14 L15 L16
K24 K25 K26 K27 K28 K29K3 K30K4 K5 K6 K15 K16 K17 K18 K19K2 K20 K21 K22 K23
J5 J6 J7 J8 J9
K1 K10 K11 K12 K13 K14
J22 J23 J24 J25 J26 J27 J28 J29J3 J30J4 J13 J14 J15 J16 J17 J18 J19J2 J20 J21
H30H4 H5 H6 H7 H8 H9
J1 J10 J11 J12
H20 H21 H22 H23 H24 H25 H26 H27 H28 H29H3 H11 H12 H13 H14 H15 H16 H17 H18 H19H2
G29G3 G30G4 G5 G6 G7 G8 G9
H1 H10
G19G2 G20 G21 G22 G23 G24 G25 G26 G27 G28G1 G10 G11 G12 G13 G14 G15 G16 G17 G18
F27 F28 F29F3 F30F4 F5 F6 F7 F8 F9 F17 F18 F19F2 F20 F21 F22 F23 F24 F25 F26
E8 E9
F1 F10 F11 F12 F13 F14 F15 F16
E25 E26 E27 E28 E29E3 E30E4 E5 E6 E7 E15 E16 E17 E18 E19E2 E20 E21 E22 E23 E24
D6 D7 D8 D9
E1 E10 E11 E12 E13 E14
D23 D24 D25 D26 D27 D28 D29D3 D30D4 D5 D13 D14 D15 D16 D17 D18 D19D2 D20 D21 D22
C4 C5 C6 C7 C8 C9
D1 D10 D11 D12
C21 C22 C23 C24 C25 C26 C27 C28 C29C3 C30C11 C12 C13 C14 C15 C16 C17 C18 C19C2 C20
B3 B30B4 B5 B6 B7 B8 B9
C1 C10
B2 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29B1 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19
AK27 AK28 AK29AK3 AK4 AK5 AK6 AK7 AK8 AK9
T
AK18
T
AK19
S
AK2 AK20
S
AK21 AK22 AK23 AK24 AK25 AK26
AJ8 AJ9
AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17
AJ25 AJ26 AJ27 AJ28 AJ29AJ3 AJ30AJ4 AJ5 AJ6 AJ7 AJ15 AJ16 AJ17 AJ18 AJ19AJ2 AJ20 AJ21 AJ22 AJ23 AJ24
AH6 AH7 AH8 AH9
AJ1 AJ10 AJ11 AJ12 AJ13 AJ14
AH23 AH24 AH25 AH26 AH27 AH28 AH29AH3 AH30AH4 AH5 AH13 AH14 AH15 AH16 AH17 AH18 AH19AH2 AH20 AH21 AH22
AG4 AG5 AG6 AG7 AG8 AG9
AH1 AH10 AH11 AH12
AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29AG3 AG30AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19AG2 AG20
AF3 AF30AF4 AF5 AF6 AF7 AF8 AF9
AG1 AG10
AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29AF1 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19
AE28 AE29AE3 AE30AE4 AE5 AE6 AE7 AE8 AE9 AE18 AE19AE2 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27
AD8 AD9
AE1 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17
AD26 AD27 AD28 AD29AD3 AD30AD4 AD5 AD6 AD7 AD16 AD17 AD18 AD19AD2 AD20 AD21 AD22 AD23 AD24 AD25
AC6 AC7 AC8 AC9
AD1 AD10 AD11 AD12 AD13 AD14 AD15
AC24 AC25 AC26 AC27 AC28 AC29AC3 AC30AC4 AC5 AC14 AC15 AC16 AC17 AC18 AC19AC2 AC20 AC21 AC22 AC23
AB4 AB5 AB6 AB7 AB8 AB9
AC1 AC10 AC11 AC12 AC13
AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29AB3 AB30AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19AB2 AB20 AB21
AA3 AA30AA4 AA5 AA6 AA7 AA8 AA9
AB1 AB10 AB11
AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19AA2
A27 A28 A29A3 A4 A5 A6 A7 A8 A9
AA1
T
A19
S
A2 A20
S
A21 A22 A23 A24 A25 A26
XC2VP7FF896
IC5004
A10 A11 A12 A13 A14 A15 A16 A17
T
A18
DP_GOL_RX3A
GOL_RXNVRP_2VCCAUX
DMAR_n
BufR_W_n
BufA(18)
SMBClkSMBDataT_Alert_n
Rst_n
GOL_LVDS
GOL_LVDS
DP_GOL_TX3A
GOL_TXN
GOL_LVDS
GOL_LVDS
DP_GOL_TX3A
GOL_TXP
GOL_LVDS
GOL_LVDS
DP_GOL_RX3A
GOL_RXP
GOL_LVDSGOL_LVDS
SDRAM_A(4)SDRAM_A(5)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(16)Adr(15)Adr(14)Adr(13)Adr(12)Adr(11)
VCCAUXVRP_7LEDs(0)GNDVCCAUXVCCAUXGND
Adr(6)Adr(5)Adr(4)GND
SDRAM_A(6)SDRAM_A(7)SDRAM_A(8)SDRAM_A(9)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5IRQ2_nData(3)VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(10)Adr(9)Adr(8)Adr(7)
SDRAM_DQ(30)SDRAM_DQ(31)SDRAM_DQM(3)SDRAM_A(3)
Data(10)Data(15)D1PWRDWN_BAdr(3)Adr(2)
GNDSDRAM_CKESDRAM_A(12)SDRAM_DQM(1)M1M2D7TestCon(10)TestCon(9)TestCon(8)IRQ1_nData(2)Data(9)Data(11)Data(16)D0DONECCLK
Data(19)Data(23)INIT_BGND
GNDGNDEmptyData(0)Data(6)GNDData(14)Data(20)Data(24)Data(25)GND
SDRAM_DQ(8)SDRAM_DQ(9)M0D6TestCon(13)TestCon(12)TestCon(11)IRQ0_nData(1)Data(7)Data(8)
VRN_5GNDTTC_n(5)GNDChaBusyLHC_ClkSharcWr_nData(4)GNDData(12)GNDVRP_4D2DOUTAdr(1)GNDAdr(0)Data(31)Data(30)
GNDRDWR_BTTC_n(4)TTC_n(6)TTC_n(7)SDRAM_CLKSDRAM_CLKinData(5)Data(13)
GNDGNDA21D4VRP_5TTC_n(3)GNDA19GNDClkSharcRd_nGNDGNDA18Data(18)VRN_4D3GNDA16Data(29)Data(28)GNDData(27)Data(26)
SDRAM_DQ(10)SDRAM_DQ(11)SDRAM_DQ(12)GNDSDRAM_DQ(13)CS_BD5
AVCCAUXTX19VTRXPAD19AVCCAUXRX19Clkx2Rocket_XClkVTTXPAD18AVCCAUXTX18VTRXPAD18AVCCAUXRX18Data(17)Data(22)VTTXPAD16AVCCAUXTX16VTRXPAD16AVCCAUXRX16VRP_3GNDVCCAUX
SDRAM_DQ(14)SDRAM_DQ(15)
GND
ROCKET_LVDS
Rocket_TXN
ROCKET_LVDS
Rocket_TXP
ROCKET_LVDS
Rocket_RXP
ROCKET_LVDS
Rocket_RXNVCCAUXVCCAUXGNDData(21)VRN_3VCCAUX
VCCAUXGNDVRP_6VTTXPAD21AVCCAUXTX21VTRXPAD21AVCCAUXRX21TTC_n(1)TTC_n(2)VTTXPAD19
VTTXPAD6AVCCAUXTX6VTRXPAD6AVCCAUXRX6GOL_XClkVTTXPAD7AVCCAUXTX7VTRXPAD7AVCCAUXRX7VTTXPAD9AVCCAUXTX9VTRXPAD9AVCCAUXRX9VRN_2GNDVCCAUX
VCCAUXVRN_6TTC_n(0)
BufCE_nGNDBufA(7)BufA(6)GNDA4LEDs(3)LEDs(2)GNDA6UpLEDGNDGNDGNDA7GNDA9GND
VCCAUXGNDVRN_7VTTXPAD4AVCCAUXTX4VTRXPAD4AVCCAUXRX4LEDs(1)
GOL_TX_FaultVRP_1VRN_1GND
BufD(33)GNDBufD(16)DXNChaID(0)ChaID(1)GNDGOL_MOD_DEF0GOL_MOD_DEF1GNDErrLEDGOL_TX_DisableGOL_RX_LOSGNDGNDGND
BufA(19)
PROG_BTestCon(2)TestCon(3)TestCon(4)TestCon(5)TestCon(6)TCK
TDIGNDTestCon(0)TestCon(1)GNDGNDGNDTDO
GNDVRP_0VRN_0ChaID(2)GOL_RATE_SELGOL_MOD_DEF2
BufD(25)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2TestCon(14)
GNDBufD(19)DXPHSWAP_ENTestCon(7)TestCon(15)TMSVBATTGND
BufD(17)BufD(18)
BufD(26)BufD(27)BufD(28)BufD(29)BufD(30)BufD(31)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2
BufD(20)BufD(21)BufD(22)BufD(23)BufD(24)
GNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufD(32)BufA(5)GNDBufA(4)BufA(3)GNDVCCO_7VCCO_7GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_2VCCO_2GNDGND
VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufA(2)BufA(1)BufA(0)BufA(10)BufA(11)BufA(12)BufA(13)BufA(14)VCCO_7VCCO_7VCCINTGNDGNDGND
BufD(11)BufD(12)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2GND
BufA(15)BufA(16)BufD(35)BufD(0)BufD(1)BufD(2)BufD(3)BufD(4)VCCO_7VCCO_7
BufA(9)BufA(8)BufA(17)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCAUX
BufD(5)BufD(6)BufD(7)BufD(8)BufD(9)GNDBufD(10)
SDRAM_DQ(4)SDRAM_DQ(5)SDRAM_DQ(6)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3Spare(0)Spare(1)Spare(2)Spare(3)Spare(4)VCCAUX
VCCAUXBufD(13)BufD(14)BufD(15)BufD(34)
SDRAM_RAS_nGNDSDRAM_CS_nSDRAM_A(11)SDRAM_BA(0)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3GND
VCCAUXSDRAM_DQ(0)SDRAM_DQ(1)SDRAM_DQ(2)SDRAM_DQ(3)
SDRAM_A(0)SDRAM_A(1)SDRAM_A(2)SDRAM_DQM(2)SDRAM_DQ(16)SDRAM_DQ(17)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3A21_Select
SDRAM_DQ(7)SDRAM_DQM(0)SDRAM_WE_nSDRAM_CAS_n
SDRAM_DQ(21)SDRAM_DQ(22)SDRAM_DQ(23)SDRAM_DQ(24)SDRAM_DQ(25)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3MS3_nMS2_nMS1_nMS0_nAdr(21)
SDRAM_BA(1)SDRAM_A(10)
SDRAM_DQ(26)SDRAM_DQ(27)GNDSDRAM_DQ(28)SDRAM_DQ(29)GNDVCCO_6VCCO_6GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_3VCCO_3GNDAdr(20)Adr(19)GNDAdr(18)Adr(17)
SDRAM_DQ(18)SDRAM_DQ(19)SDRAM_DQ(20)
XC2VP7/20 VCCINT Decoupling Capacitors
FYSICA EN HOGE ENERGIE-FYSICA
IccINT = 600 mA
Dim
A
B
C
18
A
173
K
13
Date
15 16 17 18
AVX TAJB476K010R
11
IccAUX = 250 mA (min)
ET-Nikhef Amsterdam
VCCAUX and VCCO can ramp up at any rate
3
Proj.No:
1
4
AVX TAJB476K010R
2
D
Rev
L
E
F
For Xilinx Virtex-II Pro, power supplies
can be turned on in any sequence.
8
Proj:
7
6 7
VCCINT Ramp rate 200 us min. and 50 ms max.
NIKHEFof
G
14
Pagec
K
L
Min. Power-On Current XC2VP20
Min. Power-On Current XC2VP20
G
H
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Name
Size
9 10 11 12 13
14
I
J
10
B
E
5
16
XC2VP7/20 VCCAUX Decoupling Capacitors
NATIONAAL INSTITUUT VOOR KERN-
Power Inputs
1:51:34 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
3 6
9 12
4
1
15
AVX TAJB476K010R
AVX TAJB476K010R
8
F
2
C
D
All GND nets on the FPGA need
to be connected to golbal GROUND.
6
5
Time
J
I
H
22n
C5046
GND
channel_in
Input FPGA Power Supply Decoupling
MROD-X 38405
Peter Jansweijer [email protected]
2V2
7 Feb 2006
680p
C5040
GND
47u
C5097
GND
680p
C5009
GND
GND
C5045
22n
GND
C5096
47u
22n
C5083
GND
C5084
22n
GND
C5050
22n 22n
C5052
GND
C5090
100n
GND
100n
C5095
GND
GND
680p
C5067
GND
GND
680p
C5044
GNDC5082
680p
680p
22n
C5079
GND
680p680p
C5071
GND
GND
C5008
GND
680p
C5087
C5072
GND
C5014
680p
C5041
680p
22n
C5047
22n
C5059
GND
C5039
680p
GND
GND
C5053
100n
C5055
47u
GND
GND
GND
GND
C5018
680p
680p
C5061
GND
GND
22n
C5024
22n
C5069
GND
GND
C5062
680p
GND
GND
GND
C5025
22n
C5043
680p
GND
C5051
22n
GNDGND
C5048
22n
C5023
22n
GND
680p
C5077
GND
GND GND
GND
C5022
22n
47u
C5035
C5016
680p
GND
C5019
22n
GND
680p
C5081
GND
100n
C5075
GND
GND
C5033
C5086
680p
C5068
22n
22n
C5049
C5092
680p
GND
100n
GND
GND
C5076
680p
GND
GND
680p
C5042
C5078
22n
GND
C5036
47u
C5030
100n
680p
C5017
GND
C5066
680p
GND
GND
GND
22n
C5073
GND
C5064
22n
GND
C5094
22n
GND
C5037
680p
C5028
22n
GND
GND
680p
C5015
22n
C5020
C5070
100n
680p
C5013
680p
C5091
GND
GND
100n
C5054
GND
100n
C5085
C5080
100n
680p
C5038
GNDGND
C5060
100n
GND
22n
C5021
C5058
22n
GND
100n
C5065
GND
C5012
680p
GND
GND
GND
GND
C5074
22n
C5056
680p
22n
C5093
GND
C5010
680p
22n
C5063
680p
C5057
GND
GND
C5088
22n
GND
680p
C5011
GND
GND
GND
GND
22n
C5089
C5034
100n
GND
100n
C5029
GND
GND
C5031
100n
GND
100n
C5032
22n
C5026
GND
22n
C5027
GND
1V5POWER_NET_TYPE
VCCINT
VCCINT
2V5POWER_NET_TYPE
VCCAUX
VCCAUX
POWER_NET_TYPE
3V33V3
3V3
POWER_NET_TYPE
GND
GND
GND
GND
VCCO_0
VCCO_1
VCCO_2
VCCO_4
VCCO_5
VCCO_6
VCCO_7
VCCO_3
2V5 @ 1,5A
Proj:
97
c ET-Nikhef Amsterdam
142
Buffer Memory interface
L
AVX TAJB476K010R
=> MGT Power (estimated 31 + 49 = 80 mA)
G
K
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
10
Series Termination for
3 5 131210
NIKHEF
Name
Series Termination for
Date
H
2 15
KRUISLAAN 409, 020-592 2000
16
Not (yet) used
H
General purpose
1
Size
PAD6 connected to GOL
PAD19 connected to MROD-Out FPGA
DC coupled
4
Not (yet) used
Series Termination for
L
1
AC coupled
Note: VT1V8_MGT is common to all MROD-Ins
11 14
General purpose
G
9
17 18
A
15
of
E
F
4
=> MGT TX (RX) Termination (estimated 11 mA)
1098 SJ AMSTERDAM NEDERLAND
Sharc Databus
Time
18
B
C C
J
I
Proj.No:
Series Termination for
3
D
6
6
13
SDRAM interface
B
K
Series Termination for
A
D
Series Termination for
I
J
Series Termination for
E
16
11 12
7
Sharc Addressbus
Series Termination for
17
Rev
8
channel_in
Input FPGA MGT Pwr Decoupling, Termination
MROD-X 38405
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:01 pm
tonvr
A3 4 1 4 A
420 x 297 mm
4 6
AVX TAJB476K010R
5
F
Page
Dim
8
GND
R5028
1M
1u
L5004
GND
L5018
1u
R5011
47
47
R5009
GND
L5019
1u
L5033
1u
GND GND
L5014
1u
C5100
100n
GND
2%
100 R5006
1u
L5021
GND
GND
GND
GND
GNDGND
GND
GND
L5022
1u
GND
GND
GND
220n
C5111
L5029
1u
C5101
47u
C5113
220n
GND
GND
GND GND
GND
R5009
47
GNDGND
GND
GND
C5115
220n
GND
GND
GND
GND2TAB
2IN OUT
4
5S_A
1_SHDN
47
R5009
0E01u
L5012
LT1963A_DD
IC5005
3GND1
GND
R5011
47
R5029
R5011
47
C5131
220n
GND
220n
C5104
C5129
220n
GND
GND
GND
C5133
220n
GND
GND
GND
GND
GND GND
L5025
1u
L5027
1u
C5118
GND
GND
L5009
1u
R5007
95E3
2%
220n
R5009
47
L5017
1u
GND GND
GND
C5108
220n
GND
1u
L5007
R5010
47
C5105
220n
C5123
220n
R5005
4K7
L5031
1u
1u
220n
C5116
C5107
220n
C5125
220n
C5124
220n
GND
L5026
L5010
1u
220n
C5120
GND
C5110
220n
C5103
220n
GND
C5109
220n
220n
C5102
GND
220n
C5112
C5127
220n
GND
47
R5008
C5098
47u
GND
R5008
47
C5119
220n
GND
C5117
220n
L5024
1u
L5020
1u
L5016
1u
L5015
1u1u
L5013
C5106
220n
R5008
47
1u
L5023
1u
GND
1u
L5011
C5121
220n
L5005
1u
L5030
C5099
100n
R5010
47
R5008
47
L5006
1u
C5126
220n
1u
L5003
L5032
1u1u
C5122
220n
R5011
47
L5034
1u
L5008
1u
L5028
R5010
47
47
R5010
C5114
220n
C5128
220n
GND
C5132
220n
VTRXPAD7VTRXPAD6VTRXPAD4
VT2V5_MGT
VT2V5_MGT
VT1V8_MGT
AVCCAUXTX4
VTTXPAD4
VRN_7
VRP_7
C5130
220n
VRN_4
3V3
VRP_4
VRN_5
3V3
VRP_5
VRN_6
3V3
VRP_6
3V3
VCCA_MGTPOWER_NET_TYPE
3V3
VTRXPAD9
VTRXPAD19 VTRXPAD18 VTRXPAD16
VRN_0
3V3
VRP_0
VRN_1
3V3
VRP_1
VRN_2
3V3
VRP_2
VRN_3
3V3
VRP_3
AVCCAUXTX18 AVCCAUXTX16
AVCCAUXRX16AVCCAUXRX18AVCCAUXRX19AVCCAUXRX21
VTTXPAD21 VTTXPAD19 VTTXPAD18 VTTXPAD16
VTRXPAD21
AVCCAUXTX9
AVCCAUXRX9AVCCAUXRX7AVCCAUXRX6AVCCAUXRX4
VTTXPAD6 VTTXPAD7 VTTXPAD9
AVCCAUXTX21 AVCCAUXTX19
POWER_NET_TYPE
VT2V5_MGT
VCCA_MGT
VCCA_MGT
GNDA4 GNDA6 GNDA7 GNDA9
GNDA21 GNDA19 GNDA18 GNDA16
AVCCAUXTX6 AVCCAUXTX7
18
E
5
F
B
C
7
c ET-Nikhef Amsterdam
Proj.No:
Date
Time
9
H
6
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
7 17
SDRAM_A(12) is not connected
L
1
J
11
A
of
G
NIKHEF
8
Proj:
K
8
2
16
I
163 5 14
Rev
E
17
9
18
1 10
H
4
Size
15
15
C
D
J
K
L
A
G
4
D
12
I
10
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:29 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
5 6
11 12
KRUISLAAN 409, 020-592 2000
13
2
1098 SJ AMSTERDAM NEDERLAND
6
F
Dim
Page
B
3
Name
13 14
8
GND
GND
channel_in
Buffer Memory (ZBT and SDRAM)
MROD-X 38405
9
21
22
32
GND
GND
4 1
GND
GND
8
C5142
22n
4K7
R5012
4K7
R5012
C5159
22n
4K7
R5012
C5141
22n
R5012
4K7
31
8
9
10
C5146
100n
13
GND
GND
GND
0
GND
GND
25
GND
C5144
22n
GND
6
3
GND
0
23
GND
GND
16
18
GNDGND
1
GND
2
13
15
GND GND
GND
29
30
20
9
GND
15
5
28
GND
6
7
C5162
100n
3
4
GND
30
11
GND
C5148
100n
GND
GND
GND
3 2
14
15
GND
14
19
12
GND
24
GND
GND
3
26
GND
9
16
33
7
2
GND
GND
GND
GND
GND
GND
GND
0
GND
7
16
GND
25
GND
11
10
11
0
12
4
31
27
24
19
GND
GND
35
GND
2
3
GND
17
18
VssQ438
VssQ546
VssQ652
78VssQ7
VssQ884
18_CAS
20_CS
_RAS19
17_WE
C5134
22n
49
VddQ655
VddQ775
81VddQ8
Vss144
Vss258
Vss372
86Vss4
VssQ16
VssQ212
32VssQ3
NC570
NC673
Vdd11
Vdd215
Vdd329
Vdd443
VddQ13
VddQ29
VddQ335
VddQ441
VddQ5
DQ713
DQ874
DQ976
DQM016 71
DQM1
DQM228
DQM359
NC114
NC230
NC357
69NC4
47
DQ2648
DQ2750
DQ2851
53DQ29
DQ37
DQ3054
56DQ31
DQ48
DQ510
11DQ6
85
DQ1631
DQ1733
DQ1834
DQ1936
DQ25
DQ2037
DQ2139
DQ2240
DQ2342
DQ2445
DQ25
23BA1
CKE67
CLK68
DQ02
4DQ1
DQ1077
DQ1179
80DQ12
DQ1382
DQ1483
DQ15
24
A1121
A227
A360
A461
A562
A663
A764
A865
A966
BA022
100n
27
28
MT48LC8M32B2
IC5007
A025
A126
A1010
5
6
7
C5152
22n
C5147
C5135
22n
1
2
GND
GND
GND
1
C5157
22n
GND
14
17
10
1
11
C5165
100n
C5156
22n
0
13
100n
C5164
C5161
22n
_BW4
_CE1
98
92
_CE2
_CEN
87
31
_LBO
_OE
86
C5158
22n
12
21VSS4
26VSS5
40
VSS6
55VSS7
VSS860
67VSS9
64ZZ
_BW1
93
94
_BW2
_BW3
95
96
16VDD5
20VDD6
27VDD7
VDD8
41
54VDD9
5VSS1
VSS1071
76VSS11
90
VSS12
VSS210
VSS317
VDD14
61VDD10
VDD1165
66VDD12
VDD1370
VDD1477
VDD15
91
11VDD2
VDD314
15VDD4
68IO8
69IO9
IOp151
IOp280
IOp31
IOp430
R_W
88
TCK
43
39
TDI
42
TDO
TMS
38
22
IO2723
24IO28
IO2925
57IO3
28IO30
29IO31
IO458
59IO5
IO662
IO763
IO16
IO173
6IO18
IO197
IO256
IO208
9IO21
12IO22
IO2313
18IO24
19IO25
IO2697
CE2
CLK
89
52IO0
IO153
72IO10
IO1173
74IO12
IO1375
78IO14
79IO15
2
83
84
A18
A2
35
A3
34
33
A4
32
A5
A6
100
99
A7
82
A8
81
A9
85
ADV_LD
IDT71V65603S100PF
IC5006
A0
37
36
A1
A10
44
A11
45
A12
46
A13
47
48
A14
A15
49
50
A16
A17
22n 22n
C5154
26
8
C5140
22n 22n
C5145
GND
C5138C5137
22n
5
22n
C5136
C5149
100n
GND
C5160
22n
C5143
C5153
22n
20
21
C5163
100n
22
0
4
5
22n
19
34
17
GND
6
GND
GND
GND
29
GND
23
18
22n
1
GND
22n 22n
C5155C5139
22n
C5150
BufCE_n SDRAM_CLKZ50_NET_TYPE
Z50_NET_TYPE
SDRAM_CLKin
SDRAM_WE_n
SDRAM_RAS_n
SDRAM_CAS_n
C5151
3V3
Clkx2
BufR_W_n
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
SDRAM_CS_n
SDRAM_DQ(31:0)
SDRAM_DQM(3:0)
SDRAM_BA(1:0)
SDRAM_A(12:0)
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
BufD(35:0)
BufA(19:0)
3V3
3V3
3V3
3V3
3V3
SDRAM_CKE
c
3
7
7
Answer Record #18562
14
Input Channel ID bits
10 17
K
GND
E
H
5
configuration. See Xilinx PROM Errata,
Testpoints force Spare
lines to be accessible.I
18
arc242 package
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
L
FPGA JTAG Signals
12
Temperature sensing diode
6
0 1 1 Master SelectMAP
12
0
It may be necessary to use Master SelectMap
3
I
HSWAP_EN = ’0’ => User IOs have pull-up
A
E
CLK
FPGA Configuration Signals
2
Default configuration mode will be Slave SelectMAP.
17
16
Connector
1
J J
Page
NATIONAAL INSTITUUT VOOR KERN-
H
PWRDWN_B is unsupported (should be pulled high)
Optinal Test
G
8
Clock Signals
16
chains where the same bitstream is loaded into multiple devices.
11
1098 SJ AMSTERDAM NEDERLAND
1
F
is no possibility for readback (RDWR_B = ’0’)
8 Input channels are loaded in parallel so there
Time
Dim
2
Proj:
9
to Master SelectMap and all other MROD-In FPGAs
to Slave SelectMap.
B
Size
Rocket IO Signals
15
Proj.No:
Rev
1 0 1 Boundary scan
’On’ = ’1’, ’Off’ = ’0’
13 18
Note: FCC_SelectMAP = 50 MHz so CCLK < 50 MHz!
M2 M1 M0
1 1 0 Slave SelectMAP (default)
6
D
14
-> Slave SlectMAP programming Mode -> BUSY.
15
13
Date
Name
See "Virtex-II Pro FPGA User Guide", Chapter 4 -> Configuration
F
FPGA Control signals
Cand each CS_B = ’0’
A
of
154
8
C
9
11
In this case set MROD-Out FPGA and one MROD-In FPGA
TTC Signals
NIKHEF
Pull-Ups
3
resistors during configuration
ET-Nikhef Amsterdam
K
5
4
B
2
1
D
L
G
10
66
420 x 297 mm
4 1 4 AA3
Ton van Reen
1:53:04 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405 MROD-X
Input FPGA Auxiliary Connections
channel_in
VBATT is decriptor key memory backup supply
Sharc Signals Frontend to Backend
DOUT is BUSY in SelectMAP mode and BUSY should NOT be used for parallel
1
0
6
GND
15
9
Fiducial21
22n
C5168
NC7SZ08
IC5012
1
2
3
5
4
2n2
C5171
J3A 2
GND
2
U3_3A
U2_3A
1
2
3
5
4
0E0
R5026
NC7SZ00
IC5009
1
2
3
5
4
NC7SZ00
IC5011
C5166
22n
R5027
1K0
Fiducial20
J3A 12
GND
Sw3A
17
180
R5013
GND
3
2
0
J3A 15
12
J3A
NC7SZ00
IC5010
1
2
3
5
4
SMD_LED_Red
D5002
J3A 16
GND
J3A 5
GND
GND
13
4
3
0
J3A 4
J3A 18
J3A 19
1K0
R5019
3
GND
GND
5
20
R50231K0
U1_3A
J3A
J3A 13
GND
1
2
J3A
R5015
J3A 8
4K7
R5025
180
R5024
D5004
SMD_LED_Green
180
R5025
Sw3A
D5001
SMD_LED_Red
ADD12
4DXN
5DXP
GND
3
SMBCLK8
SMBDATA9
VCC
6
10_ALERT
_STBY7
4K7
6
100n
C5172
GND
IC5013
MAX1618
1ADD0
11R5025
4K7
J3A
R50181K0
J3A 10
J3A
J3A 1
GND
SMD_LED_Green
D5003
Sw3A
J3A 7
R5020
NC7SZ00
IC5008
1
2
3
5
4
U4_3A
14
1K0
7
GND
10
4
R50224K7
6
5
GND
180
R5016 8
1
14
U0_3A
C5170
22n
R5021
180
R5014
J3A
GND
1K0
22n
C5167
7
GND
11GND
3
1K0
R5017
GND
GND
4
Spare(4:0)
J3A 9
22n
C5169
GND
CS_B
VCCAUXPWRDWN_B
CCLKCCLK
HSWAP_EN
PROG_BPROG_B
DXP
DXN
SMBClk
3V3
M2 M1
VCCAUX
M0
Spare(4:0)
Clk
TestCon(15:0)
3V3
3V3
3V3
3V3
T_Alert_n
SMBData
DOUT
INIT_BINIT_B
DONEDONE
D7
D6
D5
D4
D3
D2
D1
D0 D(7:0)
RDWR_B
3V3
ChaBusy ChaBusy
TTC_n(7:0)TTC_n(7:0)
ChaID(2:0)ChaID(2:0)
TCK
TDO
FPGA_TCK
FPGA_TMS
TDI FPGA_TDI
FPGA_TDO
Clk Clk
Clkx2Clkx2
LHC_ClkLHC_Clk
Rocket_XClk Rocket_XClk
Adr(21:0)Adr(21:0)
IRQ1_n IRQ1_n
IRQ2_n IRQ2_n
Empty Empty
DMAR_n DMAR_n
Rocket_RXPRocket_RXP
Rocket_RXN Rocket_RXN
Rocket_TXPRocket_TXP
Rocket_TXNRocket_TXN
A21_SelectA21_Select
TMS
3V3
LEDs(0)
LEDs(1)
LEDs(2)
LEDs(3)
General_Rst_n
Channel_Rst_n
Rst_n
VBATT
IRQ0_n IRQ0_n
Data(31:0) Data(31:0)
MS0_n MS0_n
MS1_nMS1_n
MS2_n MS2_n
MS3_nMS3_n
SharcRd_nSharcRd_n
SharcWr_n SharcWr_n
H
I
9
15 16 17
C
14
I
J
G
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1
Name
Size
Dim
K
L
3
Date
Time
of
4
10u Tantalum
AVX TAJB106K010R
J
13
13
10
D
62 107 8
5 15 16 17
C
11 12
D
14
B
11 12
NIKHEF
7 863 4
Page
E
F
E
F
A
H
18
G
V2
7 Feb 2006
1:50:33 pm
tonvr
A3 4 1 4 A
420 x 297 mm
1 6
GOL_MOD_DEF and GOL_TX_Fault
Signal Pull-ups in one
arc242 package
1098 SJ AMSTERDAM NEDERLANDET-Nikhef Amsterdam
B
5
Rev
c
K
1 2
L
A
9
Proj: Proj.No:
18
GND
channel_in
GOL Input
MROD-X 38405
Peter Jansweijer [email protected]
2
2
3
5
4
10u
C6002
R6002180
R6001180
IC6002
NC7SZ00
1
2
3
5
4
GND
C6007
22n
GND
GND4GND4
GND5GND5
GND6GND6
GND7GND7
GND8
GND8
GND9
GND9
GND
IC6003
NC7SZ00
1
GND12
GND13GND13
GND14GND14
GND15GND15
GND16GND16
GND17GND17
GND18
GND18
GND19
GND19
GND2GND2
GND20
GND20
GND3GND3
C6001
SFPT_cage
IC6001
GND1GND1
GND10
GND10
GND11GND11
GND12
4K7
GND
GND
GND
100n
1u
L6002
R6004
D3B
k_r
a_r
GND GND
L6001
1u
100n
C6004
D3B
Fr_LED_Gn
k_g
a_g
Fr_LED_Rd
GND
GND
22n
C6006
C6003
100n
4K7
4K7
R6003R6003
4K7
20
mod_def06
mod_def15
mod_def24
4K7
R6003R6003
Tx_disable3
Tx_fault2
VccR
15
VccT
16
VeeR1
9
VeeR2
10
VeeR3
11
14
VeeR4
VeeT1
1
VeeT2
17
VeeT3
IC6001
HFBR5720
LOS8
RD_n12 S
RD_p13 S
Rate_Sel7
TD_n19 T
TD_p18 T
GOL_XClk GOL_XClk
3V3
3V3
GOL_TX_Fault
GOL_MOD_DEF2
GOL_MOD_DEF1
GOL_MOD_DEF0
3V3
10u
C6005
GOL_RX_LOS
GOL_RXNGOL_LVDSGOL_LVDS
GOL_RXPGOL_LVDSGOL_LVDS
GOL_RATE_SEL
GOL_TXPGOL_LVDSGOL_LVDS
GOL_TX_Disable
ErrLED
UpLED
GOL_TXNGOL_LVDSGOL_LVDS
10 11 12 13
G
H
3 4
G
II
J
Date
2
VCCO_# (3V3) 10 pins each
12
Proj: Proj.No:
Rev
Size
A
Dim
1 3 6 7
7
NIKHEF
1
C
D
Input FPGA Power pins:
c ET-Nikhef Amsterdam
2
16
L
J
K
14
9
Page
A
B
C
K
6 18
E
F
KRUISLAAN 409, 020-592 2000
1715
VCCAUX (2V5) 16 pins
VCCINT (1V5) 32 pins
D
of
15
Time
Name
H
5
E
tonvr
1:50:53 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
Input FPGA
channel_in
8 9 16
8 14 18
11
1098 SJ AMSTERDAM NEDERLAND
L
B
10 13
4 5
F
17
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
GND 124 pins
62
420 x 297 mm
4 1 4 AA3
Y6 Y7 Y8 Y9 Y23 Y24 Y25 Y26 Y27 Y28 Y29Y3 Y30Y4 Y5 Y13 Y14 Y15 Y16 Y17 Y18 Y19Y2 Y20 Y21 Y22
W4 W5 W6 W7 W8 W9
Y1 Y10 Y11 Y12
W21 W22 W23 W24 W25 W26 W27 W28 W29W3 W30W11 W12 W13 W14 W15 W16 W17 W18 W19W2 W20
V3 V30V4 V5 V6 V7 V8 V9
W1 W10
V2 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29V1 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19
U28 U29U3 U30U4 U5 U6 U7 U8 U9 U18 U19U2 U20 U21 U22 U23 U24 U25 U26 U27
T8 T9
U1 U10 U11 U12 U13 U14 U15 U16 U17
T26 T27 T28 T29T3 T30T4 T5 T6 T7 T16 T17 T18 T19T2 T20 T21 T22 T23 T24 T25
R6 R7 R8 R9
T1 T10 T11 T12 T13 T14 T15
R24 R25 R26 R27 R28 R29R3 R30R4 R5 R14 R15 R16 R17 R18 R19R2 R20 R21 R22 R23
P4 P5 P6 P7 P8 P9
R1 R10 R11 R12 R13
P22 P23 P24 P25 P26 P27 P28 P29P3 P30P12 P13 P14 P15 P16 P17 P18 P19P2 P20 P21
N3 N30N4 N5 N6 N7 N8 N9
P1 P10 P11
N20 N21 N22 N23 N24 N25 N26 N27 N28 N29N10 N11 N12 N13 N14 N15 N16 N17 N18 N19N2
M28 M29M3 M30M4 M5 M6 M7 M8 M9
N1
M19M2 M20 M21 M22 M23 M24 M25 M26 M27
L9
M1 M10 M11 M12 M13 M14 M15 M16 M17 M18
L26 L27 L28 L29L3 L30L4 L5 L6 L7 L8 L17 L18 L19L2 L20 L21 L22 L23 L24 L25
K7 K8 K9
L1 L10 L11 L12 L13 L14 L15 L16
K24 K25 K26 K27 K28 K29K3 K30K4 K5 K6 K15 K16 K17 K18 K19K2 K20 K21 K22 K23
J5 J6 J7 J8 J9
K1 K10 K11 K12 K13 K14
J22 J23 J24 J25 J26 J27 J28 J29J3 J30J4 J13 J14 J15 J16 J17 J18 J19J2 J20 J21
H30H4 H5 H6 H7 H8 H9
J1 J10 J11 J12
H20 H21 H22 H23 H24 H25 H26 H27 H28 H29H3 H11 H12 H13 H14 H15 H16 H17 H18 H19H2
G29G3 G30G4 G5 G6 G7 G8 G9
H1 H10
G19G2 G20 G21 G22 G23 G24 G25 G26 G27 G28G1 G10 G11 G12 G13 G14 G15 G16 G17 G18
F27 F28 F29F3 F30F4 F5 F6 F7 F8 F9 F17 F18 F19F2 F20 F21 F22 F23 F24 F25 F26
E8 E9
F1 F10 F11 F12 F13 F14 F15 F16
E25 E26 E27 E28 E29E3 E30E4 E5 E6 E7 E15 E16 E17 E18 E19E2 E20 E21 E22 E23 E24
D6 D7 D8 D9
E1 E10 E11 E12 E13 E14
D23 D24 D25 D26 D27 D28 D29D3 D30D4 D5 D13 D14 D15 D16 D17 D18 D19D2 D20 D21 D22
C4 C5 C6 C7 C8 C9
D1 D10 D11 D12
C21 C22 C23 C24 C25 C26 C27 C28 C29C3 C30C11 C12 C13 C14 C15 C16 C17 C18 C19C2 C20
B3 B30B4 B5 B6 B7 B8 B9
C1 C10
B2 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29B1 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19
AK27 AK28 AK29AK3 AK4 AK5 AK6 AK7 AK8 AK9
T
AK18
T
AK19
S
AK2 AK20
S
AK21 AK22 AK23 AK24 AK25 AK26
AJ8 AJ9
AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17
AJ25 AJ26 AJ27 AJ28 AJ29AJ3 AJ30AJ4 AJ5 AJ6 AJ7 AJ15 AJ16 AJ17 AJ18 AJ19AJ2 AJ20 AJ21 AJ22 AJ23 AJ24
AH6 AH7 AH8 AH9
AJ1 AJ10 AJ11 AJ12 AJ13 AJ14
AH23 AH24 AH25 AH26 AH27 AH28 AH29AH3 AH30AH4 AH5 AH13 AH14 AH15 AH16 AH17 AH18 AH19AH2 AH20 AH21 AH22
AG4 AG5 AG6 AG7 AG8 AG9
AH1 AH10 AH11 AH12
AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29AG3 AG30AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19AG2 AG20
AF3 AF30AF4 AF5 AF6 AF7 AF8 AF9
AG1 AG10
AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29AF1 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19
AE28 AE29AE3 AE30AE4 AE5 AE6 AE7 AE8 AE9 AE18 AE19AE2 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27
AD8 AD9
AE1 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17
AD26 AD27 AD28 AD29AD3 AD30AD4 AD5 AD6 AD7 AD16 AD17 AD18 AD19AD2 AD20 AD21 AD22 AD23 AD24 AD25
AC6 AC7 AC8 AC9
AD1 AD10 AD11 AD12 AD13 AD14 AD15
AC24 AC25 AC26 AC27 AC28 AC29AC3 AC30AC4 AC5 AC14 AC15 AC16 AC17 AC18 AC19AC2 AC20 AC21 AC22 AC23
AB4 AB5 AB6 AB7 AB8 AB9
AC1 AC10 AC11 AC12 AC13
AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29AB3 AB30AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19AB2 AB20 AB21
AA3 AA30AA4 AA5 AA6 AA7 AA8 AA9
AB1 AB10 AB11
AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19AA2
A27 A28 A29A3 A4 A5 A6 A7 A8 A9
AA1
T
A19
S
A2 A20
S
A21 A22 A23 A24 A25 A26
XC2VP7FF896
IC6004
A10 A11 A12 A13 A14 A15 A16 A17
T
A18
DP_GOL_RX3B
GOL_RXNVRP_2VCCAUX
DMAR_n
BufR_W_n
BufA(18)
SMBClkSMBDataT_Alert_n
Rst_n
GOL_LVDS
GOL_LVDS
DP_GOL_TX3B
GOL_TXN
GOL_LVDS
GOL_LVDS
DP_GOL_TX3B
GOL_TXP
GOL_LVDS
GOL_LVDS
DP_GOL_RX3B
GOL_RXP
GOL_LVDSGOL_LVDS
SDRAM_A(4)SDRAM_A(5)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(16)Adr(15)Adr(14)Adr(13)Adr(12)Adr(11)
VCCAUXVRP_7LEDs(0)GNDVCCAUXVCCAUXGND
Adr(6)Adr(5)Adr(4)GND
SDRAM_A(6)SDRAM_A(7)SDRAM_A(8)SDRAM_A(9)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5IRQ2_nData(3)VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(10)Adr(9)Adr(8)Adr(7)
SDRAM_DQ(30)SDRAM_DQ(31)SDRAM_DQM(3)SDRAM_A(3)
Data(10)Data(15)D1PWRDWN_BAdr(3)Adr(2)
GNDSDRAM_CKESDRAM_A(12)SDRAM_DQM(1)M1M2D7TestCon(10)TestCon(9)TestCon(8)IRQ1_nData(2)Data(9)Data(11)Data(16)D0DONECCLK
Data(19)Data(23)INIT_BGND
GNDGNDEmptyData(0)Data(6)GNDData(14)Data(20)Data(24)Data(25)GND
SDRAM_DQ(8)SDRAM_DQ(9)M0D6TestCon(13)TestCon(12)TestCon(11)IRQ0_nData(1)Data(7)Data(8)
VRN_5GNDTTC_n(5)GNDChaBusyLHC_ClkSharcWr_nData(4)GNDData(12)GNDVRP_4D2DOUTAdr(1)GNDAdr(0)Data(31)Data(30)
GNDRDWR_BTTC_n(4)TTC_n(6)TTC_n(7)SDRAM_CLKSDRAM_CLKinData(5)Data(13)
GNDGNDA21D4VRP_5TTC_n(3)GNDA19GNDClkSharcRd_nGNDGNDA18Data(18)VRN_4D3GNDA16Data(29)Data(28)GNDData(27)Data(26)
SDRAM_DQ(10)SDRAM_DQ(11)SDRAM_DQ(12)GNDSDRAM_DQ(13)CS_BD5
AVCCAUXTX19VTRXPAD19AVCCAUXRX19Clkx2Rocket_XClkVTTXPAD18AVCCAUXTX18VTRXPAD18AVCCAUXRX18Data(17)Data(22)VTTXPAD16AVCCAUXTX16VTRXPAD16AVCCAUXRX16VRP_3GNDVCCAUX
SDRAM_DQ(14)SDRAM_DQ(15)
GND
ROCKET_LVDS
Rocket_TXN
ROCKET_LVDS
Rocket_TXP
ROCKET_LVDS
Rocket_RXP
ROCKET_LVDS
Rocket_RXNVCCAUXVCCAUXGNDData(21)VRN_3VCCAUX
VCCAUXGNDVRP_6VTTXPAD21AVCCAUXTX21VTRXPAD21AVCCAUXRX21TTC_n(1)TTC_n(2)VTTXPAD19
VTTXPAD6AVCCAUXTX6VTRXPAD6AVCCAUXRX6GOL_XClkVTTXPAD7AVCCAUXTX7VTRXPAD7AVCCAUXRX7VTTXPAD9AVCCAUXTX9VTRXPAD9AVCCAUXRX9VRN_2GNDVCCAUX
VCCAUXVRN_6TTC_n(0)
BufCE_nGNDBufA(7)BufA(6)GNDA4LEDs(3)LEDs(2)GNDA6UpLEDGNDGNDGNDA7GNDA9GND
VCCAUXGNDVRN_7VTTXPAD4AVCCAUXTX4VTRXPAD4AVCCAUXRX4LEDs(1)
GOL_TX_FaultVRP_1VRN_1GND
BufD(33)GNDBufD(16)DXNChaID(0)ChaID(1)GNDGOL_MOD_DEF0GOL_MOD_DEF1GNDErrLEDGOL_TX_DisableGOL_RX_LOSGNDGNDGND
BufA(19)
PROG_BTestCon(2)TestCon(3)TestCon(4)TestCon(5)TestCon(6)TCK
TDIGNDTestCon(0)TestCon(1)GNDGNDGNDTDO
GNDVRP_0VRN_0ChaID(2)GOL_RATE_SELGOL_MOD_DEF2
BufD(25)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2TestCon(14)
GNDBufD(19)DXPHSWAP_ENTestCon(7)TestCon(15)TMSVBATTGND
BufD(17)BufD(18)
BufD(26)BufD(27)BufD(28)BufD(29)BufD(30)BufD(31)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2
BufD(20)BufD(21)BufD(22)BufD(23)BufD(24)
GNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufD(32)BufA(5)GNDBufA(4)BufA(3)GNDVCCO_7VCCO_7GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_2VCCO_2GNDGND
VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufA(2)BufA(1)BufA(0)BufA(10)BufA(11)BufA(12)BufA(13)BufA(14)VCCO_7VCCO_7VCCINTGNDGNDGND
BufD(11)BufD(12)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2GND
BufA(15)BufA(16)BufD(35)BufD(0)BufD(1)BufD(2)BufD(3)BufD(4)VCCO_7VCCO_7
BufA(9)BufA(8)BufA(17)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCAUX
BufD(5)BufD(6)BufD(7)BufD(8)BufD(9)GNDBufD(10)
SDRAM_DQ(4)SDRAM_DQ(5)SDRAM_DQ(6)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3Spare(0)Spare(1)Spare(2)Spare(3)Spare(4)VCCAUX
VCCAUXBufD(13)BufD(14)BufD(15)BufD(34)
SDRAM_RAS_nGNDSDRAM_CS_nSDRAM_A(11)SDRAM_BA(0)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3GND
VCCAUXSDRAM_DQ(0)SDRAM_DQ(1)SDRAM_DQ(2)SDRAM_DQ(3)
SDRAM_A(0)SDRAM_A(1)SDRAM_A(2)SDRAM_DQM(2)SDRAM_DQ(16)SDRAM_DQ(17)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3A21_Select
SDRAM_DQ(7)SDRAM_DQM(0)SDRAM_WE_nSDRAM_CAS_n
SDRAM_DQ(21)SDRAM_DQ(22)SDRAM_DQ(23)SDRAM_DQ(24)SDRAM_DQ(25)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3MS3_nMS2_nMS1_nMS0_nAdr(21)
SDRAM_BA(1)SDRAM_A(10)
SDRAM_DQ(26)SDRAM_DQ(27)GNDSDRAM_DQ(28)SDRAM_DQ(29)GNDVCCO_6VCCO_6GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_3VCCO_3GNDAdr(20)Adr(19)GNDAdr(18)Adr(17)
SDRAM_DQ(18)SDRAM_DQ(19)SDRAM_DQ(20)
XC2VP7/20 VCCINT Decoupling Capacitors
FYSICA EN HOGE ENERGIE-FYSICA
IccINT = 600 mA
Dim
A
B
C
18
A
173
K
13
Date
15 16 17 18
AVX TAJB476K010R
11
IccAUX = 250 mA (min)
ET-Nikhef Amsterdam
VCCAUX and VCCO can ramp up at any rate
3
Proj.No:
1
4
AVX TAJB476K010R
2
D
Rev
L
E
F
For Xilinx Virtex-II Pro, power supplies
can be turned on in any sequence.
8
Proj:
7
6 7
VCCINT Ramp rate 200 us min. and 50 ms max.
NIKHEFof
G
14
Pagec
K
L
Min. Power-On Current XC2VP20
Min. Power-On Current XC2VP20
G
H
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Name
Size
9 10 11 12 13
14
I
J
10
B
E
5
16
XC2VP7/20 VCCAUX Decoupling Capacitors
NATIONAAL INSTITUUT VOOR KERN-
Power Inputs
1:51:34 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
3 6
9 12
4
1
15
AVX TAJB476K010R
AVX TAJB476K010R
8
F
2
C
D
All GND nets on the FPGA need
to be connected to golbal GROUND.
6
5
Time
J
I
H
22n
C6046
GND
channel_in
Input FPGA Power Supply Decoupling
MROD-X 38405
Peter Jansweijer [email protected]
2V2
7 Feb 2006
680p
C6040
GND
47u
C6097
GND
680p
C6009
GND
GND
C6045
22n
GND
C6096
47u
22n
C6083
GND
C6084
22n
GND
C6050
22n 22n
C6052
GND
C6090
100n
GND
100n
C6095
GND
GND
680p
C6067
GND
GND
680p
C6044
GNDC6082
680p
680p
22n
C6079
GND
680p680p
C6071
GND
GND
C6008
GND
680p
C6087
C6072
GND
C6014
680p
C6041
680p
22n
C6047
22n
C6059
GND
C6039
680p
GND
GND
C6053
100n
C6055
47u
GND
GND
GND
GND
C6018
680p
680p
C6061
GND
GND
22n
C6024
22n
C6069
GND
GND
C6062
680p
GND
GND
GND
C6025
22n
C6043
680p
GND
C6051
22n
GNDGND
C6048
22n
C6023
22n
GND
680p
C6077
GND
GND GND
GND
C6022
22n
47u
C6035
C6016
680p
GND
C6019
22n
GND
680p
C6081
GND
100n
C6075
GND
GND
C6033
C6086
680p
C6068
22n
22n
C6049
C6092
680p
GND
100n
GND
GND
C6076
680p
GND
GND
680p
C6042
C6078
22n
GND
C6036
47u
C6030
100n
680p
C6017
GND
C6066
680p
GND
GND
GND
22n
C6073
GND
C6064
22n
GND
C6094
22n
GND
C6037
680p
C6028
22n
GND
GND
680p
C6015
22n
C6020
C6070
100n
680p
C6013
680p
C6091
GND
GND
100n
C6054
GND
100n
C6085
C6080
100n
680p
C6038
GNDGND
C6060
100n
GND
22n
C6021
C6058
22n
GND
100n
C6065
GND
C6012
680p
GND
GND
GND
GND
C6074
22n
C6056
680p
22n
C6093
GND
C6010
680p
22n
C6063
680p
C6057
GND
GND
C6088
22n
GND
680p
C6011
GND
GND
GND
GND
22n
C6089
C6034
100n
GND
100n
C6029
GND
GND
C6031
100n
GND
100n
C6032
22n
C6026
GND
22n
C6027
GND
1V5POWER_NET_TYPE
VCCINT
VCCINT
2V5POWER_NET_TYPE
VCCAUX
VCCAUX
POWER_NET_TYPE
3V33V3
3V3
POWER_NET_TYPE
GND
GND
GND
GND
VCCO_0
VCCO_1
VCCO_2
VCCO_4
VCCO_5
VCCO_6
VCCO_7
VCCO_3
2V5 @ 1,5A
Proj:
97
c ET-Nikhef Amsterdam
142
Buffer Memory interface
L
AVX TAJB476K010R
=> MGT Power (estimated 31 + 49 = 80 mA)
G
K
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
10
Series Termination for
3 5 131210
NIKHEF
Name
Series Termination for
Date
H
2 15
KRUISLAAN 409, 020-592 2000
16
Not (yet) used
H
General purpose
1
Size
PAD6 connected to GOL
PAD19 connected to MROD-Out FPGA
DC coupled
4
Not (yet) used
Series Termination for
L
1
AC coupled
Note: VT1V8_MGT is common to all MROD-Ins
11 14
General purpose
G
9
17 18
A
15
of
E
F
4
=> MGT TX (RX) Termination (estimated 11 mA)
1098 SJ AMSTERDAM NEDERLAND
Sharc Databus
Time
18
B
C C
J
I
Proj.No:
Series Termination for
3
D
6
6
13
SDRAM interface
B
K
Series Termination for
A
D
Series Termination for
I
J
Series Termination for
E
16
11 12
7
Sharc Addressbus
Series Termination for
17
Rev
8
channel_in
Input FPGA MGT Pwr Decoupling, Termination
MROD-X 38405
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:01 pm
tonvr
A3 4 1 4 A
420 x 297 mm
4 6
AVX TAJB476K010R
5
F
Page
Dim
8
GND
R6028
1M
1u
L6004
GND
L6018
1u
R6011
47
47
R6009
GND
L6019
1u
L6033
1u
GND GND
L6014
1u
C6100
100n
GND
2%
100 R6006
1u
L6021
GND
GND
GND
GND
GNDGND
GND
GND
L6022
1u
GND
GND
GND
220n
C6111
L6029
1u
C6101
47u
C6113
220n
GND
GND
GND GND
GND
R6009
47
GNDGND
GND
GND
C6115
220n
GND
GND
GND
GND2TAB
2IN OUT
4
5S_A
1_SHDN
47
R6009
0E01u
L6012
LT1963A_DD
IC6005
3GND1
GND
R6011
47
R6029
R6011
47
C6131
220n
GND
220n
C6104
C6129
220n
GND
GND
GND
C6133
220n
GND
GND
GND
GND
GND GND
L6025
1u
L6027
1u
C6118
GND
GND
L6009
1u
R6007
95E3
2%
220n
R6009
47
L6017
1u
GND GND
GND
C6108
220n
GND
1u
L6007
R6010
47
C6105
220n
C6123
220n
R6005
4K7
L6031
1u
1u
220n
C6116
C6107
220n
C6125
220n
C6124
220n
GND
L6026
L6010
1u
220n
C6120
GND
C6110
220n
C6103
220n
GND
C6109
220n
220n
C6102
GND
220n
C6112
C6127
220n
GND
47
R6008
C6098
47u
GND
R6008
47
C6119
220n
GND
C6117
220n
L6024
1u
L6020
1u
L6016
1u
L6015
1u1u
L6013
C6106
220n
R6008
47
1u
L6023
1u
GND
1u
L6011
C6121
220n
L6005
1u
L6030
C6099
100n
R6010
47
R6008
47
L6006
1u
C6126
220n
1u
L6003
L6032
1u1u
C6122
220n
R6011
47
L6034
1u
L6008
1u
L6028
R6010
47
47
R6010
C6114
220n
C6128
220n
GND
C6132
220n
VTRXPAD7VTRXPAD6VTRXPAD4
VT2V5_MGT
VT2V5_MGT
VT1V8_MGT
AVCCAUXTX4
VTTXPAD4
VRN_7
VRP_7
C6130
220n
VRN_4
3V3
VRP_4
VRN_5
3V3
VRP_5
VRN_6
3V3
VRP_6
3V3
VCCA_MGTPOWER_NET_TYPE
3V3
VTRXPAD9
VTRXPAD19 VTRXPAD18 VTRXPAD16
VRN_0
3V3
VRP_0
VRN_1
3V3
VRP_1
VRN_2
3V3
VRP_2
VRN_3
3V3
VRP_3
AVCCAUXTX18 AVCCAUXTX16
AVCCAUXRX16AVCCAUXRX18AVCCAUXRX19AVCCAUXRX21
VTTXPAD21 VTTXPAD19 VTTXPAD18 VTTXPAD16
VTRXPAD21
AVCCAUXTX9
AVCCAUXRX9AVCCAUXRX7AVCCAUXRX6AVCCAUXRX4
VTTXPAD6 VTTXPAD7 VTTXPAD9
AVCCAUXTX21 AVCCAUXTX19
POWER_NET_TYPE
VT2V5_MGT
VCCA_MGT
VCCA_MGT
GNDA4 GNDA6 GNDA7 GNDA9
GNDA21 GNDA19 GNDA18 GNDA16
AVCCAUXTX6 AVCCAUXTX7
18
E
5
F
B
C
7
c ET-Nikhef Amsterdam
Proj.No:
Date
Time
9
H
6
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
7 17
SDRAM_A(12) is not connected
L
1
J
11
A
of
G
NIKHEF
8
Proj:
K
8
2
16
I
163 5 14
Rev
E
17
9
18
1 10
H
4
Size
15
15
C
D
J
K
L
A
G
4
D
12
I
10
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:29 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
5 6
11 12
KRUISLAAN 409, 020-592 2000
13
2
1098 SJ AMSTERDAM NEDERLAND
6
F
Dim
Page
B
3
Name
13 14
8
GND
GND
channel_in
Buffer Memory (ZBT and SDRAM)
MROD-X 38405
9
21
22
32
GND
GND
4 1
GND
GND
8
C6142
22n
4K7
R6012
4K7
R6012
C6159
22n
4K7
R6012
C6141
22n
R6012
4K7
31
8
9
10
C6146
100n
13
GND
GND
GND
0
GND
GND
25
GND
C6144
22n
GND
6
3
GND
0
23
GND
GND
16
18
GNDGND
1
GND
2
13
15
GND GND
GND
29
30
20
9
GND
15
5
28
GND
6
7
C6162
100n
3
4
GND
30
11
GND
C6148
100n
GND
GND
GND
3 2
14
15
GND
14
19
12
GND
24
GND
GND
3
26
GND
9
16
33
7
2
GND
GND
GND
GND
GND
GND
GND
0
GND
7
16
GND
25
GND
11
10
11
0
12
4
31
27
24
19
GND
GND
35
GND
2
3
GND
17
18
VssQ438
VssQ546
VssQ652
78VssQ7
VssQ884
18_CAS
20_CS
_RAS19
17_WE
C6134
22n
49
VddQ655
VddQ775
81VddQ8
Vss144
Vss258
Vss372
86Vss4
VssQ16
VssQ212
32VssQ3
NC570
NC673
Vdd11
Vdd215
Vdd329
Vdd443
VddQ13
VddQ29
VddQ335
VddQ441
VddQ5
DQ713
DQ874
DQ976
DQM016 71
DQM1
DQM228
DQM359
NC114
NC230
NC357
69NC4
47
DQ2648
DQ2750
DQ2851
53DQ29
DQ37
DQ3054
56DQ31
DQ48
DQ510
11DQ6
85
DQ1631
DQ1733
DQ1834
DQ1936
DQ25
DQ2037
DQ2139
DQ2240
DQ2342
DQ2445
DQ25
23BA1
CKE67
CLK68
DQ02
4DQ1
DQ1077
DQ1179
80DQ12
DQ1382
DQ1483
DQ15
24
A1121
A227
A360
A461
A562
A663
A764
A865
A966
BA022
100n
27
28
MT48LC8M32B2
IC6007
A025
A126
A1010
5
6
7
C6152
22n
C6147
C6135
22n
1
2
GND
GND
GND
1
C6157
22n
GND
14
17
10
1
11
C6165
100n
C6156
22n
0
13
100n
C6164
C6161
22n
_BW4
_CE1
98
92
_CE2
_CEN
87
31
_LBO
_OE
86
C6158
22n
12
21VSS4
26VSS5
40
VSS6
55VSS7
VSS860
67VSS9
64ZZ
_BW1
93
94
_BW2
_BW3
95
96
16VDD5
20VDD6
27VDD7
VDD8
41
54VDD9
5VSS1
VSS1071
76VSS11
90
VSS12
VSS210
VSS317
VDD14
61VDD10
VDD1165
66VDD12
VDD1370
VDD1477
VDD15
91
11VDD2
VDD314
15VDD4
68IO8
69IO9
IOp151
IOp280
IOp31
IOp430
R_W
88
TCK
43
39
TDI
42
TDO
TMS
38
22
IO2723
24IO28
IO2925
57IO3
28IO30
29IO31
IO458
59IO5
IO662
IO763
IO16
IO173
6IO18
IO197
IO256
IO208
9IO21
12IO22
IO2313
18IO24
19IO25
IO2697
CE2
CLK
89
52IO0
IO153
72IO10
IO1173
74IO12
IO1375
78IO14
79IO15
2
83
84
A18
A2
35
A3
34
33
A4
32
A5
A6
100
99
A7
82
A8
81
A9
85
ADV_LD
IDT71V65603S100PF
IC6006
A0
37
36
A1
A10
44
A11
45
A12
46
A13
47
48
A14
A15
49
50
A16
A17
22n 22n
C6154
26
8
C6140
22n 22n
C6145
GND
C6138C6137
22n
5
22n
C6136
C6149
100n
GND
C6160
22n
C6143
C6153
22n
20
21
C6163
100n
22
0
4
5
22n
19
34
17
GND
6
GND
GND
GND
29
GND
23
18
22n
1
GND
22n 22n
C6155C6139
22n
C6150
BufCE_n SDRAM_CLKZ50_NET_TYPE
Z50_NET_TYPE
SDRAM_CLKin
SDRAM_WE_n
SDRAM_RAS_n
SDRAM_CAS_n
C6151
3V3
Clkx2
BufR_W_n
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
SDRAM_CS_n
SDRAM_DQ(31:0)
SDRAM_DQM(3:0)
SDRAM_BA(1:0)
SDRAM_A(12:0)
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
BufD(35:0)
BufA(19:0)
3V3
3V3
3V3
3V3
3V3
SDRAM_CKE
c
3
7
7
Answer Record #18562
14
Input Channel ID bits
10 17
K
GND
E
H
5
configuration. See Xilinx PROM Errata,
Testpoints force Spare
lines to be accessible.I
18
arc242 package
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
L
FPGA JTAG Signals
12
Temperature sensing diode
6
0 1 1 Master SelectMAP
12
0
It may be necessary to use Master SelectMap
3
I
HSWAP_EN = ’0’ => User IOs have pull-up
A
E
CLK
FPGA Configuration Signals
2
Default configuration mode will be Slave SelectMAP.
17
16
Connector
1
J J
Page
NATIONAAL INSTITUUT VOOR KERN-
H
PWRDWN_B is unsupported (should be pulled high)
Optinal Test
G
8
Clock Signals
16
chains where the same bitstream is loaded into multiple devices.
11
1098 SJ AMSTERDAM NEDERLAND
1
F
is no possibility for readback (RDWR_B = ’0’)
8 Input channels are loaded in parallel so there
Time
Dim
2
Proj:
9
to Master SelectMap and all other MROD-In FPGAs
to Slave SelectMap.
B
Size
Rocket IO Signals
15
Proj.No:
Rev
1 0 1 Boundary scan
’On’ = ’1’, ’Off’ = ’0’
13 18
Note: FCC_SelectMAP = 50 MHz so CCLK < 50 MHz!
M2 M1 M0
1 1 0 Slave SelectMAP (default)
6
D
14
-> Slave SlectMAP programming Mode -> BUSY.
15
13
Date
Name
See "Virtex-II Pro FPGA User Guide", Chapter 4 -> Configuration
F
FPGA Control signals
Cand each CS_B = ’0’
A
of
154
8
C
9
11
In this case set MROD-Out FPGA and one MROD-In FPGA
TTC Signals
NIKHEF
Pull-Ups
3
resistors during configuration
ET-Nikhef Amsterdam
K
5
4
B
2
1
D
L
G
10
66
420 x 297 mm
4 1 4 AA3
Ton van Reen
1:53:04 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405 MROD-X
Input FPGA Auxiliary Connections
channel_in
VBATT is decriptor key memory backup supply
Sharc Signals Frontend to Backend
DOUT is BUSY in SelectMAP mode and BUSY should NOT be used for parallel
1
0
6
GND
15
9
Fiducial6002
22n
C6168
NC7SZ08
IC6012
1
2
3
5
4
2n2
C6171
J3B 2
GND
2
U3_3B
U2_3B
1
2
3
5
4
0E0
R6026
NC7SZ00
IC6009
1
2
3
5
4
NC7SZ00
IC6011
C6166
22n
R6027
1K0
Fiducial6001
J3B 12
GND
Sw3B
17
180
R6013
GND
3
2
0
J3B 15
12
J3B
NC7SZ00
IC6010
1
2
3
5
4
SMD_LED_Red
D6002
J3B 16
GND
J3B 5
GND
GND
13
4
3
0
J3B 4
J3B 18
J3B 19
1K0
R6019
3
GND
GND
5
20
R60231K0
U1_3B
J3B
J3B 13
GND
1
2
J3B
R6015
J3B 8
4K7
R6025
180
R6024
D6004
SMD_LED_Green
180
R6025
Sw3B
D6001
SMD_LED_Red
ADD12
4DXN
5DXP
GND
3
SMBCLK8
SMBDATA9
VCC
6
10_ALERT
_STBY7
4K7
6
100n
C6172
GND
IC6013
MAX1618
1ADD0
11R6025
4K7
J3B
R60181K0
J3B 10
J3B
J3B 1
GND
SMD_LED_Green
D6003
Sw3B
J3B 7
R6020
NC7SZ00
IC6008
1
2
3
5
4
U4_3B
14
1K0
7
GND
10
4
R60224K7
6
5
GND
180
R6016 8
1
14
U0_3B
C6170
22n
R6021
180
R6014
J3B
GND
1K0
22n
C6167
7
GND
11GND
3
1K0
R6017
GND
GND
4
Spare(4:0)
J3B 9
22n
C6169
GND
CS_B
VCCAUXPWRDWN_B
CCLKCCLK
HSWAP_EN
PROG_BPROG_B
DXP
DXN
SMBClk
3V3
M2 M1
VCCAUX
M0
Spare(4:0)
Clk
TestCon(15:0)
3V3
3V3
3V3
3V3
T_Alert_n
SMBData
DOUT
INIT_BINIT_B
DONEDONE
D7
D6
D5
D4
D3
D2
D1
D0 D(7:0)
RDWR_B
3V3
ChaBusy ChaBusy
TTC_n(7:0)TTC_n(7:0)
ChaID(2:0)ChaID(2:0)
TCK
TDO
FPGA_TCK
FPGA_TMS
TDI FPGA_TDI
FPGA_TDO
Clk Clk
Clkx2Clkx2
LHC_ClkLHC_Clk
Rocket_XClk Rocket_XClk
Adr(21:0)Adr(21:0)
IRQ1_n IRQ1_n
IRQ2_n IRQ2_n
Empty Empty
DMAR_n DMAR_n
Rocket_RXPRocket_RXP
Rocket_RXN Rocket_RXN
Rocket_TXPRocket_TXP
Rocket_TXNRocket_TXN
A21_SelectA21_Select
TMS
3V3
LEDs(0)
LEDs(1)
LEDs(2)
LEDs(3)
General_Rst_n
Channel_Rst_n
Rst_n
VBATT
IRQ0_n IRQ0_n
Data(31:0) Data(31:0)
MS0_n MS0_n
MS1_nMS1_n
MS2_n MS2_n
MS3_nMS3_n
SharcRd_nSharcRd_n
SharcWr_n SharcWr_n
H
I
9
15 16 17
C
14
I
J
G
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1
Name
Size
Dim
K
L
3
Date
Time
of
4
10u Tantalum
AVX TAJB106K010R
J
13
13
10
D
62 107 8
5 15 16 17
C
11 12
D
14
B
11 12
NIKHEF
7 863 4
Page
E
F
E
F
A
H
18
G
V2
7 Feb 2006
1:50:33 pm
tonvr
A3 4 1 4 A
420 x 297 mm
1 6
GOL_MOD_DEF and GOL_TX_Fault
Signal Pull-ups in one
arc242 package
1098 SJ AMSTERDAM NEDERLANDET-Nikhef Amsterdam
B
5
Rev
c
K
1 2
L
A
9
Proj: Proj.No:
18
GND
channel_in
GOL Input
MROD-X 38405
Peter Jansweijer [email protected]
2
2
3
5
4
10u
C7002
R7002180
R7001180
IC7002
NC7SZ00
1
2
3
5
4
GND
C7007
22n
GND
GND4GND4
GND5GND5
GND6GND6
GND7GND7
GND8
GND8
GND9
GND9
GND
IC7003
NC7SZ00
1
GND12
GND13GND13
GND14GND14
GND15GND15
GND16GND16
GND17GND17
GND18
GND18
GND19
GND19
GND2GND2
GND20
GND20
GND3GND3
C7001
SFPT_cage
IC7001
GND1GND1
GND10
GND10
GND11GND11
GND12
4K7
GND
GND
GND
100n
1u
L7002
R7004
D4A
k_r
a_r
GND GND
L7001
1u
100n
C7004
D4A
Fr_LED_Gn
k_g
a_g
Fr_LED_Rd
GND
GND
22n
C7006
C7003
100n
4K7
4K7
R7003R7003
4K7
20
mod_def06
mod_def15
mod_def24
4K7
R7003R7003
Tx_disable3
Tx_fault2
VccR
15
VccT
16
VeeR1
9
VeeR2
10
VeeR3
11
14
VeeR4
VeeT1
1
VeeT2
17
VeeT3
IC7001
HFBR5720
LOS8
RD_n12 S
RD_p13 S
Rate_Sel7
TD_n19 T
TD_p18 T
GOL_XClk GOL_XClk
3V3
3V3
GOL_TX_Fault
GOL_MOD_DEF2
GOL_MOD_DEF1
GOL_MOD_DEF0
3V3
10u
C7005
GOL_RX_LOS
GOL_RXNGOL_LVDSGOL_LVDS
GOL_RXPGOL_LVDSGOL_LVDS
GOL_RATE_SEL
GOL_TXPGOL_LVDSGOL_LVDS
GOL_TX_Disable
ErrLED
UpLED
GOL_TXNGOL_LVDSGOL_LVDS
10 11 12 13
G
H
3 4
G
II
J
Date
2
VCCO_# (3V3) 10 pins each
12
Proj: Proj.No:
Rev
Size
A
Dim
1 3 6 7
7
NIKHEF
1
C
D
Input FPGA Power pins:
c ET-Nikhef Amsterdam
2
16
L
J
K
14
9
Page
A
B
C
K
6 18
E
F
KRUISLAAN 409, 020-592 2000
1715
VCCAUX (2V5) 16 pins
VCCINT (1V5) 32 pins
D
of
15
Time
Name
H
5
E
tonvr
1:50:53 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
Input FPGA
channel_in
8 9 16
8 14 18
11
1098 SJ AMSTERDAM NEDERLAND
L
B
10 13
4 5
F
17
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
GND 124 pins
62
420 x 297 mm
4 1 4 AA3
Y6 Y7 Y8 Y9 Y23 Y24 Y25 Y26 Y27 Y28 Y29Y3 Y30Y4 Y5 Y13 Y14 Y15 Y16 Y17 Y18 Y19Y2 Y20 Y21 Y22
W4 W5 W6 W7 W8 W9
Y1 Y10 Y11 Y12
W21 W22 W23 W24 W25 W26 W27 W28 W29W3 W30W11 W12 W13 W14 W15 W16 W17 W18 W19W2 W20
V3 V30V4 V5 V6 V7 V8 V9
W1 W10
V2 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29V1 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19
U28 U29U3 U30U4 U5 U6 U7 U8 U9 U18 U19U2 U20 U21 U22 U23 U24 U25 U26 U27
T8 T9
U1 U10 U11 U12 U13 U14 U15 U16 U17
T26 T27 T28 T29T3 T30T4 T5 T6 T7 T16 T17 T18 T19T2 T20 T21 T22 T23 T24 T25
R6 R7 R8 R9
T1 T10 T11 T12 T13 T14 T15
R24 R25 R26 R27 R28 R29R3 R30R4 R5 R14 R15 R16 R17 R18 R19R2 R20 R21 R22 R23
P4 P5 P6 P7 P8 P9
R1 R10 R11 R12 R13
P22 P23 P24 P25 P26 P27 P28 P29P3 P30P12 P13 P14 P15 P16 P17 P18 P19P2 P20 P21
N3 N30N4 N5 N6 N7 N8 N9
P1 P10 P11
N20 N21 N22 N23 N24 N25 N26 N27 N28 N29N10 N11 N12 N13 N14 N15 N16 N17 N18 N19N2
M28 M29M3 M30M4 M5 M6 M7 M8 M9
N1
M19M2 M20 M21 M22 M23 M24 M25 M26 M27
L9
M1 M10 M11 M12 M13 M14 M15 M16 M17 M18
L26 L27 L28 L29L3 L30L4 L5 L6 L7 L8 L17 L18 L19L2 L20 L21 L22 L23 L24 L25
K7 K8 K9
L1 L10 L11 L12 L13 L14 L15 L16
K24 K25 K26 K27 K28 K29K3 K30K4 K5 K6 K15 K16 K17 K18 K19K2 K20 K21 K22 K23
J5 J6 J7 J8 J9
K1 K10 K11 K12 K13 K14
J22 J23 J24 J25 J26 J27 J28 J29J3 J30J4 J13 J14 J15 J16 J17 J18 J19J2 J20 J21
H30H4 H5 H6 H7 H8 H9
J1 J10 J11 J12
H20 H21 H22 H23 H24 H25 H26 H27 H28 H29H3 H11 H12 H13 H14 H15 H16 H17 H18 H19H2
G29G3 G30G4 G5 G6 G7 G8 G9
H1 H10
G19G2 G20 G21 G22 G23 G24 G25 G26 G27 G28G1 G10 G11 G12 G13 G14 G15 G16 G17 G18
F27 F28 F29F3 F30F4 F5 F6 F7 F8 F9 F17 F18 F19F2 F20 F21 F22 F23 F24 F25 F26
E8 E9
F1 F10 F11 F12 F13 F14 F15 F16
E25 E26 E27 E28 E29E3 E30E4 E5 E6 E7 E15 E16 E17 E18 E19E2 E20 E21 E22 E23 E24
D6 D7 D8 D9
E1 E10 E11 E12 E13 E14
D23 D24 D25 D26 D27 D28 D29D3 D30D4 D5 D13 D14 D15 D16 D17 D18 D19D2 D20 D21 D22
C4 C5 C6 C7 C8 C9
D1 D10 D11 D12
C21 C22 C23 C24 C25 C26 C27 C28 C29C3 C30C11 C12 C13 C14 C15 C16 C17 C18 C19C2 C20
B3 B30B4 B5 B6 B7 B8 B9
C1 C10
B2 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29B1 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19
AK27 AK28 AK29AK3 AK4 AK5 AK6 AK7 AK8 AK9
T
AK18
T
AK19
S
AK2 AK20
S
AK21 AK22 AK23 AK24 AK25 AK26
AJ8 AJ9
AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17
AJ25 AJ26 AJ27 AJ28 AJ29AJ3 AJ30AJ4 AJ5 AJ6 AJ7 AJ15 AJ16 AJ17 AJ18 AJ19AJ2 AJ20 AJ21 AJ22 AJ23 AJ24
AH6 AH7 AH8 AH9
AJ1 AJ10 AJ11 AJ12 AJ13 AJ14
AH23 AH24 AH25 AH26 AH27 AH28 AH29AH3 AH30AH4 AH5 AH13 AH14 AH15 AH16 AH17 AH18 AH19AH2 AH20 AH21 AH22
AG4 AG5 AG6 AG7 AG8 AG9
AH1 AH10 AH11 AH12
AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29AG3 AG30AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19AG2 AG20
AF3 AF30AF4 AF5 AF6 AF7 AF8 AF9
AG1 AG10
AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29AF1 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19
AE28 AE29AE3 AE30AE4 AE5 AE6 AE7 AE8 AE9 AE18 AE19AE2 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27
AD8 AD9
AE1 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17
AD26 AD27 AD28 AD29AD3 AD30AD4 AD5 AD6 AD7 AD16 AD17 AD18 AD19AD2 AD20 AD21 AD22 AD23 AD24 AD25
AC6 AC7 AC8 AC9
AD1 AD10 AD11 AD12 AD13 AD14 AD15
AC24 AC25 AC26 AC27 AC28 AC29AC3 AC30AC4 AC5 AC14 AC15 AC16 AC17 AC18 AC19AC2 AC20 AC21 AC22 AC23
AB4 AB5 AB6 AB7 AB8 AB9
AC1 AC10 AC11 AC12 AC13
AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29AB3 AB30AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19AB2 AB20 AB21
AA3 AA30AA4 AA5 AA6 AA7 AA8 AA9
AB1 AB10 AB11
AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19AA2
A27 A28 A29A3 A4 A5 A6 A7 A8 A9
AA1
T
A19
S
A2 A20
S
A21 A22 A23 A24 A25 A26
XC2VP7FF896
IC7004
A10 A11 A12 A13 A14 A15 A16 A17
T
A18
DP_GOL_RX4A
GOL_RXNVRP_2VCCAUX
DMAR_n
BufR_W_n
BufA(18)
SMBClkSMBDataT_Alert_n
Rst_n
GOL_LVDS
GOL_LVDS
DP_GOL_TX4A
GOL_TXN
GOL_LVDS
GOL_LVDS
DP_GOL_TX4A
GOL_TXP
GOL_LVDS
GOL_LVDS
DP_GOL_RX4A
GOL_RXP
GOL_LVDSGOL_LVDS
SDRAM_A(4)SDRAM_A(5)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(16)Adr(15)Adr(14)Adr(13)Adr(12)Adr(11)
VCCAUXVRP_7LEDs(0)GNDVCCAUXVCCAUXGND
Adr(6)Adr(5)Adr(4)GND
SDRAM_A(6)SDRAM_A(7)SDRAM_A(8)SDRAM_A(9)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5IRQ2_nData(3)VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(10)Adr(9)Adr(8)Adr(7)
SDRAM_DQ(30)SDRAM_DQ(31)SDRAM_DQM(3)SDRAM_A(3)
Data(10)Data(15)D1PWRDWN_BAdr(3)Adr(2)
GNDSDRAM_CKESDRAM_A(12)SDRAM_DQM(1)M1M2D7TestCon(10)TestCon(9)TestCon(8)IRQ1_nData(2)Data(9)Data(11)Data(16)D0DONECCLK
Data(19)Data(23)INIT_BGND
GNDGNDEmptyData(0)Data(6)GNDData(14)Data(20)Data(24)Data(25)GND
SDRAM_DQ(8)SDRAM_DQ(9)M0D6TestCon(13)TestCon(12)TestCon(11)IRQ0_nData(1)Data(7)Data(8)
VRN_5GNDTTC_n(5)GNDChaBusyLHC_ClkSharcWr_nData(4)GNDData(12)GNDVRP_4D2DOUTAdr(1)GNDAdr(0)Data(31)Data(30)
GNDRDWR_BTTC_n(4)TTC_n(6)TTC_n(7)SDRAM_CLKSDRAM_CLKinData(5)Data(13)
GNDGNDA21D4VRP_5TTC_n(3)GNDA19GNDClkSharcRd_nGNDGNDA18Data(18)VRN_4D3GNDA16Data(29)Data(28)GNDData(27)Data(26)
SDRAM_DQ(10)SDRAM_DQ(11)SDRAM_DQ(12)GNDSDRAM_DQ(13)CS_BD5
AVCCAUXTX19VTRXPAD19AVCCAUXRX19Clkx2Rocket_XClkVTTXPAD18AVCCAUXTX18VTRXPAD18AVCCAUXRX18Data(17)Data(22)VTTXPAD16AVCCAUXTX16VTRXPAD16AVCCAUXRX16VRP_3GNDVCCAUX
SDRAM_DQ(14)SDRAM_DQ(15)
GND
ROCKET_LVDS
Rocket_TXN
ROCKET_LVDS
Rocket_TXP
ROCKET_LVDS
Rocket_RXP
ROCKET_LVDS
Rocket_RXNVCCAUXVCCAUXGNDData(21)VRN_3VCCAUX
VCCAUXGNDVRP_6VTTXPAD21AVCCAUXTX21VTRXPAD21AVCCAUXRX21TTC_n(1)TTC_n(2)VTTXPAD19
VTTXPAD6AVCCAUXTX6VTRXPAD6AVCCAUXRX6GOL_XClkVTTXPAD7AVCCAUXTX7VTRXPAD7AVCCAUXRX7VTTXPAD9AVCCAUXTX9VTRXPAD9AVCCAUXRX9VRN_2GNDVCCAUX
VCCAUXVRN_6TTC_n(0)
BufCE_nGNDBufA(7)BufA(6)GNDA4LEDs(3)LEDs(2)GNDA6UpLEDGNDGNDGNDA7GNDA9GND
VCCAUXGNDVRN_7VTTXPAD4AVCCAUXTX4VTRXPAD4AVCCAUXRX4LEDs(1)
GOL_TX_FaultVRP_1VRN_1GND
BufD(33)GNDBufD(16)DXNChaID(0)ChaID(1)GNDGOL_MOD_DEF0GOL_MOD_DEF1GNDErrLEDGOL_TX_DisableGOL_RX_LOSGNDGNDGND
BufA(19)
PROG_BTestCon(2)TestCon(3)TestCon(4)TestCon(5)TestCon(6)TCK
TDIGNDTestCon(0)TestCon(1)GNDGNDGNDTDO
GNDVRP_0VRN_0ChaID(2)GOL_RATE_SELGOL_MOD_DEF2
BufD(25)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2TestCon(14)
GNDBufD(19)DXPHSWAP_ENTestCon(7)TestCon(15)TMSVBATTGND
BufD(17)BufD(18)
BufD(26)BufD(27)BufD(28)BufD(29)BufD(30)BufD(31)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2
BufD(20)BufD(21)BufD(22)BufD(23)BufD(24)
GNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufD(32)BufA(5)GNDBufA(4)BufA(3)GNDVCCO_7VCCO_7GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_2VCCO_2GNDGND
VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufA(2)BufA(1)BufA(0)BufA(10)BufA(11)BufA(12)BufA(13)BufA(14)VCCO_7VCCO_7VCCINTGNDGNDGND
BufD(11)BufD(12)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2GND
BufA(15)BufA(16)BufD(35)BufD(0)BufD(1)BufD(2)BufD(3)BufD(4)VCCO_7VCCO_7
BufA(9)BufA(8)BufA(17)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCAUX
BufD(5)BufD(6)BufD(7)BufD(8)BufD(9)GNDBufD(10)
SDRAM_DQ(4)SDRAM_DQ(5)SDRAM_DQ(6)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3Spare(0)Spare(1)Spare(2)Spare(3)Spare(4)VCCAUX
VCCAUXBufD(13)BufD(14)BufD(15)BufD(34)
SDRAM_RAS_nGNDSDRAM_CS_nSDRAM_A(11)SDRAM_BA(0)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3GND
VCCAUXSDRAM_DQ(0)SDRAM_DQ(1)SDRAM_DQ(2)SDRAM_DQ(3)
SDRAM_A(0)SDRAM_A(1)SDRAM_A(2)SDRAM_DQM(2)SDRAM_DQ(16)SDRAM_DQ(17)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3A21_Select
SDRAM_DQ(7)SDRAM_DQM(0)SDRAM_WE_nSDRAM_CAS_n
SDRAM_DQ(21)SDRAM_DQ(22)SDRAM_DQ(23)SDRAM_DQ(24)SDRAM_DQ(25)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3MS3_nMS2_nMS1_nMS0_nAdr(21)
SDRAM_BA(1)SDRAM_A(10)
SDRAM_DQ(26)SDRAM_DQ(27)GNDSDRAM_DQ(28)SDRAM_DQ(29)GNDVCCO_6VCCO_6GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_3VCCO_3GNDAdr(20)Adr(19)GNDAdr(18)Adr(17)
SDRAM_DQ(18)SDRAM_DQ(19)SDRAM_DQ(20)
XC2VP7/20 VCCINT Decoupling Capacitors
FYSICA EN HOGE ENERGIE-FYSICA
IccINT = 600 mA
Dim
A
B
C
18
A
173
K
13
Date
15 16 17 18
AVX TAJB476K010R
11
IccAUX = 250 mA (min)
ET-Nikhef Amsterdam
VCCAUX and VCCO can ramp up at any rate
3
Proj.No:
1
4
AVX TAJB476K010R
2
D
Rev
L
E
F
For Xilinx Virtex-II Pro, power supplies
can be turned on in any sequence.
8
Proj:
7
6 7
VCCINT Ramp rate 200 us min. and 50 ms max.
NIKHEFof
G
14
Pagec
K
L
Min. Power-On Current XC2VP20
Min. Power-On Current XC2VP20
G
H
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Name
Size
9 10 11 12 13
14
I
J
10
B
E
5
16
XC2VP7/20 VCCAUX Decoupling Capacitors
NATIONAAL INSTITUUT VOOR KERN-
Power Inputs
1:51:34 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
3 6
9 12
4
1
15
AVX TAJB476K010R
AVX TAJB476K010R
8
F
2
C
D
All GND nets on the FPGA need
to be connected to golbal GROUND.
6
5
Time
J
I
H
22n
C7046
GND
channel_in
Input FPGA Power Supply Decoupling
MROD-X 38405
Peter Jansweijer [email protected]
2V2
7 Feb 2006
680p
C7040
GND
47u
C7097
GND
680p
C7009
GND
GND
C7045
22n
GND
C7096
47u
22n
C7083
GND
C7084
22n
GND
C7050
22n 22n
C7052
GND
C7090
100n
GND
100n
C7095
GND
GND
680p
C7067
GND
GND
680p
C7044
GNDC7082
680p
680p
22n
C7079
GND
680p680p
C7071
GND
GND
C7008
GND
680p
C7087
C7072
GND
C7014
680p
C7041
680p
22n
C7047
22n
C7059
GND
C7039
680p
GND
GND
C7053
100n
C7055
47u
GND
GND
GND
GND
C7018
680p
680p
C7061
GND
GND
22n
C7024
22n
C7069
GND
GND
C7062
680p
GND
GND
GND
C7025
22n
C7043
680p
GND
C7051
22n
GNDGND
C7048
22n
C7023
22n
GND
680p
C7077
GND
GND GND
GND
C7022
22n
47u
C7035
C7016
680p
GND
C7019
22n
GND
680p
C7081
GND
100n
C7075
GND
GND
C7033
C7086
680p
C7068
22n
22n
C7049
C7092
680p
GND
100n
GND
GND
C7076
680p
GND
GND
680p
C7042
C7078
22n
GND
C7036
47u
C7030
100n
680p
C7017
GND
C7066
680p
GND
GND
GND
22n
C7073
GND
C7064
22n
GND
C7094
22n
GND
C7037
680p
C7028
22n
GND
GND
680p
C7015
22n
C7020
C7070
100n
680p
C7013
680p
C7091
GND
GND
100n
C7054
GND
100n
C7085
C7080
100n
680p
C7038
GNDGND
C7060
100n
GND
22n
C7021
C7058
22n
GND
100n
C7065
GND
C7012
680p
GND
GND
GND
GND
C7074
22n
C7056
680p
22n
C7093
GND
C7010
680p
22n
C7063
680p
C7057
GND
GND
C7088
22n
GND
680p
C7011
GND
GND
GND
GND
22n
C7089
C7034
100n
GND
100n
C7029
GND
GND
C7031
100n
GND
100n
C7032
22n
C7026
GND
22n
C7027
GND
1V5POWER_NET_TYPE
VCCINT
VCCINT
2V5POWER_NET_TYPE
VCCAUX
VCCAUX
POWER_NET_TYPE
3V33V3
3V3
POWER_NET_TYPE
GND
GND
GND
GND
VCCO_0
VCCO_1
VCCO_2
VCCO_4
VCCO_5
VCCO_6
VCCO_7
VCCO_3
2V5 @ 1,5A
Proj:
97
c ET-Nikhef Amsterdam
142
Buffer Memory interface
L
AVX TAJB476K010R
=> MGT Power (estimated 31 + 49 = 80 mA)
G
K
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
10
Series Termination for
3 5 131210
NIKHEF
Name
Series Termination for
Date
H
2 15
KRUISLAAN 409, 020-592 2000
16
Not (yet) used
H
General purpose
1
Size
PAD6 connected to GOL
PAD19 connected to MROD-Out FPGA
DC coupled
4
Not (yet) used
Series Termination for
L
1
AC coupled
Note: VT1V8_MGT is common to all MROD-Ins
11 14
General purpose
G
9
17 18
A
15
of
E
F
4
=> MGT TX (RX) Termination (estimated 11 mA)
1098 SJ AMSTERDAM NEDERLAND
Sharc Databus
Time
18
B
C C
J
I
Proj.No:
Series Termination for
3
D
6
6
13
SDRAM interface
B
K
Series Termination for
A
D
Series Termination for
I
J
Series Termination for
E
16
11 12
7
Sharc Addressbus
Series Termination for
17
Rev
8
channel_in
Input FPGA MGT Pwr Decoupling, Termination
MROD-X 38405
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:01 pm
tonvr
A3 4 1 4 A
420 x 297 mm
4 6
AVX TAJB476K010R
5
F
Page
Dim
8
GND
R7028
1M
1u
L7004
GND
L7018
1u
R7011
47
47
R7009
GND
L7019
1u
L7033
1u
GND GND
L7014
1u
C7100
100n
GND
2%
100 R7006
1u
L7021
GND
GND
GND
GND
GNDGND
GND
GND
L7022
1u
GND
GND
GND
220n
C7111
L7029
1u
C7101
47u
C7113
220n
GND
GND
GND GND
GND
R7009
47
GNDGND
GND
GND
C7115
220n
GND
GND
GND
GND2TAB
2IN OUT
4
5S_A
1_SHDN
47
R7009
0E01u
L7012
LT1963A_DD
IC7005
3GND1
GND
R7011
47
R7029
R7011
47
C7131
220n
GND
220n
C7104
C7129
220n
GND
GND
GND
C7133
220n
GND
GND
GND
GND
GND GND
L7025
1u
L7027
1u
C7118
GND
GND
L7009
1u
R7007
95E3
2%
220n
R7009
47
L7017
1u
GND GND
GND
C7108
220n
GND
1u
L7007
R7010
47
C7105
220n
C7123
220n
R7005
4K7
L7031
1u
1u
220n
C7116
C7107
220n
C7125
220n
C7124
220n
GND
L7026
L7010
1u
220n
C7120
GND
C7110
220n
C7103
220n
GND
C7109
220n
220n
C7102
GND
220n
C7112
C7127
220n
GND
47
R7008
C7098
47u
GND
R7008
47
C7119
220n
GND
C7117
220n
L7024
1u
L7020
1u
L7016
1u
L7015
1u1u
L7013
C7106
220n
R7008
47
1u
L7023
1u
GND
1u
L7011
C7121
220n
L7005
1u
L7030
C7099
100n
R7010
47
R7008
47
L7006
1u
C7126
220n
1u
L7003
L7032
1u1u
C7122
220n
R7011
47
L7034
1u
L7008
1u
L7028
R7010
47
47
R7010
C7114
220n
C7128
220n
GND
C7132
220n
VTRXPAD7VTRXPAD6VTRXPAD4
VT2V5_MGT
VT2V5_MGT
VT1V8_MGT
AVCCAUXTX4
VTTXPAD4
VRN_7
VRP_7
C7130
220n
VRN_4
3V3
VRP_4
VRN_5
3V3
VRP_5
VRN_6
3V3
VRP_6
3V3
VCCA_MGTPOWER_NET_TYPE
3V3
VTRXPAD9
VTRXPAD19 VTRXPAD18 VTRXPAD16
VRN_0
3V3
VRP_0
VRN_1
3V3
VRP_1
VRN_2
3V3
VRP_2
VRN_3
3V3
VRP_3
AVCCAUXTX18 AVCCAUXTX16
AVCCAUXRX16AVCCAUXRX18AVCCAUXRX19AVCCAUXRX21
VTTXPAD21 VTTXPAD19 VTTXPAD18 VTTXPAD16
VTRXPAD21
AVCCAUXTX9
AVCCAUXRX9AVCCAUXRX7AVCCAUXRX6AVCCAUXRX4
VTTXPAD6 VTTXPAD7 VTTXPAD9
AVCCAUXTX21 AVCCAUXTX19
POWER_NET_TYPE
VT2V5_MGT
VCCA_MGT
VCCA_MGT
GNDA4 GNDA6 GNDA7 GNDA9
GNDA21 GNDA19 GNDA18 GNDA16
AVCCAUXTX6 AVCCAUXTX7
18
E
5
F
B
C
7
c ET-Nikhef Amsterdam
Proj.No:
Date
Time
9
H
6
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
7 17
SDRAM_A(12) is not connected
L
1
J
11
A
of
G
NIKHEF
8
Proj:
K
8
2
16
I
163 5 14
Rev
E
17
9
18
1 10
H
4
Size
15
15
C
D
J
K
L
A
G
4
D
12
I
10
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:29 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
5 6
11 12
KRUISLAAN 409, 020-592 2000
13
2
1098 SJ AMSTERDAM NEDERLAND
6
F
Dim
Page
B
3
Name
13 14
8
GND
GND
channel_in
Buffer Memory (ZBT and SDRAM)
MROD-X 38405
9
21
22
32
GND
GND
4 1
GND
GND
8
C7142
22n
4K7
R7012
4K7
R7012
C7159
22n
4K7
R7012
C7141
22n
R7012
4K7
31
8
9
10
C7146
100n
13
GND
GND
GND
0
GND
GND
25
GND
C7144
22n
GND
6
3
GND
0
23
GND
GND
16
18
GNDGND
1
GND
2
13
15
GND GND
GND
29
30
20
9
GND
15
5
28
GND
6
7
C7162
100n
3
4
GND
30
11
GND
C7148
100n
GND
GND
GND
3 2
14
15
GND
14
19
12
GND
24
GND
GND
3
26
GND
9
16
33
7
2
GND
GND
GND
GND
GND
GND
GND
0
GND
7
16
GND
25
GND
11
10
11
0
12
4
31
27
24
19
GND
GND
35
GND
2
3
GND
17
18
VssQ438
VssQ546
VssQ652
78VssQ7
VssQ884
18_CAS
20_CS
_RAS19
17_WE
C7134
22n
49
VddQ655
VddQ775
81VddQ8
Vss144
Vss258
Vss372
86Vss4
VssQ16
VssQ212
32VssQ3
NC570
NC673
Vdd11
Vdd215
Vdd329
Vdd443
VddQ13
VddQ29
VddQ335
VddQ441
VddQ5
DQ713
DQ874
DQ976
DQM016 71
DQM1
DQM228
DQM359
NC114
NC230
NC357
69NC4
47
DQ2648
DQ2750
DQ2851
53DQ29
DQ37
DQ3054
56DQ31
DQ48
DQ510
11DQ6
85
DQ1631
DQ1733
DQ1834
DQ1936
DQ25
DQ2037
DQ2139
DQ2240
DQ2342
DQ2445
DQ25
23BA1
CKE67
CLK68
DQ02
4DQ1
DQ1077
DQ1179
80DQ12
DQ1382
DQ1483
DQ15
24
A1121
A227
A360
A461
A562
A663
A764
A865
A966
BA022
100n
27
28
MT48LC8M32B2
IC7007
A025
A126
A1010
5
6
7
C7152
22n
C7147
C7135
22n
1
2
GND
GND
GND
1
C7157
22n
GND
14
17
10
1
11
C7165
100n
C7156
22n
0
13
100n
C7164
C7161
22n
_BW4
_CE1
98
92
_CE2
_CEN
87
31
_LBO
_OE
86
C7158
22n
12
21VSS4
26VSS5
40
VSS6
55VSS7
VSS860
67VSS9
64ZZ
_BW1
93
94
_BW2
_BW3
95
96
16VDD5
20VDD6
27VDD7
VDD8
41
54VDD9
5VSS1
VSS1071
76VSS11
90
VSS12
VSS210
VSS317
VDD14
61VDD10
VDD1165
66VDD12
VDD1370
VDD1477
VDD15
91
11VDD2
VDD314
15VDD4
68IO8
69IO9
IOp151
IOp280
IOp31
IOp430
R_W
88
TCK
43
39
TDI
42
TDO
TMS
38
22
IO2723
24IO28
IO2925
57IO3
28IO30
29IO31
IO458
59IO5
IO662
IO763
IO16
IO173
6IO18
IO197
IO256
IO208
9IO21
12IO22
IO2313
18IO24
19IO25
IO2697
CE2
CLK
89
52IO0
IO153
72IO10
IO1173
74IO12
IO1375
78IO14
79IO15
2
83
84
A18
A2
35
A3
34
33
A4
32
A5
A6
100
99
A7
82
A8
81
A9
85
ADV_LD
IDT71V65603S100PF
IC7006
A0
37
36
A1
A10
44
A11
45
A12
46
A13
47
48
A14
A15
49
50
A16
A17
22n 22n
C7154
26
8
C7140
22n 22n
C7145
GND
C7138C7137
22n
5
22n
C7136
C7149
100n
GND
C7160
22n
C7143
C7153
22n
20
21
C7163
100n
22
0
4
5
22n
19
34
17
GND
6
GND
GND
GND
29
GND
23
18
22n
1
GND
22n 22n
C7155C7139
22n
C7150
BufCE_n SDRAM_CLKZ50_NET_TYPE
Z50_NET_TYPE
SDRAM_CLKin
SDRAM_WE_n
SDRAM_RAS_n
SDRAM_CAS_n
C7151
3V3
Clkx2
BufR_W_n
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
SDRAM_CS_n
SDRAM_DQ(31:0)
SDRAM_DQM(3:0)
SDRAM_BA(1:0)
SDRAM_A(12:0)
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
BufD(35:0)
BufA(19:0)
3V3
3V3
3V3
3V3
3V3
SDRAM_CKE
c
3
7
7
Answer Record #18562
14
Input Channel ID bits
10 17
K
GND
E
H
5
configuration. See Xilinx PROM Errata,
Testpoints force Spare
lines to be accessible.I
18
arc242 package
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
L
FPGA JTAG Signals
12
Temperature sensing diode
6
0 1 1 Master SelectMAP
12
0
It may be necessary to use Master SelectMap
3
I
HSWAP_EN = ’0’ => User IOs have pull-up
A
E
CLK
FPGA Configuration Signals
2
Default configuration mode will be Slave SelectMAP.
17
16
Connector
1
J J
Page
NATIONAAL INSTITUUT VOOR KERN-
H
PWRDWN_B is unsupported (should be pulled high)
Optinal Test
G
8
Clock Signals
16
chains where the same bitstream is loaded into multiple devices.
11
1098 SJ AMSTERDAM NEDERLAND
1
F
is no possibility for readback (RDWR_B = ’0’)
8 Input channels are loaded in parallel so there
Time
Dim
2
Proj:
9
to Master SelectMap and all other MROD-In FPGAs
to Slave SelectMap.
B
Size
Rocket IO Signals
15
Proj.No:
Rev
1 0 1 Boundary scan
’On’ = ’1’, ’Off’ = ’0’
13 18
Note: FCC_SelectMAP = 50 MHz so CCLK < 50 MHz!
M2 M1 M0
1 1 0 Slave SelectMAP (default)
6
D
14
-> Slave SlectMAP programming Mode -> BUSY.
15
13
Date
Name
See "Virtex-II Pro FPGA User Guide", Chapter 4 -> Configuration
F
FPGA Control signals
Cand each CS_B = ’0’
A
of
154
8
C
9
11
In this case set MROD-Out FPGA and one MROD-In FPGA
TTC Signals
NIKHEF
Pull-Ups
3
resistors during configuration
ET-Nikhef Amsterdam
K
5
4
B
2
1
D
L
G
10
66
420 x 297 mm
4 1 4 AA3
Ton van Reen
1:53:04 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405 MROD-X
Input FPGA Auxiliary Connections
channel_in
VBATT is decriptor key memory backup supply
Sharc Signals Frontend to Backend
DOUT is BUSY in SelectMAP mode and BUSY should NOT be used for parallel
1
0
6
GND
15
9
Fiducial7002
22n
C7168
NC7SZ08
IC7012
1
2
3
5
4
2n2
C7171
J4A 2
GND
2
U3_4A
U2_4A
1
2
3
5
4
0E0
R7026
NC7SZ00
IC7009
1
2
3
5
4
NC7SZ00
IC7011
C7166
22n
R7027
1K0
Fiducial7001
J4A 12
GND
Sw4A
17
180
R7013
GND
3
2
0
J4A 15
12
J4A
NC7SZ00
IC7010
1
2
3
5
4
SMD_LED_Red
D7002
J4A 16
GND
J4A 5
GND
GND
13
4
3
0
J4A 4
J4A 18
J4A 19
1K0
R7019
3
GND
GND
5
20
R70231K0
U1_4A
J4A
J4A 13
GND
1
2
J4A
R7015
J4A 8
4K7
R7025
180
R7024
D7004
SMD_LED_Green
180
R7025
Sw4A
D7001
SMD_LED_Red
ADD12
4DXN
5DXP
GND
3
SMBCLK8
SMBDATA9
VCC
6
10_ALERT
_STBY7
4K7
6
100n
C7172
GND
IC7013
MAX1618
1ADD0
11R7025
4K7
J4A
R70181K0
J4A 10
J4A
J4A 1
GND
SMD_LED_Green
D7003
Sw4A
J4A 7
R7020
NC7SZ00
IC7008
1
2
3
5
4
U4_4A
14
1K0
7
GND
10
4
R70224K7
6
5
GND
180
R7016 8
1
14
U0_4A
C7170
22n
R7021
180
R7014
J4A
GND
1K0
22n
C7167
7
GND
11GND
3
1K0
R7017
GND
GND
4
Spare(4:0)
J4A 9
22n
C7169
GND
CS_B
VCCAUXPWRDWN_B
CCLKCCLK
HSWAP_EN
PROG_BPROG_B
DXP
DXN
SMBClk
3V3
M2 M1
VCCAUX
M0
Spare(4:0)
Clk
TestCon(15:0)
3V3
3V3
3V3
3V3
T_Alert_n
SMBData
DOUT
INIT_BINIT_B
DONEDONE
D7
D6
D5
D4
D3
D2
D1
D0 D(7:0)
RDWR_B
3V3
ChaBusy ChaBusy
TTC_n(7:0)TTC_n(7:0)
ChaID(2:0)ChaID(2:0)
TCK
TDO
FPGA_TCK
FPGA_TMS
TDI FPGA_TDI
FPGA_TDO
Clk Clk
Clkx2Clkx2
LHC_ClkLHC_Clk
Rocket_XClk Rocket_XClk
Adr(21:0)Adr(21:0)
IRQ1_n IRQ1_n
IRQ2_n IRQ2_n
Empty Empty
DMAR_n DMAR_n
Rocket_RXPRocket_RXP
Rocket_RXN Rocket_RXN
Rocket_TXPRocket_TXP
Rocket_TXNRocket_TXN
A21_SelectA21_Select
TMS
3V3
LEDs(0)
LEDs(1)
LEDs(2)
LEDs(3)
General_Rst_n
Channel_Rst_n
Rst_n
VBATT
IRQ0_n IRQ0_n
Data(31:0) Data(31:0)
MS0_n MS0_n
MS1_nMS1_n
MS2_n MS2_n
MS3_nMS3_n
SharcRd_nSharcRd_n
SharcWr_n SharcWr_n
H
I
9
15 16 17
C
14
I
J
G
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1
Name
Size
Dim
K
L
3
Date
Time
of
4
10u Tantalum
AVX TAJB106K010R
J
13
13
10
D
62 107 8
5 15 16 17
C
11 12
D
14
B
11 12
NIKHEF
7 863 4
Page
E
F
E
F
A
H
18
G
V2
7 Feb 2006
1:50:33 pm
tonvr
A3 4 1 4 A
420 x 297 mm
1 6
GOL_MOD_DEF and GOL_TX_Fault
Signal Pull-ups in one
arc242 package
1098 SJ AMSTERDAM NEDERLANDET-Nikhef Amsterdam
B
5
Rev
c
K
1 2
L
A
9
Proj: Proj.No:
18
GND
channel_in
GOL Input
MROD-X 38405
Peter Jansweijer [email protected]
2
2
3
5
4
10u
C8002
R8002180
R8001180
IC8002
NC7SZ00
1
2
3
5
4
GND
C8007
22n
GND
GND4GND4
GND5GND5
GND6GND6
GND7GND7
GND8
GND8
GND9
GND9
GND
IC8003
NC7SZ00
1
GND12
GND13GND13
GND14GND14
GND15GND15
GND16GND16
GND17GND17
GND18
GND18
GND19
GND19
GND2GND2
GND20
GND20
GND3GND3
C8001
SFPT_cage
IC8001
GND1GND1
GND10
GND10
GND11GND11
GND12
4K7
GND
GND
GND
100n
1u
L8002
R8004
D4B
k_r
a_r
GND GND
L8001
1u
100n
C8004
D4B
Fr_LED_Gn
k_g
a_g
Fr_LED_Rd
GND
GND
22n
C8006
C8003
100n
4K7
4K7
R8003R8003
4K7
20
mod_def06
mod_def15
mod_def24
4K7
R8003R8003
Tx_disable3
Tx_fault2
VccR
15
VccT
16
VeeR1
9
VeeR2
10
VeeR3
11
14
VeeR4
VeeT1
1
VeeT2
17
VeeT3
IC8001
HFBR5720
LOS8
RD_n12 S
RD_p13 S
Rate_Sel7
TD_n19 T
TD_p18 T
GOL_XClk GOL_XClk
3V3
3V3
GOL_TX_Fault
GOL_MOD_DEF2
GOL_MOD_DEF1
GOL_MOD_DEF0
3V3
10u
C8005
GOL_RX_LOS
GOL_RXNGOL_LVDSGOL_LVDS
GOL_RXPGOL_LVDSGOL_LVDS
GOL_RATE_SEL
GOL_TXPGOL_LVDSGOL_LVDS
GOL_TX_Disable
ErrLED
UpLED
GOL_TXNGOL_LVDSGOL_LVDS
10 11 12 13
G
H
3 4
G
II
J
Date
2
VCCO_# (3V3) 10 pins each
12
Proj: Proj.No:
Rev
Size
A
Dim
1 3 6 7
7
NIKHEF
1
C
D
Input FPGA Power pins:
c ET-Nikhef Amsterdam
2
16
L
J
K
14
9
Page
A
B
C
K
6 18
E
F
KRUISLAAN 409, 020-592 2000
1715
VCCAUX (2V5) 16 pins
VCCINT (1V5) 32 pins
D
of
15
Time
Name
H
5
E
tonvr
1:50:53 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
Input FPGA
channel_in
8 9 16
8 14 18
11
1098 SJ AMSTERDAM NEDERLAND
L
B
10 13
4 5
F
17
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
GND 124 pins
62
420 x 297 mm
4 1 4 AA3
Y6 Y7 Y8 Y9 Y23 Y24 Y25 Y26 Y27 Y28 Y29Y3 Y30Y4 Y5 Y13 Y14 Y15 Y16 Y17 Y18 Y19Y2 Y20 Y21 Y22
W4 W5 W6 W7 W8 W9
Y1 Y10 Y11 Y12
W21 W22 W23 W24 W25 W26 W27 W28 W29W3 W30W11 W12 W13 W14 W15 W16 W17 W18 W19W2 W20
V3 V30V4 V5 V6 V7 V8 V9
W1 W10
V2 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29V1 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19
U28 U29U3 U30U4 U5 U6 U7 U8 U9 U18 U19U2 U20 U21 U22 U23 U24 U25 U26 U27
T8 T9
U1 U10 U11 U12 U13 U14 U15 U16 U17
T26 T27 T28 T29T3 T30T4 T5 T6 T7 T16 T17 T18 T19T2 T20 T21 T22 T23 T24 T25
R6 R7 R8 R9
T1 T10 T11 T12 T13 T14 T15
R24 R25 R26 R27 R28 R29R3 R30R4 R5 R14 R15 R16 R17 R18 R19R2 R20 R21 R22 R23
P4 P5 P6 P7 P8 P9
R1 R10 R11 R12 R13
P22 P23 P24 P25 P26 P27 P28 P29P3 P30P12 P13 P14 P15 P16 P17 P18 P19P2 P20 P21
N3 N30N4 N5 N6 N7 N8 N9
P1 P10 P11
N20 N21 N22 N23 N24 N25 N26 N27 N28 N29N10 N11 N12 N13 N14 N15 N16 N17 N18 N19N2
M28 M29M3 M30M4 M5 M6 M7 M8 M9
N1
M19M2 M20 M21 M22 M23 M24 M25 M26 M27
L9
M1 M10 M11 M12 M13 M14 M15 M16 M17 M18
L26 L27 L28 L29L3 L30L4 L5 L6 L7 L8 L17 L18 L19L2 L20 L21 L22 L23 L24 L25
K7 K8 K9
L1 L10 L11 L12 L13 L14 L15 L16
K24 K25 K26 K27 K28 K29K3 K30K4 K5 K6 K15 K16 K17 K18 K19K2 K20 K21 K22 K23
J5 J6 J7 J8 J9
K1 K10 K11 K12 K13 K14
J22 J23 J24 J25 J26 J27 J28 J29J3 J30J4 J13 J14 J15 J16 J17 J18 J19J2 J20 J21
H30H4 H5 H6 H7 H8 H9
J1 J10 J11 J12
H20 H21 H22 H23 H24 H25 H26 H27 H28 H29H3 H11 H12 H13 H14 H15 H16 H17 H18 H19H2
G29G3 G30G4 G5 G6 G7 G8 G9
H1 H10
G19G2 G20 G21 G22 G23 G24 G25 G26 G27 G28G1 G10 G11 G12 G13 G14 G15 G16 G17 G18
F27 F28 F29F3 F30F4 F5 F6 F7 F8 F9 F17 F18 F19F2 F20 F21 F22 F23 F24 F25 F26
E8 E9
F1 F10 F11 F12 F13 F14 F15 F16
E25 E26 E27 E28 E29E3 E30E4 E5 E6 E7 E15 E16 E17 E18 E19E2 E20 E21 E22 E23 E24
D6 D7 D8 D9
E1 E10 E11 E12 E13 E14
D23 D24 D25 D26 D27 D28 D29D3 D30D4 D5 D13 D14 D15 D16 D17 D18 D19D2 D20 D21 D22
C4 C5 C6 C7 C8 C9
D1 D10 D11 D12
C21 C22 C23 C24 C25 C26 C27 C28 C29C3 C30C11 C12 C13 C14 C15 C16 C17 C18 C19C2 C20
B3 B30B4 B5 B6 B7 B8 B9
C1 C10
B2 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29B1 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19
AK27 AK28 AK29AK3 AK4 AK5 AK6 AK7 AK8 AK9
T
AK18
T
AK19
S
AK2 AK20
S
AK21 AK22 AK23 AK24 AK25 AK26
AJ8 AJ9
AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17
AJ25 AJ26 AJ27 AJ28 AJ29AJ3 AJ30AJ4 AJ5 AJ6 AJ7 AJ15 AJ16 AJ17 AJ18 AJ19AJ2 AJ20 AJ21 AJ22 AJ23 AJ24
AH6 AH7 AH8 AH9
AJ1 AJ10 AJ11 AJ12 AJ13 AJ14
AH23 AH24 AH25 AH26 AH27 AH28 AH29AH3 AH30AH4 AH5 AH13 AH14 AH15 AH16 AH17 AH18 AH19AH2 AH20 AH21 AH22
AG4 AG5 AG6 AG7 AG8 AG9
AH1 AH10 AH11 AH12
AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29AG3 AG30AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19AG2 AG20
AF3 AF30AF4 AF5 AF6 AF7 AF8 AF9
AG1 AG10
AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29AF1 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19
AE28 AE29AE3 AE30AE4 AE5 AE6 AE7 AE8 AE9 AE18 AE19AE2 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27
AD8 AD9
AE1 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17
AD26 AD27 AD28 AD29AD3 AD30AD4 AD5 AD6 AD7 AD16 AD17 AD18 AD19AD2 AD20 AD21 AD22 AD23 AD24 AD25
AC6 AC7 AC8 AC9
AD1 AD10 AD11 AD12 AD13 AD14 AD15
AC24 AC25 AC26 AC27 AC28 AC29AC3 AC30AC4 AC5 AC14 AC15 AC16 AC17 AC18 AC19AC2 AC20 AC21 AC22 AC23
AB4 AB5 AB6 AB7 AB8 AB9
AC1 AC10 AC11 AC12 AC13
AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29AB3 AB30AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19AB2 AB20 AB21
AA3 AA30AA4 AA5 AA6 AA7 AA8 AA9
AB1 AB10 AB11
AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19AA2
A27 A28 A29A3 A4 A5 A6 A7 A8 A9
AA1
T
A19
S
A2 A20
S
A21 A22 A23 A24 A25 A26
XC2VP7FF896
IC8004
A10 A11 A12 A13 A14 A15 A16 A17
T
A18
DP_GOL_RX4B
GOL_RXNVRP_2VCCAUX
DMAR_n
BufR_W_n
BufA(18)
SMBClkSMBDataT_Alert_n
Rst_n
GOL_LVDS
GOL_LVDS
DP_GOL_TX4B
GOL_TXN
GOL_LVDS
GOL_LVDS
DP_GOL_TX4B
GOL_TXP
GOL_LVDS
GOL_LVDS
DP_GOL_RX4B
GOL_RXP
GOL_LVDSGOL_LVDS
SDRAM_A(4)SDRAM_A(5)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(16)Adr(15)Adr(14)Adr(13)Adr(12)Adr(11)
VCCAUXVRP_7LEDs(0)GNDVCCAUXVCCAUXGND
Adr(6)Adr(5)Adr(4)GND
SDRAM_A(6)SDRAM_A(7)SDRAM_A(8)SDRAM_A(9)VCCO_6VCCO_5VCCO_5VCCO_5VCCO_5IRQ2_nData(3)VCCO_4VCCO_4VCCO_4VCCO_4VCCO_3Adr(10)Adr(9)Adr(8)Adr(7)
SDRAM_DQ(30)SDRAM_DQ(31)SDRAM_DQM(3)SDRAM_A(3)
Data(10)Data(15)D1PWRDWN_BAdr(3)Adr(2)
GNDSDRAM_CKESDRAM_A(12)SDRAM_DQM(1)M1M2D7TestCon(10)TestCon(9)TestCon(8)IRQ1_nData(2)Data(9)Data(11)Data(16)D0DONECCLK
Data(19)Data(23)INIT_BGND
GNDGNDEmptyData(0)Data(6)GNDData(14)Data(20)Data(24)Data(25)GND
SDRAM_DQ(8)SDRAM_DQ(9)M0D6TestCon(13)TestCon(12)TestCon(11)IRQ0_nData(1)Data(7)Data(8)
VRN_5GNDTTC_n(5)GNDChaBusyLHC_ClkSharcWr_nData(4)GNDData(12)GNDVRP_4D2DOUTAdr(1)GNDAdr(0)Data(31)Data(30)
GNDRDWR_BTTC_n(4)TTC_n(6)TTC_n(7)SDRAM_CLKSDRAM_CLKinData(5)Data(13)
GNDGNDA21D4VRP_5TTC_n(3)GNDA19GNDClkSharcRd_nGNDGNDA18Data(18)VRN_4D3GNDA16Data(29)Data(28)GNDData(27)Data(26)
SDRAM_DQ(10)SDRAM_DQ(11)SDRAM_DQ(12)GNDSDRAM_DQ(13)CS_BD5
AVCCAUXTX19VTRXPAD19AVCCAUXRX19Clkx2Rocket_XClkVTTXPAD18AVCCAUXTX18VTRXPAD18AVCCAUXRX18Data(17)Data(22)VTTXPAD16AVCCAUXTX16VTRXPAD16AVCCAUXRX16VRP_3GNDVCCAUX
SDRAM_DQ(14)SDRAM_DQ(15)
GND
ROCKET_LVDS
Rocket_TXN
ROCKET_LVDS
Rocket_TXP
ROCKET_LVDS
Rocket_RXP
ROCKET_LVDS
Rocket_RXNVCCAUXVCCAUXGNDData(21)VRN_3VCCAUX
VCCAUXGNDVRP_6VTTXPAD21AVCCAUXTX21VTRXPAD21AVCCAUXRX21TTC_n(1)TTC_n(2)VTTXPAD19
VTTXPAD6AVCCAUXTX6VTRXPAD6AVCCAUXRX6GOL_XClkVTTXPAD7AVCCAUXTX7VTRXPAD7AVCCAUXRX7VTTXPAD9AVCCAUXTX9VTRXPAD9AVCCAUXRX9VRN_2GNDVCCAUX
VCCAUXVRN_6TTC_n(0)
BufCE_nGNDBufA(7)BufA(6)GNDA4LEDs(3)LEDs(2)GNDA6UpLEDGNDGNDGNDA7GNDA9GND
VCCAUXGNDVRN_7VTTXPAD4AVCCAUXTX4VTRXPAD4AVCCAUXRX4LEDs(1)
GOL_TX_FaultVRP_1VRN_1GND
BufD(33)GNDBufD(16)DXNChaID(0)ChaID(1)GNDGOL_MOD_DEF0GOL_MOD_DEF1GNDErrLEDGOL_TX_DisableGOL_RX_LOSGNDGNDGND
BufA(19)
PROG_BTestCon(2)TestCon(3)TestCon(4)TestCon(5)TestCon(6)TCK
TDIGNDTestCon(0)TestCon(1)GNDGNDGNDTDO
GNDVRP_0VRN_0ChaID(2)GOL_RATE_SELGOL_MOD_DEF2
BufD(25)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2TestCon(14)
GNDBufD(19)DXPHSWAP_ENTestCon(7)TestCon(15)TMSVBATTGND
BufD(17)BufD(18)
BufD(26)BufD(27)BufD(28)BufD(29)BufD(30)BufD(31)VCCO_7VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_0VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_1VCCO_2
BufD(20)BufD(21)BufD(22)BufD(23)BufD(24)
GNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufD(32)BufA(5)GNDBufA(4)BufA(3)GNDVCCO_7VCCO_7GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_2VCCO_2GNDGND
VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCO_2
BufA(2)BufA(1)BufA(0)BufA(10)BufA(11)BufA(12)BufA(13)BufA(14)VCCO_7VCCO_7VCCINTGNDGNDGND
BufD(11)BufD(12)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2GND
BufA(15)BufA(16)BufD(35)BufD(0)BufD(1)BufD(2)BufD(3)BufD(4)VCCO_7VCCO_7
BufA(9)BufA(8)BufA(17)VCCO_7VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_2VCCAUX
BufD(5)BufD(6)BufD(7)BufD(8)BufD(9)GNDBufD(10)
SDRAM_DQ(4)SDRAM_DQ(5)SDRAM_DQ(6)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3Spare(0)Spare(1)Spare(2)Spare(3)Spare(4)VCCAUX
VCCAUXBufD(13)BufD(14)BufD(15)BufD(34)
SDRAM_RAS_nGNDSDRAM_CS_nSDRAM_A(11)SDRAM_BA(0)VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3GND
VCCAUXSDRAM_DQ(0)SDRAM_DQ(1)SDRAM_DQ(2)SDRAM_DQ(3)
SDRAM_A(0)SDRAM_A(1)SDRAM_A(2)SDRAM_DQM(2)SDRAM_DQ(16)SDRAM_DQ(17)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3A21_Select
SDRAM_DQ(7)SDRAM_DQM(0)SDRAM_WE_nSDRAM_CAS_n
SDRAM_DQ(21)SDRAM_DQ(22)SDRAM_DQ(23)SDRAM_DQ(24)SDRAM_DQ(25)VCCO_6VCCO_6VCCINTGNDGNDGNDGNDGNDGNDGNDGNDVCCINTVCCO_3VCCO_3MS3_nMS2_nMS1_nMS0_nAdr(21)
SDRAM_BA(1)SDRAM_A(10)
SDRAM_DQ(26)SDRAM_DQ(27)GNDSDRAM_DQ(28)SDRAM_DQ(29)GNDVCCO_6VCCO_6GNDVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTGNDVCCO_3VCCO_3GNDAdr(20)Adr(19)GNDAdr(18)Adr(17)
SDRAM_DQ(18)SDRAM_DQ(19)SDRAM_DQ(20)
XC2VP7/20 VCCINT Decoupling Capacitors
FYSICA EN HOGE ENERGIE-FYSICA
IccINT = 600 mA
Dim
A
B
C
18
A
173
K
13
Date
15 16 17 18
AVX TAJB476K010R
11
IccAUX = 250 mA (min)
ET-Nikhef Amsterdam
VCCAUX and VCCO can ramp up at any rate
3
Proj.No:
1
4
AVX TAJB476K010R
2
D
Rev
L
E
F
For Xilinx Virtex-II Pro, power supplies
can be turned on in any sequence.
8
Proj:
7
6 7
VCCINT Ramp rate 200 us min. and 50 ms max.
NIKHEFof
G
14
Pagec
K
L
Min. Power-On Current XC2VP20
Min. Power-On Current XC2VP20
G
H
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Name
Size
9 10 11 12 13
14
I
J
10
B
E
5
16
XC2VP7/20 VCCAUX Decoupling Capacitors
NATIONAAL INSTITUUT VOOR KERN-
Power Inputs
1:51:34 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
3 6
9 12
4
1
15
AVX TAJB476K010R
AVX TAJB476K010R
8
F
2
C
D
All GND nets on the FPGA need
to be connected to golbal GROUND.
6
5
Time
J
I
H
22n
C8046
GND
channel_in
Input FPGA Power Supply Decoupling
MROD-X 38405
Peter Jansweijer [email protected]
2V2
7 Feb 2006
680p
C8040
GND
47u
C8097
GND
680p
C8009
GND
GND
C8045
22n
GND
C8096
47u
22n
C8083
GND
C8084
22n
GND
C8050
22n 22n
C8052
GND
C8090
100n
GND
100n
C8095
GND
GND
680p
C8067
GND
GND
680p
C8044
GNDC8082
680p
680p
22n
C8079
GND
680p680p
C8071
GND
GND
C8008
GND
680p
C8087
C8072
GND
C8014
680p
C8041
680p
22n
C8047
22n
C8059
GND
C8039
680p
GND
GND
C8053
100n
C8055
47u
GND
GND
GND
GND
C8018
680p
680p
C8061
GND
GND
22n
C8024
22n
C8069
GND
GND
C8062
680p
GND
GND
GND
C8025
22n
C8043
680p
GND
C8051
22n
GNDGND
C8048
22n
C8023
22n
GND
680p
C8077
GND
GND GND
GND
C8022
22n
47u
C8035
C8016
680p
GND
C8019
22n
GND
680p
C8081
GND
100n
C8075
GND
GND
C8033
C8086
680p
C8068
22n
22n
C8049
C8092
680p
GND
100n
GND
GND
C8076
680p
GND
GND
680p
C8042
C8078
22n
GND
C8036
47u
C8030
100n
680p
C8017
GND
C8066
680p
GND
GND
GND
22n
C8073
GND
C8064
22n
GND
C8094
22n
GND
C8037
680p
C8028
22n
GND
GND
680p
C8015
22n
C8020
C8070
100n
680p
C8013
680p
C8091
GND
GND
100n
C8054
GND
100n
C8085
C8080
100n
680p
C8038
GNDGND
C8060
100n
GND
22n
C8021
C8058
22n
GND
100n
C8065
GND
C8012
680p
GND
GND
GND
GND
C8074
22n
C8056
680p
22n
C8093
GND
C8010
680p
22n
C8063
680p
C8057
GND
GND
C8088
22n
GND
680p
C8011
GND
GND
GND
GND
22n
C8089
C8034
100n
GND
100n
C8029
GND
GND
C8031
100n
GND
100n
C8032
22n
C8026
GND
22n
C8027
GND
1V5POWER_NET_TYPE
VCCINT
VCCINT
2V5POWER_NET_TYPE
VCCAUX
VCCAUX
POWER_NET_TYPE
3V33V3
3V3
POWER_NET_TYPE
GND
GND
GND
GND
VCCO_0
VCCO_1
VCCO_2
VCCO_4
VCCO_5
VCCO_6
VCCO_7
VCCO_3
2V5 @ 1,5A
Proj:
97
c ET-Nikhef Amsterdam
142
Buffer Memory interface
L
AVX TAJB476K010R
=> MGT Power (estimated 31 + 49 = 80 mA)
G
K
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
10
Series Termination for
3 5 131210
NIKHEF
Name
Series Termination for
Date
H
2 15
KRUISLAAN 409, 020-592 2000
16
Not (yet) used
H
General purpose
1
Size
PAD6 connected to GOL
PAD19 connected to MROD-Out FPGA
DC coupled
4
Not (yet) used
Series Termination for
L
1
AC coupled
Note: VT1V8_MGT is common to all MROD-Ins
11 14
General purpose
G
9
17 18
A
15
of
E
F
4
=> MGT TX (RX) Termination (estimated 11 mA)
1098 SJ AMSTERDAM NEDERLAND
Sharc Databus
Time
18
B
C C
J
I
Proj.No:
Series Termination for
3
D
6
6
13
SDRAM interface
B
K
Series Termination for
A
D
Series Termination for
I
J
Series Termination for
E
16
11 12
7
Sharc Addressbus
Series Termination for
17
Rev
8
channel_in
Input FPGA MGT Pwr Decoupling, Termination
MROD-X 38405
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:01 pm
tonvr
A3 4 1 4 A
420 x 297 mm
4 6
AVX TAJB476K010R
5
F
Page
Dim
8
GND
R8028
1M
1u
L8004
GND
L8018
1u
R8011
47
47
R8009
GND
L8019
1u
L8033
1u
GND GND
L8014
1u
C8100
100n
GND
2%
100 R8006
1u
L8021
GND
GND
GND
GND
GNDGND
GND
GND
L8022
1u
GND
GND
GND
220n
C8111
L8029
1u
C8101
47u
C8113
220n
GND
GND
GND GND
GND
R8009
47
GNDGND
GND
GND
C8115
220n
GND
GND
GND
GND2TAB
2IN OUT
4
5S_A
1_SHDN
47
R8009
0E01u
L8012
LT1963A_DD
IC8005
3GND1
GND
R8011
47
R8029
R8011
47
C8131
220n
GND
220n
C8104
C8129
220n
GND
GND
GND
C8133
220n
GND
GND
GND
GND
GND GND
L8025
1u
L8027
1u
C8118
GND
GND
L8009
1u
R8007
95E3
2%
220n
R8009
47
L8017
1u
GND GND
GND
C8108
220n
GND
1u
L8007
R8010
47
C8105
220n
C8123
220n
R8005
4K7
L8031
1u
1u
220n
C8116
C8107
220n
C8125
220n
C8124
220n
GND
L8026
L8010
1u
220n
C8120
GND
C8110
220n
C8103
220n
GND
C8109
220n
220n
C8102
GND
220n
C8112
C8127
220n
GND
47
R8008
C8098
47u
GND
R8008
47
C8119
220n
GND
C8117
220n
L8024
1u
L8020
1u
L8016
1u
L8015
1u1u
L8013
C8106
220n
R8008
47
1u
L8023
1u
GND
1u
L8011
C8121
220n
L8005
1u
L8030
C8099
100n
R8010
47
R8008
47
L8006
1u
C8126
220n
1u
L8003
L8032
1u1u
C8122
220n
R8011
47
L8034
1u
L8008
1u
L8028
R8010
47
47
R8010
C8114
220n
C8128
220n
GND
C8132
220n
VTRXPAD7VTRXPAD6VTRXPAD4
VT2V5_MGT
VT2V5_MGT
VT1V8_MGT
AVCCAUXTX4
VTTXPAD4
VRN_7
VRP_7
C8130
220n
VRN_4
3V3
VRP_4
VRN_5
3V3
VRP_5
VRN_6
3V3
VRP_6
3V3
VCCA_MGTPOWER_NET_TYPE
3V3
VTRXPAD9
VTRXPAD19 VTRXPAD18 VTRXPAD16
VRN_0
3V3
VRP_0
VRN_1
3V3
VRP_1
VRN_2
3V3
VRP_2
VRN_3
3V3
VRP_3
AVCCAUXTX18 AVCCAUXTX16
AVCCAUXRX16AVCCAUXRX18AVCCAUXRX19AVCCAUXRX21
VTTXPAD21 VTTXPAD19 VTTXPAD18 VTTXPAD16
VTRXPAD21
AVCCAUXTX9
AVCCAUXRX9AVCCAUXRX7AVCCAUXRX6AVCCAUXRX4
VTTXPAD6 VTTXPAD7 VTTXPAD9
AVCCAUXTX21 AVCCAUXTX19
POWER_NET_TYPE
VT2V5_MGT
VCCA_MGT
VCCA_MGT
GNDA4 GNDA6 GNDA7 GNDA9
GNDA21 GNDA19 GNDA18 GNDA16
AVCCAUXTX6 AVCCAUXTX7
18
E
5
F
B
C
7
c ET-Nikhef Amsterdam
Proj.No:
Date
Time
9
H
6
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
7 17
SDRAM_A(12) is not connected
L
1
J
11
A
of
G
NIKHEF
8
Proj:
K
8
2
16
I
163 5 14
Rev
E
17
9
18
1 10
H
4
Size
15
15
C
D
J
K
L
A
G
4
D
12
I
10
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:52:29 pm
Ton van Reen
A3 4 1 4 A
420 x 297 mm
5 6
11 12
KRUISLAAN 409, 020-592 2000
13
2
1098 SJ AMSTERDAM NEDERLAND
6
F
Dim
Page
B
3
Name
13 14
8
GND
GND
channel_in
Buffer Memory (ZBT and SDRAM)
MROD-X 38405
9
21
22
32
GND
GND
4 1
GND
GND
8
C8142
22n
4K7
R8012
4K7
R8012
C8159
22n
4K7
R8012
C8141
22n
R8012
4K7
31
8
9
10
C8146
100n
13
GND
GND
GND
0
GND
GND
25
GND
C8144
22n
GND
6
3
GND
0
23
GND
GND
16
18
GNDGND
1
GND
2
13
15
GND GND
GND
29
30
20
9
GND
15
5
28
GND
6
7
C8162
100n
3
4
GND
30
11
GND
C8148
100n
GND
GND
GND
3 2
14
15
GND
14
19
12
GND
24
GND
GND
3
26
GND
9
16
33
7
2
GND
GND
GND
GND
GND
GND
GND
0
GND
7
16
GND
25
GND
11
10
11
0
12
4
31
27
24
19
GND
GND
35
GND
2
3
GND
17
18
VssQ438
VssQ546
VssQ652
78VssQ7
VssQ884
18_CAS
20_CS
_RAS19
17_WE
C8134
22n
49
VddQ655
VddQ775
81VddQ8
Vss144
Vss258
Vss372
86Vss4
VssQ16
VssQ212
32VssQ3
NC570
NC673
Vdd11
Vdd215
Vdd329
Vdd443
VddQ13
VddQ29
VddQ335
VddQ441
VddQ5
DQ713
DQ874
DQ976
DQM016 71
DQM1
DQM228
DQM359
NC114
NC230
NC357
69NC4
47
DQ2648
DQ2750
DQ2851
53DQ29
DQ37
DQ3054
56DQ31
DQ48
DQ510
11DQ6
85
DQ1631
DQ1733
DQ1834
DQ1936
DQ25
DQ2037
DQ2139
DQ2240
DQ2342
DQ2445
DQ25
23BA1
CKE67
CLK68
DQ02
4DQ1
DQ1077
DQ1179
80DQ12
DQ1382
DQ1483
DQ15
24
A1121
A227
A360
A461
A562
A663
A764
A865
A966
BA022
100n
27
28
MT48LC8M32B2
IC8007
A025
A126
A1010
5
6
7
C8152
22n
C8147
C8135
22n
1
2
GND
GND
GND
1
C8157
22n
GND
14
17
10
1
11
C8165
100n
C8156
22n
0
13
100n
C8164
C8161
22n
_BW4
_CE1
98
92
_CE2
_CEN
87
31
_LBO
_OE
86
C8158
22n
12
21VSS4
26VSS5
40
VSS6
55VSS7
VSS860
67VSS9
64ZZ
_BW1
93
94
_BW2
_BW3
95
96
16VDD5
20VDD6
27VDD7
VDD8
41
54VDD9
5VSS1
VSS1071
76VSS11
90
VSS12
VSS210
VSS317
VDD14
61VDD10
VDD1165
66VDD12
VDD1370
VDD1477
VDD15
91
11VDD2
VDD314
15VDD4
68IO8
69IO9
IOp151
IOp280
IOp31
IOp430
R_W
88
TCK
43
39
TDI
42
TDO
TMS
38
22
IO2723
24IO28
IO2925
57IO3
28IO30
29IO31
IO458
59IO5
IO662
IO763
IO16
IO173
6IO18
IO197
IO256
IO208
9IO21
12IO22
IO2313
18IO24
19IO25
IO2697
CE2
CLK
89
52IO0
IO153
72IO10
IO1173
74IO12
IO1375
78IO14
79IO15
2
83
84
A18
A2
35
A3
34
33
A4
32
A5
A6
100
99
A7
82
A8
81
A9
85
ADV_LD
IDT71V65603S100PF
IC8006
A0
37
36
A1
A10
44
A11
45
A12
46
A13
47
48
A14
A15
49
50
A16
A17
22n 22n
C8154
26
8
C8140
22n 22n
C8145
GND
C8138C8137
22n
5
22n
C8136
C8149
100n
GND
C8160
22n
C8143
C8153
22n
20
21
C8163
100n
22
0
4
5
22n
19
34
17
GND
6
GND
GND
GND
29
GND
23
18
22n
1
GND
22n 22n
C8155C8139
22n
C8150
BufCE_n SDRAM_CLKZ50_NET_TYPE
Z50_NET_TYPE
SDRAM_CLKin
SDRAM_WE_n
SDRAM_RAS_n
SDRAM_CAS_n
C8151
3V3
Clkx2
BufR_W_n
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
SDRAM_CS_n
SDRAM_DQ(31:0)
SDRAM_DQM(3:0)
SDRAM_BA(1:0)
SDRAM_A(12:0)
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
BufD(35:0)
BufA(19:0)
3V3
3V3
3V3
3V3
3V3
SDRAM_CKE
c
3
7
7
Answer Record #18562
14
Input Channel ID bits
10 17
K
GND
E
H
5
configuration. See Xilinx PROM Errata,
Testpoints force Spare
lines to be accessible.I
18
arc242 package
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
L
FPGA JTAG Signals
12
Temperature sensing diode
6
0 1 1 Master SelectMAP
12
0
It may be necessary to use Master SelectMap
3
I
HSWAP_EN = ’0’ => User IOs have pull-up
A
E
CLK
FPGA Configuration Signals
2
Default configuration mode will be Slave SelectMAP.
17
16
Connector
1
J J
Page
NATIONAAL INSTITUUT VOOR KERN-
H
PWRDWN_B is unsupported (should be pulled high)
Optinal Test
G
8
Clock Signals
16
chains where the same bitstream is loaded into multiple devices.
11
1098 SJ AMSTERDAM NEDERLAND
1
F
is no possibility for readback (RDWR_B = ’0’)
8 Input channels are loaded in parallel so there
Time
Dim
2
Proj:
9
to Master SelectMap and all other MROD-In FPGAs
to Slave SelectMap.
B
Size
Rocket IO Signals
15
Proj.No:
Rev
1 0 1 Boundary scan
’On’ = ’1’, ’Off’ = ’0’
13 18
Note: FCC_SelectMAP = 50 MHz so CCLK < 50 MHz!
M2 M1 M0
1 1 0 Slave SelectMAP (default)
6
D
14
-> Slave SlectMAP programming Mode -> BUSY.
15
13
Date
Name
See "Virtex-II Pro FPGA User Guide", Chapter 4 -> Configuration
F
FPGA Control signals
Cand each CS_B = ’0’
A
of
154
8
C
9
11
In this case set MROD-Out FPGA and one MROD-In FPGA
TTC Signals
NIKHEF
Pull-Ups
3
resistors during configuration
ET-Nikhef Amsterdam
K
5
4
B
2
1
D
L
G
10
66
420 x 297 mm
4 1 4 AA3
Ton van Reen
1:53:04 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405 MROD-X
Input FPGA Auxiliary Connections
channel_in
VBATT is decriptor key memory backup supply
Sharc Signals Frontend to Backend
DOUT is BUSY in SelectMAP mode and BUSY should NOT be used for parallel
1
0
6
GND
15
9
Fiducial8002
22n
C8168
NC7SZ08
IC8012
1
2
3
5
4
2n2
C8171
J4B 2
GND
2
U3_4B
U2_4B
1
2
3
5
4
0E0
R8026
NC7SZ00
IC8009
1
2
3
5
4
NC7SZ00
IC8011
C8166
22n
R8027
1K0
Fiducial8001
J4B 12
GND
Sw4B
17
180
R8013
GND
3
2
0
J4B 15
12
J4B
NC7SZ00
IC8010
1
2
3
5
4
SMD_LED_Red
D8002
J4B 16
GND
J4B 5
GND
GND
13
4
3
0
J4B 4
J4B 18
J4B 19
1K0
R8019
3
GND
GND
5
20
R80231K0
U1_4B
J4B
J4B 13
GND
1
2
J4B
R8015
J4B 8
4K7
R8025
180
R8024
D8004
SMD_LED_Green
180
R8025
Sw4B
D8001
SMD_LED_Red
ADD12
4DXN
5DXP
GND
3
SMBCLK8
SMBDATA9
VCC
6
10_ALERT
_STBY7
4K7
6
100n
C8172
GND
IC8013
MAX1618
1ADD0
11R8025
4K7
J4B
R80181K0
J4B 10
J4B
J4B 1
GND
SMD_LED_Green
D8003
Sw4B
J4B 7
R8020
NC7SZ00
IC8008
1
2
3
5
4
U4_4B
14
1K0
7
GND
10
4
R80224K7
6
5
GND
180
R8016 8
1
14
U0_4B
C8170
22n
R8021
180
R8014
J4B
GND
1K0
22n
C8167
7
GND
11GND
3
1K0
R8017
GND
GND
4
Spare(4:0)
J4B 9
22n
C8169
GND
CS_B
VCCAUXPWRDWN_B
CCLKCCLK
HSWAP_EN
PROG_BPROG_B
DXP
DXN
SMBClk
3V3
M2 M1
VCCAUX
M0
Spare(4:0)
Clk
TestCon(15:0)
3V3
3V3
3V3
3V3
T_Alert_n
SMBData
DOUT
INIT_BINIT_B
DONEDONE
D7
D6
D5
D4
D3
D2
D1
D0 D(7:0)
RDWR_B
3V3
ChaBusy ChaBusy
TTC_n(7:0)TTC_n(7:0)
ChaID(2:0)ChaID(2:0)
TCK
TDO
FPGA_TCK
FPGA_TMS
TDI FPGA_TDI
FPGA_TDO
Clk Clk
Clkx2Clkx2
LHC_ClkLHC_Clk
Rocket_XClk Rocket_XClk
Adr(21:0)Adr(21:0)
IRQ1_n IRQ1_n
IRQ2_n IRQ2_n
Empty Empty
DMAR_n DMAR_n
Rocket_RXPRocket_RXP
Rocket_RXN Rocket_RXN
Rocket_TXPRocket_TXP
Rocket_TXNRocket_TXN
A21_SelectA21_Select
TMS
3V3
LEDs(0)
LEDs(1)
LEDs(2)
LEDs(3)
General_Rst_n
Channel_Rst_n
Rst_n
VBATT
IRQ0_n IRQ0_n
Data(31:0) Data(31:0)
MS0_n MS0_n
MS1_nMS1_n
MS2_n MS2_n
MS3_nMS3_n
SharcRd_nSharcRd_n
SharcWr_n SharcWr_n
11
Date
K
3
H
2
12
17 18
16 17
NATIONAAL INSTITUUT VOOR KERN-
18
A
Dim
C
L
J
6
4
4
I
FYSICA EN HOGE ENERGIE-FYSICA
7
C
B
13
F
117 8
H
D
E
1
E
14
G
F
1098 SJ AMSTERDAM NEDERLAND
Proj:
Size
Rev
A
12
Page
14
G
KRUISLAAN 409, 020-592 2000
5
bits (2:1) are effectively the MROD-In number.
Proj.No:
B
J
of
L
c ET-Nikhef Amsterdam
I
Name
6
Channel ID Bit 0 is determines channel A or B
3
D
15
1
NIKHEF
8
15 16
13
Time
5
K
2
9 10
41
420 x 297 mm
4 1 4 AA3
tonvr
1:45:51 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
Input Channels
MROD-In
9 10
TTC_n(7:0)
VT1V8_MGT
IRQ0_n
IRQ1_n
IRQ2_n
LHC_Clk
MS0_n
MS1_n
MS2_n
MS3_n
PROG_B
Rocket_RXN
Rocket_RXP
Rocket_TXN
Rocket_TXP
Rocket_XClk
SharcRd_n
SharcWr_n
Spare(4:0)
Channel_Rst_n
Clk
Clkx2
D(7:0)
DMAR_n
DONE
Data(31:0)
Empty
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
GOL_XClk
General_Rst_n
INIT_B
2
1B
Channel_B
1V5
2V5
3V3
A21_Select
Adr(21:0)
CCLK
ChaBusy
ChaID(2:0)
GND
PROG_B
Rocket_RXN
Rocket_RXP
Rocket_TXN
Rocket_TXP
Rocket_XClk
SharcRd_n
SharcWr_n
Spare(4:0)
TTC_n(7:0)
VT1V8_MGT
Empty
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
GOL_XClk
General_Rst_n
INIT_B
IRQ0_n
IRQ1_n
IRQ2_n
LHC_Clk
MS0_n
MS1_n
MS2_n
MS3_n
1A
Channel_A
1V5
2V5
3V3
A21_Select
Adr(21:0)
CCLK
ChaBusy
ChaID(2:0)
Channel_Rst_n
Clk
Clkx2
D(7:0)
DMAR_n
DONE
Data(31:0)
001 1
SharcRd_n
SharcWr_n
Rocket_XClk_A
DONE
LHC_ClkLHC_Clk
Cha_B_ID(2:0)MROD_In_ID0
MROD_In_ID1
MROD_In_ID0
MROD_In_ID1
VT1V8_MGT VT1V8_MGT
2
1V5
2V5
3V3
FPGA_TCK
FPGA_TMS
TTC_n(7:0)
General_Rst_n
Adr(21:0)
Data(31:0)
MS0_n
MS1_n
MS2_n
MS3_n
SharcRd_n
SharcWr_n
Adr(21:0)
Data(31:0)
IRQ0_n
IRQ1_n
IRQ2_n
MS0_n
MS1_n
MS2_n
MS3_n
ChA_DMAR_n
D(7:0)
ChA_Clkx2
ChA_Clk
ChA_Rst_n
Cha_A_ID(2:0)
ChA_Busy
CCLK
GOL_XClk_B
Rocket_XClk_B
General_Rst_n
LHC_Clk LHC_Clk
1V5
2V5
3V3
INIT_B
D(7:0)
PROG_B
DONE
CCLK
FPGA_TMS
FPGA_TCK
GOL_XClk_A
ChB_Spare(4:0)
Rocket_ChB_TXP
Rocket_ChB_TXN
Rocket_ChB_RXP
Rocket_ChB_RXN
FPGA_TDO
ChB_Empty
ChB_DMAR_n
ChB_Clkx2
ChB_Clk
ChB_Rst_n
ChB_Busy
3V3
TTC_n(7:0)
ChA_Spare(4:0)
Rocket_ChA_TXP
Rocket_ChA_TXN
Rocket_ChA_RXP
Rocket_ChA_RXN
PROG_B
IRQ2_n
IRQ1_n
IRQ0_n
INIT_B
FPGA_TDI
ChA_Empty
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
I
1 2 3 4
Proj:
B
C
DD
E
J
12
K
9
Time
15
Page
17
3
Clock Configuration:
CLK_CFG(3:0) = "0010"
187
NIKHEF
8
EBOOT = ’0’, LBOOT = ’1’, BMS_n = ’1’ (Input)
10 11
=> Core / CLKIN Ration 2:1
Name
Dim
1
8
c
K
SizeNATIONAAL INSTITUUT VOOR KERN-
J
9
A
B
C
18
Booting Mode:
L
VDDINT (1V9) 40 pins
VDDEXT (3V3) 43 pins
GND 82 pins
NC 9 pins
SHARC Power pins:
ET-Nikhef Amsterdam
5 6
of
15 16 174 5
Date
E
F
G
H
I
6
7
Proj.No:
Rev
4 1 4 AA3
tonvr
1:46:33 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
SHARC
MROD-In
16
1098 SJ AMSTERDAM NEDERLAND
L
A
F
G
=> Link Port Booting
ID = "000"
10 11 12 13 14
2
H
13 14
42
420 x 297 mm
T12 VDDINT_T12 T13 VDDINT_T13 T14 VDDINT_T14 T15 VDDINT_T15T6 VDDINT_T6 T7 VDDINT_T7 T8 VDDINT_T8 T9 VDDINT_T9
Y15 WRH_n Y16 WRL_n
VDDINT_L15L6 VDDINT_L6
M15 VDDINT_M15M6 VDDINT_M6
N15 VDDINT_N15N6 VDDINT_N6
VDDINT_P15P15P6 VDDINT_P6
R6 VDDINT_R6
T10 VDDINT_T10 T11 VDDINT_T11
VDDINT_E9
F15 VDDINT_F15F6 VDDINT_F6
G15 VDDINT_G15G6 VDDINT_G6
H15 VDDINT_H15VDDINT_H6H6
J15 VDDINT_J15J6 VDDINT_J6
K15 VDDINT_K15K6 VDDINT_K6
L15
D13 VDDINT_D13D7 VDDINT_D7
E10 VDDINT_E10 E12 VDDINT_E12 E13 VDDINT_E13 E14 VDDINT_E14 E15 VDDINT_E15E6 VDDINT_E6 E7 VDDINT_E7 E8 VDDINT_E8 E9
VDDEXT_U11U11 U12 VDDEXT_U12 U13 VDDEXT_U13 U14 VDDEXT_U14 U15 VDDEXT_U15 U16 VDDEXT_U16U5 VDDEXT_U5 U6 VDDEXT_U6 U7 VDDEXT_U7 U8 VDDEXT_U8 U9 VDDEXT_U9
M5 VDDEXT_M5
VDDEXT_N16N16N5 VDDEXT_N5
P16 VDDEXT_P16P5 VDDEXT_P5
R16 VDDEXT_R16R5 VDDEXT_R5
T16 VDDEXT_T16T5 VDDEXT_T5
U10 VDDEXT_U10
G16 VDDEXT_G16G5 VDDEXT_G5
H16 VDDEXT_H16H5 VDDEXT_H5
J16 VDDEXT_J16VDDEXT_J5J5
K16 VDDEXT_K16K5 VDDEXT_K5
L16 VDDEXT_L16L5 VDDEXT_L5
M16 VDDEXT_M16
VDDEXT_D10 D11 VDDEXT_D11 D12 VDDEXT_D12 D14 VDDEXT_D14D6 VDDEXT_D6 D8 VDDEXT_D8 D9 VDDEXT_D9
E16 VDDEXT_E16E5 VDDEXT_E5
F16 VDDEXT_F16F5 VDDEXT_F5
B8 TCK B18 TCLK0
C14 TCLK1
TDIA7
C9 TDO
D15 TFS0
A16 TFS1A13 TIMEXP
C8 TMS
A8 TRST_n
D10
M19 PA_n
A18 RCLK0
B16 RCLK1
W15 RDH_n
V14 RDL_n
L20 REDY
A9 RESET_n
B17 RFS0
A17 RFS1A10 RPBA
M18 SBTS_n
MS3_n
A14 NC_A14 A15 NC_A15
B13 NC_B13 NC_B14B14
C12 NC_C12 C13 NC_C13
M4 NC_M4
N1 NC_N1 N2 NC_N2
PAGEM17
L5DAT(1)
V17 L5DAT(2)
W19 L5DAT(3)
V19 L5DAT(4)
W20 L5DAT(5)
V20 L5DAT(6)
U17 L5DAT(7)
W17 LBOOT
Y13 MS0_n
V12 MS1_n
W13 MS2_n
Y14
L4DAT(1)U19 U20 L4DAT(2)
T17 L4DAT(3) L4DAT(4)T20
R17 L4DAT(5) R18 L4DAT(6) R19 L4DAT(7)
L5ACKV18
Y20 L5CLK
V16 L5DAT(0)
W18
L3DAT(0)
P18 L3DAT(1)P17 L3DAT(2) P19 L3DAT(3)
N19 L3DAT(4)N17 L3DAT(5) N18 L3DAT(6)
M20 L3DAT(7)
T18 L4ACK T19 L4CLK
U18 L4DAT(0)
L2CLK
J18 L2DAT(0)
H20 L2DAT(1)
J17 L2DAT(2)
H19 L2DAT(3)
G19 L2DAT(4)
H17 L2DAT(5)
G18 L2DAT(6)
F20 L2DAT(7)
P20 L3ACK
N20 L3CLK
R20
D20 L1CLK
F19 L1DAT(0)
E20 L1DAT(1)
G17 L1DAT(2)
F18 L1DAT(3)L1DAT(4)F17
E18 L1DAT(5)E17 L1DAT(6)
D16 L1DAT(7)
H18 L2ACK
G20
L0ACK
D17 L0CLK
C20 L0DAT(0)
D19 L0DAT(1)
B20 L0DAT(2)
D18 L0DAT(3)
A20 L0DAT(4)
B19 L0DAT(5)
C18 L0DAT(6)C17 L0DAT(7)
E19 L1ACK
GND_R7 R8 GND_R8 R9 GND_R9
J19 HBG_n J20 HBR_n
ID0V10
W10 ID1
Y11 ID2
A11 IRQ0_n
C10 IRQ1_n
B10 IRQ2_n
C19
P14 GND_P14GND_P7P7 P8 GND_P8 P9 GND_P9
R10 GND_R10 R11 GND_R11 R12 GND_R12 R13 GND_R13 R14 GND_R14 R15 GND_R15R7
GND_N11 N12 GND_N12 N13 GND_N13 N14 GND_N14N7 GND_N7 GND_N8N8 N9 GND_N9
P10 GND_P10 P11 GND_P11 P12 GND_P12 P13 GND_P13
L9 GND_L9
M10 GND_M10 M11 GND_M11 M12 GND_M12 M13 GND_M13 M14 GND_M14M7 GND_M7 M8 GND_M8 GND_M9M9
N10 GND_N10 N11
K14 GND_K14K7 GND_K7 K8 GND_K8 K9 GND_K9
L10 GND_L10 L11 GND_L11 L12 GND_L12 L13 GND_L13 L14 GND_L14L7 GND_L7 L8 GND_L8
GND_J11 J12 GND_J12 J13 GND_J13 J14 GND_J14J7 GND_J7 J8 GND_J8 J9 GND_J9
K10 GND_K10 K11 GND_K11 GND_K12K12 K13 GND_K13
G9 GND_G9
H10 GND_H10 H11 GND_H11 H12 GND_H12 H13 GND_H13 H14 GND_H14H7 GND_H7 H8 GND_H8 H9 GND_H9
J10 GND_J10 J11
F14 GND_F14F7 GND_F7 F8 GND_F8 GND_F9F9
G10 GND_G10 G11 GND_G11 G12 GND_G12 G13 GND_G13 G14 GND_G14G7 GND_G7 G8 GND_G8
EBOOT
B9 EMU_n B12 FLAG0
A12 FLAG1
C11 FLAG2
B11 FLAG3
E11 GND_E11
F10 GND_F10 F11 GND_F11 F12 GND_F12 F13 GND_F13
DATA(7)
A4 DATA(8)
B4 DATA(9)
Y17 DMAG1_n
W16 DMAG2_n
Y18 DMAR1_n
V15 DMAR2_n
C16 DR0C15 DR1
A19 DT0
B15 DT1
Y19
P4 DATA(55)
T1 DATA(56)
R3 DATA(57)
T2 DATA(58) T3 DATA(59)
B5 DATA(6)
R4 DATA(60)
U1 DATA(61) U2 DATA(62)
DATA(63)T4
C5
DATA(45)K2 DATA(46) DATA(47)K4
N3 DATA(48)
P1 DATA(49)
C6 DATA(5)
P2 DATA(50)
N4 DATA(51)
P3 DATA(52)
R1 DATA(53) R2 DATA(54)
DATA(35)
H4 DATA(36)H3 DATA(37)
G1 DATA(38)
H2 DATA(39)
A5 DATA(4)
H1 DATA(40)
J4 DATA(41)J3 DATA(42)J2 DATA(43)J1 DATA(44)
K3
F4 DATA(26)F3 DATA(27)
D1 DATA(28)
DATA(29)E2
DATA(3)B6
E1 DATA(30)
G4 DATA(31)G3 DATA(32)
F2 DATA(33)DATA(34)F1
G2
DATA(16)
C3 DATA(17)C2 DATA(18)
D4 DATA(19)
A6 DATA(2)
DATA(20)D3
E4 DATA(21)
B1 DATA(22)
E3 DATA(23)
C1 DATA(24)
D2 DATA(25)
CLK_CFG_2
M2 CLK_CFG_3
V13 CS_n
B7 DATA(0)
C7 DATA(1)
A3 DATA(10)
C4 DATA(11)
D5 DATA(12)
A2 DATA(13)A1 DATA(14)
B3 DATA(15)B2
BR3_nK20K19 BR4_nK18 BR5_nK17 BR6_n
BRSTY12
W14 CIF_n
L1 CLKIN
M3 CLKOUT
K1 CLK_CFG_0
L2 CLK_CFG_1 L4
ADDR(4)
W1 ADDR(5)
ADDR(6)V2 V3 ADDR(7)
Y1 ADDR(8)
W2 ADDR(9)
L3 AGND
M1 AVDD
W12 BMS_n
L18 BR1_nL17 BR2_n
W7 ADDR(23)
ADDR(24)Y7
V8 ADDR(25)
W8 ADDR(26)
Y8 ADDR(27)
V9 ADDR(28)
W9 ADDR(29)
U3 ADDR(3)
Y9 ADDR(30) Y10 ADDR(31)
V1
Y3 ADDR(13)
V5 ADDR(14)
W4 ADDR(15)
Y4 ADDR(16)
W5 ADDR(17)
V6 ADDR(18)
Y5 ADDR(19)
U4 ADDR(2)
W6 ADDR(20)
Y6 ADDR(21)
V7 ADDR(22)
IC101
ADSP21160N
L19 ACK
W11 ADDR(0)
V11 ADDR(1)V4 ADDR(10)
Y2 ADDR(11)
W3 ADDR(12)
VDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINT
VDDINT VDDINT VDDINT VDDINT VDDINT VDDINTVDDINT VDDINT VDDINT VDDINT
SharcWr_n
VDDEXT VDDEXT VDDEXT VDDEXT VDDEXTVDDEXT VDDEXT VDDEXT VDDEXT VDDEXT
VDDINTVDDINT
VDDINT VDDINT VDDINT VDDINT VDDINTVDDINT VDDINT VDDINT VDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINT
VDDEXT VDDEXT VDDEXTVDDEXT VDDEXT VDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXT VDDEXT
L5DATi(4)
L5DATi(5)
L5DATi(6)
L5DATi(7)
VDDEXT
MS0_n
MS1_n
MS2_n
MS3_n
SharcRd_n
Rst_n
RFS0
RFS1GND
VDDEXT
TCK
TDI
TDO
TFS0
TFS1
TMS
TRST_n
VDDEXT
L3DATi(2) L3DATi(3)
L3DATi(4)L3DATi(5) L3DATi(6)
L3DATi(7)
L4ACKi L4CLKi
L4DATi(0) L4DATi(1) L4DATi(2)
L4DATi(3) L4DATi(4)
L4DATi(5) L4DATi(6) L4DATi(7)
L5ACKi
L5CLKi
L5DATi(0)
L5DATi(1)
L5DATi(2)
L5DATi(3)
L1DATi(1)
L1DATi(2)
L1DATi(3)L1DATi(4)
L1DATi(5)L1DATi(6)
L1DATi(7)
L2ACKi
L2CLKi
L2DATi(0)
L2DATi(1)
L2DATi(2)
L2DATi(3)
L2DATi(4)
L2DATi(5)
L2DATi(6)
L2DATi(7)
L3ACKi
L3CLKi
L3DATi(0)
L3DATi(1)
VDDEXT
GND
GND
GND
IRQ0_n
IRQ1_n
IRQ2_n
L0ACKi
L0CLKi
L0DATi(0)
L0DATi(1)
L0DATi(2)
L0DATi(3)
L0DATi(4)
L0DATi(5)
L0DATi(6)L0DATi(7)
L1ACKi
L1CLKi
L1DATi(0)
GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GND GNDGND GND GND
HBG_n
GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND
ChB_DMAR_n
GND
Sharc_EMU_n ChA_Rst_n
ChB_Rst_n
ChA_Empty
ChB_Empty
GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND
Data(17) Data(18)
Data(19)
Data(20)
Data(21) Data(22)
Data(23)
Data(24)
Data(25)
Data(26) Data(27)
Data(28)
Data(29) Data(30)
Data(31)
ChA_DMAR_n
Data(1)Data(2)
Data(3)
Data(4)Data(5)
Data(6)
Data(7)Data(8)
Data(9)Data(10)Data(11)Data(12)
Data(13)Data(14) Data(15)
Data(16)
Adr(4)
Adr(5)
Adr(6) Adr(7)
Adr(8)
Adr(9)
GND
AVDD
BMS_n
BReq_nBReq_n
BReq_nBReq_nBReq_nBReq_n
BRST
Sharc_Clk
GND
VDDEXT GND
GND
VDDEXT
Data(0)
Adr(0)
Adr(1)Adr(10)
Adr(11)
Adr(12)
Adr(13)
Adr(14)
Adr(15)
Adr(16)
Adr(17)
Adr(18)
Adr(19)
Adr(2)
Adr(20)
Adr(21)
Adr(3)
5 6
J
IRQ signal
Pull-ups in one
0
NIKHEF
C
1716
C
Rev
16
G
2 3 4 8 9
Proj.No:
14
L
Name
6
12 13 14 15
Date
a General_Rst_n, or when a reset is
Optional Test
Connector
Data Link to MROD-Out Sharc-B
Communication Link
12 13
The Sharc is reset when there is
Pull-ups in one
arc242 package
B
1
D
1
Communication Link
Communication Link
Communication Link
Sharc JTAG (and Emulator) Signals
2
asked via the MROD-Out FPGA
17 18
Size
Dim
11
G
H
I
J
GND
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
8 9 10
A
Page1098 SJ AMSTERDAM NEDERLAND
Proj:
4 5
Data Link to MROD-Out Sharc-A
F
Time
L
15
B
K
arc242 package
[email protected] Jansweijer
38405MROD-X
SHARC Auxiliary and Decoupling
MROD-In
of
7
Reset Signals
Also Boot Link
E
11
15
CLK
ADSP21160 VDDINT (40 pins) Decoupling Capacitors
ADSP21160 VDDEXT (43 pins) Decoupling Capacitors
SHARC Link Serie Termination
A
18
F
10
K
3
D
ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
I
TFS and RFS signal
7
E
c
H
2
3
43
420 x 297 mm
4 1 4 AA3
tonvr
1:46:57 pm
7 Feb 2006
V2 2
0
1
100n
0
GND
C118
22n
GND
7
GND
22n
C150
GND
C161
5
7
GND
1
GND
GND
C115
22n
22n
C104
0
GND
GND
R11233
33R101
33R102
R116
R1164K7
5
6
C155
22n
7
R1164K7
4K7
3
R10933
5
GND
GND
3
6
5
GND
0
R108
100n
C125
GND
GND
C152
22n
100n
C128
33
6
5
1
2
3
4
GND
0
1
2
2C108
680p
R10133
IC102
NC7SZ08
1
2
3
5
4
GND
33R103
22n
C117
4K7R117
680p
C113
22n
C148
GND
GND
C121
22n
4
5
GND
33
R11233
GND
R10433
33R108
R105
3
4
33R103
R10333
10
R122
C135
680p
6
4
GND
6
2
680p
C136
GND
GND
22n
C153
GND
680p
C134
GND
C133
680p
4
7
33R114
1
2
R10633
33R105
33
33R107
1
7
C137
680p
4K7R121
R105
R1174K7
GND
GND
C130
100n
C159
100n
GND
7
C163
47u
GND
C102
22n
R10933
GND
680p
C138
R11133
33R110
R10833
GND
R10633
33R106
R1184K7
4K7R119
GND
GND
100n
C162
4K7R116
R104
680p
C109
4
GND GND
C110
680p
33
R11533
GND
GND
C154
22n
R11433
GND GND
5
GND
R11033
33R111
R10333
733
R109
4K7R117
100n
C160
6
C145
22n
GND
GND
GND
C114
680p
33R111
4
680p
C107
33R110
R11133
1
R11033
C112
680p
GND
680p
C111
4
3
7
6
5
GND
GND
22n
C156
0
2
33R107 GND
33R107
4
33R114
6
680p
C142
R115
R11533
GND GND
5
6
6
6
0
33
R1204K7
47u
C164
1
GND
C157
100n
100n
C129
GND
3
2
33R102
0
22n
C122
R10133
22n
C120
R10633
33R102
4
33R113
C139
680p
2
2
R10233
R11333
C132
47u
GND
GND
R11233
33R112
0
R10133
33R113
22n
C116
680p
C105
GND
C106
680p
3
3
2
1
GND
GND
7
3
R10733
2
33R114
6
5
33R113
GND
7
1
0
C103
680p
C126
100n
GND
C101
100n
33R109
22n
C146 C147
22n
7
J11 20
100n
C158
33R104
3
J11 16
5
J11 18
J11 10
J11 12
J11 14
6
J11 7
J11 8
680p
C144
J11 3
J11 4
J11 5
J11
GND
J11 1
GND
J11 2
47u
C131
C141
680p
Fiducial101
4
5
680p
C140
7
1
GND
GNDGND
R10833
GND
1
C127
100n1
3
3
4
22n
C151
3
GND
22n
C123
GND
C124
22n
C119
22n
2
1
0
R10433
33R105
GND
J11 19
C149
22n
0
Fiducial102
2
J11 15
0
J11 17
J11 114
J11 13
Sharc_Rst_n
Rst_n
3V3
General_Rst_n
General_Rst_n
R11533
J11 9
C143
680p
L2DAT(7:0)
L1DAT(7:0)
L0DAT(7:0)
Sharc_Clk
SharcRd_n
SharcWr_n
MS3_n
MS2_n
MS1_n
MS0_n
Adr(21:0)
Data(31:0)
ChA_DMAR_n
ChA_Empty
L2ACKi
L2CLKi
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L2ACK50_OHM_SHARC_LINK
L2CLK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L1ACK
50_OHM_SHARC_LINK
L1CLK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L0ACK
50_OHM_SHARC_LINK
L0CLK
Sharc_EMU_n
TCK
TDO
TDI
TMS
Sharc_TDI
Sharc_TCK
Sharc_TMS
Sharc_TDO
TRST_n
L1DATi(7:0)
L1ACKi
L1CLKi
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L2DATi(7:0)
VDDINT
VDDEXT
VDDINT
AVDD
Sharc_EMU_n
50_OHM_SHARC_LINK
L5ACK50_OHM_SHARC_LINK
L5ACKi
L5CLK50_OHM_SHARC_LINK
L5CLKi
L5DAT(7:0)
TFS0
RFS0
TFS1
RFS1
BReq_n
BMS_n
HBG_n
BRST
IRQ0_n
IRQ1_n
IRQ2_n
Sharc_TRST_n
3V3
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L4ACKL4ACKi
50_OHM_SHARC_LINK
L4CLKL4CLKi
L4DAT(7:0)
L5DATi(7:0)50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L0DATi(7:0)
L0ACKi
L0CLKi
L3DATi(7:0)
L3ACKi L3ACK50_OHM_SHARC_LINK
L3CLKi L3CLK50_OHM_SHARC_LINK
L3DAT(7:0)
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L4DATi(7:0)
to be connected to golbal GROUND.
15 16
ET-Nikhef Amsterdam
7
4
3 15 16
GOL Frequency
5
J
Proj:
9
VCCINT Ramp rate 200 us min. and 50 ms max.
Input Channel, 250 mA per Channel
100MHz
1 2
D
12
B
Time between power-on VDDINT -> VDDEXT
FYSICA EN HOGE ENERGIE-FYSICA
100MHz
Fnom = 100 MHz
G
50MHz
7
Serie termination close to XTAL
Rocket-IO Inter-FPGA Link Frequency
100 MHz 16 bit = 50 MHz 32 bit
Date
Time
B
KRUISLAAN 409, 020-592 2000
All GND nets on the SHARC need
11
41
18
C
Parallel termination at the end of the line
= 200 MB/s
Serie termination close to XTAL
A
17
= 160 MB/s
E
50MHz
8
J
C
K
NIKHEFNATIONAAL INSTITUUT VOOR KERN-
K
= VCCAUX for the Xilinx Virtex-II Pro in the
FF
Page
Dim
17
10
85
I
= VDDEXT for the ADSP21160N
3
960 mA peak per ADSP21160N
G
H
I
of
The System Clock can be locked to a crystal or
= VCCINT for Xilinx Virtex-II Pro in the
100 MHz Phase Adjust
SHARC and Input Channel System Clock
10
2F(1:0)= "mm" => 0 tu
L
6
Rev
100 mA per ADSP21160N
6 9
12
11
A
Input Channels, 600 mA per Channel
c
Note ADSP21160N Power-On Sequence!
or to the LHC_Clk depending on the resistors placed.
80 MHz 16 bit = 40 MHz 32 bit
1F(1:0)= "mm" => 0 tu
Name
4F(1:0)= "00" => 100 Divide by 2 = 50 MHz
18
14
Proj.No:
14
44
420 x 297 mm
4 1 4 AA3
tonvr
1:47:20 pm
7 Feb 2006
V2 20
[email protected] Jansweijer
38405MROD-X
Power and Clocks
MROD-In
D
13
= VDDINT for the ADSP21160N
E
2
= -50 ms to +200 ms
H
LSize
1098 SJ AMSTERDAM NEDERLAND
13
3F(1:0)= "00" => 100 Divide by 2 = 50 MHz
GND
GND
J2F1_1
1
2
3
GND
GND
82
R131
GND
R134
130
GND
130
R136
IC103
S1703B_80
80MHz
1Ctrl
2
GND
OUT3
4
Vcc
GND
C167
100n
GND
22n
C165
33
GND
22n
C170
GND
R128
0E0
R125
82
R137
22n
C168
82
R135
GND
GND
R129
1M
GND
OUT3
4
Vcc
J2F0_1
1
2
3
22n
C172
R140
130
IC105
S1703B_50
50MHz
1Ctrl
2
16 18 252 8
GND
C171
22n
15
3Q114
4F06
74F1
4Q011
4Q110
FB17
FS3
1REF
TEST31
9
1F026
271F1
1Q024
1Q123
292F0
2F130
2Q020
2Q119
43F0
3F15
3Q0
GND
4K7
R127
CY7B9911V
IC106
Vccq Vccn
GND
MBRD835L
D101C173
22n
GND
130
R138
GND
GND
82
GND
C169
22n
130
R132
5V_to_1V5_?
1V55V
GND
R13982
R133
100MHz
S1703B_100
IC104
Ctrl1
GND
2
3OUT
Vcc
4
C176
100n
GND
C166
22n
1K0
R130
22n
C174
100n
C175
R124
33
33
R123GND
GND
Z50_NET_TYPE
Z50_NET_TYPE
Rocket_XClk_B
GND
33
R126
3V3
Z50_NET_TYPE
Sharc_Clk
VDDEXTPOWER_NET_TYPE
VDDINTPOWER_NET_TYPE
LHC_Clk
5V
2V5POWER_NET_TYPE
2V5
1V5POWER_NET_TYPE
GNDPOWER_NET_TYPE
Z50_NET_TYPE
GOL_XClk_B
GOL_XClk_AZ50_NET_TYPE
Rocket_XClk_A
3V3
Z50_NET_TYPE
ChA_Clkx2
Z50_NET_TYPE
ChB_Clkx2
Z50_NET_TYPE
ChA_Clk
Z50_NET_TYPE
ChB_Clk
1V9
3V3POWER_NET_TYPE
3V3
15 16 17
c ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
6
A
7 8
Dim
Page
2 3
of
15
A
B
C
G
H
I
G
B
C
10 11 12
D
13 144 52 3 9 10 11
Output Adjustable (1V5)
12
J
Low ESR
L
1
K
L
Rev
Size
Ceramic X7R
Ceramic X7R
=> Ramp rate = 6,6 ms
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Low ESR
Proj: Proj.No:
Reference C
Ceramic X7R
Input C
18
1V5 @ 2Amp
1 9 13 16 17 184 5
tonvr
1:38:24 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
5V -> 1V5 @ 2A
Power Supply
AVX
TPSD157K010R0100
Date
Time
Name
Css = 22 nF
H
I
E
F
14
K
D
E
F
J
6 7 8
NIKHEF
FBSEL = REF
270K
11
420 x 297 mm
4 1 4 AA3
22n
C181
R142
0E0
R143
R144
17K8
2%
2%48K7 R145
C179
2u2
C177150u
GND
10u
C178
R141
10
GND
GND
GND
C182
1u
GND GND
TOFF
7
12VCC
_SHDN1
GND
GND
470pC180
FBSEL
9
GND
IN1
2 4
IN216
LX1
LX214
3LX3
15PGND1
PGND213
REF
10
SS5
L101
6u8
IC107
MAX16446COMP
FB8
11
5V
1V5
GND
C183100u
11
Date
K
3
H
2
12
17 18
16 17
NATIONAAL INSTITUUT VOOR KERN-
18
A
Dim
C
L
J
6
4
4
I
FYSICA EN HOGE ENERGIE-FYSICA
7
C
B
13
F
117 8
H
D
E
1
E
14
G
F
1098 SJ AMSTERDAM NEDERLAND
Proj:
Size
Rev
A
12
Page
14
G
KRUISLAAN 409, 020-592 2000
5
bits (2:1) are effectively the MROD-In number.
Proj.No:
B
J
of
L
c ET-Nikhef Amsterdam
I
Name
6
Channel ID Bit 0 is determines channel A or B
3
D
15
1
NIKHEF
8
15 16
13
Time
5
K
2
9 10
41
420 x 297 mm
4 1 4 AA3
tonvr
1:45:51 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
Input Channels
MROD-In
9 10
TTC_n(7:0)
VT1V8_MGT
IRQ0_n
IRQ1_n
IRQ2_n
LHC_Clk
MS0_n
MS1_n
MS2_n
MS3_n
PROG_B
Rocket_RXN
Rocket_RXP
Rocket_TXN
Rocket_TXP
Rocket_XClk
SharcRd_n
SharcWr_n
Spare(4:0)
Channel_Rst_n
Clk
Clkx2
D(7:0)
DMAR_n
DONE
Data(31:0)
Empty
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
GOL_XClk
General_Rst_n
INIT_B
2
2B
Channel_B
1V5
2V5
3V3
A21_Select
Adr(21:0)
CCLK
ChaBusy
ChaID(2:0)
GND
PROG_B
Rocket_RXN
Rocket_RXP
Rocket_TXN
Rocket_TXP
Rocket_XClk
SharcRd_n
SharcWr_n
Spare(4:0)
TTC_n(7:0)
VT1V8_MGT
Empty
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
GOL_XClk
General_Rst_n
INIT_B
IRQ0_n
IRQ1_n
IRQ2_n
LHC_Clk
MS0_n
MS1_n
MS2_n
MS3_n
2A
Channel_A
1V5
2V5
3V3
A21_Select
Adr(21:0)
CCLK
ChaBusy
ChaID(2:0)
Channel_Rst_n
Clk
Clkx2
D(7:0)
DMAR_n
DONE
Data(31:0)
001 1
SharcRd_n
SharcWr_n
Rocket_XClk_A
DONE
LHC_ClkLHC_Clk
Cha_B_ID(2:0)MROD_In_ID0
MROD_In_ID1
MROD_In_ID0
MROD_In_ID1
VT1V8_MGT VT1V8_MGT
2
1V5
2V5
3V3
FPGA_TCK
FPGA_TMS
TTC_n(7:0)
General_Rst_n
Adr(21:0)
Data(31:0)
MS0_n
MS1_n
MS2_n
MS3_n
SharcRd_n
SharcWr_n
Adr(21:0)
Data(31:0)
IRQ0_n
IRQ1_n
IRQ2_n
MS0_n
MS1_n
MS2_n
MS3_n
ChA_DMAR_n
D(7:0)
ChA_Clkx2
ChA_Clk
ChA_Rst_n
Cha_A_ID(2:0)
ChA_Busy
CCLK
GOL_XClk_B
Rocket_XClk_B
General_Rst_n
LHC_Clk LHC_Clk
1V5
2V5
3V3
INIT_B
D(7:0)
PROG_B
DONE
CCLK
FPGA_TMS
FPGA_TCK
GOL_XClk_A
ChB_Spare(4:0)
Rocket_ChB_TXP
Rocket_ChB_TXN
Rocket_ChB_RXP
Rocket_ChB_RXN
FPGA_TDO
ChB_Empty
ChB_DMAR_n
ChB_Clkx2
ChB_Clk
ChB_Rst_n
ChB_Busy
3V3
TTC_n(7:0)
ChA_Spare(4:0)
Rocket_ChA_TXP
Rocket_ChA_TXN
Rocket_ChA_RXP
Rocket_ChA_RXN
PROG_B
IRQ2_n
IRQ1_n
IRQ0_n
INIT_B
FPGA_TDI
ChA_Empty
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
I
1 2 3 4
Proj:
B
C
DD
E
J
12
K
9
Time
15
Page
17
3
Clock Configuration:
CLK_CFG(3:0) = "0010"
187
NIKHEF
8
EBOOT = ’0’, LBOOT = ’1’, BMS_n = ’1’ (Input)
10 11
=> Core / CLKIN Ration 2:1
Name
Dim
1
8
c
K
SizeNATIONAAL INSTITUUT VOOR KERN-
J
9
A
B
C
18
Booting Mode:
L
VDDINT (1V9) 40 pins
VDDEXT (3V3) 43 pins
GND 82 pins
NC 9 pins
SHARC Power pins:
ET-Nikhef Amsterdam
5 6
of
15 16 174 5
Date
E
F
G
H
I
6
7
Proj.No:
Rev
4 1 4 AA3
tonvr
1:46:33 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
SHARC
MROD-In
16
1098 SJ AMSTERDAM NEDERLAND
L
A
F
G
=> Link Port Booting
ID = "000"
10 11 12 13 14
2
H
13 14
42
420 x 297 mm
T12 VDDINT_T12 T13 VDDINT_T13 T14 VDDINT_T14 T15 VDDINT_T15T6 VDDINT_T6 T7 VDDINT_T7 T8 VDDINT_T8 T9 VDDINT_T9
Y15 WRH_n Y16 WRL_n
VDDINT_L15L6 VDDINT_L6
M15 VDDINT_M15M6 VDDINT_M6
N15 VDDINT_N15N6 VDDINT_N6
VDDINT_P15P15P6 VDDINT_P6
R6 VDDINT_R6
T10 VDDINT_T10 T11 VDDINT_T11
VDDINT_E9
F15 VDDINT_F15F6 VDDINT_F6
G15 VDDINT_G15G6 VDDINT_G6
H15 VDDINT_H15VDDINT_H6H6
J15 VDDINT_J15J6 VDDINT_J6
K15 VDDINT_K15K6 VDDINT_K6
L15
D13 VDDINT_D13D7 VDDINT_D7
E10 VDDINT_E10 E12 VDDINT_E12 E13 VDDINT_E13 E14 VDDINT_E14 E15 VDDINT_E15E6 VDDINT_E6 E7 VDDINT_E7 E8 VDDINT_E8 E9
VDDEXT_U11U11 U12 VDDEXT_U12 U13 VDDEXT_U13 U14 VDDEXT_U14 U15 VDDEXT_U15 U16 VDDEXT_U16U5 VDDEXT_U5 U6 VDDEXT_U6 U7 VDDEXT_U7 U8 VDDEXT_U8 U9 VDDEXT_U9
M5 VDDEXT_M5
VDDEXT_N16N16N5 VDDEXT_N5
P16 VDDEXT_P16P5 VDDEXT_P5
R16 VDDEXT_R16R5 VDDEXT_R5
T16 VDDEXT_T16T5 VDDEXT_T5
U10 VDDEXT_U10
G16 VDDEXT_G16G5 VDDEXT_G5
H16 VDDEXT_H16H5 VDDEXT_H5
J16 VDDEXT_J16VDDEXT_J5J5
K16 VDDEXT_K16K5 VDDEXT_K5
L16 VDDEXT_L16L5 VDDEXT_L5
M16 VDDEXT_M16
VDDEXT_D10 D11 VDDEXT_D11 D12 VDDEXT_D12 D14 VDDEXT_D14D6 VDDEXT_D6 D8 VDDEXT_D8 D9 VDDEXT_D9
E16 VDDEXT_E16E5 VDDEXT_E5
F16 VDDEXT_F16F5 VDDEXT_F5
B8 TCK B18 TCLK0
C14 TCLK1
TDIA7
C9 TDO
D15 TFS0
A16 TFS1A13 TIMEXP
C8 TMS
A8 TRST_n
D10
M19 PA_n
A18 RCLK0
B16 RCLK1
W15 RDH_n
V14 RDL_n
L20 REDY
A9 RESET_n
B17 RFS0
A17 RFS1A10 RPBA
M18 SBTS_n
MS3_n
A14 NC_A14 A15 NC_A15
B13 NC_B13 NC_B14B14
C12 NC_C12 C13 NC_C13
M4 NC_M4
N1 NC_N1 N2 NC_N2
PAGEM17
L5DAT(1)
V17 L5DAT(2)
W19 L5DAT(3)
V19 L5DAT(4)
W20 L5DAT(5)
V20 L5DAT(6)
U17 L5DAT(7)
W17 LBOOT
Y13 MS0_n
V12 MS1_n
W13 MS2_n
Y14
L4DAT(1)U19 U20 L4DAT(2)
T17 L4DAT(3) L4DAT(4)T20
R17 L4DAT(5) R18 L4DAT(6) R19 L4DAT(7)
L5ACKV18
Y20 L5CLK
V16 L5DAT(0)
W18
L3DAT(0)
P18 L3DAT(1)P17 L3DAT(2) P19 L3DAT(3)
N19 L3DAT(4)N17 L3DAT(5) N18 L3DAT(6)
M20 L3DAT(7)
T18 L4ACK T19 L4CLK
U18 L4DAT(0)
L2CLK
J18 L2DAT(0)
H20 L2DAT(1)
J17 L2DAT(2)
H19 L2DAT(3)
G19 L2DAT(4)
H17 L2DAT(5)
G18 L2DAT(6)
F20 L2DAT(7)
P20 L3ACK
N20 L3CLK
R20
D20 L1CLK
F19 L1DAT(0)
E20 L1DAT(1)
G17 L1DAT(2)
F18 L1DAT(3)L1DAT(4)F17
E18 L1DAT(5)E17 L1DAT(6)
D16 L1DAT(7)
H18 L2ACK
G20
L0ACK
D17 L0CLK
C20 L0DAT(0)
D19 L0DAT(1)
B20 L0DAT(2)
D18 L0DAT(3)
A20 L0DAT(4)
B19 L0DAT(5)
C18 L0DAT(6)C17 L0DAT(7)
E19 L1ACK
GND_R7 R8 GND_R8 R9 GND_R9
J19 HBG_n J20 HBR_n
ID0V10
W10 ID1
Y11 ID2
A11 IRQ0_n
C10 IRQ1_n
B10 IRQ2_n
C19
P14 GND_P14GND_P7P7 P8 GND_P8 P9 GND_P9
R10 GND_R10 R11 GND_R11 R12 GND_R12 R13 GND_R13 R14 GND_R14 R15 GND_R15R7
GND_N11 N12 GND_N12 N13 GND_N13 N14 GND_N14N7 GND_N7 GND_N8N8 N9 GND_N9
P10 GND_P10 P11 GND_P11 P12 GND_P12 P13 GND_P13
L9 GND_L9
M10 GND_M10 M11 GND_M11 M12 GND_M12 M13 GND_M13 M14 GND_M14M7 GND_M7 M8 GND_M8 GND_M9M9
N10 GND_N10 N11
K14 GND_K14K7 GND_K7 K8 GND_K8 K9 GND_K9
L10 GND_L10 L11 GND_L11 L12 GND_L12 L13 GND_L13 L14 GND_L14L7 GND_L7 L8 GND_L8
GND_J11 J12 GND_J12 J13 GND_J13 J14 GND_J14J7 GND_J7 J8 GND_J8 J9 GND_J9
K10 GND_K10 K11 GND_K11 GND_K12K12 K13 GND_K13
G9 GND_G9
H10 GND_H10 H11 GND_H11 H12 GND_H12 H13 GND_H13 H14 GND_H14H7 GND_H7 H8 GND_H8 H9 GND_H9
J10 GND_J10 J11
F14 GND_F14F7 GND_F7 F8 GND_F8 GND_F9F9
G10 GND_G10 G11 GND_G11 G12 GND_G12 G13 GND_G13 G14 GND_G14G7 GND_G7 G8 GND_G8
EBOOT
B9 EMU_n B12 FLAG0
A12 FLAG1
C11 FLAG2
B11 FLAG3
E11 GND_E11
F10 GND_F10 F11 GND_F11 F12 GND_F12 F13 GND_F13
DATA(7)
A4 DATA(8)
B4 DATA(9)
Y17 DMAG1_n
W16 DMAG2_n
Y18 DMAR1_n
V15 DMAR2_n
C16 DR0C15 DR1
A19 DT0
B15 DT1
Y19
P4 DATA(55)
T1 DATA(56)
R3 DATA(57)
T2 DATA(58) T3 DATA(59)
B5 DATA(6)
R4 DATA(60)
U1 DATA(61) U2 DATA(62)
DATA(63)T4
C5
DATA(45)K2 DATA(46) DATA(47)K4
N3 DATA(48)
P1 DATA(49)
C6 DATA(5)
P2 DATA(50)
N4 DATA(51)
P3 DATA(52)
R1 DATA(53) R2 DATA(54)
DATA(35)
H4 DATA(36)H3 DATA(37)
G1 DATA(38)
H2 DATA(39)
A5 DATA(4)
H1 DATA(40)
J4 DATA(41)J3 DATA(42)J2 DATA(43)J1 DATA(44)
K3
F4 DATA(26)F3 DATA(27)
D1 DATA(28)
DATA(29)E2
DATA(3)B6
E1 DATA(30)
G4 DATA(31)G3 DATA(32)
F2 DATA(33)DATA(34)F1
G2
DATA(16)
C3 DATA(17)C2 DATA(18)
D4 DATA(19)
A6 DATA(2)
DATA(20)D3
E4 DATA(21)
B1 DATA(22)
E3 DATA(23)
C1 DATA(24)
D2 DATA(25)
CLK_CFG_2
M2 CLK_CFG_3
V13 CS_n
B7 DATA(0)
C7 DATA(1)
A3 DATA(10)
C4 DATA(11)
D5 DATA(12)
A2 DATA(13)A1 DATA(14)
B3 DATA(15)B2
BR3_nK20K19 BR4_nK18 BR5_nK17 BR6_n
BRSTY12
W14 CIF_n
L1 CLKIN
M3 CLKOUT
K1 CLK_CFG_0
L2 CLK_CFG_1 L4
ADDR(4)
W1 ADDR(5)
ADDR(6)V2 V3 ADDR(7)
Y1 ADDR(8)
W2 ADDR(9)
L3 AGND
M1 AVDD
W12 BMS_n
L18 BR1_nL17 BR2_n
W7 ADDR(23)
ADDR(24)Y7
V8 ADDR(25)
W8 ADDR(26)
Y8 ADDR(27)
V9 ADDR(28)
W9 ADDR(29)
U3 ADDR(3)
Y9 ADDR(30) Y10 ADDR(31)
V1
Y3 ADDR(13)
V5 ADDR(14)
W4 ADDR(15)
Y4 ADDR(16)
W5 ADDR(17)
V6 ADDR(18)
Y5 ADDR(19)
U4 ADDR(2)
W6 ADDR(20)
Y6 ADDR(21)
V7 ADDR(22)
IC201
ADSP21160N
L19 ACK
W11 ADDR(0)
V11 ADDR(1)V4 ADDR(10)
Y2 ADDR(11)
W3 ADDR(12)
VDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINT
VDDINT VDDINT VDDINT VDDINT VDDINT VDDINTVDDINT VDDINT VDDINT VDDINT
SharcWr_n
VDDEXT VDDEXT VDDEXT VDDEXT VDDEXTVDDEXT VDDEXT VDDEXT VDDEXT VDDEXT
VDDINTVDDINT
VDDINT VDDINT VDDINT VDDINT VDDINTVDDINT VDDINT VDDINT VDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINT
VDDEXT VDDEXT VDDEXTVDDEXT VDDEXT VDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXT VDDEXT
L5DATi(4)
L5DATi(5)
L5DATi(6)
L5DATi(7)
VDDEXT
MS0_n
MS1_n
MS2_n
MS3_n
SharcRd_n
Rst_n
RFS0
RFS1GND
VDDEXT
TCK
TDI
TDO
TFS0
TFS1
TMS
TRST_n
VDDEXT
L3DATi(2) L3DATi(3)
L3DATi(4)L3DATi(5) L3DATi(6)
L3DATi(7)
L4ACKi L4CLKi
L4DATi(0) L4DATi(1) L4DATi(2)
L4DATi(3) L4DATi(4)
L4DATi(5) L4DATi(6) L4DATi(7)
L5ACKi
L5CLKi
L5DATi(0)
L5DATi(1)
L5DATi(2)
L5DATi(3)
L1DATi(1)
L1DATi(2)
L1DATi(3)L1DATi(4)
L1DATi(5)L1DATi(6)
L1DATi(7)
L2ACKi
L2CLKi
L2DATi(0)
L2DATi(1)
L2DATi(2)
L2DATi(3)
L2DATi(4)
L2DATi(5)
L2DATi(6)
L2DATi(7)
L3ACKi
L3CLKi
L3DATi(0)
L3DATi(1)
VDDEXT
GND
GND
GND
IRQ0_n
IRQ1_n
IRQ2_n
L0ACKi
L0CLKi
L0DATi(0)
L0DATi(1)
L0DATi(2)
L0DATi(3)
L0DATi(4)
L0DATi(5)
L0DATi(6)L0DATi(7)
L1ACKi
L1CLKi
L1DATi(0)
GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GND GNDGND GND GND
HBG_n
GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND
ChB_DMAR_n
GND
Sharc_EMU_n ChA_Rst_n
ChB_Rst_n
ChA_Empty
ChB_Empty
GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND
Data(17) Data(18)
Data(19)
Data(20)
Data(21) Data(22)
Data(23)
Data(24)
Data(25)
Data(26) Data(27)
Data(28)
Data(29) Data(30)
Data(31)
ChA_DMAR_n
Data(1)Data(2)
Data(3)
Data(4)Data(5)
Data(6)
Data(7)Data(8)
Data(9)Data(10)Data(11)Data(12)
Data(13)Data(14) Data(15)
Data(16)
Adr(4)
Adr(5)
Adr(6) Adr(7)
Adr(8)
Adr(9)
GND
AVDD
BMS_n
BReq_nBReq_n
BReq_nBReq_nBReq_nBReq_n
BRST
Sharc_Clk
GND
VDDEXT GND
GND
VDDEXT
Data(0)
Adr(0)
Adr(1)Adr(10)
Adr(11)
Adr(12)
Adr(13)
Adr(14)
Adr(15)
Adr(16)
Adr(17)
Adr(18)
Adr(19)
Adr(2)
Adr(20)
Adr(21)
Adr(3)
5 6
J
IRQ signal
Pull-ups in one
0
NIKHEF
C
1716
C
Rev
16
G
2 3 4 8 9
Proj.No:
14
L
Name
6
12 13 14 15
Date
a General_Rst_n, or when a reset is
Optional Test
Connector
Data Link to MROD-Out Sharc-B
Communication Link
12 13
The Sharc is reset when there is
Pull-ups in one
arc242 package
B
1
D
1
Communication Link
Communication Link
Communication Link
Sharc JTAG (and Emulator) Signals
2
asked via the MROD-Out FPGA
17 18
Size
Dim
11
G
H
I
J
GND
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
8 9 10
A
Page1098 SJ AMSTERDAM NEDERLAND
Proj:
4 5
Data Link to MROD-Out Sharc-A
F
Time
L
15
B
K
arc242 package
[email protected] Jansweijer
38405MROD-X
SHARC Auxiliary and Decoupling
MROD-In
of
7
Reset Signals
Also Boot Link
E
11
15
CLK
ADSP21160 VDDINT (40 pins) Decoupling Capacitors
ADSP21160 VDDEXT (43 pins) Decoupling Capacitors
SHARC Link Serie Termination
A
18
F
10
K
3
D
ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
I
TFS and RFS signal
7
E
c
H
2
3
43
420 x 297 mm
4 1 4 AA3
tonvr
1:46:57 pm
7 Feb 2006
V2 2
0
1
100n
0
GND
C218
22n
GND
7
GND
22n
C250
GND
C261
5
7
GND
1
GND
GND
C215
22n
22n
C204
0
GND
GND
R21233
33R201
33R202
R216
R2164K7
5
6
C255
22n
7
R2164K7
4K7
3
R20933
5
GND
GND
3
6
5
GND
0
R208
100n
C225
GND
GND
C252
22n
100n
C228
33
6
5
1
2
3
4
GND
0
1
2
2C208
680p
R20133
IC202
NC7SZ08
1
2
3
5
4
GND
33R203
22n
C217
4K7R217
680p
C213
22n
C248
GND
GND
C221
22n
4
5
GND
33
R21233
GND
R20433
33R208
R205
3
4
33R203
R20333
10
R222
C235
680p
6
4
GND
6
2
680p
C236
GND
GND
22n
C253
GND
680p
C234
GND
C233
680p
4
7
33R214
1
2
R20633
33R205
33
33R207
1
7
C237
680p
4K7R221
R205
R2174K7
GND
GND
C230
100n
C259
100n
GND
7
C263
47u
GND
C202
22n
R20933
GND
680p
C238
R21133
33R210
R20833
GND
R20633
33R206
R2184K7
4K7R219
GND
GND
100n
C262
4K7R216
R204
680p
C209
4
GND GND
C210
680p
33
R21533
GND
GND
C254
22n
R21433
GND GND
5
GND
R21033
33R211
R20333
733
R209
4K7R217
100n
C260
6
C245
22n
GND
GND
GND
C214
680p
33R211
4
680p
C207
33R210
R21133
1
R21033
C212
680p
GND
680p
C211
4
3
7
6
5
GND
GND
22n
C256
0
2
33R207 GND
33R207
4
33R214
6
680p
C242
R215
R21533
GND GND
5
6
6
6
0
33
R2204K7
47u
C264
1
GND
C257
100n
100n
C229
GND
3
2
33R202
0
22n
C222
R20133
22n
C220
R20633
33R202
4
33R213
C239
680p
2
2
R20233
R21333
C232
47u
GND
GND
R21233
33R212
0
R20133
33R213
22n
C216
680p
C205
GND
C206
680p
3
3
2
1
GND
GND
7
3
R20733
2
33R214
6
5
33R213
GND
7
1
0
C203
680p
C226
100n
GND
C201
100n
33R209
22n
C246 C247
22n
7
J12 20
100n
C258
33R204
3
J12 16
5
J12 18
J12 10
J12 12
J12 14
6
J12 7
J12 8
680p
C244
J12 3
J12 4
J12 5
J12
GND
J12 1
GND
J12 2
47u
C231
C241
680p
Fiducial201
4
5
680p
C240
7
1
GND
GNDGND
R20833
GND
1
C227
100n1
3
3
4
22n
C251
3
GND
22n
C223
GND
C224
22n
C219
22n
2
1
0
R20433
33R205
GND
J12 19
C249
22n
0
Fiducial202
2
J12 15
0
J12 17
J12 114
J12 13
Sharc_Rst_n
Rst_n
3V3
General_Rst_n
General_Rst_n
R21533
J12 9
C243
680p
L2DAT(7:0)
L1DAT(7:0)
L0DAT(7:0)
Sharc_Clk
SharcRd_n
SharcWr_n
MS3_n
MS2_n
MS1_n
MS0_n
Adr(21:0)
Data(31:0)
ChA_DMAR_n
ChA_Empty
L2ACKi
L2CLKi
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L2ACK50_OHM_SHARC_LINK
L2CLK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L1ACK
50_OHM_SHARC_LINK
L1CLK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L0ACK
50_OHM_SHARC_LINK
L0CLK
Sharc_EMU_n
TCK
TDO
TDI
TMS
Sharc_TDI
Sharc_TCK
Sharc_TMS
Sharc_TDO
TRST_n
L1DATi(7:0)
L1ACKi
L1CLKi
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L2DATi(7:0)
VDDINT
VDDEXT
VDDINT
AVDD
Sharc_EMU_n
50_OHM_SHARC_LINK
L5ACK50_OHM_SHARC_LINK
L5ACKi
L5CLK50_OHM_SHARC_LINK
L5CLKi
L5DAT(7:0)
TFS0
RFS0
TFS1
RFS1
BReq_n
BMS_n
HBG_n
BRST
IRQ0_n
IRQ1_n
IRQ2_n
Sharc_TRST_n
3V3
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L4ACKL4ACKi
50_OHM_SHARC_LINK
L4CLKL4CLKi
L4DAT(7:0)
L5DATi(7:0)50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L0DATi(7:0)
L0ACKi
L0CLKi
L3DATi(7:0)
L3ACKi L3ACK50_OHM_SHARC_LINK
L3CLKi L3CLK50_OHM_SHARC_LINK
L3DAT(7:0)
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L4DATi(7:0)
to be connected to golbal GROUND.
15 16
ET-Nikhef Amsterdam
7
4
3 15 16
GOL Frequency
5
J
Proj:
9
VCCINT Ramp rate 200 us min. and 50 ms max.
Input Channel, 250 mA per Channel
100MHz
1 2
D
12
B
Time between power-on VDDINT -> VDDEXT
FYSICA EN HOGE ENERGIE-FYSICA
100MHz
Fnom = 100 MHz
G
50MHz
7
Serie termination close to XTAL
Rocket-IO Inter-FPGA Link Frequency
100 MHz 16 bit = 50 MHz 32 bit
Date
Time
B
KRUISLAAN 409, 020-592 2000
All GND nets on the SHARC need
11
41
18
C
Parallel termination at the end of the line
= 200 MB/s
Serie termination close to XTAL
A
17
= 160 MB/s
E
50MHz
8
J
C
K
NIKHEFNATIONAAL INSTITUUT VOOR KERN-
K
= VCCAUX for the Xilinx Virtex-II Pro in the
FF
Page
Dim
17
10
85
I
= VDDEXT for the ADSP21160N
3
960 mA peak per ADSP21160N
G
H
I
of
The System Clock can be locked to a crystal or
= VCCINT for Xilinx Virtex-II Pro in the
100 MHz Phase Adjust
SHARC and Input Channel System Clock
10
2F(1:0)= "mm" => 0 tu
L
6
Rev
100 mA per ADSP21160N
6 9
12
11
A
Input Channels, 600 mA per Channel
c
Note ADSP21160N Power-On Sequence!
or to the LHC_Clk depending on the resistors placed.
80 MHz 16 bit = 40 MHz 32 bit
1F(1:0)= "mm" => 0 tu
Name
4F(1:0)= "00" => 100 Divide by 2 = 50 MHz
18
14
Proj.No:
14
44
420 x 297 mm
4 1 4 AA3
tonvr
1:47:20 pm
7 Feb 2006
V2 20
[email protected] Jansweijer
38405MROD-X
Power and Clocks
MROD-In
D
13
= VDDINT for the ADSP21160N
E
2
= -50 ms to +200 ms
H
LSize
1098 SJ AMSTERDAM NEDERLAND
13
3F(1:0)= "00" => 100 Divide by 2 = 50 MHz
GND
GND
J2F1_2
1
2
3
GND
GND
82
R231
GND
R234
130
GND
130
R236
IC203
S1703B_80
80MHz
1Ctrl
2
GND
OUT3
4
Vcc
GND
C267
100n
GND
22n
C265
33
GND
22n
C270
GND
R228
0E0
R225
82
R237
22n
C268
82
R235
GND
GND
R229
1M
GND
OUT3
4
Vcc
J2F0_2
1
2
3
22n
C272
R240
130
IC205
S1703B_50
50MHz
1Ctrl
2
16 18 252 8
GND
C271
22n
15
3Q114
4F06
74F1
4Q011
4Q110
FB17
FS3
1REF
TEST31
9
1F026
271F1
1Q024
1Q123
292F0
2F130
2Q020
2Q119
43F0
3F15
3Q0
GND
4K7
R227
CY7B9911V
IC206
Vccq Vccn
GND
MBRD835L
D201C273
22n
GND
130
R238
GND
GND
82
GND
C269
22n
130
R232
5V_to_1V5_?
1V55V
GND
R23982
R233
100MHz
S1703B_100
IC204
Ctrl1
GND
2
3OUT
Vcc
4
C276
100n
GND
C266
22n
1K0
R230
22n
C274
100n
C275
R224
33
33
R223GND
GND
Z50_NET_TYPE
Z50_NET_TYPE
Rocket_XClk_B
GND
33
R226
3V3
Z50_NET_TYPE
Sharc_Clk
VDDEXTPOWER_NET_TYPE
VDDINTPOWER_NET_TYPE
LHC_Clk
5V
2V5POWER_NET_TYPE
2V5
1V5POWER_NET_TYPE
GNDPOWER_NET_TYPE
Z50_NET_TYPE
GOL_XClk_B
GOL_XClk_AZ50_NET_TYPE
Rocket_XClk_A
3V3
Z50_NET_TYPE
ChA_Clkx2
Z50_NET_TYPE
ChB_Clkx2
Z50_NET_TYPE
ChA_Clk
Z50_NET_TYPE
ChB_Clk
1V9
3V3POWER_NET_TYPE
3V3
15 16 17
c ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
6
A
7 8
Dim
Page
2 3
of
15
A
B
C
G
H
I
G
B
C
10 11 12
D
13 144 52 3 9 10 11
Output Adjustable (1V5)
12
J
Low ESR
L
1
K
L
Rev
Size
Ceramic X7R
Ceramic X7R
=> Ramp rate = 6,6 ms
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Low ESR
Proj: Proj.No:
Reference C
Ceramic X7R
Input C
18
1V5 @ 2Amp
1 9 13 16 17 184 5
tonvr
1:38:24 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
5V -> 1V5 @ 2A
Power Supply
AVX
TPSD157K010R0100
Date
Time
Name
Css = 22 nF
H
I
E
F
14
K
D
E
F
J
6 7 8
NIKHEF
FBSEL = REF
270K
11
420 x 297 mm
4 1 4 AA3
22n
C281
R242
0E0
R243
R244
17K8
2%
2%48K7 R245
C279
2u2
C277150u
GND
10u
C278
R241
10
GND
GND
GND
C282
1u
GND GND
TOFF
7
12VCC
_SHDN1
GND
GND
470pC280
FBSEL
9
GND
IN1
2 4
IN216
LX1
LX214
3LX3
15PGND1
PGND213
REF
10
SS5
L201
6u8
IC207
MAX16446COMP
FB8
11
5V
1V5
GND
C283100u
11
Date
K
3
H
2
12
17 18
16 17
NATIONAAL INSTITUUT VOOR KERN-
18
A
Dim
C
L
J
6
4
4
I
FYSICA EN HOGE ENERGIE-FYSICA
7
C
B
13
F
117 8
H
D
E
1
E
14
G
F
1098 SJ AMSTERDAM NEDERLAND
Proj:
Size
Rev
A
12
Page
14
G
KRUISLAAN 409, 020-592 2000
5
bits (2:1) are effectively the MROD-In number.
Proj.No:
B
J
of
L
c ET-Nikhef Amsterdam
I
Name
6
Channel ID Bit 0 is determines channel A or B
3
D
15
1
NIKHEF
8
15 16
13
Time
5
K
2
9 10
41
420 x 297 mm
4 1 4 AA3
tonvr
1:45:51 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
Input Channels
MROD-In
9 10
TTC_n(7:0)
VT1V8_MGT
IRQ0_n
IRQ1_n
IRQ2_n
LHC_Clk
MS0_n
MS1_n
MS2_n
MS3_n
PROG_B
Rocket_RXN
Rocket_RXP
Rocket_TXN
Rocket_TXP
Rocket_XClk
SharcRd_n
SharcWr_n
Spare(4:0)
Channel_Rst_n
Clk
Clkx2
D(7:0)
DMAR_n
DONE
Data(31:0)
Empty
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
GOL_XClk
General_Rst_n
INIT_B
2
3B
Channel_B
1V5
2V5
3V3
A21_Select
Adr(21:0)
CCLK
ChaBusy
ChaID(2:0)
GND
PROG_B
Rocket_RXN
Rocket_RXP
Rocket_TXN
Rocket_TXP
Rocket_XClk
SharcRd_n
SharcWr_n
Spare(4:0)
TTC_n(7:0)
VT1V8_MGT
Empty
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
GOL_XClk
General_Rst_n
INIT_B
IRQ0_n
IRQ1_n
IRQ2_n
LHC_Clk
MS0_n
MS1_n
MS2_n
MS3_n
3A
Channel_A
1V5
2V5
3V3
A21_Select
Adr(21:0)
CCLK
ChaBusy
ChaID(2:0)
Channel_Rst_n
Clk
Clkx2
D(7:0)
DMAR_n
DONE
Data(31:0)
001 1
SharcRd_n
SharcWr_n
Rocket_XClk_A
DONE
LHC_ClkLHC_Clk
Cha_B_ID(2:0)MROD_In_ID0
MROD_In_ID1
MROD_In_ID0
MROD_In_ID1
VT1V8_MGT VT1V8_MGT
2
1V5
2V5
3V3
FPGA_TCK
FPGA_TMS
TTC_n(7:0)
General_Rst_n
Adr(21:0)
Data(31:0)
MS0_n
MS1_n
MS2_n
MS3_n
SharcRd_n
SharcWr_n
Adr(21:0)
Data(31:0)
IRQ0_n
IRQ1_n
IRQ2_n
MS0_n
MS1_n
MS2_n
MS3_n
ChA_DMAR_n
D(7:0)
ChA_Clkx2
ChA_Clk
ChA_Rst_n
Cha_A_ID(2:0)
ChA_Busy
CCLK
GOL_XClk_B
Rocket_XClk_B
General_Rst_n
LHC_Clk LHC_Clk
1V5
2V5
3V3
INIT_B
D(7:0)
PROG_B
DONE
CCLK
FPGA_TMS
FPGA_TCK
GOL_XClk_A
ChB_Spare(4:0)
Rocket_ChB_TXP
Rocket_ChB_TXN
Rocket_ChB_RXP
Rocket_ChB_RXN
FPGA_TDO
ChB_Empty
ChB_DMAR_n
ChB_Clkx2
ChB_Clk
ChB_Rst_n
ChB_Busy
3V3
TTC_n(7:0)
ChA_Spare(4:0)
Rocket_ChA_TXP
Rocket_ChA_TXN
Rocket_ChA_RXP
Rocket_ChA_RXN
PROG_B
IRQ2_n
IRQ1_n
IRQ0_n
INIT_B
FPGA_TDI
ChA_Empty
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
I
1 2 3 4
Proj:
B
C
DD
E
J
12
K
9
Time
15
Page
17
3
Clock Configuration:
CLK_CFG(3:0) = "0010"
187
NIKHEF
8
EBOOT = ’0’, LBOOT = ’1’, BMS_n = ’1’ (Input)
10 11
=> Core / CLKIN Ration 2:1
Name
Dim
1
8
c
K
SizeNATIONAAL INSTITUUT VOOR KERN-
J
9
A
B
C
18
Booting Mode:
L
VDDINT (1V9) 40 pins
VDDEXT (3V3) 43 pins
GND 82 pins
NC 9 pins
SHARC Power pins:
ET-Nikhef Amsterdam
5 6
of
15 16 174 5
Date
E
F
G
H
I
6
7
Proj.No:
Rev
4 1 4 AA3
tonvr
1:46:33 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
SHARC
MROD-In
16
1098 SJ AMSTERDAM NEDERLAND
L
A
F
G
=> Link Port Booting
ID = "000"
10 11 12 13 14
2
H
13 14
42
420 x 297 mm
T12 VDDINT_T12 T13 VDDINT_T13 T14 VDDINT_T14 T15 VDDINT_T15T6 VDDINT_T6 T7 VDDINT_T7 T8 VDDINT_T8 T9 VDDINT_T9
Y15 WRH_n Y16 WRL_n
VDDINT_L15L6 VDDINT_L6
M15 VDDINT_M15M6 VDDINT_M6
N15 VDDINT_N15N6 VDDINT_N6
VDDINT_P15P15P6 VDDINT_P6
R6 VDDINT_R6
T10 VDDINT_T10 T11 VDDINT_T11
VDDINT_E9
F15 VDDINT_F15F6 VDDINT_F6
G15 VDDINT_G15G6 VDDINT_G6
H15 VDDINT_H15VDDINT_H6H6
J15 VDDINT_J15J6 VDDINT_J6
K15 VDDINT_K15K6 VDDINT_K6
L15
D13 VDDINT_D13D7 VDDINT_D7
E10 VDDINT_E10 E12 VDDINT_E12 E13 VDDINT_E13 E14 VDDINT_E14 E15 VDDINT_E15E6 VDDINT_E6 E7 VDDINT_E7 E8 VDDINT_E8 E9
VDDEXT_U11U11 U12 VDDEXT_U12 U13 VDDEXT_U13 U14 VDDEXT_U14 U15 VDDEXT_U15 U16 VDDEXT_U16U5 VDDEXT_U5 U6 VDDEXT_U6 U7 VDDEXT_U7 U8 VDDEXT_U8 U9 VDDEXT_U9
M5 VDDEXT_M5
VDDEXT_N16N16N5 VDDEXT_N5
P16 VDDEXT_P16P5 VDDEXT_P5
R16 VDDEXT_R16R5 VDDEXT_R5
T16 VDDEXT_T16T5 VDDEXT_T5
U10 VDDEXT_U10
G16 VDDEXT_G16G5 VDDEXT_G5
H16 VDDEXT_H16H5 VDDEXT_H5
J16 VDDEXT_J16VDDEXT_J5J5
K16 VDDEXT_K16K5 VDDEXT_K5
L16 VDDEXT_L16L5 VDDEXT_L5
M16 VDDEXT_M16
VDDEXT_D10 D11 VDDEXT_D11 D12 VDDEXT_D12 D14 VDDEXT_D14D6 VDDEXT_D6 D8 VDDEXT_D8 D9 VDDEXT_D9
E16 VDDEXT_E16E5 VDDEXT_E5
F16 VDDEXT_F16F5 VDDEXT_F5
B8 TCK B18 TCLK0
C14 TCLK1
TDIA7
C9 TDO
D15 TFS0
A16 TFS1A13 TIMEXP
C8 TMS
A8 TRST_n
D10
M19 PA_n
A18 RCLK0
B16 RCLK1
W15 RDH_n
V14 RDL_n
L20 REDY
A9 RESET_n
B17 RFS0
A17 RFS1A10 RPBA
M18 SBTS_n
MS3_n
A14 NC_A14 A15 NC_A15
B13 NC_B13 NC_B14B14
C12 NC_C12 C13 NC_C13
M4 NC_M4
N1 NC_N1 N2 NC_N2
PAGEM17
L5DAT(1)
V17 L5DAT(2)
W19 L5DAT(3)
V19 L5DAT(4)
W20 L5DAT(5)
V20 L5DAT(6)
U17 L5DAT(7)
W17 LBOOT
Y13 MS0_n
V12 MS1_n
W13 MS2_n
Y14
L4DAT(1)U19 U20 L4DAT(2)
T17 L4DAT(3) L4DAT(4)T20
R17 L4DAT(5) R18 L4DAT(6) R19 L4DAT(7)
L5ACKV18
Y20 L5CLK
V16 L5DAT(0)
W18
L3DAT(0)
P18 L3DAT(1)P17 L3DAT(2) P19 L3DAT(3)
N19 L3DAT(4)N17 L3DAT(5) N18 L3DAT(6)
M20 L3DAT(7)
T18 L4ACK T19 L4CLK
U18 L4DAT(0)
L2CLK
J18 L2DAT(0)
H20 L2DAT(1)
J17 L2DAT(2)
H19 L2DAT(3)
G19 L2DAT(4)
H17 L2DAT(5)
G18 L2DAT(6)
F20 L2DAT(7)
P20 L3ACK
N20 L3CLK
R20
D20 L1CLK
F19 L1DAT(0)
E20 L1DAT(1)
G17 L1DAT(2)
F18 L1DAT(3)L1DAT(4)F17
E18 L1DAT(5)E17 L1DAT(6)
D16 L1DAT(7)
H18 L2ACK
G20
L0ACK
D17 L0CLK
C20 L0DAT(0)
D19 L0DAT(1)
B20 L0DAT(2)
D18 L0DAT(3)
A20 L0DAT(4)
B19 L0DAT(5)
C18 L0DAT(6)C17 L0DAT(7)
E19 L1ACK
GND_R7 R8 GND_R8 R9 GND_R9
J19 HBG_n J20 HBR_n
ID0V10
W10 ID1
Y11 ID2
A11 IRQ0_n
C10 IRQ1_n
B10 IRQ2_n
C19
P14 GND_P14GND_P7P7 P8 GND_P8 P9 GND_P9
R10 GND_R10 R11 GND_R11 R12 GND_R12 R13 GND_R13 R14 GND_R14 R15 GND_R15R7
GND_N11 N12 GND_N12 N13 GND_N13 N14 GND_N14N7 GND_N7 GND_N8N8 N9 GND_N9
P10 GND_P10 P11 GND_P11 P12 GND_P12 P13 GND_P13
L9 GND_L9
M10 GND_M10 M11 GND_M11 M12 GND_M12 M13 GND_M13 M14 GND_M14M7 GND_M7 M8 GND_M8 GND_M9M9
N10 GND_N10 N11
K14 GND_K14K7 GND_K7 K8 GND_K8 K9 GND_K9
L10 GND_L10 L11 GND_L11 L12 GND_L12 L13 GND_L13 L14 GND_L14L7 GND_L7 L8 GND_L8
GND_J11 J12 GND_J12 J13 GND_J13 J14 GND_J14J7 GND_J7 J8 GND_J8 J9 GND_J9
K10 GND_K10 K11 GND_K11 GND_K12K12 K13 GND_K13
G9 GND_G9
H10 GND_H10 H11 GND_H11 H12 GND_H12 H13 GND_H13 H14 GND_H14H7 GND_H7 H8 GND_H8 H9 GND_H9
J10 GND_J10 J11
F14 GND_F14F7 GND_F7 F8 GND_F8 GND_F9F9
G10 GND_G10 G11 GND_G11 G12 GND_G12 G13 GND_G13 G14 GND_G14G7 GND_G7 G8 GND_G8
EBOOT
B9 EMU_n B12 FLAG0
A12 FLAG1
C11 FLAG2
B11 FLAG3
E11 GND_E11
F10 GND_F10 F11 GND_F11 F12 GND_F12 F13 GND_F13
DATA(7)
A4 DATA(8)
B4 DATA(9)
Y17 DMAG1_n
W16 DMAG2_n
Y18 DMAR1_n
V15 DMAR2_n
C16 DR0C15 DR1
A19 DT0
B15 DT1
Y19
P4 DATA(55)
T1 DATA(56)
R3 DATA(57)
T2 DATA(58) T3 DATA(59)
B5 DATA(6)
R4 DATA(60)
U1 DATA(61) U2 DATA(62)
DATA(63)T4
C5
DATA(45)K2 DATA(46) DATA(47)K4
N3 DATA(48)
P1 DATA(49)
C6 DATA(5)
P2 DATA(50)
N4 DATA(51)
P3 DATA(52)
R1 DATA(53) R2 DATA(54)
DATA(35)
H4 DATA(36)H3 DATA(37)
G1 DATA(38)
H2 DATA(39)
A5 DATA(4)
H1 DATA(40)
J4 DATA(41)J3 DATA(42)J2 DATA(43)J1 DATA(44)
K3
F4 DATA(26)F3 DATA(27)
D1 DATA(28)
DATA(29)E2
DATA(3)B6
E1 DATA(30)
G4 DATA(31)G3 DATA(32)
F2 DATA(33)DATA(34)F1
G2
DATA(16)
C3 DATA(17)C2 DATA(18)
D4 DATA(19)
A6 DATA(2)
DATA(20)D3
E4 DATA(21)
B1 DATA(22)
E3 DATA(23)
C1 DATA(24)
D2 DATA(25)
CLK_CFG_2
M2 CLK_CFG_3
V13 CS_n
B7 DATA(0)
C7 DATA(1)
A3 DATA(10)
C4 DATA(11)
D5 DATA(12)
A2 DATA(13)A1 DATA(14)
B3 DATA(15)B2
BR3_nK20K19 BR4_nK18 BR5_nK17 BR6_n
BRSTY12
W14 CIF_n
L1 CLKIN
M3 CLKOUT
K1 CLK_CFG_0
L2 CLK_CFG_1 L4
ADDR(4)
W1 ADDR(5)
ADDR(6)V2 V3 ADDR(7)
Y1 ADDR(8)
W2 ADDR(9)
L3 AGND
M1 AVDD
W12 BMS_n
L18 BR1_nL17 BR2_n
W7 ADDR(23)
ADDR(24)Y7
V8 ADDR(25)
W8 ADDR(26)
Y8 ADDR(27)
V9 ADDR(28)
W9 ADDR(29)
U3 ADDR(3)
Y9 ADDR(30) Y10 ADDR(31)
V1
Y3 ADDR(13)
V5 ADDR(14)
W4 ADDR(15)
Y4 ADDR(16)
W5 ADDR(17)
V6 ADDR(18)
Y5 ADDR(19)
U4 ADDR(2)
W6 ADDR(20)
Y6 ADDR(21)
V7 ADDR(22)
IC301
ADSP21160N
L19 ACK
W11 ADDR(0)
V11 ADDR(1)V4 ADDR(10)
Y2 ADDR(11)
W3 ADDR(12)
VDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINT
VDDINT VDDINT VDDINT VDDINT VDDINT VDDINTVDDINT VDDINT VDDINT VDDINT
SharcWr_n
VDDEXT VDDEXT VDDEXT VDDEXT VDDEXTVDDEXT VDDEXT VDDEXT VDDEXT VDDEXT
VDDINTVDDINT
VDDINT VDDINT VDDINT VDDINT VDDINTVDDINT VDDINT VDDINT VDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINT
VDDEXT VDDEXT VDDEXTVDDEXT VDDEXT VDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXT VDDEXT
L5DATi(4)
L5DATi(5)
L5DATi(6)
L5DATi(7)
VDDEXT
MS0_n
MS1_n
MS2_n
MS3_n
SharcRd_n
Rst_n
RFS0
RFS1GND
VDDEXT
TCK
TDI
TDO
TFS0
TFS1
TMS
TRST_n
VDDEXT
L3DATi(2) L3DATi(3)
L3DATi(4)L3DATi(5) L3DATi(6)
L3DATi(7)
L4ACKi L4CLKi
L4DATi(0) L4DATi(1) L4DATi(2)
L4DATi(3) L4DATi(4)
L4DATi(5) L4DATi(6) L4DATi(7)
L5ACKi
L5CLKi
L5DATi(0)
L5DATi(1)
L5DATi(2)
L5DATi(3)
L1DATi(1)
L1DATi(2)
L1DATi(3)L1DATi(4)
L1DATi(5)L1DATi(6)
L1DATi(7)
L2ACKi
L2CLKi
L2DATi(0)
L2DATi(1)
L2DATi(2)
L2DATi(3)
L2DATi(4)
L2DATi(5)
L2DATi(6)
L2DATi(7)
L3ACKi
L3CLKi
L3DATi(0)
L3DATi(1)
VDDEXT
GND
GND
GND
IRQ0_n
IRQ1_n
IRQ2_n
L0ACKi
L0CLKi
L0DATi(0)
L0DATi(1)
L0DATi(2)
L0DATi(3)
L0DATi(4)
L0DATi(5)
L0DATi(6)L0DATi(7)
L1ACKi
L1CLKi
L1DATi(0)
GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GND GNDGND GND GND
HBG_n
GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND
ChB_DMAR_n
GND
Sharc_EMU_n ChA_Rst_n
ChB_Rst_n
ChA_Empty
ChB_Empty
GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND
Data(17) Data(18)
Data(19)
Data(20)
Data(21) Data(22)
Data(23)
Data(24)
Data(25)
Data(26) Data(27)
Data(28)
Data(29) Data(30)
Data(31)
ChA_DMAR_n
Data(1)Data(2)
Data(3)
Data(4)Data(5)
Data(6)
Data(7)Data(8)
Data(9)Data(10)Data(11)Data(12)
Data(13)Data(14) Data(15)
Data(16)
Adr(4)
Adr(5)
Adr(6) Adr(7)
Adr(8)
Adr(9)
GND
AVDD
BMS_n
BReq_nBReq_n
BReq_nBReq_nBReq_nBReq_n
BRST
Sharc_Clk
GND
VDDEXT GND
GND
VDDEXT
Data(0)
Adr(0)
Adr(1)Adr(10)
Adr(11)
Adr(12)
Adr(13)
Adr(14)
Adr(15)
Adr(16)
Adr(17)
Adr(18)
Adr(19)
Adr(2)
Adr(20)
Adr(21)
Adr(3)
5 6
J
IRQ signal
Pull-ups in one
0
NIKHEF
C
1716
C
Rev
16
G
2 3 4 8 9
Proj.No:
14
L
Name
6
12 13 14 15
Date
a General_Rst_n, or when a reset is
Optional Test
Connector
Data Link to MROD-Out Sharc-B
Communication Link
12 13
The Sharc is reset when there is
Pull-ups in one
arc242 package
B
1
D
1
Communication Link
Communication Link
Communication Link
Sharc JTAG (and Emulator) Signals
2
asked via the MROD-Out FPGA
17 18
Size
Dim
11
G
H
I
J
GND
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
8 9 10
A
Page1098 SJ AMSTERDAM NEDERLAND
Proj:
4 5
Data Link to MROD-Out Sharc-A
F
Time
L
15
B
K
arc242 package
[email protected] Jansweijer
38405MROD-X
SHARC Auxiliary and Decoupling
MROD-In
of
7
Reset Signals
Also Boot Link
E
11
15
CLK
ADSP21160 VDDINT (40 pins) Decoupling Capacitors
ADSP21160 VDDEXT (43 pins) Decoupling Capacitors
SHARC Link Serie Termination
A
18
F
10
K
3
D
ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
I
TFS and RFS signal
7
E
c
H
2
3
43
420 x 297 mm
4 1 4 AA3
tonvr
1:46:57 pm
7 Feb 2006
V2 2
0
1
100n
0
GND
C318
22n
GND
7
GND
22n
C350
GND
C361
5
7
GND
1
GND
GND
C315
22n
22n
C304
0
GND
GND
R31233
33R301
33R302
R316
R3164K7
5
6
C355
22n
7
R3164K7
4K7
3
R30933
5
GND
GND
3
6
5
GND
0
R308
100n
C325
GND
GND
C352
22n
100n
C328
33
6
5
1
2
3
4
GND
0
1
2
2C308
680p
R30133
IC302
NC7SZ08
1
2
3
5
4
GND
33R303
22n
C317
4K7R317
680p
C313
22n
C348
GND
GND
C321
22n
4
5
GND
33
R31233
GND
R30433
33R308
R305
3
4
33R303
R30333
10
R322
C335
680p
6
4
GND
6
2
680p
C336
GND
GND
22n
C353
GND
680p
C334
GND
C333
680p
4
7
33R314
1
2
R30633
33R305
33
33R307
1
7
C337
680p
4K7R321
R305
R3174K7
GND
GND
C330
100n
C359
100n
GND
7
C363
47u
GND
C302
22n
R30933
GND
680p
C338
R31133
33R310
R30833
GND
R30633
33R306
R3184K7
4K7R319
GND
GND
100n
C362
4K7R316
R304
680p
C309
4
GND GND
C310
680p
33
R31533
GND
GND
C354
22n
R31433
GND GND
5
GND
R31033
33R311
R30333
733
R309
4K7R317
100n
C360
6
C345
22n
GND
GND
GND
C314
680p
33R311
4
680p
C307
33R310
R31133
1
R31033
C312
680p
GND
680p
C311
4
3
7
6
5
GND
GND
22n
C356
0
2
33R307 GND
33R307
4
33R314
6
680p
C342
R315
R31533
GND GND
5
6
6
6
0
33
R3204K7
47u
C364
1
GND
C357
100n
100n
C329
GND
3
2
33R302
0
22n
C322
R30133
22n
C320
R30633
33R302
4
33R313
C339
680p
2
2
R30233
R31333
C332
47u
GND
GND
R31233
33R312
0
R30133
33R313
22n
C316
680p
C305
GND
C306
680p
3
3
2
1
GND
GND
7
3
R30733
2
33R314
6
5
33R313
GND
7
1
0
C303
680p
C326
100n
GND
C301
100n
33R309
22n
C346 C347
22n
7
J13 20
100n
C358
33R304
3
J13 16
5
J13 18
J13 10
J13 12
J13 14
6
J13 7
J13 8
680p
C344
J13 3
J13 4
J13 5
J13
GND
J13 1
GND
J13 2
47u
C331
C341
680p
Fiducial301
4
5
680p
C340
7
1
GND
GNDGND
R30833
GND
1
C327
100n1
3
3
4
22n
C351
3
GND
22n
C323
GND
C324
22n
C319
22n
2
1
0
R30433
33R305
GND
J13 19
C349
22n
0
Fiducial302
2
J13 15
0
J13 17
J13 114
J13 13
Sharc_Rst_n
Rst_n
3V3
General_Rst_n
General_Rst_n
R31533
J13 9
C343
680p
L2DAT(7:0)
L1DAT(7:0)
L0DAT(7:0)
Sharc_Clk
SharcRd_n
SharcWr_n
MS3_n
MS2_n
MS1_n
MS0_n
Adr(21:0)
Data(31:0)
ChA_DMAR_n
ChA_Empty
L2ACKi
L2CLKi
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L2ACK50_OHM_SHARC_LINK
L2CLK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L1ACK
50_OHM_SHARC_LINK
L1CLK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L0ACK
50_OHM_SHARC_LINK
L0CLK
Sharc_EMU_n
TCK
TDO
TDI
TMS
Sharc_TDI
Sharc_TCK
Sharc_TMS
Sharc_TDO
TRST_n
L1DATi(7:0)
L1ACKi
L1CLKi
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L2DATi(7:0)
VDDINT
VDDEXT
VDDINT
AVDD
Sharc_EMU_n
50_OHM_SHARC_LINK
L5ACK50_OHM_SHARC_LINK
L5ACKi
L5CLK50_OHM_SHARC_LINK
L5CLKi
L5DAT(7:0)
TFS0
RFS0
TFS1
RFS1
BReq_n
BMS_n
HBG_n
BRST
IRQ0_n
IRQ1_n
IRQ2_n
Sharc_TRST_n
3V3
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L4ACKL4ACKi
50_OHM_SHARC_LINK
L4CLKL4CLKi
L4DAT(7:0)
L5DATi(7:0)50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L0DATi(7:0)
L0ACKi
L0CLKi
L3DATi(7:0)
L3ACKi L3ACK50_OHM_SHARC_LINK
L3CLKi L3CLK50_OHM_SHARC_LINK
L3DAT(7:0)
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L4DATi(7:0)
to be connected to golbal GROUND.
15 16
ET-Nikhef Amsterdam
7
4
3 15 16
GOL Frequency
5
J
Proj:
9
VCCINT Ramp rate 200 us min. and 50 ms max.
Input Channel, 250 mA per Channel
100MHz
1 2
D
12
B
Time between power-on VDDINT -> VDDEXT
FYSICA EN HOGE ENERGIE-FYSICA
100MHz
Fnom = 100 MHz
G
50MHz
7
Serie termination close to XTAL
Rocket-IO Inter-FPGA Link Frequency
100 MHz 16 bit = 50 MHz 32 bit
Date
Time
B
KRUISLAAN 409, 020-592 2000
All GND nets on the SHARC need
11
41
18
C
Parallel termination at the end of the line
= 200 MB/s
Serie termination close to XTAL
A
17
= 160 MB/s
E
50MHz
8
J
C
K
NIKHEFNATIONAAL INSTITUUT VOOR KERN-
K
= VCCAUX for the Xilinx Virtex-II Pro in the
FF
Page
Dim
17
10
85
I
= VDDEXT for the ADSP21160N
3
960 mA peak per ADSP21160N
G
H
I
of
The System Clock can be locked to a crystal or
= VCCINT for Xilinx Virtex-II Pro in the
100 MHz Phase Adjust
SHARC and Input Channel System Clock
10
2F(1:0)= "mm" => 0 tu
L
6
Rev
100 mA per ADSP21160N
6 9
12
11
A
Input Channels, 600 mA per Channel
c
Note ADSP21160N Power-On Sequence!
or to the LHC_Clk depending on the resistors placed.
80 MHz 16 bit = 40 MHz 32 bit
1F(1:0)= "mm" => 0 tu
Name
4F(1:0)= "00" => 100 Divide by 2 = 50 MHz
18
14
Proj.No:
14
44
420 x 297 mm
4 1 4 AA3
tonvr
1:47:20 pm
7 Feb 2006
V2 20
[email protected] Jansweijer
38405MROD-X
Power and Clocks
MROD-In
D
13
= VDDINT for the ADSP21160N
E
2
= -50 ms to +200 ms
H
LSize
1098 SJ AMSTERDAM NEDERLAND
13
3F(1:0)= "00" => 100 Divide by 2 = 50 MHz
GND
GND
J2F1_3
1
2
3
GND
GND
82
R331
GND
R334
130
GND
130
R336
IC303
S1703B_80
80MHz
1Ctrl
2
GND
OUT3
4
Vcc
GND
C367
100n
GND
22n
C365
33
GND
22n
C370
GND
R328
0E0
R325
82
R337
22n
C368
82
R335
GND
GND
R329
1M
GND
OUT3
4
Vcc
J2F0_3
1
2
3
22n
C372
R340
130
IC305
S1703B_50
50MHz
1Ctrl
2
16 18 252 8
GND
C371
22n
15
3Q114
4F06
74F1
4Q011
4Q110
FB17
FS3
1REF
TEST31
9
1F026
271F1
1Q024
1Q123
292F0
2F130
2Q020
2Q119
43F0
3F15
3Q0
GND
4K7
R327
CY7B9911V
IC306
Vccq Vccn
GND
MBRD835L
D301C373
22n
GND
130
R338
GND
GND
82
GND
C369
22n
130
R332
5V_to_1V5_?
1V55V
GND
R33982
R333
100MHz
S1703B_100
IC304
Ctrl1
GND
2
3OUT
Vcc
4
C376
100n
GND
C366
22n
1K0
R330
22n
C374
100n
C375
R324
33
33
R323GND
GND
Z50_NET_TYPE
Z50_NET_TYPE
Rocket_XClk_B
GND
33
R326
3V3
Z50_NET_TYPE
Sharc_Clk
VDDEXTPOWER_NET_TYPE
VDDINTPOWER_NET_TYPE
LHC_Clk
5V
2V5POWER_NET_TYPE
2V5
1V5POWER_NET_TYPE
GNDPOWER_NET_TYPE
Z50_NET_TYPE
GOL_XClk_B
GOL_XClk_AZ50_NET_TYPE
Rocket_XClk_A
3V3
Z50_NET_TYPE
ChA_Clkx2
Z50_NET_TYPE
ChB_Clkx2
Z50_NET_TYPE
ChA_Clk
Z50_NET_TYPE
ChB_Clk
1V9
3V3POWER_NET_TYPE
3V3
15 16 17
c ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
6
A
7 8
Dim
Page
2 3
of
15
A
B
C
G
H
I
G
B
C
10 11 12
D
13 144 52 3 9 10 11
Output Adjustable (1V5)
12
J
Low ESR
L
1
K
L
Rev
Size
Ceramic X7R
Ceramic X7R
=> Ramp rate = 6,6 ms
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Low ESR
Proj: Proj.No:
Reference C
Ceramic X7R
Input C
18
1V5 @ 2Amp
1 9 13 16 17 184 5
tonvr
1:38:24 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
5V -> 1V5 @ 2A
Power Supply
AVX
TPSD157K010R0100
Date
Time
Name
Css = 22 nF
H
I
E
F
14
K
D
E
F
J
6 7 8
NIKHEF
FBSEL = REF
270K
11
420 x 297 mm
4 1 4 AA3
22n
C381
R342
0E0
R343
R344
17K8
2%
2%48K7 R345
C379
2u2
C377150u
GND
10u
C378
R341
10
GND
GND
GND
C382
1u
GND GND
TOFF
7
12VCC
_SHDN1
GND
GND
470pC380
FBSEL
9
GND
IN1
2 4
IN216
LX1
LX214
3LX3
15PGND1
PGND213
REF
10
SS5
L301
6u8
IC307
MAX16446COMP
FB8
11
5V
1V5
GND
C383100u
11
Date
K
3
H
2
12
17 18
16 17
NATIONAAL INSTITUUT VOOR KERN-
18
A
Dim
C
L
J
6
4
4
I
FYSICA EN HOGE ENERGIE-FYSICA
7
C
B
13
F
117 8
H
D
E
1
E
14
G
F
1098 SJ AMSTERDAM NEDERLAND
Proj:
Size
Rev
A
12
Page
14
G
KRUISLAAN 409, 020-592 2000
5
bits (2:1) are effectively the MROD-In number.
Proj.No:
B
J
of
L
c ET-Nikhef Amsterdam
I
Name
6
Channel ID Bit 0 is determines channel A or B
3
D
15
1
NIKHEF
8
15 16
13
Time
5
K
2
9 10
41
420 x 297 mm
4 1 4 AA3
tonvr
1:45:51 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
Input Channels
MROD-In
9 10
TTC_n(7:0)
VT1V8_MGT
IRQ0_n
IRQ1_n
IRQ2_n
LHC_Clk
MS0_n
MS1_n
MS2_n
MS3_n
PROG_B
Rocket_RXN
Rocket_RXP
Rocket_TXN
Rocket_TXP
Rocket_XClk
SharcRd_n
SharcWr_n
Spare(4:0)
Channel_Rst_n
Clk
Clkx2
D(7:0)
DMAR_n
DONE
Data(31:0)
Empty
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
GOL_XClk
General_Rst_n
INIT_B
2
4B
Channel_B
1V5
2V5
3V3
A21_Select
Adr(21:0)
CCLK
ChaBusy
ChaID(2:0)
GND
PROG_B
Rocket_RXN
Rocket_RXP
Rocket_TXN
Rocket_TXP
Rocket_XClk
SharcRd_n
SharcWr_n
Spare(4:0)
TTC_n(7:0)
VT1V8_MGT
Empty
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
GOL_XClk
General_Rst_n
INIT_B
IRQ0_n
IRQ1_n
IRQ2_n
LHC_Clk
MS0_n
MS1_n
MS2_n
MS3_n
4A
Channel_A
1V5
2V5
3V3
A21_Select
Adr(21:0)
CCLK
ChaBusy
ChaID(2:0)
Channel_Rst_n
Clk
Clkx2
D(7:0)
DMAR_n
DONE
Data(31:0)
001 1
SharcRd_n
SharcWr_n
Rocket_XClk_A
DONE
LHC_ClkLHC_Clk
Cha_B_ID(2:0)MROD_In_ID0
MROD_In_ID1
MROD_In_ID0
MROD_In_ID1
VT1V8_MGT VT1V8_MGT
2
1V5
2V5
3V3
FPGA_TCK
FPGA_TMS
TTC_n(7:0)
General_Rst_n
Adr(21:0)
Data(31:0)
MS0_n
MS1_n
MS2_n
MS3_n
SharcRd_n
SharcWr_n
Adr(21:0)
Data(31:0)
IRQ0_n
IRQ1_n
IRQ2_n
MS0_n
MS1_n
MS2_n
MS3_n
ChA_DMAR_n
D(7:0)
ChA_Clkx2
ChA_Clk
ChA_Rst_n
Cha_A_ID(2:0)
ChA_Busy
CCLK
GOL_XClk_B
Rocket_XClk_B
General_Rst_n
LHC_Clk LHC_Clk
1V5
2V5
3V3
INIT_B
D(7:0)
PROG_B
DONE
CCLK
FPGA_TMS
FPGA_TCK
GOL_XClk_A
ChB_Spare(4:0)
Rocket_ChB_TXP
Rocket_ChB_TXN
Rocket_ChB_RXP
Rocket_ChB_RXN
FPGA_TDO
ChB_Empty
ChB_DMAR_n
ChB_Clkx2
ChB_Clk
ChB_Rst_n
ChB_Busy
3V3
TTC_n(7:0)
ChA_Spare(4:0)
Rocket_ChA_TXP
Rocket_ChA_TXN
Rocket_ChA_RXP
Rocket_ChA_RXN
PROG_B
IRQ2_n
IRQ1_n
IRQ0_n
INIT_B
FPGA_TDI
ChA_Empty
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
I
1 2 3 4
Proj:
B
C
DD
E
J
12
K
9
Time
15
Page
17
3
Clock Configuration:
CLK_CFG(3:0) = "0010"
187
NIKHEF
8
EBOOT = ’0’, LBOOT = ’1’, BMS_n = ’1’ (Input)
10 11
=> Core / CLKIN Ration 2:1
Name
Dim
1
8
c
K
SizeNATIONAAL INSTITUUT VOOR KERN-
J
9
A
B
C
18
Booting Mode:
L
VDDINT (1V9) 40 pins
VDDEXT (3V3) 43 pins
GND 82 pins
NC 9 pins
SHARC Power pins:
ET-Nikhef Amsterdam
5 6
of
15 16 174 5
Date
E
F
G
H
I
6
7
Proj.No:
Rev
4 1 4 AA3
tonvr
1:46:33 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
SHARC
MROD-In
16
1098 SJ AMSTERDAM NEDERLAND
L
A
F
G
=> Link Port Booting
ID = "000"
10 11 12 13 14
2
H
13 14
42
420 x 297 mm
T12 VDDINT_T12 T13 VDDINT_T13 T14 VDDINT_T14 T15 VDDINT_T15T6 VDDINT_T6 T7 VDDINT_T7 T8 VDDINT_T8 T9 VDDINT_T9
Y15 WRH_n Y16 WRL_n
VDDINT_L15L6 VDDINT_L6
M15 VDDINT_M15M6 VDDINT_M6
N15 VDDINT_N15N6 VDDINT_N6
VDDINT_P15P15P6 VDDINT_P6
R6 VDDINT_R6
T10 VDDINT_T10 T11 VDDINT_T11
VDDINT_E9
F15 VDDINT_F15F6 VDDINT_F6
G15 VDDINT_G15G6 VDDINT_G6
H15 VDDINT_H15VDDINT_H6H6
J15 VDDINT_J15J6 VDDINT_J6
K15 VDDINT_K15K6 VDDINT_K6
L15
D13 VDDINT_D13D7 VDDINT_D7
E10 VDDINT_E10 E12 VDDINT_E12 E13 VDDINT_E13 E14 VDDINT_E14 E15 VDDINT_E15E6 VDDINT_E6 E7 VDDINT_E7 E8 VDDINT_E8 E9
VDDEXT_U11U11 U12 VDDEXT_U12 U13 VDDEXT_U13 U14 VDDEXT_U14 U15 VDDEXT_U15 U16 VDDEXT_U16U5 VDDEXT_U5 U6 VDDEXT_U6 U7 VDDEXT_U7 U8 VDDEXT_U8 U9 VDDEXT_U9
M5 VDDEXT_M5
VDDEXT_N16N16N5 VDDEXT_N5
P16 VDDEXT_P16P5 VDDEXT_P5
R16 VDDEXT_R16R5 VDDEXT_R5
T16 VDDEXT_T16T5 VDDEXT_T5
U10 VDDEXT_U10
G16 VDDEXT_G16G5 VDDEXT_G5
H16 VDDEXT_H16H5 VDDEXT_H5
J16 VDDEXT_J16VDDEXT_J5J5
K16 VDDEXT_K16K5 VDDEXT_K5
L16 VDDEXT_L16L5 VDDEXT_L5
M16 VDDEXT_M16
VDDEXT_D10 D11 VDDEXT_D11 D12 VDDEXT_D12 D14 VDDEXT_D14D6 VDDEXT_D6 D8 VDDEXT_D8 D9 VDDEXT_D9
E16 VDDEXT_E16E5 VDDEXT_E5
F16 VDDEXT_F16F5 VDDEXT_F5
B8 TCK B18 TCLK0
C14 TCLK1
TDIA7
C9 TDO
D15 TFS0
A16 TFS1A13 TIMEXP
C8 TMS
A8 TRST_n
D10
M19 PA_n
A18 RCLK0
B16 RCLK1
W15 RDH_n
V14 RDL_n
L20 REDY
A9 RESET_n
B17 RFS0
A17 RFS1A10 RPBA
M18 SBTS_n
MS3_n
A14 NC_A14 A15 NC_A15
B13 NC_B13 NC_B14B14
C12 NC_C12 C13 NC_C13
M4 NC_M4
N1 NC_N1 N2 NC_N2
PAGEM17
L5DAT(1)
V17 L5DAT(2)
W19 L5DAT(3)
V19 L5DAT(4)
W20 L5DAT(5)
V20 L5DAT(6)
U17 L5DAT(7)
W17 LBOOT
Y13 MS0_n
V12 MS1_n
W13 MS2_n
Y14
L4DAT(1)U19 U20 L4DAT(2)
T17 L4DAT(3) L4DAT(4)T20
R17 L4DAT(5) R18 L4DAT(6) R19 L4DAT(7)
L5ACKV18
Y20 L5CLK
V16 L5DAT(0)
W18
L3DAT(0)
P18 L3DAT(1)P17 L3DAT(2) P19 L3DAT(3)
N19 L3DAT(4)N17 L3DAT(5) N18 L3DAT(6)
M20 L3DAT(7)
T18 L4ACK T19 L4CLK
U18 L4DAT(0)
L2CLK
J18 L2DAT(0)
H20 L2DAT(1)
J17 L2DAT(2)
H19 L2DAT(3)
G19 L2DAT(4)
H17 L2DAT(5)
G18 L2DAT(6)
F20 L2DAT(7)
P20 L3ACK
N20 L3CLK
R20
D20 L1CLK
F19 L1DAT(0)
E20 L1DAT(1)
G17 L1DAT(2)
F18 L1DAT(3)L1DAT(4)F17
E18 L1DAT(5)E17 L1DAT(6)
D16 L1DAT(7)
H18 L2ACK
G20
L0ACK
D17 L0CLK
C20 L0DAT(0)
D19 L0DAT(1)
B20 L0DAT(2)
D18 L0DAT(3)
A20 L0DAT(4)
B19 L0DAT(5)
C18 L0DAT(6)C17 L0DAT(7)
E19 L1ACK
GND_R7 R8 GND_R8 R9 GND_R9
J19 HBG_n J20 HBR_n
ID0V10
W10 ID1
Y11 ID2
A11 IRQ0_n
C10 IRQ1_n
B10 IRQ2_n
C19
P14 GND_P14GND_P7P7 P8 GND_P8 P9 GND_P9
R10 GND_R10 R11 GND_R11 R12 GND_R12 R13 GND_R13 R14 GND_R14 R15 GND_R15R7
GND_N11 N12 GND_N12 N13 GND_N13 N14 GND_N14N7 GND_N7 GND_N8N8 N9 GND_N9
P10 GND_P10 P11 GND_P11 P12 GND_P12 P13 GND_P13
L9 GND_L9
M10 GND_M10 M11 GND_M11 M12 GND_M12 M13 GND_M13 M14 GND_M14M7 GND_M7 M8 GND_M8 GND_M9M9
N10 GND_N10 N11
K14 GND_K14K7 GND_K7 K8 GND_K8 K9 GND_K9
L10 GND_L10 L11 GND_L11 L12 GND_L12 L13 GND_L13 L14 GND_L14L7 GND_L7 L8 GND_L8
GND_J11 J12 GND_J12 J13 GND_J13 J14 GND_J14J7 GND_J7 J8 GND_J8 J9 GND_J9
K10 GND_K10 K11 GND_K11 GND_K12K12 K13 GND_K13
G9 GND_G9
H10 GND_H10 H11 GND_H11 H12 GND_H12 H13 GND_H13 H14 GND_H14H7 GND_H7 H8 GND_H8 H9 GND_H9
J10 GND_J10 J11
F14 GND_F14F7 GND_F7 F8 GND_F8 GND_F9F9
G10 GND_G10 G11 GND_G11 G12 GND_G12 G13 GND_G13 G14 GND_G14G7 GND_G7 G8 GND_G8
EBOOT
B9 EMU_n B12 FLAG0
A12 FLAG1
C11 FLAG2
B11 FLAG3
E11 GND_E11
F10 GND_F10 F11 GND_F11 F12 GND_F12 F13 GND_F13
DATA(7)
A4 DATA(8)
B4 DATA(9)
Y17 DMAG1_n
W16 DMAG2_n
Y18 DMAR1_n
V15 DMAR2_n
C16 DR0C15 DR1
A19 DT0
B15 DT1
Y19
P4 DATA(55)
T1 DATA(56)
R3 DATA(57)
T2 DATA(58) T3 DATA(59)
B5 DATA(6)
R4 DATA(60)
U1 DATA(61) U2 DATA(62)
DATA(63)T4
C5
DATA(45)K2 DATA(46) DATA(47)K4
N3 DATA(48)
P1 DATA(49)
C6 DATA(5)
P2 DATA(50)
N4 DATA(51)
P3 DATA(52)
R1 DATA(53) R2 DATA(54)
DATA(35)
H4 DATA(36)H3 DATA(37)
G1 DATA(38)
H2 DATA(39)
A5 DATA(4)
H1 DATA(40)
J4 DATA(41)J3 DATA(42)J2 DATA(43)J1 DATA(44)
K3
F4 DATA(26)F3 DATA(27)
D1 DATA(28)
DATA(29)E2
DATA(3)B6
E1 DATA(30)
G4 DATA(31)G3 DATA(32)
F2 DATA(33)DATA(34)F1
G2
DATA(16)
C3 DATA(17)C2 DATA(18)
D4 DATA(19)
A6 DATA(2)
DATA(20)D3
E4 DATA(21)
B1 DATA(22)
E3 DATA(23)
C1 DATA(24)
D2 DATA(25)
CLK_CFG_2
M2 CLK_CFG_3
V13 CS_n
B7 DATA(0)
C7 DATA(1)
A3 DATA(10)
C4 DATA(11)
D5 DATA(12)
A2 DATA(13)A1 DATA(14)
B3 DATA(15)B2
BR3_nK20K19 BR4_nK18 BR5_nK17 BR6_n
BRSTY12
W14 CIF_n
L1 CLKIN
M3 CLKOUT
K1 CLK_CFG_0
L2 CLK_CFG_1 L4
ADDR(4)
W1 ADDR(5)
ADDR(6)V2 V3 ADDR(7)
Y1 ADDR(8)
W2 ADDR(9)
L3 AGND
M1 AVDD
W12 BMS_n
L18 BR1_nL17 BR2_n
W7 ADDR(23)
ADDR(24)Y7
V8 ADDR(25)
W8 ADDR(26)
Y8 ADDR(27)
V9 ADDR(28)
W9 ADDR(29)
U3 ADDR(3)
Y9 ADDR(30) Y10 ADDR(31)
V1
Y3 ADDR(13)
V5 ADDR(14)
W4 ADDR(15)
Y4 ADDR(16)
W5 ADDR(17)
V6 ADDR(18)
Y5 ADDR(19)
U4 ADDR(2)
W6 ADDR(20)
Y6 ADDR(21)
V7 ADDR(22)
IC401
ADSP21160N
L19 ACK
W11 ADDR(0)
V11 ADDR(1)V4 ADDR(10)
Y2 ADDR(11)
W3 ADDR(12)
VDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINT
VDDINT VDDINT VDDINT VDDINT VDDINT VDDINTVDDINT VDDINT VDDINT VDDINT
SharcWr_n
VDDEXT VDDEXT VDDEXT VDDEXT VDDEXTVDDEXT VDDEXT VDDEXT VDDEXT VDDEXT
VDDINTVDDINT
VDDINT VDDINT VDDINT VDDINT VDDINTVDDINT VDDINT VDDINT VDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINT
VDDEXT VDDEXT VDDEXTVDDEXT VDDEXT VDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXT VDDEXT
L5DATi(4)
L5DATi(5)
L5DATi(6)
L5DATi(7)
VDDEXT
MS0_n
MS1_n
MS2_n
MS3_n
SharcRd_n
Rst_n
RFS0
RFS1GND
VDDEXT
TCK
TDI
TDO
TFS0
TFS1
TMS
TRST_n
VDDEXT
L3DATi(2) L3DATi(3)
L3DATi(4)L3DATi(5) L3DATi(6)
L3DATi(7)
L4ACKi L4CLKi
L4DATi(0) L4DATi(1) L4DATi(2)
L4DATi(3) L4DATi(4)
L4DATi(5) L4DATi(6) L4DATi(7)
L5ACKi
L5CLKi
L5DATi(0)
L5DATi(1)
L5DATi(2)
L5DATi(3)
L1DATi(1)
L1DATi(2)
L1DATi(3)L1DATi(4)
L1DATi(5)L1DATi(6)
L1DATi(7)
L2ACKi
L2CLKi
L2DATi(0)
L2DATi(1)
L2DATi(2)
L2DATi(3)
L2DATi(4)
L2DATi(5)
L2DATi(6)
L2DATi(7)
L3ACKi
L3CLKi
L3DATi(0)
L3DATi(1)
VDDEXT
GND
GND
GND
IRQ0_n
IRQ1_n
IRQ2_n
L0ACKi
L0CLKi
L0DATi(0)
L0DATi(1)
L0DATi(2)
L0DATi(3)
L0DATi(4)
L0DATi(5)
L0DATi(6)L0DATi(7)
L1ACKi
L1CLKi
L1DATi(0)
GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GND GNDGND GND GND
HBG_n
GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND
ChB_DMAR_n
GND
Sharc_EMU_n ChA_Rst_n
ChB_Rst_n
ChA_Empty
ChB_Empty
GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND
Data(17) Data(18)
Data(19)
Data(20)
Data(21) Data(22)
Data(23)
Data(24)
Data(25)
Data(26) Data(27)
Data(28)
Data(29) Data(30)
Data(31)
ChA_DMAR_n
Data(1)Data(2)
Data(3)
Data(4)Data(5)
Data(6)
Data(7)Data(8)
Data(9)Data(10)Data(11)Data(12)
Data(13)Data(14) Data(15)
Data(16)
Adr(4)
Adr(5)
Adr(6) Adr(7)
Adr(8)
Adr(9)
GND
AVDD
BMS_n
BReq_nBReq_n
BReq_nBReq_nBReq_nBReq_n
BRST
Sharc_Clk
GND
VDDEXT GND
GND
VDDEXT
Data(0)
Adr(0)
Adr(1)Adr(10)
Adr(11)
Adr(12)
Adr(13)
Adr(14)
Adr(15)
Adr(16)
Adr(17)
Adr(18)
Adr(19)
Adr(2)
Adr(20)
Adr(21)
Adr(3)
5 6
J
IRQ signal
Pull-ups in one
0
NIKHEF
C
1716
C
Rev
16
G
2 3 4 8 9
Proj.No:
14
L
Name
6
12 13 14 15
Date
a General_Rst_n, or when a reset is
Optional Test
Connector
Data Link to MROD-Out Sharc-B
Communication Link
12 13
The Sharc is reset when there is
Pull-ups in one
arc242 package
B
1
D
1
Communication Link
Communication Link
Communication Link
Sharc JTAG (and Emulator) Signals
2
asked via the MROD-Out FPGA
17 18
Size
Dim
11
G
H
I
J
GND
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
8 9 10
A
Page1098 SJ AMSTERDAM NEDERLAND
Proj:
4 5
Data Link to MROD-Out Sharc-A
F
Time
L
15
B
K
arc242 package
[email protected] Jansweijer
38405MROD-X
SHARC Auxiliary and Decoupling
MROD-In
of
7
Reset Signals
Also Boot Link
E
11
15
CLK
ADSP21160 VDDINT (40 pins) Decoupling Capacitors
ADSP21160 VDDEXT (43 pins) Decoupling Capacitors
SHARC Link Serie Termination
A
18
F
10
K
3
D
ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
I
TFS and RFS signal
7
E
c
H
2
3
43
420 x 297 mm
4 1 4 AA3
tonvr
1:46:57 pm
7 Feb 2006
V2 2
0
1
100n
0
GND
C418
22n
GND
7
GND
22n
C450
GND
C461
5
7
GND
1
GND
GND
C415
22n
22n
C404
0
GND
GND
R41233
33R401
33R402
R416
R4164K7
5
6
C455
22n
7
R4164K7
4K7
3
R40933
5
GND
GND
3
6
5
GND
0
R408
100n
C425
GND
GND
C452
22n
100n
C428
33
6
5
1
2
3
4
GND
0
1
2
2C408
680p
R40133
IC402
NC7SZ08
1
2
3
5
4
GND
33R403
22n
C417
4K7R417
680p
C413
22n
C448
GND
GND
C421
22n
4
5
GND
33
R41233
GND
R40433
33R408
R405
3
4
33R403
R40333
10
R422
C435
680p
6
4
GND
6
2
680p
C436
GND
GND
22n
C453
GND
680p
C434
GND
C433
680p
4
7
33R414
1
2
R40633
33R405
33
33R407
1
7
C437
680p
4K7R421
R405
R4174K7
GND
GND
C430
100n
C459
100n
GND
7
C463
47u
GND
C402
22n
R40933
GND
680p
C438
R41133
33R410
R40833
GND
R40633
33R406
R4184K7
4K7R419
GND
GND
100n
C462
4K7R416
R404
680p
C409
4
GND GND
C410
680p
33
R41533
GND
GND
C454
22n
R41433
GND GND
5
GND
R41033
33R411
R40333
733
R409
4K7R417
100n
C460
6
C445
22n
GND
GND
GND
C414
680p
33R411
4
680p
C407
33R410
R41133
1
R41033
C412
680p
GND
680p
C411
4
3
7
6
5
GND
GND
22n
C456
0
2
33R407 GND
33R407
4
33R414
6
680p
C442
R415
R41533
GND GND
5
6
6
6
0
33
R4204K7
47u
C464
1
GND
C457
100n
100n
C429
GND
3
2
33R402
0
22n
C422
R40133
22n
C420
R40633
33R402
4
33R413
C439
680p
2
2
R40233
R41333
C432
47u
GND
GND
R41233
33R412
0
R40133
33R413
22n
C416
680p
C405
GND
C406
680p
3
3
2
1
GND
GND
7
3
R40733
2
33R414
6
5
33R413
GND
7
1
0
C403
680p
C426
100n
GND
C401
100n
33R409
22n
C446 C447
22n
7
J14 20
100n
C458
33R404
3
J14 16
5
J14 18
J14 10
J14 12
J14 14
6
J14 7
J14 8
680p
C444
J14 3
J14 4
J14 5
J14
GND
J14 1
GND
J14 2
47u
C431
C441
680p
Fiducial401
4
5
680p
C440
7
1
GND
GNDGND
R40833
GND
1
C427
100n1
3
3
4
22n
C451
3
GND
22n
C423
GND
C424
22n
C419
22n
2
1
0
R40433
33R405
GND
J14 19
C449
22n
0
Fiducial402
2
J14 15
0
J14 17
J14 114
J14 13
Sharc_Rst_n
Rst_n
3V3
General_Rst_n
General_Rst_n
R41533
J14 9
C443
680p
L2DAT(7:0)
L1DAT(7:0)
L0DAT(7:0)
Sharc_Clk
SharcRd_n
SharcWr_n
MS3_n
MS2_n
MS1_n
MS0_n
Adr(21:0)
Data(31:0)
ChA_DMAR_n
ChA_Empty
L2ACKi
L2CLKi
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L2ACK50_OHM_SHARC_LINK
L2CLK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L1ACK
50_OHM_SHARC_LINK
L1CLK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L0ACK
50_OHM_SHARC_LINK
L0CLK
Sharc_EMU_n
TCK
TDO
TDI
TMS
Sharc_TDI
Sharc_TCK
Sharc_TMS
Sharc_TDO
TRST_n
L1DATi(7:0)
L1ACKi
L1CLKi
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L2DATi(7:0)
VDDINT
VDDEXT
VDDINT
AVDD
Sharc_EMU_n
50_OHM_SHARC_LINK
L5ACK50_OHM_SHARC_LINK
L5ACKi
L5CLK50_OHM_SHARC_LINK
L5CLKi
L5DAT(7:0)
TFS0
RFS0
TFS1
RFS1
BReq_n
BMS_n
HBG_n
BRST
IRQ0_n
IRQ1_n
IRQ2_n
Sharc_TRST_n
3V3
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L4ACKL4ACKi
50_OHM_SHARC_LINK
L4CLKL4CLKi
L4DAT(7:0)
L5DATi(7:0)50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L0DATi(7:0)
L0ACKi
L0CLKi
L3DATi(7:0)
L3ACKi L3ACK50_OHM_SHARC_LINK
L3CLKi L3CLK50_OHM_SHARC_LINK
L3DAT(7:0)
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L4DATi(7:0)
to be connected to golbal GROUND.
15 16
ET-Nikhef Amsterdam
7
4
3 15 16
GOL Frequency
5
J
Proj:
9
VCCINT Ramp rate 200 us min. and 50 ms max.
Input Channel, 250 mA per Channel
100MHz
1 2
D
12
B
Time between power-on VDDINT -> VDDEXT
FYSICA EN HOGE ENERGIE-FYSICA
100MHz
Fnom = 100 MHz
G
50MHz
7
Serie termination close to XTAL
Rocket-IO Inter-FPGA Link Frequency
100 MHz 16 bit = 50 MHz 32 bit
Date
Time
B
KRUISLAAN 409, 020-592 2000
All GND nets on the SHARC need
11
41
18
C
Parallel termination at the end of the line
= 200 MB/s
Serie termination close to XTAL
A
17
= 160 MB/s
E
50MHz
8
J
C
K
NIKHEFNATIONAAL INSTITUUT VOOR KERN-
K
= VCCAUX for the Xilinx Virtex-II Pro in the
FF
Page
Dim
17
10
85
I
= VDDEXT for the ADSP21160N
3
960 mA peak per ADSP21160N
G
H
I
of
The System Clock can be locked to a crystal or
= VCCINT for Xilinx Virtex-II Pro in the
100 MHz Phase Adjust
SHARC and Input Channel System Clock
10
2F(1:0)= "mm" => 0 tu
L
6
Rev
100 mA per ADSP21160N
6 9
12
11
A
Input Channels, 600 mA per Channel
c
Note ADSP21160N Power-On Sequence!
or to the LHC_Clk depending on the resistors placed.
80 MHz 16 bit = 40 MHz 32 bit
1F(1:0)= "mm" => 0 tu
Name
4F(1:0)= "00" => 100 Divide by 2 = 50 MHz
18
14
Proj.No:
14
44
420 x 297 mm
4 1 4 AA3
tonvr
1:47:20 pm
7 Feb 2006
V2 20
[email protected] Jansweijer
38405MROD-X
Power and Clocks
MROD-In
D
13
= VDDINT for the ADSP21160N
E
2
= -50 ms to +200 ms
H
LSize
1098 SJ AMSTERDAM NEDERLAND
13
3F(1:0)= "00" => 100 Divide by 2 = 50 MHz
GND
GND
J2F1_4
1
2
3
GND
GND
82
R431
GND
R434
130
GND
130
R436
IC403
S1703B_80
80MHz
1Ctrl
2
GND
OUT3
4
Vcc
GND
C467
100n
GND
22n
C465
33
GND
22n
C470
GND
R428
0E0
R425
82
R437
22n
C468
82
R435
GND
GND
R429
1M
GND
OUT3
4
Vcc
J2F0_4
1
2
3
22n
C472
R440
130
IC405
S1703B_50
50MHz
1Ctrl
2
16 18 252 8
GND
C471
22n
15
3Q114
4F06
74F1
4Q011
4Q110
FB17
FS3
1REF
TEST31
9
1F026
271F1
1Q024
1Q123
292F0
2F130
2Q020
2Q119
43F0
3F15
3Q0
GND
4K7
R427
CY7B9911V
IC406
Vccq Vccn
GND
MBRD835L
D401C473
22n
GND
130
R438
GND
GND
82
GND
C469
22n
130
R432
5V_to_1V5_?
1V55V
GND
R43982
R433
100MHz
S1703B_100
IC404
Ctrl1
GND
2
3OUT
Vcc
4
C476
100n
GND
C466
22n
1K0
R430
22n
C474
100n
C475
R424
33
33
R423GND
GND
Z50_NET_TYPE
Z50_NET_TYPE
Rocket_XClk_B
GND
33
R426
3V3
Z50_NET_TYPE
Sharc_Clk
VDDEXTPOWER_NET_TYPE
VDDINTPOWER_NET_TYPE
LHC_Clk
5V
2V5POWER_NET_TYPE
2V5
1V5POWER_NET_TYPE
GNDPOWER_NET_TYPE
Z50_NET_TYPE
GOL_XClk_B
GOL_XClk_AZ50_NET_TYPE
Rocket_XClk_A
3V3
Z50_NET_TYPE
ChA_Clkx2
Z50_NET_TYPE
ChB_Clkx2
Z50_NET_TYPE
ChA_Clk
Z50_NET_TYPE
ChB_Clk
1V9
3V3POWER_NET_TYPE
3V3
15 16 17
c ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
6
A
7 8
Dim
Page
2 3
of
15
A
B
C
G
H
I
G
B
C
10 11 12
D
13 144 52 3 9 10 11
Output Adjustable (1V5)
12
J
Low ESR
L
1
K
L
Rev
Size
Ceramic X7R
Ceramic X7R
=> Ramp rate = 6,6 ms
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Low ESR
Proj: Proj.No:
Reference C
Ceramic X7R
Input C
18
1V5 @ 2Amp
1 9 13 16 17 184 5
tonvr
1:38:24 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
5V -> 1V5 @ 2A
Power Supply
AVX
TPSD157K010R0100
Date
Time
Name
Css = 22 nF
H
I
E
F
14
K
D
E
F
J
6 7 8
NIKHEF
FBSEL = REF
270K
11
420 x 297 mm
4 1 4 AA3
22n
C481
R442
0E0
R443
R444
17K8
2%
2%48K7 R445
C479
2u2
C477150u
GND
10u
C478
R441
10
GND
GND
GND
C482
1u
GND GND
TOFF
7
12VCC
_SHDN1
GND
GND
470pC480
FBSEL
9
GND
IN1
2 4
IN216
LX1
LX214
3LX3
15PGND1
PGND213
REF
10
SS5
L401
6u8
IC407
MAX16446COMP
FB8
11
5V
1V5
GND
C483100u
of
D
G
I
3
KRUISLAAN 409, 020-592 2000
5
17
Name
7
13
2 9 17
14
c
Time
184
FF
G
H
14
E
8
A
Size
18
13
L
Date
I
B
C
A
B
9 10
1615
Page
11
C
H
K
Proj:
J
Proj.No:
J
E
7
L
1 2 8
D
K
4 5
NATIONAAL INSTITUUT VOOR KERN-
Rev
15 1612
NIKHEF1098 SJ AMSTERDAM NEDERLAND
1
6
ET-Nikhef Amsterdam
FYSICA EN HOGE ENERGIE-FYSICA
MROD-Out
MROD-Ins
MROD-X 38405
Peter Jansweijer [email protected]
3 V2
7 Feb 2006
1:25:06 pm
tonvr
A3 4 1 4 A
420 x 297 mm
1 19
6 10 11 123
Dim
VT1V8_MGT
Rocket_ChA_RXN
Rocket_ChA_RXP
Rocket_ChA_TXN
Rocket_ChA_TXP
Rocket_ChB_RXN
Rocket_ChB_RXP
Rocket_ChB_TXN
Rocket_ChB_TXP
Sharc_EMU_n
Sharc_Rst_n
Sharc_TCK
Sharc_TDI
Sharc_TDO
Sharc_TMS
Sharc_TRST_n
TTC_n(7:0)
L2ACK
L2CLK
L2DAT(7:0)
L3ACK
L3CLK
L3DAT(7:0)
L4ACK
L4CLK
L4DAT(7:0)
L5ACK
L5CLK
L5DAT(7:0)
LHC_Clk
MROD_In_ID0
MROD_In_ID1
PROG_B
ChB_Busy
ChB_Spare(4:0)
D(7:0)
DONE
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
General_Rst_n
INIT_B
L0ACK
L0CLK
L0DAT(7:0)
L1ACK
L1CLK
L1DAT(7:0)
Sharc_Rst_n
Sharc_TCK
Sharc_TDI
Sharc_TDO
Sharc_TMS
Sharc_TRST_n
TTC_n(7:0)
VT1V8_MGT
2
MROD_In2
1V9
2V5
3V3
5V
CCLK
ChA_Busy
ChA_Spare(4:0)
L5ACK
L5CLK
L5DAT(7:0)
LHC_Clk
MROD_In_ID0
MROD_In_ID1
PROG_B
Rocket_ChA_RXN
Rocket_ChA_RXP
Rocket_ChA_TXN
Rocket_ChA_TXP
Rocket_ChB_RXN
Rocket_ChB_RXP
Rocket_ChB_TXN
Rocket_ChB_TXP
Sharc_EMU_n
INIT_B
L0ACK
L0CLK
L0DAT(7:0)
L1ACK
L1CLK
L1DAT(7:0)
L2ACK
L2CLK
L2DAT(7:0)
L3ACK
L3CLK
L3DAT(7:0)
L4ACK
L4CLK
L4DAT(7:0)
1V9
2V5
3V3
5V
CCLK
ChA_Busy
ChA_Spare(4:0)
ChB_Busy
ChB_Spare(4:0)
D(7:0)
DONE
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
General_Rst_n
Rocket_ChA_TXN
Rocket_ChA_TXP
Rocket_ChB_RXN
Rocket_ChB_RXP
Rocket_ChB_TXN
Rocket_ChB_TXP
Sharc_EMU_n
Sharc_Rst_n
Sharc_TCK
Sharc_TDI
Sharc_TDO
Sharc_TMS
Sharc_TRST_n
TTC_n(7:0)
VT1V8_MGT
3
MROD_In3
L2DAT(7:0)
L3ACK
L3CLK
L3DAT(7:0)
L4ACK
L4CLK
L4DAT(7:0)
L5ACK
L5CLK
L5DAT(7:0)
LHC_Clk
MROD_In_ID0
MROD_In_ID1
PROG_B
Rocket_ChA_RXN
Rocket_ChA_RXP
D(7:0)
DONE
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
General_Rst_n
INIT_B
L0ACK
L0CLK
L0DAT(7:0)
L1ACK
L1CLK
L1DAT(7:0)
L2ACK
L2CLK
Sharc_TMS
Sharc_TRST_n
TTC_n(7:0)
VT1V8_MGT
4
MROD_In4
1V9
2V5
3V3
5V
CCLK
ChA_Busy
ChA_Spare(4:0)
ChB_Busy
ChB_Spare(4:0)
MROD_In_ID0
MROD_In_ID1
PROG_B
Rocket_ChA_RXN
Rocket_ChA_RXP
Rocket_ChA_TXN
Rocket_ChA_TXP
Rocket_ChB_RXN
Rocket_ChB_RXP
Rocket_ChB_TXN
Rocket_ChB_TXP
Sharc_EMU_n
Sharc_Rst_n
Sharc_TCK
Sharc_TDI
Sharc_TDO
L1ACK
L1CLK
L1DAT(7:0)
L2ACK
L2CLK
L2DAT(7:0)
L3ACK
L3CLK
L3DAT(7:0)
L4ACK
L4CLK
L4DAT(7:0)
L5ACK
L5CLK
L5DAT(7:0)
LHC_Clk
CCLK
ChA_Busy
ChA_Spare(4:0)
ChB_Busy
ChB_Spare(4:0)
D(7:0)
DONE
FPGA_TCK
FPGA_TDI
FPGA_TDO
FPGA_TMS
General_Rst_n
INIT_B
L0ACK
L0CLK
L0DAT(7:0)
MROD_In1
1
1V9
2V5
3V3
5V
76543210
76543210
GND GND GND
Sharc_TMS
Sharc_TRST_n
TTC_n(7:0)
VT1V8_MGT VT1V8_MGT VT1V8_MGT VT1V8_MGT
50_OHM_SHARC_LINK
E1_F5_ACK
50_OHM_SHARC_LINK
E1_F5_CLK
ROCKET_LVDS
TXP_1AROCKET_LVDS
RXN_1AROCKET_LVDS
RXP_1AROCKET_LVDS
TXN_1BROCKET_LVDS
TXP_1BROCKET_LVDS
RXN_1BROCKET_LVDS
RXP_1BROCKET_LVDS
Sharc_EMU_n
RstSharcC_n
Sharc_TCK
Sharc_TDOab
Z50_NET_TYPE
C2_F0_CLK50_OHM_SHARC_LINK
C2_F0_DAT(7:0)
C3_B1_ACK50_OHM_SHARC_LINK
C3_B1_CLK50_OHM_SHARC_LINK
C3_B1_DAT(7:0)
C4_A1_ACK50_OHM_SHARC_LINK
C4_A1_CLK50_OHM_SHARC_LINK
C4_A1_DAT(7:0)
C5_E0_ACK50_OHM_SHARC_LINK
C5_E0_CLK50_OHM_SHARC_LINK
C5_E0_DAT(7:0)
LHC_Clk1
MRI_PROG_B
TXN_1A
Spare_1B(4:0)
MRI_D(7:0)
MRI_DONE
FPGA_TCK
FPGA_TDI
Z50_NET_TYPE
FPGA_TMS
General_Rst_n
MRI_INIT_B
C0_D5_ACK50_OHM_SHARC_LINK
C0_D5_CLK50_OHM_SHARC_LINK
C0_D5_DAT(7:0)
C1_A0_ACK50_OHM_SHARC_LINK
C1_A0_CLK50_OHM_SHARC_LINK
C1_A0_DAT(7:0)
C2_F0_ACK50_OHM_SHARC_LINK
FPGA_TCK
MRI_DONE
MRI_D(7:0)
Spare_4B(4:0)
Busy_4B
Spare_4A(4:0)
Busy_4A
MRI_CCLK
2V5_MRI_34
1V9_MRI_341V9_MRI_12
2V5_MRI_12
3V3
5V
MRI_CCLK
Busy_1A
Spare_1A(4:0)
Busy_1B
ROCKET_LVDS
TXN_4A
MRI_PROG_B
LHC_Clk4
E1_F5_DAT(7:0)
E1_F5_CLK
E1_F5_ACK
F4_A4_DAT(7:0)50_OHM_SHARC_LINK
F4_A4_CLK50_OHM_SHARC_LINK
F4_A4_ACK
F3_B4_DAT(7:0)
F3_B4_CLK50_OHM_SHARC_LINK
F3_B4_ACK50_OHM_SHARC_LINK
C2_F0_DAT(7:0)
C2_F0_CLK
C2_F0_ACK
MRI_INIT_B
General_Rst_n
FPGA_TMS
FPGA_TDO4
FPGA_TDO3
TTC_n(7:0)
Sharc_TRST_n
Sharc_TMS
Sharc_TDO4
Sharc_TDO3
Sharc_TCK
RstSharcF_n
Sharc_EMU_n
RXP_4BROCKET_LVDS
RXN_4BROCKET_LVDS
TXP_4BROCKET_LVDS
TXN_4BROCKET_LVDS
ROCKET_LVDS
RXP_4AROCKET_LVDS
RXN_4A
ROCKET_LVDS
TXP_4A
50_OHM_SHARC_LINK
E3_B3_DAT(7:0)
E3_B3_CLK50_OHM_SHARC_LINK
E3_B3_ACK50_OHM_SHARC_LINK
E2_B5_DAT(7:0)
E2_B5_CLK50_OHM_SHARC_LINK
E2_B5_ACK50_OHM_SHARC_LINK
E1_F5_DAT(7:0)
C5_E0_DAT(7:0)
C5_E0_CLK
C5_E0_ACK
MRI_INIT_B
General_Rst_n
FPGA_TMS
FPGA_TCK
MRI_DONE
MRI_D(7:0)
Spare_3B(4:0)
Busy_3B
Spare_3A(4:0)
Busy_3A
MRI_CCLK
ROCKET_LVDS
TXP_3BROCKET_LVDS
TXN_3BROCKET_LVDS
RXP_3AROCKET_LVDS
RXN_3AROCKET_LVDS
TXP_3AROCKET_LVDS
TXN_3AROCKET_LVDS
MRI_PROG_B
LHC_Clk3
D0_E5_DAT(7:0)
D0_E5_CLK
D0_E5_ACK
E4_A3_DAT(7:0)
E4_A3_CLK50_OHM_SHARC_LINK
E4_A3_ACK
50_OHM_SHARC_LINK
D0_E5_DAT(7:0)
D0_E5_CLK
50_OHM_SHARC_LINK
D0_E5_ACK
50_OHM_SHARC_LINK
MRI_INIT_B
General_Rst_n
FPGA_TMS
FPGA_TCK
MRI_DONE
MRI_D(7:0)
Spare_2B(4:0)
Busy_2B
Spare_2A(4:0)
Busy_2A
MRI_CCLK
TTC_n(7:0)
Sharc_TRST_n
Sharc_TMS
Sharc_TCK
RstSharcE_n
Sharc_EMU_n
RXP_3BROCKET_LVDS
RXN_3B
LHC_Clk2
C0_D5_DAT(7:0)
C0_D5_CLK
C0_D5_ACK
D4_A2_DAT(7:0)
D4_A2_CLK
50_OHM_SHARC_LINK
D4_A2_ACK
50_OHM_SHARC_LINK
D3_B2_DAT(7:0)
D3_B2_CLK
50_OHM_SHARC_LINK
D3_B2_ACK
50_OHM_SHARC_LINK
D2_B0_DAT(7:0)50_OHM_SHARC_LINK
D2_B0_CLK50_OHM_SHARC_LINK
D2_B0_ACK
D1_A5_DAT(7:0)
D1_A5_CLK
50_OHM_SHARC_LINK
D1_A5_ACK
TTC_n(7:0)
Sharc_TRST_n
Sharc_TMS
Sharc_TCK
RstSharcD_n
Sharc_EMU_n
RXP_2BROCKET_LVDS
RXN_2BROCKET_LVDS
TXP_2BROCKET_LVDS
TXN_2BROCKET_LVDS
RXP_2AROCKET_LVDS
RXN_2AROCKET_LVDS
TXP_2AROCKET_LVDS
TXN_2AROCKET_LVDS
MRI_PROG_B
17 18
ID = "001"
NIKHEFc ET-Nikhef Amsterdam
A
Page of
Name
Size
Dim
7 184 8 10 11
K
L
B
C
H
I
B
C
3 4
J
SHARC A
G
D
E
F
K
L
81
VDDINT (1V9) 40 pins
Proj:
9 10 11
VDDEXT (3V3) 43 pins
GND 82 pins
NC 9 pins
SHARC Power pins:
162 12 13 14 15
3
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Booting Mode:
EBOOT = ’0’, LBOOT = ’0’, BMS_n = ’1’ (Input)
=> Host Port Booting
Clock Configuration:
CLK_CFG(3:0) = "0010"
=> Core / CLKIN Ration 2:1
1 2
A
15 16 176
Proj.No:
Rev
Date
Time
125 9 13 14
MROD-Out
SHARC-A
MROD-X 38405
Peter Jansweijer [email protected]
3 V2
7 Feb 2006
1:25:29 pm
tonvr
A3 4 1 4 A
420 x 297 mm
2 19
D
E
F
G
H
I
5
J
6 7
Y16 WRL_n
T10 VDDINT_T10 T11 VDDINT_T11 T12 VDDINT_T12 T13 VDDINT_T13 T14 VDDINT_T14 T15 VDDINT_T15T6 VDDINT_T6 T7 VDDINT_T7 T8 VDDINT_T8 T9 VDDINT_T9
Y15 WRH_n
VDDINT_K15K6 VDDINT_K6
L15 VDDINT_L15L6 VDDINT_L6
M15 VDDINT_M15M6 VDDINT_M6
N15 VDDINT_N15N6 VDDINT_N6
VDDINT_P15P15P6 VDDINT_P6
R6 VDDINT_R6
E8 VDDINT_E8 E9 VDDINT_E9
F15 VDDINT_F15F6 VDDINT_F6
G15 VDDINT_G15G6 VDDINT_G6
H15 VDDINT_H15VDDINT_H6H6
J15 VDDINT_J15J6 VDDINT_J6
K15
U8 VDDEXT_U8 U9 VDDEXT_U9
D13 VDDINT_D13D7 VDDINT_D7
E10 VDDINT_E10 E12 VDDINT_E12 E13 VDDINT_E13 E14 VDDINT_E14 E15 VDDINT_E15E6 VDDINT_E6 E7 VDDINT_E7
VDDEXT_T5
U10 VDDEXT_U10 VDDEXT_U11U11 U12 VDDEXT_U12 U13 VDDEXT_U13 U14 VDDEXT_U14 U15 VDDEXT_U15 U16 VDDEXT_U16U5 VDDEXT_U5 U6 VDDEXT_U6 U7 VDDEXT_U7
L5 VDDEXT_L5
M16 VDDEXT_M16M5 VDDEXT_M5
VDDEXT_N16N16N5 VDDEXT_N5
P16 VDDEXT_P16P5 VDDEXT_P5
R16 VDDEXT_R16R5 VDDEXT_R5
T16 VDDEXT_T16T5
F16 VDDEXT_F16F5 VDDEXT_F5
G16 VDDEXT_G16G5 VDDEXT_G5
H16 VDDEXT_H16H5 VDDEXT_H5
J16 VDDEXT_J16VDDEXT_J5J5
K16 VDDEXT_K16K5 VDDEXT_K5
L16 VDDEXT_L16
TMS
A8 TRST_n
D10 VDDEXT_D10 D11 VDDEXT_D11 D12 VDDEXT_D12 D14 VDDEXT_D14D6 VDDEXT_D6 D8 VDDEXT_D8 D9 VDDEXT_D9
E16 VDDEXT_E16E5 VDDEXT_E5
A10 RPBA
M18 SBTS_n
B8 TCK B18 TCLK0
C14 TCLK1
TDIA7
C9 TDO
D15 TFS0
A16 TFS1A13 TIMEXP
C8
N2 NC_N2
PAGEM17 M19 PA_n
A18 RCLK0
B16 RCLK1
W15 RDH_n
V14 RDL_n
L20 REDY
A9 RESET_n
B17 RFS0
A17 RFS1
MS1_n
W13 MS2_n
Y14 MS3_n
A14 NC_A14 A15 NC_A15
B13 NC_B13 NC_B14B14
C12 NC_C12 C13 NC_C13
M4 NC_M4
N1 NC_N1
V16 L5DAT(0)
W18 L5DAT(1)
V17 L5DAT(2)
W19 L5DAT(3)
V19 L5DAT(4)
W20 L5DAT(5)
V20 L5DAT(6)
U17 L5DAT(7)
W17 LBOOT
Y13 MS0_n
V12
T19 L4CLK
U18 L4DAT(0) L4DAT(1)U19 U20 L4DAT(2)
T17 L4DAT(3) L4DAT(4)T20
R17 L4DAT(5) R18 L4DAT(6) R19 L4DAT(7)
L5ACKV18
Y20 L5CLK
L3ACK
N20 L3CLK
R20 L3DAT(0)
P18 L3DAT(1)P17 L3DAT(2) P19 L3DAT(3)
N19 L3DAT(4)N17 L3DAT(5) N18 L3DAT(6)
M20 L3DAT(7)
T18 L4ACK
L1DAT(7)
H18 L2ACK
G20 L2CLK
J18 L2DAT(0)
H20 L2DAT(1)
J17 L2DAT(2)
H19 L2DAT(3)
G19 L2DAT(4)
H17 L2DAT(5)
G18 L2DAT(6)
F20 L2DAT(7)
P20
C17 L0DAT(7)
E19 L1ACK
D20 L1CLK
F19 L1DAT(0)
E20 L1DAT(1)
G17 L1DAT(2)
F18 L1DAT(3)L1DAT(4)F17
E18 L1DAT(5)E17 L1DAT(6)
D16
IRQ1_n
B10 IRQ2_n
C19 L0ACK
D17 L0CLK
C20 L0DAT(0)
D19 L0DAT(1)
B20 L0DAT(2)
D18 L0DAT(3)
A20 L0DAT(4)
B19 L0DAT(5)
C18 L0DAT(6)
GND_R14 R15 GND_R15R7 GND_R7 R8 GND_R8 R9 GND_R9
J19 HBG_n J20 HBR_n
ID0V10
W10 ID1
Y11 ID2
A11 IRQ0_n
C10
P12 GND_P12 P13 GND_P13 P14 GND_P14GND_P7P7 P8 GND_P8 P9 GND_P9
R10 GND_R10 R11 GND_R11 R12 GND_R12 R13 GND_R13 R14
M9
N10 GND_N10 N11 GND_N11 N12 GND_N12 N13 GND_N13 N14 GND_N14N7 GND_N7 GND_N8N8 N9 GND_N9
P10 GND_P10 P11 GND_P11
L7 GND_L7 L8 GND_L8 L9 GND_L9
M10 GND_M10 M11 GND_M11 M12 GND_M12 M13 GND_M13 M14 GND_M14M7 GND_M7 M8 GND_M8 GND_M9
GND_K12K12 K13 GND_K13 K14 GND_K14K7 GND_K7 K8 GND_K8 K9 GND_K9
L10 GND_L10 L11 GND_L11 L12 GND_L12 L13 GND_L13 L14 GND_L14
GND_H9
J10 GND_J10 J11 GND_J11 J12 GND_J12 J13 GND_J13 J14 GND_J14J7 GND_J7 J8 GND_J8 J9 GND_J9
K10 GND_K10 K11 GND_K11
G7 GND_G7 G8 GND_G8 G9 GND_G9
H10 GND_H10 H11 GND_H11 H12 GND_H12 H13 GND_H13 H14 GND_H14H7 GND_H7 H8 GND_H8 H9
F12 GND_F12 F13 GND_F13 F14 GND_F14F7 GND_F7 F8 GND_F8 GND_F9F9
G10 GND_G10 G11 GND_G11 G12 GND_G12 G13 GND_G13 G14 GND_G14
DT0
B15 DT1
Y19 EBOOT
B9 EMU_n B12 FLAG0
A12 FLAG1
C11 FLAG2
B11 FLAG3
E11 GND_E11
F10 GND_F10 F11 GND_F11
DATA(62)
DATA(63)T4
C5 DATA(7)
A4 DATA(8)
B4 DATA(9)
Y17 DMAG1_n
W16 DMAG2_n
Y18 DMAR1_n
V15 DMAR2_n
C16 DR0C15 DR1
A19
R1 DATA(53) R2 DATA(54)
P4 DATA(55)
T1 DATA(56)
R3 DATA(57)
T2 DATA(58) T3 DATA(59)
B5 DATA(6)
R4 DATA(60)
U1 DATA(61) U2
DATA(43)J1 DATA(44)
K3 DATA(45)K2 DATA(46) DATA(47)K4
N3 DATA(48)
P1 DATA(49)
C6 DATA(5)
P2 DATA(50)
N4 DATA(51)
P3 DATA(52)
DATA(34)F1
G2 DATA(35)
H4 DATA(36)H3 DATA(37)
G1 DATA(38)
H2 DATA(39)
A5 DATA(4)
H1 DATA(40)
J4 DATA(41)J3 DATA(42)J2
C1 DATA(24)
D2 DATA(25)
F4 DATA(26)F3 DATA(27)
D1 DATA(28)
DATA(29)E2
DATA(3)B6
E1 DATA(30)
G4 DATA(31)G3 DATA(32)
F2 DATA(33)
DATA(14)
B3 DATA(15)B2 DATA(16)
C3 DATA(17)C2 DATA(18)
D4 DATA(19)
A6 DATA(2)
DATA(20)D3
E4 DATA(21)
B1 DATA(22)
E3 DATA(23)
CLK_CFG_0
L2 CLK_CFG_1 L4 CLK_CFG_2
M2 CLK_CFG_3
V13 CS_n
B7 DATA(0)
C7 DATA(1)
A3 DATA(10)
C4 DATA(11)
D5 DATA(12)
A2 DATA(13)A1
L18 BR1_nL17 BR2_n
BR3_nK20K19 BR4_nK18 BR5_nK17 BR6_n
BRSTY12
W14 CIF_n
L1 CLKIN
M3 CLKOUT
K1
ADDR(30) Y10 ADDR(31)
V1 ADDR(4)
W1 ADDR(5)
ADDR(6)V2 V3 ADDR(7)
Y1 ADDR(8)
W2 ADDR(9)
L3 AGND
M1 AVDD
W12 BMS_n
Y6 ADDR(21)
V7 ADDR(22)
W7 ADDR(23)
ADDR(24)Y7
V8 ADDR(25)
W8 ADDR(26)
Y8 ADDR(27)
V9 ADDR(28)
W9 ADDR(29)
U3 ADDR(3)
Y9Y2 ADDR(11)
W3 ADDR(12)
Y3 ADDR(13)
V5 ADDR(14)
W4 ADDR(15)
Y4 ADDR(16)
W5 ADDR(17)
V6 ADDR(18)
Y5 ADDR(19)
U4 ADDR(2)
W6 ADDR(20)
SharcAdr(13)
SharcAdr(12)
SharcAdr(11)
SharcAdr(10) SharcAdr(1)
SharcAdr(0)
ACK
IC501
ADSP21160N
L19 ACK
W11 ADDR(0)
V11 ADDR(1)V4 ADDR(10)
SharcAdr(28)
SharcAdr(27)
SharcAdr(26)
SharcAdr(25)
SharcAdr(24)
SharcAdr(23)
SharcAdr(22)
SharcAdr(21)
SharcAdr(20)
SharcAdr(2)
SharcAdr(19)
SharcAdr(18)
SharcAdr(17)
SharcAdr(16)
SharcAdr(15)
SharcAdr(14)
BR4_n BR3_n
BR2_n BR1_n
BMSa_n
AVDDa
SharcAdr(9)
SharcAdr(8)
SharcAdr(7)SharcAdr(6)
SharcAdr(5)
SharcAdr(4)
SharcAdr(31)SharcAdr(30)
SharcAdr(3)
SharcAdr(29)
SharcD(20)
SharcD(2)
SharcD(19)
SharcD(17)
SharcD(15)
SharcD(12)
SharcD(11)
SharcD(10)
SharcD(1)
SharcD(0)
CSa_n
Sharc_Clk
CIF_n
BRST
BR6_n BR5_n
SharcD(40)
SharcD(4)
SharcD(39)
SharcD(38)
SharcD(37) SharcD(36)
SharcD(35)
SharcD(34) SharcD(33)
SharcD(32) SharcD(31)
SharcD(3)
SharcD(27) SharcD(26)
SharcD(23) SharcD(21)
SharcD(55)
SharcD(54)SharcD(53)
SharcD(52)
SharcD(51)
SharcD(50)
SharcD(5)
SharcD(49)
SharcD(48)
SharcD(47)SharcD(46) SharcD(45)
SharcD(44) SharcD(43) SharcD(42) SharcD(41)
DMAR2_n
DMAR1_n
DMAG2_n
DMAG1_n
SharcD(9)
SharcD(8)
SharcD(7)
SharcD(63)
SharcD(62)SharcD(61)
SharcD(60)
SharcD(6)
SharcD(59)SharcD(58)
SharcD(57)
SharcD(56)
L0DATa(4)
L0DATa(3) L0DATa(1)
L0DATa(0)
L0CLKa
L0ACKa
IRQ2a_n
IRQ1a_n
IRQ0a_n
HBR_nHBG_n
Flag3a
Flag2a
Flag1a
Flag0aSharc_EMU_n
L2DATa(0)
L2CLKa
L2ACKa
L1DATa(7)
L1DATa(6) L1DATa(5)
L1DATa(4) L1DATa(3)
L1DATa(2)
L1DATa(1)
L1DATa(0)
L1CLKa
L1ACKa
L0DATa(7) L0DATa(6)
L0DATa(5)
L3DATa(6)L3DATa(5) L3DATa(4)
L3DATa(3)L3DATa(2) L3DATa(1)
L3DATa(0)
L3CLKa
L3ACKa
L2DATa(7)
L2DATa(6)
L2DATa(5)
L2DATa(4)
L2DATa(3)
L2DATa(2)
L2DATa(1)
MS0_n
GND
L5DATa(7)
L5DATa(6)
L5DATa(5)
L5DATa(4)L5DATa(2)
L5DATa(1)
L5DATa(0) L5ACKa
L4DATa(6)L4DATa(5)
L4DATa(3)
L4DATa(0)
L4ACKa
L3DATa(7)
Sharc_TDOa
Sharc_TDI
Sharc_TCK
SBTS_n
RPBA RFS1a
RFS0a
RstSharcAB_n
Redy_a
RDL_n
RDH_n
PA_nPAGE
MS3_n
MS2_n
MS1_n
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINT
VDDINT VDDINT VDDINT VDDINT VDDINT VDDINTVDDINT VDDINT VDDINT
WRL_nWRH_n
VDDINT
VDDEXT
Sharc_TRST_n
Sharc_TMS
TFS1a
TFS0a
VDDEXT VDDEXT VDDEXT VDDEXT VDDEXTVDDEXT VDDEXT VDDEXT VDDEXT
VDDINTVDDINT
VDDINT VDDINT VDDINT VDDINT VDDINTVDDINT VDDINT VDDINT VDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDEXT VDDEXT VDDEXTVDDEXT VDDEXT VDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXT VDDEXT
GND GND GND
GND GND GND GND GND GNDGND GND GND
VDDEXT
GND
GND
L0DATa(2)
L4CLKa
L4DATa(1) L4DATa(2)
L4DATa(4)
L4DATa(7)
L5CLKa
L5DATa(3)
VDDEXT
GND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GND
GND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GND
GND
GND
VDDEXT GND
GND
SharcD(13)SharcD(14)
SharcD(16)
SharcD(18)
SharcD(22)
SharcD(24)
SharcD(25)SharcD(28)
SharcD(29)SharcD(30)
GND
GND
GND GND GND GND GND
c ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
9
Date
Name
Booting Mode:
C
D
E
F
13 17 18
A
B
14
B
G
C
A
H
I
E
D
K
SHARC B
GND 82 pins
NC 9 pins
F
G
H
I
J
K
L
ID = "010"
14 15 16 17 18
1
NIKHEF
4 5 6 7
Size
Proj: Proj.No:
Rev
8 9 10 11
Time
=> Host Port Booting
Clock Configuration:
12 13
CLK_CFG(3:0) = "0010"
4
EBOOT = ’0’, LBOOT = ’0’, BMS_n = ’1’ (Input)
=> Core / CLKIN Ration 2:1
5 62 3 7 8
Dim
Page of
15 16
193
420 x 297 mm
4 1 4 AA3
tonvr
1:25:46 pm
7 Feb 2006
V2 3
[email protected] Jansweijer
38405MROD-X
SHARC-B
MROD-Out
10 11 12
L
J
VDDINT (1V9) 40 pins
VDDEXT (3V3) 43 pins
SHARC Power pins:
1 2 3
WRL_nY16
VDDINT_T10T10 VDDINT_T11T11 VDDINT_T12T12 VDDINT_T13T13 VDDINT_T14T14 VDDINT_T15T15VDDINT_T6T6 VDDINT_T7T7 VDDINT_T8T8 VDDINT_T9T9
WRH_nY15
K15VDDINT_K6K6
VDDINT_L15L15VDDINT_L6L6
VDDINT_M15M15VDDINT_M6M6
VDDINT_N15N15VDDINT_N6N6
P15 VDDINT_P15VDDINT_P6P6
VDDINT_R6R6
VDDINT_E8E8 VDDINT_E9E9
VDDINT_F15F15VDDINT_F6F6
VDDINT_G15G15VDDINT_G6G6
VDDINT_H15H15H6 VDDINT_H6
VDDINT_J15J15VDDINT_J6J6
VDDINT_K15
VDDEXT_U8U8 VDDEXT_U9U9
VDDINT_D13D13VDDINT_D7D7
VDDINT_E10E10 VDDINT_E12E12 VDDINT_E13E13 VDDINT_E14E14 VDDINT_E15E15VDDINT_E6E6 VDDINT_E7E7
T5
VDDEXT_U10U10 U11 VDDEXT_U11 VDDEXT_U12U12 VDDEXT_U13U13 VDDEXT_U14U14 VDDEXT_U15U15 VDDEXT_U16U16VDDEXT_U5U5 VDDEXT_U6U6 VDDEXT_U7U7
VDDEXT_L5L5
VDDEXT_M16M16VDDEXT_M5M5
N16 VDDEXT_N16VDDEXT_N5N5
VDDEXT_P16P16VDDEXT_P5P5
VDDEXT_R16R16VDDEXT_R5R5
VDDEXT_T16T16VDDEXT_T5
F16VDDEXT_F5F5
VDDEXT_G16G16VDDEXT_G5G5
VDDEXT_H16H16VDDEXT_H5H5
VDDEXT_J16J16J5 VDDEXT_J5
VDDEXT_K16K16VDDEXT_K5K5
VDDEXT_L16L16
C8
TRST_nA8
VDDEXT_D10D10 VDDEXT_D11D11 VDDEXT_D12D12 VDDEXT_D14D14VDDEXT_D6D6 VDDEXT_D8D8 VDDEXT_D9D9
VDDEXT_E16E16VDDEXT_E5E5
VDDEXT_F16
RPBAA10
SBTS_nM18
TCKB8 TCLK0B18
TCLK1C14
A7 TDI
TDOC9
TFS0D15
TFS1A16TIMEXPA13
TMS
NC_N2N2
M17 PAGE PA_nM19
RCLK0A18
RCLK1B16
RDH_nW15
RDL_nV14
REDYL20
RESET_nA9
RFS0B17
RFS1A17
V12
MS2_nW13
MS3_nY14
NC_A14A14 NC_A15A15
NC_B13B13 B14 NC_B14
NC_C12C12 NC_C13C13
NC_M4M4
NC_N1N1
L5DAT(0)V16
L5DAT(1)W18
L5DAT(2)V17
L5DAT(3)W19
L5DAT(4)V19
L5DAT(5)W20
L5DAT(6)V20
L5DAT(7)U17
LBOOTW17
MS0_nY13
MS1_n
T19
L4DAT(0)U18 U19 L4DAT(1) L4DAT(2)U20
L4DAT(3)T17 T20 L4DAT(4)
L4DAT(5)R17 L4DAT(6)R18 L4DAT(7)R19
V18 L5ACK
L5CLKY20
P20
L3CLKN20
L3DAT(0)R20
L3DAT(1)P18L3DAT(2)P17 L3DAT(3)P19
L3DAT(4)N19L3DAT(5)N17 L3DAT(6)N18
L3DAT(7)M20
L4ACKT18 L4CLK
L2ACKH18
L2CLKG20
L2DAT(0)J18
L2DAT(1)H20
L2DAT(2)J17
L2DAT(3)H19
L2DAT(4)G19
L2DAT(5)H17
L2DAT(6)G18
L2DAT(7)F20
L3ACK
L0DAT(7)C17
L1ACKE19
L1CLKD20
L1DAT(0)F19
L1DAT(1)E20
L1DAT(2)G17
L1DAT(3)F18F17 L1DAT(4)
L1DAT(5)E18L1DAT(6)E17
L1DAT(7)D16
C10
IRQ2_nB10
L0ACKC19
L0CLKD17
L0DAT(0)C20
L0DAT(1)D19
L0DAT(2)B20
L0DAT(3)D18
L0DAT(4)A20
L0DAT(5)B19
L0DAT(6)C18
GND_R15R15GND_R7R7 GND_R8R8 GND_R9R9
HBG_nJ19 HBR_nJ20
V10 ID0
ID1W10
ID2Y11
IRQ0_nA11
IRQ1_n
GND_P12P12 GND_P13P13 GND_P14P14P7 GND_P7 GND_P8P8 GND_P9P9
GND_R10R10 GND_R11R11 GND_R12R12 GND_R13R13 GND_R14R14
GND_M9
GND_N10N10 GND_N11N11 GND_N12N12 GND_N13N13 GND_N14N14GND_N7N7 N8 GND_N8 GND_N9N9
GND_P10P10 GND_P11P11
GND_L7L7 GND_L8L8 GND_L9L9
GND_M10M10 GND_M11M11 GND_M12M12 GND_M13M13 GND_M14M14GND_M7M7 GND_M8M8 M9
GND_K12 GND_K13K13 GND_K14K14GND_K7K7 GND_K8K8 GND_K9K9
GND_L10L10 GND_L11L11 GND_L12L12 GND_L13L13 GND_L14L14
H9
GND_J10J10 GND_J11J11 GND_J12J12 GND_J13J13 GND_J14J14GND_J7J7 GND_J8J8 GND_J9J9
GND_K10K10 GND_K11K11 K12
GND_G7G7 GND_G8G8 GND_G9G9
GND_H10H10 GND_H11H11 GND_H12H12 GND_H13H13 GND_H14H14GND_H7H7 GND_H8H8 GND_H9
F12 GND_F13F13 GND_F14F14GND_F7F7 GND_F8F8 F9 GND_F9
GND_G10G10 GND_G11G11 GND_G12G12 GND_G13G13 GND_G14G14
A19
DT1B15
EBOOTY19
EMU_nB9 FLAG0B12
FLAG1A12
FLAG2C11
FLAG3B11
GND_E11E11
GND_F10F10 GND_F11F11 GND_F12
T4 DATA(63)
DATA(7)C5
DATA(8)A4
DATA(9)B4
DMAG1_nY17
DMAG2_nW16
DMAR1_nY18
DMAR2_nV15
DR0C16DR1C15
DT0
DATA(53)R1 DATA(54)R2
DATA(55)P4
DATA(56)T1
DATA(57)R3
DATA(58)T2 DATA(59)T3
DATA(6)B5
DATA(60)R4
DATA(61)U1 DATA(62)U2
J2DATA(44)J1
DATA(45)K3DATA(46)K2 K4 DATA(47)
DATA(48)N3
DATA(49)P1
DATA(5)C6
DATA(50)P2
DATA(51)N4
DATA(52)P3
F1 DATA(34)
DATA(35)G2
DATA(36)H4DATA(37)H3
DATA(38)G1
DATA(39)H2
DATA(4)A5
DATA(40)H1
DATA(41)J4DATA(42)J3DATA(43)
DATA(24)C1
DATA(25)D2
DATA(26)F4DATA(27)F3
DATA(28)D1
E2 DATA(29)
B6 DATA(3)
DATA(30)E1
DATA(31)G4DATA(32)G3
DATA(33)F2
A1
DATA(15)B3DATA(16)B2
DATA(17)C3DATA(18)C2
DATA(19)D4
DATA(2)A6
D3 DATA(20)
DATA(21)E4
DATA(22)B1
DATA(23)E3
CLK_CFG_1L2 CLK_CFG_2L4
CLK_CFG_3M2
CS_nV13
DATA(0)B7
DATA(1)C7
DATA(10)A3
DATA(11)C4
DATA(12)D5
DATA(13)A2DATA(14)
BR1_nL18BR2_nL17
K20 BR3_nBR4_nK19BR5_nK18BR6_nK17
Y12 BRST
CIF_nW14
CLKINL1
CLKOUTM3
CLK_CFG_0K1
Y9 ADDR(31)Y10
ADDR(4)V1
ADDR(5)W1
V2 ADDR(6) ADDR(7)V3
ADDR(8)Y1
ADDR(9)W2
AGNDL3
AVDDM1
BMS_nW12
ADDR(21)Y6
ADDR(22)V7
ADDR(23)W7
Y7 ADDR(24)
ADDR(25)V8
ADDR(26)W8
ADDR(27)Y8
ADDR(28)V9
ADDR(29)W9
ADDR(3)U3
ADDR(30)ADDR(11)Y2
ADDR(12)W3
ADDR(13)Y3
ADDR(14)V5
ADDR(15)W4
ADDR(16)Y4
ADDR(17)W5
ADDR(18)V6
ADDR(19)Y5
ADDR(2)U4
ADDR(20)W6
VDDINT VDDINT VDDINT VDDINTVDDINT VDDINT VDDINT VDDINT
WRH_n WRL_n
ADSP21160N
IC502
ACKL19
ADDR(0)W11
ADDR(1)V11ADDR(10)V4
VDDINTVDDINT
VDDINT VDDINT VDDINT VDDINT VDDINTVDDINT VDDINT VDDINT VDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINTVDDINT
VDDINT
VDDINT VDDINT
VDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXTVDDEXT VDDEXT VDDEXT VDDEXT VDDEXT
RFS1bRPBA
SBTS_n
Sharc_TCK
Sharc_TDOa
Sharc_TDOb
TFS0b
TFS1b
Sharc_TMS
Sharc_TRST_n
VDDEXT VDDEXT VDDEXT VDDEXTVDDEXT VDDEXT VDDEXT
VDDEXTVDDEXT
VDDEXTVDDEXT
VDDEXT
L5DATb(4)
L5DATb(5)
L5DATb(6)
L5DATb(7)
GND
MS0_n
MS1_n
MS2_n
MS3_n
PAGE PA_n
RDH_n
RDL_n
Redy_b
RstSharcAB_n
RFS0b
L4ACKb L4CLKb
L4DATb(0) L4DATb(1) L4DATb(2)
L4DATb(3) L4DATb(4)
L4DATb(5) L4DATb(6) L4DATb(7)
L5ACKb
L5CLKb
L5DATb(0)
L5DATb(1)
L5DATb(2)
L5DATb(3)
L2DATb(2)
L2DATb(3)
L2DATb(4)
L2DATb(5)
L2DATb(6)
L2DATb(7)
L3ACKb
L3CLKb
L3DATb(0)
L3DATb(1)L3DATb(2) L3DATb(3)
L3DATb(4)L3DATb(5) L3DATb(6)
L3DATb(7)
L0DATb(6)L0DATb(7)
L1ACKb
L1CLKb
L1DATb(0)
L1DATb(1)
L1DATb(2)
L1DATb(3)L1DATb(4)
L1DATb(5)L1DATb(6)
L1DATb(7)
L2ACKb
L2CLKb
L2DATb(0)
L2DATb(1)
GNDGND GND GND
HBG_n HBR_n
GND
VDDEXT
GND
IRQ0b_n
IRQ1b_n
IRQ2b_n
L0ACKb
L0CLKb
L0DATb(0)
L0DATb(1)
L0DATb(2)
L0DATb(3)
L0DATb(4)
L0DATb(5)
GND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GND
GND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GND
DMAG2_n
DMAR1_n
DMAR2_n
GND
Sharc_EMU_n Flag0b
Flag1b
Flag2b
Flag3b
GND
GND GND GND GND GNDGND GND GND
GND GND GND GND GND
SharcD(53) SharcD(54)
SharcD(55)
SharcD(56)
SharcD(57)
SharcD(58) SharcD(59)
SharcD(6)
SharcD(60)
SharcD(61) SharcD(62)
SharcD(63)
SharcD(7)
SharcD(8)
SharcD(9)
DMAG1_n
SharcD(39)
SharcD(4)
SharcD(40)
SharcD(41)SharcD(42)SharcD(43)SharcD(44)
SharcD(45)SharcD(46) SharcD(47)
SharcD(48)
SharcD(49)
SharcD(5)
SharcD(50)
SharcD(51)
SharcD(52)
SharcD(24)
SharcD(25)
SharcD(26)SharcD(27)
SharcD(28)
SharcD(29)
SharcD(3)
SharcD(30)
SharcD(31)SharcD(32)
SharcD(33)SharcD(34)
SharcD(35)
SharcD(36)SharcD(37)
SharcD(38)
SharcD(1)
SharcD(10)
SharcD(11)
SharcD(12)
SharcD(13)SharcD(14)
SharcD(15)SharcD(16)
SharcD(17)SharcD(18)
SharcD(19)
SharcD(2)
SharcD(20)
SharcD(21)
SharcD(22)
SharcD(23)
SharcAdr(9)
GND
AVDDb
BMSb_n
BR1_nBR2_n
BR3_nBR4_nBR5_nBR6_n
BRST
CIF_n
Sharc_Clk
GND
VDDEXT GND
GND
CSb_n
SharcD(0)
SharcAdr(22)
SharcAdr(23)
SharcAdr(24)
SharcAdr(25)
SharcAdr(26)
SharcAdr(27)
SharcAdr(28)
SharcAdr(29)
SharcAdr(3)
SharcAdr(30) SharcAdr(31)
SharcAdr(4)
SharcAdr(5)
SharcAdr(6) SharcAdr(7)
SharcAdr(8)
ACK
SharcAdr(0)
SharcAdr(1)SharcAdr(10)
SharcAdr(11)
SharcAdr(12)
SharcAdr(13)
SharcAdr(14)
SharcAdr(15)
SharcAdr(16)
SharcAdr(17)
SharcAdr(18)
SharcAdr(19)
SharcAdr(2)
SharcAdr(20)
SharcAdr(21)
K
Time
Name
Size
I
G
REDY needs a Pull-Up (can be open drain).
12 13
Both Sharcs are reset when there is
TCK
1
Note. Parallel Termination can be placed
when using the EZ-ICE
NIKHEFc
arc242 package
IRQa signal
Pull-ups in one
arc242 package
IRQb signal
BR(6:3)_n signal
14
Dim
Page of
15
arc242 package
are common to SHARC A & B
depending on the resistor configuration.
6
Serie termination is added
2 3 4
1098 SJ AMSTERDAM NEDERLAND
TMS
EMU_n
ET-Nikhef Amsterdam
Select either Sharc_TDO3 or 4 depending on
wether SharcF (MROD_In4) is placed on the board.
MROD_In4_Present = ’0’ => SharcF is absent.
wether SharcB is placed on the board.
TRST_n
GND
TDI
in VME64x CSR space.
PAGE and PA_n are common to SHARC A & B
No need for Pull-Ups.
Note that BR2_n and BR1_n pull-ups can be installed
E
P_ENA
because Sharc_TDO might be
a long traces. Place close
to the buffers and buffers
close to each other.
Rev
VCC
13
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
F
KRUISLAAN 409, 020-592 2000
H
F
G
H
Date
select is set to "Fixed Priority"
Rotating Priority Bus Arbitration
J
A
B
asked via the bit Set/Clr register
I
J
K
16
Note that pin 2 (EMU_n)
and pin 9 (TRST_n) are
SharcB_Present = ’0’ => SharcB is absent.
SharcB_Present = ’1’ => SharcB is present.
by default (SHARC A has priority).
Pull-ups in one
Pull-ups in one
TFSa and RFSa signal
4
arc242 package
Serie termination is added because
Sharc_TDI might be a long trace.
Place close to the driving buffer.
Parallel termination for Sharc_TCK/TMS.
Place termination at the end of the line.REDY needs a Pull-Up (can be open drain).
HBG_n is always driven by the Bus Master
3
L
7 8
GND
MS0_n .. MS3_n, RDH_n, RDL_n, WRH_n and WRL_n
are common to SHARC A & B and have internal Pull-Ups
No need for Pull-Ups.MROD_In4_Present = ’1’ => SharcF is present.
Sharc_TDO
Select either Sharc_TDOa or b depending on
D
HBR_n and HBG_n are common to SHARC A & B
ACK, SBTS_n and CIF_n pins
5
Place R21 (0 ohm)
Check the pinout of J21!
a General_Rst_n, or when a reset is
BR_n pins are common to SHARC A & B
15 16 18
DMAG1_n and DMAG2_n are common to SHARC A & B
No need for Pull-Ups, they are driven by the Bus Master.
17
A
when only SHARC A is mounted on the board.
RDL_n and WRL_n are tri-state
during a HOST-bus access.
E
B
L
145 6
C
17
DMAR1_n and DMAR2_n are common to SHARC A & B
C
D
TRST_n is (Pulsed) Low after Power-Up.
The SHARC Datasheet explicitly states that
HBR_n is always driven by the FPGA.
ByteBlaster
not connected in the
The are always driven by the FPGA.
No need for Pull-Ups.
12
Pull-ups in one
1 2
11
TDO
arc242 package
9 10 11
TFSb and RFSb signal
Pull-ups in one
Proj: Proj.No:
Unused BR_n lines need Pull_Up (see datasheet)
MROD-Out
SHARC JTAG and Auxiliary connections
MROD-X 38405
Peter Jansweijer [email protected]
3 V2
7 Feb 2006
1:26:10 pm
tonvr
A3 4 1 4 A
420 x 297 mm
4 19
7 8 9 10
BRST is common to SHARC A & B
18
GND
U21
22n
1
5
4
GND
22n
U20
1M
R526
IC509
NC7SZ1262
3
C55
GND
C54
100n
0E0
R525
R51982
R515
130
100n
R78133
22n
U22
GND
R5434K7
GND
U25
22n
2
3
1
5
4
R508
4K7
NC7SZ126
IC511
2
3
1
5
4
IC506
NC7SZ126R532
4K7
4K7R532
IC508
NC7SZ1262
3
1
5
4
R528
10
3
5
4
1
GND
R51633
4K7R532
GND
NC7SZ125
IC503
2
R511
4K7
GND
GND
1M
R518
5
4
100p
C503
R510
4K7
C504
100p
NC7SZ126
IC507
2
3
1
0E0
R517
GND
33
R506
4K7R540
4K7R543
GND
10
R527
82
R512
4K7R547
680p
C510
R5464K7
R5464K7
R5474K7
R538
GND
4K7R531
4K7R536
R5374K7
4K7
R524
1M
GND
R5354K7
R51482
R523
0E0
22n
U16
IC504
NC7SZ126
2
3
1
5
4
R509
4K7
GND
4K7R529
R5294K7
7
0E0
R545
R5304K7
33
GND
J21
R50333
33R504
R505
J21 4
J21 3
R501
4E7
C502
100p
GND
C501
100p
GND
22n
U24
R507
33
GND
R521
0E0
R520
130
GND
J21 1
130
R513
22n
U18
GND
U19
22n
GND
GND
IC512
NC7SZ08
1
2
3
5
4
R542
GND
GND
GND
R5411M
GND
1M
R5294K7
100n
C508
GND
R5334K7
R5324K7
GND
4K7R534
GND
J21 2
J21 5
GND
GND
GND
4K7R546
2
3
5
4
1
GND
U23
22n
Fiducial501
GND
Fiducial503
IC510
NC7SZ125
GND
GND
22n
C509
GND
3
1
5
4
4K7R547
R522 4K7
C505
100n
NC7SZ126
IC505
2
GND
1M
R544
J21 6
J21 10
GND
U17
22n
J21 8
C506
22n
C507
680p
Fiducial502
Fiducial504
J21 9
4K7R529
33R502
4K7R543
R5394K7
GND
GND
R5434K7
3V3
SharcD(63:32)
Sharc_TMSZ50_NET_TYPE
3V3
Sharc_TRST_nZ50_NET_TYPE
Z50_NET_TYPE
Sharc_TDOabZ50_NET_TYPE
Sharc_TDOa
Sharc_TDOb
3V3
3V3
3V3
MROD_In4_Present
3V3
3V3
SharcB_Present
3V3
3V3
SharcB_Present
3V3
Sharc_TDIZ50_NET_TYPE
3V3
VDDEXT
VDDEXT
Sharc_TCKZ50_NET_TYPE
Sharc_TDO3
Sharc_TDO4
MROD_In4_Present
3V3
3V3
Redy_a
SBTS_n
CIF_n
BR2_n
BR1_n
RDL_n
WRL_n
TFS1b
RFS1b
TFS0b
RFS0b
BMSa_n
ACK
Redy_b
RstSharcAB_n
IRQ0b_n
IRQ1b_n
VDDINT
AVDDb
TFS1a
RFS1a
TFS0a
RFS0a
BMSb_n
BRST
BR6_n
BR5_n
BR4_n
BR3_n
Sharc_EMU_n
General_Rst_n
RstSharc_n
RPBA
VDDEXT
IRQ2a_n
IRQ0a_n
IRQ1a_n
VME_D(31:0)
SharcRd_nRDH_n
WRH_n SharcWr_n
VDDINT
AVDDa
IRQ2b_n
10
D
K
I
SHARC-B
SHARC-B
I
signals and the BUSY LEDs are disabled!
G
H
Proj:
NIKHEFc
86 7
Name
ADSP21160 VDDINT (40 pins) Decoupling Capacitors
ADSP21160 VDDEXT (43 pins) Decoupling Capacitors
ADSP21160 VDDINT (40 pins) Decoupling Capacitors
18
1
3 4
of
Time
Busy_2A
Sharc Flag pin is an Input by default after Power-Up.
This means the LEDs light up during and after Power-Up.
2
Dim
Page
11 12 13 14
FLAG1b
FLAG2b
3
15 16 17
FLAG2a
14
A
114 5 6 7 8
E
F
B
If MROD_In4 is absent then the BUSY
Busy_1B
Busy_1A
ADSP21160 VDDEXT (43 pins) Decoupling Capacitors
MROD-In 1 Busy
MROD-In 2 Busy
9
L
A
C
D
E
18
SHARC-A
SHARC-A
K
L
MROD-In 4 Busy
Rev
Date
KRUISLAAN 409, 020-592 2000
JJ
F
G
H
Proj.No:
FYSICA EN HOGE ENERGIE-FYSICA
1 2
Busy_3B
Busy_3A
Busy_4B
9 105
Size
FLAG3b
FLAG0b
3 V2
7 Feb 2006
1:26:41 pm
tonvr
A3 4 1 4 A
420 x 297 mm
5 19
Busy_2B
Busy_4A
12 13
FLAG3a
C
MROD-In 3 Busy
FLAG1a
15 16 17
BFLAG0a
ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
1098 SJ AMSTERDAM NEDERLAND
k_y
a_y
Fr_LED_Ye
D4Ak_y
a_y
MROD-Out
SHARC Power Supply Decoupling and LEDs
MROD-X 38405
Peter Jansweijer
GND
GND
GND
GND
D3B
Fr_LED_Ye
R552
4K7
GND
C565
680p
4K7
R556
R554
4K7
a_y
D2B
Fr_LED_Ye
k_y
a_y
Fr_LED_Ye
D3Ak_y
a_y
4K7
R550
R558
R560
4K7
Fr_LED_Ye
D2Ak_y
GND
GND
GND
C516
22n
4K7
1
2
3
5
4
R562
4K7
D4B
Fr_LED_Ye
k_y
a_y
GND
IC521
NC7SZ00
GND
C626
680p
GND
C633
22n
k_y
a_y
100n
C580
GND
C532
680p
GND
680p
C535
GND
GNDD1B
Fr_LED_Ye
NC7SZ00
IC526
1
2
3
5
4
C534
680p
680p
C619
C569
22n
GND
680p
C531
GND
680p
C615
GND
GND
22n
C519
GND
GND
C616
680p
C555
680p
GND
22n
C570
GND
2
3
5
4
GND
GND
GND
IC524
NC7SZ00
1
2
3
5
4
NC7SZ00
IC516
1
GND
100n
C550
GND
GND
SMD_LED_Red
D505
C522
22n
GND
C549
100n
GND
IC520
NC7SZ00
1
2
3
5
4
22n
C514
GND
GND
SMD_LED_Green
D504
3
5
4
GND
22n
C572
GND
GND
22n
C526
NC7SZ00
IC519
1
2
NC7SZ00
IC523
1
2
3
5
4
D507
SMD_LED_Green
C552
100n
680p
C592
GND
GND
GND
22n
C544
GND
GND
SMD_LED_Green
D508
C518
22n
GND
C543
22n
C573
GND
NC7SZ00
IC528
1
2
3
5
4
C624
680p
680p
C566
GND
22n
C646
47u
GND
GND
22n
C542
100n
C641
C523
22n
3
5
4
GND
22n
C515
4K7
R548
GND
680p
C527
IC527
NC7SZ00
1
2
GND
22n
C578
GND
GND
C579
100n
GND
C644
100n
GND
C587
680p
GND
GND
C540
22n
C611
100n
C576
22n
GND
C577
22n
GND
C607
100n
C530
680p
GND
GND
C638
22n
GND
22n
C637
GND
680p
C564
GND
22n
C601
GND
GND
680p
C590
GND
C599
22n
GND
680p
C560
GND
C563
680p
22n
C631
GND
C632
22n
680p
C623
GND
680p
C556
GND
4
GND
47u
C645
GND
SMD_LED_Red
D501
GND
GND
IC515
NC7SZ00
1
2
3
5
22n
C603
C610
100n
C604
22n
22n
C538
GND
GND
100n
C609
100n
C608
GND
GND
GND
GND
680p
C529
GND
GND
GND
C613
47u
GND
C591
680p
GND
R5721K0
22n
C575
D506
SMD_LED_Red
22n
C517
GND
22n
C524
GND
IC522
NC7SZ00
1
2
3
5
4
680p
C625
GND GND
47u
C586
GND
100n
C639
C561
680p
GND
180
C630
22n
C640
100n
D502
SMD_LED_Red
C583
100n
R569
GND
GND
R551
180
C598
22n
5
4
GND
D503
SMD_LED_Green
180
R568
k_y
a_y
C525
22n
NC7SZ00
IC514
1
2
3
680p
C533
GND GND
GND
Fr_LED_Ye
D1A
C547
GND
GND
GND
22n
C521
GND
C528
680p
GND
100n
22n
C629
GND
100n
C551
C602
22n
GND
22n
C627
GND
C620
680p
GND
C513
22n
GND
C628
22n
GND
680p
C558
GND
1K0
R573
GND
GND
GND
C554
47u
GND
C642
100n
GND
GND
680p
C562
GND
22n
C512
180
R570
R559
180
180
R571
180
R561
R563
180
4
22n
C539
GND
47u
C553
3
5
4
NC7SZ00
IC517
1
2
3
5
1
2
3
5
4
NC7SZ00
IC513
1
2
GND
GND
GND
C520
22n
IC525
NC7SZ00
GND
GND
R549
180
GND
1
2
3
5
4
GND
C559
680p
180
R557
C511
22n
IC518
NC7SZ00
180
R566
R567
180
R565
180
180
R553
R555
180
GND
C546
22n
180
R564
GND
22n
C597
GND
680p
C596
GND
C593
680p
GND
680p
C588
GND
100n
C582
GND
C585
47u
GND
C571
22n
GND
C567
22n
GND
C541
22n
GND
22n
C600
GND
22n
C634
GND
C536
680p
GND
100n
C612
GND
22n
C545
GND
C548
100n
GND
22n
C606
GND
C622
680p
GND
C581
100n
22n
C568
100n
C643
680p
C621C618
680p
C557
680p
680p
C617
GND
GND
47u
C614
GND
GND
C537
22n
GND
C605
22n
GND
680p
C594
GND
C595
680p
GND
C574
22n
GND
100n
C584
GND
C635
22n
GND
22n
C636
Busy_3A
Busy_3B
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
Busy_4A
Busy_4B
C589
680p
FLAG2a
FLAG3a
FLAG0b
FLAG1b
FLAG2b
FLAG3b
Busy_1A
Busy_1B
Busy_2A
Busy_2B
FLAG1a
FLAG0a
VDDEXT
VDDINT
VDDINT
VDDEXT
17
17 18
1 2
D
12 13 14
Page of
Also BOOT Link SHARC D
Datalink SHARC E
Also BOOT Link SHARC E
Datalink SHARC F
Also BOOT Link SHARC F
SHARC B Link Serie Termination
Communication Link
H
Datalink SHARC C
Datalink SHARC D
Proj.No:
9 10 11 12 13 14
Communication Link
7
L
1 8
4 5
c ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Datalink SHARC D
Datalink SHARC C
Communication Link
4 5 6
Datalink SHARC E
Datalink SHARC F
NIKHEF Dim
SHARC A Link Serie Termination
16
Also BOOT Link SHARC C
18
A
B
C
Time
Name
Size
6 7
C
158 9 10 11
3
I
A
B
J
K
D
E
F
G
J
K
L
H
I
Proj:
MROD-Out
Sharc AB Link termination
MROD-X 38405
Peter Jansweijer [email protected]
3 V2
7 Feb 2006
1:26:56 pm
tonvr
A3 4 1 4 A
420 x 297 mm
6 19
2
Communication Link
15 16
E
F
G
Date
3
Rev
1
2
3
4
7
6
5
0
R574
33R575
R57433
33R575
R57533
33
33
33R575
R57933
R57433
33R576
R5761
2
3
4
5
6
7
0
1
2
3
4
0
R576
7
6
5
R57933
R57633
33
R57933
33R579
33R577
R57833
33R578
733
R574
R57733
0
1
2
3
4
5
6
0
1
2
3
4
R58033
7
6
5
33R582
33R582
R58433
33R582
R58233
R58333
33R583
6
7 R58133
33R584
4
0
1
2
3
4
5
0
1
2
3
33R587
7
6
533
R583
R58333
R58533
33R585
R58433
33
33R587
R58733
4
5
6
733
R584
R585
3
4
0
1
2
3
5
0
1
2
R586
R58833
7
6
R58833
33R587
33
R586
R58833
33R588
33R586
R58633
33
4
5
6
7 R58533
4
0
1
2
3
5
0
1
2
3
33R581
7
6
33R580
R57833
R57833
33R581
R57733
R58033
33R581
R58033
4
5
6
733
R577
3
4
0
1
2
3
6
5
0
1
2
33R591
R59133
7
R59433
33R594
R593
R59433
33R593
33R592
R59233
33
3
4
5
6
7 R59433
2
3
4
0
1
2
7
6
5
0
1
R59733
33R597
33
33R599
R59533
R59933
33R597
R597
R596
R59833
33R599
2
3
4
5
6
733
1
2
3
4
0
1
7
6
5
0
R599
33R600
R59833
33R598
R60033
33
33R601
R60033
3
4
5
33R600
R60133
2
3
4
0
1
2
7
6
5
0
1
R59033
33R589
33
33R590
R58933
R59033
33R589
R590
R589
R59133
33R591
2
3
4
5
6
733
1
2
3
4
0
1
7
6
5
0
R593
33R593
R59633
33R592
R59533
33
33
33R595
R59633
R59233
33R595
R5961
2
3
4
5
6
7
2
3
4
R60333
0
1
2
3
4
0
1
7
6
5
0
33
R59833
33R602
R60133
33R602
R601
6
33R602
7
33R602
R60333
6
7
5
50_OHM_SHARC_LINK
D2_B0_CLK50_OHM_SHARC_LINK50_OHM_SHARC_LINK
D2_B0_ACK
R60333
R60333
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
E4_A3_CLK50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
F4_A4_ACK50_OHM_SHARC_LINK
D1_A5_ACK50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
E3_B3_CLK50_OHM_SHARC_LINK50_OHM_SHARC_LINK
E3_B3_ACK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
E2_B5_CLK50_OHM_SHARC_LINK50_OHM_SHARC_LINK
E2_B5_ACK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
E3_B3_DAT(7:0)
C1_A0_ACK50_OHM_SHARC_LINK50_OHM_SHARC_LINK
C1_A0_CLK50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
C4_A1_CLK
50_OHM_SHARC_LINK
D4_A2_ACK50_OHM_SHARC_LINK
E4_A3_ACK
L2DATb(7:0)
L2ACKb
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
D3_B2_CLKL2CLKb50_OHM_SHARC_LINK50_OHM_SHARC_LINK
D3_B2_ACK
D3_B2_DAT(7:0)
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
L0DATb(7:0)
L0ACKb
L0CLKb
D2_B0_DAT(7:0)
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
L5ACKb
L5CLKb
E2_B5_DAT(7:0)
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
F3_B4_CLK
L4ACKb50_OHM_SHARC_LINK50_OHM_SHARC_LINK
F3_B4_ACK
L4CLKb
F3_B4_DAT(7:0)
L5DATb(7:0)50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
L4DATb(7:0)50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L3DATb(7:0)
L3ACKb
L3CLKb
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
C3_B1_CLKL1CLKb50_OHM_SHARC_LINK50_OHM_SHARC_LINK
C3_B1_ACK
C3_B1_DAT(7:0)
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
L1DATb(7:0)
L1ACKb
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
L2DATa(7:0)
L2ACKa
L2CLKa D4_A2_CLK50_OHM_SHARC_LINK50_OHM_SHARC_LINK
D4_A2_DAT(7:0)
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L5CLKa
D1_A5_DAT(7:0)
L0DATa(7:0)
L0ACKa
L0CLKa
C1_A0_DAT(7:0)
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
D1_A5_CLK
L5ACKa
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
L4ACKa
F4_A4_CLK50_OHM_SHARC_LINK50_OHM_SHARC_LINK
L4CLKa
F4_A4_DAT(7:0)
L5DATa(7:0)
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
L4DATa(7:0)50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
L3DATa(7:0)
L3ACKa
L3CLKa
E4_A3_DAT(7:0)
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK
L1DATa(7:0)
L1ACKa C4_A1_ACK50_OHM_SHARC_LINK50_OHM_SHARC_LINK
L1CLKa
C4_A1_DAT(7:0)
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
50_OHM_SHARC_LINK50_OHM_SHARC_LINK
13 14
95
c ET-Nikhef Amsterdam
C
D
10
L
I
3 4
KRUISLAAN 409, 020-592 2000
11 12 13
VCCINT (1V5) 32 pins
GND 124 pins
Input FPGA Power pins:
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
Name
Size
Dim
Page
Proj:
VCCAUX (2V5) 16 pins
11 12
of
15 16 176 7 8
16
VCCO_# (3V3) 10 pins each
1098 SJ AMSTERDAM NEDERLAND
L
B
H
18
A
9
C
D
E
F
G G
H
I
J
K
Time
10
1
J
K
E
F
6 7 8
4 V2
7 Feb 2006
1:27:21 pm
tonvr
A3 4 1 4 A
420 x 297 mm
7 19
A
B
17 18
1 2
14 15
NIKHEF
2
Proj.No:
Rev
Date
3 4 5
MROD-Out
Output FPGA
MROD-X 38405
Peter Jansweijer
Y27 Y28 Y29Y3 Y30Y4 Y5 Y6 Y7 Y8 Y9 Y17 Y18 Y19Y2 Y20 Y21 Y22 Y23 Y24 Y25 Y26
W8 W9
Y1 Y10 Y11 Y12 Y13 Y14 Y15 Y16
W25 W26 W27 W28 W29W3 W30W4 W5 W6 W7 W15 W16 W17 W18 W19W2 W20 W21 W22 W23 W24
V6 V7 V8 V9
W1 W10 W11 W12 W13 W14
V23 V24 V25 V26 V27 V28 V29V3 V30V4 V5 V13 V14 V15 V16 V17 V18 V19V2 V20 V21 V22
U4 U5 U6 U7 U8 U9
V1 V10 V11 V12
U21 U22 U23 U24 U25 U26 U27 U28 U29U3 U30U11 U12 U13 U14 U15 U16 U17 U18 U19U2 U20
T3 T30T4 T5 T6 T7 T8 T9
U1 U10
T2 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29T1 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
R28 R29R3 R30R4 R5 R6 R7 R8 R9 R18 R19R2 R20 R21 R22 R23 R24 R25 R26 R27
P8 P9
R1 R10 R11 R12 R13 R14 R15 R16 R17
P26 P27 P28 P29P3 P30P4 P5 P6 P7 P16 P17 P18 P19P2 P20 P21 P22 P23 P24 P25
N6 N7 N8 N9
P1 P10 P11 P12 P13 P14 P15
N24 N25 N26 N27 N28 N29N3 N30N4 N5 N14 N15 N16 N17 N18 N19N2 N20 N21 N22 N23
M4 M5 M6 M7 M8 M9
N1 N10 N11 N12 N13
M22 M23 M24 M25 M26 M27 M28 M29M3 M30M12 M13 M14 M15 M16 M17 M18 M19M2 M20 M21
L3 L30L4 L5 L6 L7 L8 L9
M1 M10 M11
L20 L21 L22 L23 L24 L25 L26 L27 L28 L29L10 L11 L12 L13 L14 L15 L16 L17 L18 L19L2
K28 K29K3 K30K4 K5 K6 K7 K8 K9
L1
K19K2 K20 K21 K22 K23 K24 K25 K26 K27
J9
K1 K10 K11 K12 K13 K14 K15 K16 K17 K18
J26 J27 J28 J29J3 J30J4 J5 J6 J7 J8 J17 J18 J19J2 J20 J21 J22 J23 J24 J25
H7 H8 H9
J1 J10 J11 J12 J13 J14 J15 J16
H24 H25 H26 H27 H28 H29H3 H30H4 H5 H6 H15 H16 H17 H18 H19H2 H20 H21 H22 H23
G5 G6 G7 G8 G9
H1 H10 H11 H12 H13 H14
G22 G23 G24 G25 G26 G27 G28 G29G3 G30G4 G13 G14 G15 G16 G17 G18 G19G2 G20 G21
F30F4 F5 F6 F7 F8 F9
G1 G10 G11 G12
F20 F21 F22 F23 F24 F25 F26 F27 F28 F29F3 F11 F12 F13 F14 F15 F16 F17 F18 F19F2
E29E3 E30E4 E5 E6 E7 E8 E9
F1 F10
E19E2 E20 E21 E22 E23 E24 E25 E26 E27 E28E1 E10 E11 E12 E13 E14 E15 E16 E17 E18
D27 D28 D29D3 D30D4 D5 D6 D7 D8 D9 D17 D18 D19D2 D20 D21 D22 D23 D24 D25 D26
C8 C9
D1 D10 D11 D12 D13 D14 D15 D16
C25 C26 C27 C28 C29C3 C30C4 C5 C6 C7 C15 C16 C17 C18 C19C2 C20 C21 C22 C23 C24
B6 B7 B8 B9
C1 C10 C11 C12 C13 C14
B23 B24 B25 B26 B27 B28 B29B3 B30B4 B5 B13 B14 B15 B16 B17 B18 B19B2 B20 B21 B22
T
AK5
S
AK6
S
AK7 AK8 AK9
B1 B10 B11 B12
AK23
T
AK24
T
AK25
S
AK26
S
AK27 AK28 AK29AK3
T
AK4 AK14 AK15 AK16
T
AK17
T
AK18
S
AK19AK2
S
AK20 AK21 AK22
AJ5 AJ6 AJ7 AJ8 AJ9
AK10
T
AK11
T
AK12
S
AK13
S
AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29AJ3 AJ30AJ4 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19AJ2 AJ20 AJ21
AH30AH4 AH5 AH6 AH7 AH8 AH9
AJ1 AJ10 AJ11 AJ12
AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29AH3 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19AH2
AG29AG3 AG30AG4 AG5 AG6 AG7 AG8 AG9
AH1 AH10
AG19AG2 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28AG1 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18
AF27 AF28 AF29AF3 AF30AF4 AF5 AF6 AF7 AF8 AF9 AF17 AF18 AF19AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26
AE8 AE9
AF1 AF10 AF11 AF12 AF13 AF14 AF15 AF16
AE25 AE26 AE27 AE28 AE29AE3 AE30AE4 AE5 AE6 AE7 AE15 AE16 AE17 AE18 AE19AE2 AE20 AE21 AE22 AE23 AE24
AD6 AD7 AD8 AD9
AE1 AE10 AE11 AE12 AE13 AE14
AD23 AD24 AD25 AD26 AD27 AD28 AD29AD3 AD30AD4 AD5 AD13 AD14 AD15 AD16 AD17 AD18 AD19AD2 AD20 AD21 AD22
AC4 AC5 AC6 AC7 AC8 AC9
AD1 AD10 AD11 AD12
AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29AC3 AC30AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19AC2 AC20
AB3 AB30AB4 AB5 AB6 AB7 AB8 AB9
AC1 AC10
AB2 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29AB1 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19
AA28 AA29AA3 AA30AA4 AA5 AA6 AA7 AA8 AA9 AA18 AA19AA2 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27
A8 A9
AA1 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17
A26
S
A27 A28 A29A3
T
A4
T
A5
S
A6
S
A7 A18
S
A19A2
S
A20 A21 A22 A23
T
A24
T
A25
S
A10
T
A11
T
A12
S
A13
S
A14 A15 A16
T
A17
TIC529
XC2VP20FF896
GND SDRAM_WE_nGND SDRAM_DQM(0)UD(8) UD(7) GND VCCO_3
ROCKET_LDVS
RXN_3A
DP_RX_3A
ROCKET_LVDS
ROCKET_LDVS
RXP_3A
DP_RX_3A
ROCKET_LVDS
UD(12) UD(11) VCCO_3
UD(10) VCCO_3 GND VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINTUD(9) GND VCCO_6 VCCO_6 SDRAM_A(11) SDRAM_CS_n GND SDRAM_RAS_n SDRAM_CAS_n
GND GND GND GNDUD(17) VCCINT VCCO_6 VCCO_6 SDRAM_DQ(7) SDRAM_DQ(6) SDRAM_DQ(5) SDRAM_DQ(4) VME_D(31) VME_D(30) VME_D(29)UD(16) VME_D(28)UD(15) UD(14) UD(13)
SDRAM_DQ(0) VME_D(27) VME_D(26) VME_D(25)UD(24) VME_D(24)UD(23) UD(22) UD(21) UD(20) UD(19) VCCO_3
UD(18) VCCO_3 VCCINT GND GND GND GND
UD(30) GND UD(29) UD(28) UD(27)
UD(26) VCCO_3 VCCINT GND GND GND GND GND GND GND GNDUD(25) VCCINT VCCO_6 VCCO_6 SDRAM_DQ(3) SDRAM_DQ(2) SDRAM_DQ(1)
GND GND GND GND GND GND GND GNDUTEST_n VCCINT VCCO_6 VME_D(23) VME_D(22) VME_D(21) GND VME_D(20) VME_D(19) VME_D(18) VME_D(17)UCTRL_n VME_D(16)UD(31)
VME_A(29) VME_A(28) VME_A(27) VME_A(26) VME_A(25) VME_A(24)LRL(3) VCCAUXLRL(2) LRL(1) LRL(0) LDOWN_n LFF_n UWEN_n
URESET_n VCCO_3 VCCINT
VCCAUXSharcAdr(16) SharcAdr(17) SharcAdr(18) SharcAdr(19) SharcAdr(20) SharcAdr(21)
VCCAUX VCCO_3 VCCINT GND GND GND GND GND GND GND GNDSharcAdr(22) VCCINT VCCO_6 VME_A(31) VME_A(30)
VCCO_2 VCCINT GND GND GND GND GND GND GND GNDSharcAdr(14) VCCINT VCCO_7 VME_A(1) VME_A(8) VME_A(2) VME_A(9) VME_A(3) VME_A(10) VME_A(4) VME_A(11)SharcAdr(15)
VCCO_7 VME_A(5) VME_A(12) VME_A(6) GND VME_A(13) VME_A(7) VME_A(14) VME_A(15)SharcAdr(8) VME_A(16)SharcAdr(9) SharcAdr(10) GND SharcAdr(11) SharcAdr(12) SharcAdr(13)
VCCAUX
VME_A(23)SharcAdr(1) VME_IRQ_n(1)SharcAdr(2) SharcAdr(3) SharcAdr(4) SharcAdr(5) VCCO_2
SharcAdr(6) VCCO_2 VCCINT GND GND GND GND GND GND GND GNDSharcAdr(7) VCCINT
DMAR2_n VCCO_2
RstSharc_n VCCO_2 VCCINT GND GND GND GND GND GND GND GNDSharcAdr(0) VCCINT VCCO_7 VCCO_7 VME_A(17) VME_A(18) VME_A(19) VME_A(20) VME_A(21) VME_A(22)
GND GND GNDMS0_n VCCINT VCCO_7 VCCO_7 VME_IRQ_n(2) VME_IRQ_n(3) VME_IRQ_n(4) VME_IRQ_n(5) VME_IRQ_n(6) VME_IRQ_n(7) AM(0)MS1_n AM(1)MS2_n MS3_n DMAR1_n
VCCO_7 AM(2) AM(3) GND AM(4) AM(5) GND IACKOUT_nGND IACK_nSpare_3A(4) GND VCCO_2
Ack VCCO_2 VCCINT GND GND GND GND GND
GA_n(0) GAP_nSpare_3A(1) Spare_1B(0)Spare_3A(0) VCCO_2
HBR_n VCCO_2 GND VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINTHBG_n GND VCCO_7
Spare_3B(2) Spare_3B(1) VCCO_2
Spare_3A(3) VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_0 VCCO_0 VCCO_0 VCCO_0Spare_3A(2) VCCO_0 VCCO_0 VCCO_7 IACKIN_n GA_n(4) GA_n(3) GA_n(2) GA_n(1)
Spare_2A(3)
VCCO_1 VCCO_1 VCCO_1 VCCO_1 FLAG3a R_W_n VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_7 Spare_1B(1) Spare_1B(2) Spare_1B(3) Spare_1B(4)Spare_3B(4) Spare_3B(3)
SWDEN_n SMBClk LEAB_nSpare_3B(0) DENO_n DENIN1_n DENIN0_n HSWAP_EN DXP GNDVBATT TMS
DTACK_n WRITE_n PROG_BASP_Con_n DS2401 TCK Spare_2A(4) Spare_2A(2)
GND Spare_2B(3) Spare_2B(0) FLAG2a
TDO GND LocalBAR(4) Spare_2A(1)
Spare_2B(2) RstSharcD_n SharcWr_n AS_n SMBData T_Alert_n RstSharcC_n AM10_Rst_n DTACK_OE_n
GND VRN_1 VRP_1 LocalBAR(3) Spare_2A(0)
GND SharcRd_n GND LWORD_n DS0_n DS1_n BERR_n GND TDI
GND
Spare_2B(4) Spare_2B(1) Redy_a FLAG1a VME_D(7) VME_D(15) VME_D(6) VME_D(14) VME_D(5) VME_D(13) VRN_0 VRP_0 GND
FLAG0a VME_D(4) VME_D(12) VME_D(3) GND VME_D(11) VME_D(2) GND VME_D(10) VME_D(1) DXN GND Spare_1A(4)LEDs(2) GND LEDs(3) LocalBAR(2)
VME_D(0) GNDA4 Spare_1A(3) Spare_1A(2) GND Spare_1A(1)GND Spare_1A(0)LEDs(0) LEDs(1) GNDA9 LocalBAR(1)
IRQ0a_n IRQ1a_n GND IRQ2a_n CSa_n
VTTXPAD4 VRN_7 GNDVRN_2 VCCAUXAVCCAUXRX9 VTRXPAD9 AVCCAUXTX9 VTTXPAD9 LocalBAR(0)
Module_En GNDA7 Busy_2B GND GND Busy_1A GNDA6SYSFAIL_En VME_D(9)
Busy_3B GND
VCCAUX AVCCAUXRX7 VTRXPAD7 AVCCAUXTX7 VTTXPAD7 Rst_n Rocket_XClk AVCCAUXRX6 VTRXPAD6 AVCCAUXTX6GND VTTXPAD6 VME_D(8) AVCCAUXRX4 VTRXPAD4 AVCCAUXTX4
DP_TX_4A
ROCKET_LVDS
ROCKET_LDVS
TXN_4A
DP_TX_4A
VRN_6 VCCAUXVRN_3
ROCKET_LVDS
ROCKET_LDVS
RXN_3B
DP_RX_3B
ROCKET_LVDS
ROCKET_LDVS
RXP_3B
DP_RX_3B
ROCKET_LVDS
ROCKET_LDVS
TXP_3B
DP_TX_3B
ROCKET_LVDS
ROCKET_LDVS
TXN_3B
DP_TX_3B
ROCKET_LVDS
ROCKET_LDVS
RXP_4B
DP_RX_4B
ROCKET_LVDS
ROCKET_LDVS
TXP_4B
DP_TX_4B
VCCAUX
ROCKET_LVDS
ROCKET_LDVS
TXN_4B
DP_TX_4B
GND Busy_4A
ROCKET_LVDS
ROCKET_LDVS
RXN_4A
DP_RX_4A
ROCKET_LVDS
ROCKET_LDVS
RXP_4A
DP_RX_4A
ROCKET_LVDS
ROCKET_LDVS
TXP_4A
VRP_6 GNDVRP_3 VCCAUXAVCCAUXRX16 VTRXPAD16 AVCCAUXTX16 VTTXPAD16
ROCKET_LVDS
ROCKET_LDVS
TXP_3A
DP_TX_3A
ROCKET_LVDS
ROCKET_LDVS
TXN_3A
DP_TX_3A
VCCAUX VCCAUX
ROCKET_LVDS
ROCKET_LDVS
RXN_4B
DP_RX_4B
AVCCAUXRX18 VTRXPAD18 AVCCAUXTX18 VTTXPAD18 Clk AVCCAUXRX19 VTRXPAD19 AVCCAUXTX19GND VTTXPAD19 TTC_n(1)Z50_NET_TYPE
TTC_n(0)Z50_NET_TYPE
AVCCAUXRX21 VTRXPAD21 AVCCAUXTX21 VTTXPAD21
GND DOUT D2 VRP_4 GND
GNDA18 GND SLINK_CLKin Clkx2 GND GNDA19 TTC_n(3)Z50_NET_TYPE
VRP_5 D4 GNDA21 GNDGND SDRAM_DQ(15)GNDA16 D3 VRN_4
VCCAUX
IRQ0b_n GND Busy_3A SLINK_CLK LHC_Clk Busy_4B GND TTC_n(2)Z50_NET_TYPE
GND VRN_5 D5 CS_B SDRAM_DQ(12) GND SDRAM_DQ(11) SDRAM_DQ(14) SDRAM_DQ(13)
TTC_n(6)Z50_NET_TYPE
TTC_n(5)Z50_NET_TYPE
TTC_n(4)Z50_NET_TYPE
RDWR_B SDRAM_DQ(10) GND SDRAM_DQ(9) SDRAM_DQ(8) SDRAM_DQM(1) SDRAM_A(12)GND INIT_B IRQ2b_n IRQ1b_n
GND TTC_n(7)Z50_NET_TYPE
ROD_Busy GND SDRAM_CKE SDRAM_A(9) SDRAM_A(8) SDRAM_A(7) SDRAM_A(6)GND
CSb_n SDRAM_CLKin SDRAM_CLK TestCon(5)
SDRAM_A(5) SDRAM_A(4) SDRAM_A(3) SDRAM_DQM(3) SDRAM_DQ(31) SDRAM_DQ(30)PWRDWN_B D1
GND Redy_b FLAG0b TestCon(8) TestCon(6)
CCLK DONE D0
Spare_4A(4) Spare_4A(2) RstSharcE_n FLAG1b TestCon(9) TestCon(7) TestCon(15) RstSharcF_n TestCon(2) TestCon(0) D6 M0
TestCon(13) TestCon(14) TestCon(4)Spare_4B(3) TestCon(3) TestCon(1) D7 M2 M1 SDRAM_DQ(29) SDRAM_DQ(28) SDRAM_DQ(27) SDRAM_DQ(26) SDRAM_DQ(25)Spare_4B(4) GND
SDRAM_DQ(22) SDRAM_DQ(21) SDRAM_DQ(20) SDRAM_DQ(19) SDRAM_DQ(18)Spare_4B(0) SDRAM_DQ(17)UD(0) VCCO_3
GND Spare_4A(3) Spare_4A(1) Spare_4A(0) FLAG2b TestCon(10)
UD(3) UD(2) UD(1) VCCO_3
Spare_4B(2) VCCO_4 VCCO_4 VCCO_4 VCCO_4 FLAG3b TestCon(11) TestCon(12) VCCO_5 VCCO_5Spare_4B(1) VCCO_5 VCCO_5 VCCO_6 SDRAM_DQ(24) SDRAM_DQ(23)
VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5UD(5) VCCO_5 VCCO_5 VCCO_6 SDRAM_DQ(16) SDRAM_DQM(2) SDRAM_A(2) SDRAM_A(1) SDRAM_A(0) SDRAM_A(10) SDRAM_BA(1)UD(4) SDRAM_BA(0)
DP_TX_1B
VRP_7 VCCAUXVRP_2
ROCKET_LVDS
DP_RX_2A
ROCKET_LDVS
RXN_2A
ROCKET_LVDS
DP_RX_2A
ROCKET_LDVS
RXP_2A
ROCKET_LVDS
ROCKET_LDVS
TXP_2A
DP_TX_2A
ROCKET_LVDS
ROCKET_LDVS
TXN_2A
DP_TX_2A
Busy_2A GND
UD(6)
ROCKET_LVDS
ROCKET_LDVS
TXP_1A
DP_TX_1A
VCCAUX
ROCKET_LVDS
ROCKET_LDVS
TXN_1A
DP_TX_1A
GND Busy_1B
ROCKET_LVDS
ROCKET_LDVS
RXN_1B
DP_RX_1B
ROCKET_LVDS
ROCKET_LDVS
RXP_1B
DP_RX_1B
ROCKET_LVDS
ROCKET_LDVS
TXP_1B
DP_TX_1B
ROCKET_LVDS
ROCKET_LDVS
TXN_1B
ROCKET_LVDS
ROCKET_LDVS
RXN_2B
DP_RX_2B
ROCKET_LVDS
ROCKET_LDVS
RXP_2B
DP_RX_2B
ROCKET_LVDS
ROCKET_LDVS
TXP_2B
DP_TX_2B
ROCKET_LVDS
ROCKET_LDVS
TXN_2B
DP_TX_2B
VCCAUX VCCAUX
ROCKET_LVDS
ROCKET_LDVS
RXN_1A
DP_RX_1A
ROCKET_LVDS
ROCKET_LDVS
RXP_1A
DP_RX_1A
4 5
F
can be turned on in any sequence.
F
NIKHEFc
14 15 1612
G
3 4 5 6
IccAUX = 250 mA (min)
IccINT = 600 mA
Min. Power-On Current XC2VP20
Min. Power-On Current XC2VP20
XC2VP20 VCCINT Decoupling Capacitors
Power Inputs
AVX TAJB476K010R
AVX TAJB476K010R
AVX TAJB476K010R
AVX TAJB476K010R
2
ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
12 133
VCCINT Ramp rate 200 us min. and 50 ms max.
9 10 11
1098 SJ AMSTERDAM NEDERLAND
VCCAUX and VCCO can ramp up at any rate
For Xilinx Virtex-II Pro, power supplies
Rev
6 7 8
Proj: Proj.No:
G
H
I
Name
Size
A
9 10 11
2 18
H
I
J
XC2VP20 VCCAUX Decoupling Capacitors
B
C
D
E
420 x 297 mm
8 19
Date
Time
17 18
1
J
K
L
1 13
K
L Dim
7 8
Page of
15 16 1714
A
B
C
D
E
GND
MROD-Out
Output FPGA Power Supply Decoupling
MROD-X 38405
Peter Jansweijer [email protected]
3 V2
7 Feb 2006
1:27:36 pm
tonvr
A3 4 1 4 A
GND
GND
100n
C670
22n
C690
22n
C684
GND
C685
22n
GND
C652
680p
GND
C681
680p
C691
22n
GND
C674
47u
C704
100n
GND
100n
C709
C671
100n
C680
680p
C695
GND
680p
C715
100n
C719
GND
680p
C654
680p
GND
22n
C713
GND
680p
C647
GND
680p
C653
GND
GND
680p
C682
C693
100n
GND
GND
680p
C657
GND
100n
C729
C677
680p
GNDC720
680p
GND
C716
680p
GND
22n
C717
GND
GND
22n
C723
GND
22n
C733
GND
100n
C699
C672
100n
C692
GND
47u
C694
GND
100n
C669
GND
47u
C675
100n
680p
C701
GND
C663
22n
GND
C700
680p
GND
C724
100n
GND
22n
C697
GND
C714
100n
GND
GND
GND
C696
680p
GND
GND
C732
22n
GND
GND
C734
100n
GND
C656
680p
680p
C676
GND
680p
C649
GND
680p
C655
C683
680p
GND
C686
22n
C648
680p
GNDGND
C722
22n
GND
GND
C718
22n
GND
GND
680p
C725
GND
C726
680p
GND
GND
22n
C707
GND
GND
680p
C678
GND
C679
680p
680p
C731
22n
C689
GND
GND
680p
C721
GND
22n
C662
GND
GND
C710
680p
GND
GND
GND
GND
GND
C698
22n
GND
22n
C66747u
C735
GND
C736
47u
C702
22n
C666
22n
GND
C659
22n
680p
C711
GND
GND
GND
C688
22n
22n
C658
GND
22n
C703
GND
GND
22n
C687
22n
C661
GND
C712
22n
GND
GND
GND
C730
680p
GND
GND
22n
C727
GND
C728
22n
680p
C651
C668
100nC708
22n
C706
680p
GND
C650
680p
GND
100n
C673
GND
680p
C705
GND
22n
C664
GND
C665
22n
GND
GND
C660
22n
GND
VCCAUX
VCCINT
3V3 VCCO_0
VCCO_1
VCCO_2
VCCO_3
VCCO_4
VCCO_5
VCCO_6
VCCO_7
Series Termination for
H
PAD16 connected to MROD-In 3A FPGA
DC coupled
ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
1V8 @ 1,5A
Note: VT1V8_MGT is common to all MROD-Ins
1312 14
I
J
K
L
E
PAD4 connected to MROD-In 1A FPGA
DC coupled
=> MGT Power (estimated 21 + 44 = 65 mA)
A
B
I
J
K
L
PAD7 connected to MROD-In 2A FPGA
DC coupled
PAD9 connected to MROD-In 2B FPGA
DC coupled
Series Termination for
Series Termination for
13 14 15 16
General purpose
PAD6 connected to MROD-In 1B FPGA
DC coupled
18
1 2 7
Date
Time
12
AVX TAJB476K010R
=> MGT RX Termination (estimated 8 * 11 mA = 88 mA)
AVX TAJB476K010R
SDRAM Interface
E
F
G
2V5 @ 1,5A
4 5
PAD21 connected to MROD-In 4B FPGA
DC coupled
PAD19 connected to MROD-In 4A FPGA
DC coupled
PAD18 connected to MROD-In 3B FPGA
DC coupled
11
VME-bus Signals
Series Termination for
C
D
NIKHEFc
F
G
Sharc AddressbusGeneral purpose
A
B
4 9 10 117 8
Proj.No:
Rev
Dim
Page
17 18
AVX TAJB476K010R
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Proj:
5 6
Name
Size
Series Termination for
3 15 16
Series Termination for
7 Feb 2006
1:29:37 pm
tonvr
A3 4 1 4 A
420 x 297 mm
9 19
AVX TAJB476K010R
of
C
17
General purposeS-Link Signals
6
Series Termination for
Series Termination for
8 9 10
D
VME-bus Signals
2 3
H
=> MGT Termination (estimated 2 * 11 mA = 22 mA)
1
C774
GND
MROD-Out
Outp FPGA MGT Pwr Decoupling, Termination
MROD-X 38405
Peter Jansweijer [email protected]
3 V2
GND
GND
100n
C775
100n
GND
GND
47u
C740
47
R614
C771
220n
R613
47
47
R613
GND
GND
220n
C748
47
R614
100 R610
GND
R614
47
GND
GND
GND
GND2%
1u
L527
R609
100
2%
1u
L528
47u
C773
C746
220n220n
C744C742
220n
GND
47
R611
1u
L514
L506
1u
1u
L507
2%95E3 R606
C739
100n
GND
GNDGND
GND
R605
100
2%
L512
1u
GND GND
220n
C756
2%
100 R608
L511
1u
220n
C753 C755
220n
47
R613
GND
C751
220n
C737
47u
GND GND
GND
R614
47
GND
GND
GND
GND
GND
C738
100n
C768
220n 220n
C770
L521
L529
1u
L530
1u
220n
C760
L520
1u
1u
L525
1u
GND
GND
4K7
R604
1u
L508
1u
L517
220n
C764C762
220n
L516
1u
5_SHDN
1
1u
L513
C763
220n
GND GND
IC530
LT1963A_DD
GND13
GND2TAB
IN2 4
OUT
S_A
1u
L504
GND
GND
GND
GND
1u
L503
GND GND
220n
C749
GND
GND
C747
220n
R611
47
GND
GND
C743
220n 220n
C745
L524
1u
GND
GND
GND
GND
R612
47
1u
L518
L519
1u
C772
220n
220n
C769
220n
C766
C758
220n
220n
C765 C767
220n
L523
1u
GND
47
R611
R611
47
47
R612
L502
1u
L515
1u
220n
C761
1u
L509
1u
L510
GND
R607
4K7
GND
220n
C757 C759
220n
GNDGND
GND
220n
C752C750
220n
GNDGND
1u
L522
R612
47
L526
1u
R613
47
47
R612
1u
L532
GND
L505
1u
220n
GND
1u
L531
LT1963A_DD
IC531
3GND1
TABGND2
2IN OUT
4
5S_A
1_SHDN
GND
C754
GND GND GND
L501
1u
GND
C776
47u
220n
C741
GND
VRP_6
VRN_7
3V3
VRP_7
VRN_0
3V3
VRP_0
VT_MGT
VT_MGT
3V3POWER_NET_TYPE
VT1V8_MGT
3V3
VRP_1
VRN_2
3V3
VRP_2
VRN_3
3V3
VRP_3
VRN_4
3V3
VRP_4
VRN_5
3V3
VRP_5
VRN_6
3V3
VRN_1
AVCCAUXRX16
3V3POWER_NET_TYPE
VCCA_MGT
POWER_NET_TYPE
VT_MGT
GNDA4 GNDA6 GNDA7 GNDA9
GNDA21 GNDA19 GNDA18 GNDA16
AVCCAUXRX9
AVCCAUXTX21
VTTXPAD21
VTRXPAD21
AVCCAUXRX21
VCCA_MGT
AVCCAUXTX19
VTTXPAD19
VTRXPAD19
AVCCAUXRX19
AVCCAUXTX18
VTTXPAD18
VTRXPAD18
AVCCAUXRX18
AVCCAUXTX16
VTTXPAD16
VTRXPAD16
AVCCAUXTX4
VTTXPAD4
VTRXPAD4
AVCCAUXRX4
VCCA_MGT
AVCCAUXTX6
VTTXPAD6
VTRXPAD6
AVCCAUXRX6
AVCCAUXTX7
VTTXPAD7
VTRXPAD7
AVCCAUXRX7
AVCCAUXTX9
VTTXPAD9
VTRXPAD9
Connector
UD31
Ceramic X7R
8
ROD_Busy
G
H
VBATT is decriptor key memory backup supply
Temperature sensing diode
arc242 package
Pull-Ups
G
H
AVX 3V3 @ 2Amp
Proj.No:
J
UD6
UD5
UDW1
UD15
LRL3
3 8
of
15
Keyhole_1
2
FEMB Connector
S-LINK 3V3 Power
LRL0
UD16
9
Css = 22 nF
10
Size
F
Note that the 33 ohm serie termination
resistors for the LRL, LDOWN_n and
LFF_n signals should be placed near the
UD13
KRUISLAAN 409, 020-592 2000
Time
Name
UD21
UD20
Board Fiducials
14
UD26
B
K
UD22
Rev
6
Date
Optinal Test
Proj:
18
GND
J
A
B
CLDOWN_n
Low ESR
E
TPSD157K010R0100
for test purposes only.
16
I
UD17
is incorporated by the Digital Contolled
c
UD11
UD10
1 arc242 package and 1 0603
2 arc242 packages
LRL2
UD0
14
UD7
E
UD14
4 5
UD24
UD23
Page
1
48-bit MROD Identifier
17
Keyhole_2
S-Link connector.
UD4
UD3
UD19
UD18
UD27
I
LRL1
Dim
resistors during configuration
PWRDWN_B is unsupported (should be pulled high)
Other (Output) FPGA Control signals
Module_En and SYSFAIL_En Terminals, UD12
No Pin = 3V3
Yes Pin = LSC
Termination resistors for UCLKdrawn at the RoboClock (Sheet 14)
7
Ceramic X7R
16
UTEST_n
=> Ramp rate = 6,6 ms
C
UD30
1211
1098 SJ AMSTERDAM NEDERLAND
UD28
Receptable
Low ESR
0
6
D
These settings are used for BAR at power-up when this module
L
1 13
A
Note that serie termination
LocalBAR
FBSEL = Unconnected
2
Impedance (DCI) feature of the Output FPGA.
S-LINK
NATIONAAL INSTITUUT VOOR KERN-
F
K
FYSICA EN HOGE ENERGIE-FYSICA
5
UD9
UD8
L
GA_n(4:0) and GAP_n are either ’open’ or ’ground’
on the VME64x Back Plane.
NIKHEF
LFF_n
13
ET-Nikhef Amsterdam
18
Peter Jansweijer
38405MROD-X
S-Link and Outp. FPGA Auxiliary Connections
MROD-Out
10 11 127 9
UCTRL_n
D
17
UDW0
is plugged into a non-VME64x backplane (without GA pins).
15
CLK
15
UD2
UD1
UD25
HSWAP_EN = ’0’ => User IOs have pull-up
UCLK
Output (3V3)
Reference C
Ceramic X7R
Input C
UWEN_n
URESET_n
3 4
UD29
34
1910
420 x 297 mm
4 1 4 AA3
tonvr
1:29:59 pm
7 Feb 2006
V2 8
1
J24 3
J24 33
J24
J24 60
J24 61
R630
120K
Fiducial512
Fiducial513
25
T502BFR92
J24 50
GND
Fiducial511
3
J24 36
J24 37
R621
470
C784
100n
22n
C792
9
22n
C781
31
15
GND
2n2
C799
14
3LX3
15PGND1
PGND213
REF
10
SS5
TOFF
7
12VCC
_SHDN1
GND
IC540
MAX16446COMP
FB8
11FBSEL
9
GND
IN1
2 4
IN216
LX1
LX2
R635180
C777
22n
L533
6u8
10
8
7
6
29
GND
J24 16
J24 15
Fiducial508
J24 55
12
R6274K7
J23 16
17
R619
180
1 4
J24 52
C795
100n
0E0
30
24
23
IC539
DS2401Z
DQ2
4
J24 18
J24 19
R634
5
GND
J22 6
J24
26
GND
2
C788150u
3
2
J24 45
GND GND
6
10_ALERT
_STBY7
Fiducial514
D511
SMD_LED_Green
4
IC541
MAX1618
1ADD0
ADD12
4DXN
5DXP
GND
3
SMBCLK8
SMBDATA9
VCC
5
4
GND
J24 51
FRONT_LED_Red
D513
J23 11
1
IC533
NC7SZ00
1
2
3
J24 49
J22 4
GND
22n
C780
59
J24 58
GND
R63833
4K7R628
J23 6
4
J24
47
4K7R627
R6274K7
GND
J24 8
J24 28
J24
12
J25
470
R620
0
GND
J22 10
J23
IC536
NC7SZ00
1
2
3
5
4
7
14
13
GND
J24 25
24
J24 12
J24 13
1K0
R6335
J24 26
18
J24
20
19
J24 32
J24 48
0
0
1K0
R624
21
GND
33R640
J24 11
GND
6
J23 18
J23 20
GND
9
J23 10
MC100ELT24
IC538
2
GND
5
78
1
38
J24 20
GND
12
J23
GND
J23 7
J24 39
J24
180
R615
R616
180
GND
GND
GND
J24 46
100n
C800
GND
0
GND
4K7
R625
16
GND
10u
C789
R629
10
J23 19
22n
C787
22n
C778
GND
U6
3
28
C786
22n
J24 14
4K7
R632
GND
27
J24 35
J24 29
J24 30
R623
470
GND
6
4
J24
1
4K7
R626
J24 10
GND
470
R622
22
2
J22 3
J22 1
J24 44
GND
27
BAV99
D514
GND
J22 5
8
1
J23 1
R6414K7
56
J24 21
C779
22n
J23
J23 13
J23 14
J23 15
J24
R631
4K7
R6284K7
GND
C794100u
R625
4K7
470pC791
2
4K7
R636
41
IC534
NC7SZ00
1
2
3
5
4
4
GND
Fiducial509 Fiducial510
J24
J24 22
NC7SZ00
IC532
1
2
3
5
GND
GND
J24 23
C790
2u2
J24 31
J24 2
J24 1
R617
NC7SZ00
IC535
1
2
3
5
4
GND
11
J22 7
J23 2
180
9
1
J24 63
BFR92T501
GND
C793
1u
13
J24
R637
GND
J24 40
10
9
Fiducial507
Fiducial505 Fiducial506
33
C785
22u22u
C782
U7
U8
R636
4K7
11
C797
100n
J24 57
J24 64
J22 8
100n
C796
J22 2
4K7
R625
R625
4K7
SMD_LED_Red
D509
J23 3
J22 9
J23 5
J23 17
15
D510
SMD_LED_Red
C783
J24 62
J23 4
R618
180
4
3
8
100n
4K7
R639
GNDGND
GND
33
J24 53
R636
4K7
_Vin1
3_Vin2
_Vin36
_Vin47
1_Vout
33R637
R637
42
3
4K7R627
IC537
LM79L05ACM
GND5
2
7
J24 17
J24 43
J24
0
14
J24 5
J24 6
J24
GND
R63733
GND
100n
C798
J24 54
2
SMD_LED_Green
D512
VBATT
DXP
DXN
SMBClk
SMBData
T_Alert_n
3V3
Module_En
SYSFAIL_En
VME_12V_Neg
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
HSWAP_EN
PWRDWN_B VCCAUX
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
3V3
UCLKZ50_NET_TYPE
UCTRL_nZ50_NET_TYPE
LFF_nZ50_NET_TYPE
3V3
V_ROD_BUSY_nROD_Busy
LDOWN_nZ50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
5V
3V3
3V3
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
URESET_n
TestCon(15:0)
Clk
3V3
3V3
3V3
UTEST_nZ50_NET_TYPE
LRL(3:0)
UD(31:0)
UWEN_nZ50_NET_TYPE
5V
LEDs(0)
LEDs(1)
LEDs(2)
LEDs(3)
3V3
LocalBAR(4:0)
GA_n(4:0)
GAP_n
DS2401
6
c
Cable is connected,
B
K
L
JTAG Parallel IV Connector
NATIONAAL INSTITUUT VOOR KERN-
13 14 15
GND/Sel
of
15
GND
TDO
GND
TDI
17
11
G
H
I
Size
TCK, TMS, TDI and TDO connect to the
Output FPGA JTAG pins.
NIKHEF
Select either FPGA_TDO3 or 4 depending on
FPGA_TDO
3
18
E
13 14
F
Note: On the MROD-Out level of schematic
wether input FPGA 7 and 8 (MROD_In4)
GND
TCK
D
E
F
G
DNC
GND
traces. Place termination at end
of the line; driving buffers close
Parallel termination for FPGA_TCK/TMS.
Place termination at the end of the line.
to each other.
NC
2 18
1
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
4
B
C
MROD_In4_Present = ’0’ => Input FPGA 7&8 are absent.
5 10 11 12
are placed on the board.
Rev
Proj.No:
1098 SJ AMSTERDAM NEDERLAND
Proj:
9
GND
TMS
Page
Date
’0’ When Parallel IV
9 10
ET-Nikhef Amsterdam
8
ASP_Connected
VREF
MTM-Bus ASP Connection
Dim
J
K
L
A
MROD_In4_Present = ’1’ => Input FPGA 7&8 are present.
16
1612
[email protected] Jansweijer
38405MROD-X
FPGA JTAG Chain
MROD-Out
4 5
Place all the NC7SZ125 buffers close to
Time
Name
176 7
Some serie termination is added because
MRO_XCF08P_TDI might be a long trace.
GND
C
H
I
J
1
2 3
Place close to the driving buffer.
Parallel termination is added
because FPGA_TDO might be a long
connector J26.
A
7 8
’1’ when NOT.
1911
420 x 297 mm
4 1 4 AA3
tonvr
1:32:17 pm
7 Feb 2006
V2 4
33
R644
R64633
GND
C819
100n
82
R652
130
R653
R785
33
R658
4K7
GND
33R783
R78433
33
R782
3
R65082
C810
22n
GND
33
R654
J26
GND
J26 13
GND
4K7
R645
IC552
7
19
C812
22n
J26 9
GND
GND
J26 6
J26 7
74LVT8996.NH
33
R648
J26 14
4K7
R649
IC551
NC7SZ126
2
3
1
5
4
GND
R651
130
C802
100p
2
3
1
5
4
GND
22n
C807
GND
GND
4K7
R643
IC548
NC7SZ126
2
3
5
4
1
J26 11
GND
2
3
5
4
1
22n
C805
NC7SZ125
IC545
J26 5
22n
C982
GND
IC542
NC7SZ125
GND
C808
22n
GND
J26 8
GND
4E7
R642
C806
22n
4K7
R6473
5
4
1
IC544
NC7SZ1252
3
5
4
1
4
100p
C801
GND
NC7SZ125
IC543
2
17
STDO14
15STMS
13STRST
IC547
NC7SZ126
2
3
1
5
A721
A820
A9
6BYP
CON18
PTCK9
11PTDI
8PTDO
PTMS10
PTRST12
16STCK
STDI
IC552
74LVT8996
5A0
A14
3A2
2A3
1A4
24A5
23A6
22
GND
C818
100n
D515
FRONT_LED_Green
GND
100p
C803
GND
GND
5
4
1
NC7SZ126
IC550
2
3
1
5
4
J26 4
GND
GND
NC7SZ125
IC546
2
3
130
R656
GND
22n
C811
J26 10
GND
82 R655
1
5
4
C816
100n
GND
100n
C817
22n
C814
GND
GND
NC7SZ126
IC549
2
3
180
GND
100n
C815
GND GND
C981
22n
GND
R657
0
1
C979
22n
22n
C809
GND
GND
GND
GND
GND
IC589
NC7SZ00
IC587
NC7SZ00
NC7SZ00
IC588
IC586
NC7SZ00
J26 1
J26 2
NC7SZ00
IC585
GND
J26 12
GND
22n
C813
GND GND
GND
GND
4
3
2
GND
C804
22n
C983
22n
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
GA_n(4:0)
3V3
GND
22n
C980
3V3
3V3
3V3
3V3
3V33V3
Z50_NET_TYPE
TMS
3V3
Z50_NET_TYPE
TCK
Z50_NET_TYPE
Z50_NET_TYPE
V_TMS
V_TDI
V_TCK
3V3
Z50_NET_TYPE
MRO_XCF08P_TDI
FPGA_TDO3
FPGA_TDO4
MROD_In4_Present
3V3
FPGA_TCK
FPGA_TMS
3V3
3V3
3V3
3V3
ASP_Con_n
3V3
V_TDO
V_TRST_n
For proper POR, VccInt:
1098 SJ AMSTERDAM NEDERLAND
15
4
c ET-Nikhef Amsterdam
Configuration -> Slave SlectMAP programming Mode -> BUSY.
9
In this case set MROD-Out FPGA and one MROD-In FPGA
and CS_B = ’0’).
Note: these connections are made
D
1
13
3
C
9
Note: There is only space for one revision
Answer Record #18562
7
See "Virtex-II Pro FPGA User Guide", Chapter 4 ->
D
CT=0 => 10ms
All MROD-Ins are loaded with the
TCK, TMS, TDI and TDO connect to the
12
same bitstream (all RDWR_B = ’0’
KRUISLAAN 409, 020-592 2000
MRI_CCLK and D are routed to all input FPGAs
parralel termination at the end of the bus.
Default configuration mode will be Slave SelectMAP.
J
3
10
2
10 13 14
18
A
DOUT is BUSY in SelectMAP mode and BUSY is not used.
Note: On the MROD-Out level of schematic
B
to Master SelectMap and all other MROD-In FPGAs
A
B
C
5
17
0.2 ms < Risetime < 50 ms
Note: MROD-In M(2..0) are drawn on the Channel_In schematics.
M(2..0) are drawn on the Channel_In schematics.
’On’ = ’1’, ’Off’ = ’0’
Output FPGA JTAG pins.
Note: On the MROD-Out level of schematic
Rev
16
of
IMPACT chooses revision "00".
Name
2
After re-configuration ’General_Rst_n’ is kept active for 10 ms.
FPGA_Config
17
8
Proj: Proj.No:
16
2 12
J
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
Output FPGA JTAG pins.
IMPACT chooses revision "00".
K
L
6
It may be necessary to use Master SelectMap
A reset also issues a re-configuration of all FPGAs
14
11
H
I
MROD-Out FPGA Configuration
E
L Dim
Page
G
18
No possibility for readback (RDWR_B = ’0’).
4
Time
1
in the Channel_In schematics.
TCK, TMS, TDI and TDO connect to the
NIKHEF
Note: There is only space for one revision
configuration. See Xilinx PROM Errata,
Date
1 1 0 Slave SelectMAP (default )
7
1 0 1 Boundary scan
15
0 1 1 Master SelectMAP
1
CT=1 => 200ms
E
F
H
I
8
11
F
M2 M1 M0
ALL MROD-In FPGA Configuration
5 6
Size
to Slave SelectMap.
Note: FCC_SelectMAP = 50 MHz so CCLK < 50 MHz!
G
K
1912
420 x 297 mm
4 1 4 AA3
Ton van Reen
1:33:23 pm
7 Feb 2006
V2 9
[email protected] Jansweijer
38405MROD-X
FPGA Configuration And Resets
MROD-Out
3
7
GND GND
4
5
GND
1K0
R790
1K0R667
GND
GND
7
C978
22n
GND
6
82
R676h
R677h
130
5
R676g
82
130
R677g
GND
R676f
82
130
R677f
GND
R677e
130
GND
4
130
R677d
R676d
82
82
R676e
2
GND
R677c
130
GND
2
82
R676b
82
R676c
1
130
R677a
GND
R677b
130
GND
R676a
82
GND
0
GND
GND
22n
C832
R675
130
Vcco2
Vcco338
Vcco445
13_CE
10_CEO
6_CF
25_EN_EXT_SEL
22n
C834
26
REV_SEL127
20TCK
19TDI
22TDO
21TMS
4Vccint1
15Vccint2 Vccint3
34
24Vccj
8Vcco1
30
DNC839
DNC940
2GND1
7GND2
17GND3
23GND4
GND531
GND636
GND746
11OE_RESET
REV_SEL0
D6
D7481
DNC1
DNC1041
DNC1142
3DNC2
14DNC3
16DNC4
18DNC5
DNC635
DNC737IC554
5BUSY
12CLK
9CLKout
D028
D129
D232
D333
D443
D544
47
GND
GND
GND
4K7
R688
XCF08P
6
GNDGND
GND GND
C835
22n
C830
100n
1
3
Vcco4
13_CE
10_CEO
6_CF
25_EN_EXT_SEL
C840
22n
19TDI
22TDO
21TMS
4Vccint1
15Vccint2 Vccint3
34
24Vccj
8Vcco1
Vcco230
Vcco338
45
GND12
7GND2
17GND3
23GND4
GND531
GND636
GND746
11OE_RESET
REV_SEL026
REV_SEL127
20TCK
DNC1041
DNC1142
3DNC2
14DNC3
16DNC4
18DNC5
DNC635
DNC737
DNC839
DNC940
12CLK
9CLKout
D028
D129
D232
D333
D443
D544
D647
D748
DNC11
R786
33
XCF08P
IC553
5BUSY
GND
33
R664
GND
GND
R671
4K7
C843
100n
D516
HSMS2825
GND
R662
330
GND
22n
C841
3
R685
4K7
R6801K0
GND
GND
0
GND
R6781K0
GND
5
4
4K7
R660 R661
4K7
1K0
R665
IC555
NC7SZ08
1
2
3
GND
GND
R6661K0
GND
R687
180
R6681K0
GND
22n
C824
Sw9
3RESET
4
VDD5
GND
C826
22n
Sw9
100n
C842
MAX6863UK29
IC558
CT1
GND2
MR
GND
22n
C836
R663
4K7
22n
C839
GND
1K0
R682
GND GND
22n
C837
100n
C831C825
D517
FRONT_LED_Red
HSMS2825
D516
4K7
R674
GND
22n
4
C827
22n
C833
22n
Sw9
330
R673
NC7SZ08
IC557
1
2
3
5
C823
22n82
R672
22n
C828
22n
22n
C822
GND
GND
GND
22n
C829
C820
1K0
R683
GND
C838
22n
GND
GND
R6700E0
22n
C821R686
4K7
1K0R679
1K0R669
RESET
5VDD
0E0
R659
GND
IC556
MAX6863UK29
1CT
2GND
3MR
4
3V3
3V3
R6840E0
1K0
R681
MRI_DONE
MRI_PROG_B
MRI_D(7:0)
TDI
M1
Z50_NET_TYPE
FPGA_TDI
M2 M0
VCCAUX
D0
D1
D2
D3
D4
D5
D6
D7
DOUT
RDWR_B
CS_B
INIT_B
DONE
PROG_B
CCLK
MRI_INIT_B
MRI_DONE
General_Rst_n
VCCAUX
1V9
3V3
Rst_n
MRI_CCLK
VCCAUX
MRO_XCF08P_TDI
SYSRESET_n
AM10_Rst_n
3V3
PROG_B
MRI_PROG_B
DONE
TCK
TMS
TDO
1V9
3V3
7 8 9 10
Date
Time
Name
18
A
B
I
10
K
L
C
D
SDRAM_A(12) is not connected
NIKHEFc
I
J
K
11 12
A
B
13 14
E
F
ET-Nikhef Amsterdam
18
2
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
5 6
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Proj: Proj.No:
Rev
1
62 3 4 11 12 13 14 15 16 17
C
D
E
F
G
Size
Dim
Page of
153 4 7 8 9 16 17
H
G
H
5
J
MROD-Out
SDRAM
MROD-X 38405
Peter Jansweijer [email protected]
3 V2
7 Feb 2006
1:33:40 pm
tonvr
A3 4 1 4 A
420 x 297 mm
13 19
L
1
GND
22n
C848
16
GND
GND
22n
C844
GND
C846
22n
GND
22n
C852
GND
C855
22n
GND
C858
100n
_WE
0
6
VssQ212
VssQ332
VssQ438
VssQ546
VssQ652
78VssQ7
VssQ884
18_CAS
20_CS
19_RAS
17
VddQ335
VddQ441
VddQ549
VddQ655
VddQ775
81VddQ8
Vss144
Vss258
Vss372
Vss486
VssQ1
30NC3
57
NC469
NC570
NC673
Vdd11
Vdd215
Vdd329
Vdd443
VddQ13
VddQ29
8
DQ510
DQ611
DQ713
DQ874
DQ976
DQM016 71
DQM1
DQM228
DQM359
NC114
NC2
DQ2342
DQ2445
DQ2547
DQ2648
DQ2750
DQ2851
53DQ29
DQ37
DQ3054
DQ3156
DQ4
82
DQ1483
DQ1585
DQ1631
DQ1733
DQ1834
DQ1936
DQ25
DQ2037
DQ2139
DQ2240
A966
22BA0
23BA1
CKE67
CLK68
DQ02
4DQ1
DQ1077
DQ1179
DQ1280
DQ13
A025
A126
A1024
A1121
A227
A360
A461
A562
A663
A764
A865
3
7
8
IC559
MT48LC8M32B20
0
1
5
GND
GND
GND
0
100n
C856
GND
C857
100n
GND
GND
24
25
GND
GND
GND
22n
C847
22
23
GND
C849
22n
GND
C845
22n
20
21
GND
17
GND
100n
C859
18
19
C853
22n
GND
22n
C854
7
22n
C851
3
4
5
6
GND
9
1
2
C850
22n
GND
1
11
2
10
4
6
GND
GND
GND
1
32
11
12
13
14
15
GND
GND
29
30
31
8
9
10
SDRAM_CLKinZ50_NET_TYPE
26
27
28
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
SDRAM_WE_n
SDRAM_DQ(31:0)
SDRAM_DQM(3:0)
SDRAM_BA(1:0)
SDRAM_A(12:0)
3V3
SDRAM_RAS_n
3V3
3V3
3V3
SDRAM_CAS_n
SDRAM_CKEZ50_NET_TYPE
SDRAM_CLK
SDRAM_CS_n
c
3
100 MHz 16 bit = 50 MHz 32 bit
3F(1:0)= "mm" => 0 tu
18
A
2F(1:0)= "mm" => 0 tu
1F(1:0)= "mm" => 0 tu
5
2 3
15
100 MHz Phase Adjust
Parallel termination at the end of the line
50MHz
50MHz
3F(1:0)= "00" => 100 Divide by 2 = 50 MHz
G
9
I
C
D
1
Dim
40MHz
6
40MHz
8
L
B
NATIONAAL INSTITUUT VOOR KERN-
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
J
K
E
40MHz
40MHz
18
1
NIKHEF
11
ET-Nikhef Amsterdam
124
Fnom = 40 MHz
Rocket-IO Inter-FPGA Link Frequency
15 16
L
9
2 13
7
Page of
Clk from TIM via P3
16 17
= 200 MB/s
10
B
G
H
5
Parallel termination at the end of the line
Fnom = 100 MHz
C
4F(1:0)= "00" => 100 Divide by 2 = 50 MHz
6
1710
I
J
K
100MHz
A
D
Peter Jansweijer
38405MROD-X
Clocks
MROD-Out
4
100MHz
E
F
2F(1:0)= "mm" => 0 tu
1F(1:0)= "mm" => 0 tu
11 12 13 14
F
Time
Name
Size
14
Proj: Proj.No:
Rev
Date
FYSICA EN HOGE ENERGIE-FYSICA
LHC Clocks for the MROD-Ins
AVX TAJB476K010R
Clocks for the MROD-Out
7 8
4F(1:0)= "mm" => 0 tu
H
GND
1914
420 x 297 mm
4 1 4 AA3
Ton van Reen
1:34:07 pm
7 Feb 2006
V2 12
R700
4K7
GND
82
R714
GND
0E0
R794
1M0
R792
1M0
R793
GND
GND
GND
R7911M0
GND
C882
22n
GND
GND
R71833
R703
130
100n
C884
22n
C881
47u
C887
82
R710
GND
GND
GND
GND
1REF
TEST31
9 16 18 252 8
GND
2Q119
43F0
3F15
3Q015
3Q114
4F06
74F1
4Q011
4Q110
FB17
FS3
CY7B9911V
IC566
Vccq Vccn
1F026
271F1
1Q024
1Q123
292F0
2F130
2Q020
22n
C867
22n
C861
GND
100nC862
R713
130
R691
27
GND
R71682
R696
17K8
2%
GND
50MHz
S1703B_50
IC562
Ctrl1
GND
2
3OUT
Vcc
4
130
R715
GND
R71282
22n
C879
GND
C886
100n
C878
22n
GND
GND
C875
22n
GND
1K0
130
R707
82
R706
GND GND
100n
C864
R701
GND
C860
22n
GND
GND
R709
130
R68927
GND
GND
GND
C883
100n
C866
22n
GND
C870
22n
22n
C877
C888
47u
GND
_EN9
100n
C885
GND
C876
22n
3
4
11
6
5
10
7
8
EN16
12
13
16 18 252 8
DS90LV048ATMTC
IC560
15
2
1
14
153Q0
143Q1
64F0
4F17
114Q0
104Q1
17FB
3FS
REF1
31TEST
9
261F0
1F127
241Q0
231Q1
2F029
302F1
202Q0
192Q1
3F04
53F1
J2F1_MRO
1
2
3
GND
VccnVccq
IC567
CY7B9911V
100MHz
S1703B_100
IC565
Ctrl1
GND
2
3OUT
Vcc
4
GND
C880
22n
22n
C871
GNDGND
R695
1K5
C872
22n
GND
C868
22n
GND
22n
C874
1K5
R694
GND
R70882
R717
130R693
34K8
2%
C865
22n
130
R705
R702
82
130
R711
GND
27
R690
27
R692
22n
C873
J2F0_MRO
1
2
3
22n
C869
3V3
UCLKZ50_NET_TYPE
GND
82
R704
GND
GND
Rocket_XClkZ50_NET_TYPE
3V3
3V3
DP_RCLK40
+RCLK40DP_RCLK40
DP_RCLK40
-RCLK40DP_RCLK40
3V3
3V3
LHC_ClkZ50_NET_TYPE
SLINK_CLKinSLINK_CLK
ClkZ50_NET_TYPE
Z50_NET_TYPE
LHC_Clk1Z50_NET_TYPE
LHC_Clk2Z50_NET_TYPE
LHC_Clk4Z50_NET_TYPE
3V3
Clkx2Z50_NET_TYPE
3V3
Sharc_ClkZ50_NET_TYPE
LHC_Clk3
UD
UD
UD
GND
UD
UD
UD
UD
UD
UD
GND
UD
UD
GND
UD
UD
UD
+3V3
UD
+3V3
UD
UD
UD
+3V3
+3V3
+3V3
UD
ROD_Sense
UD
+RCLK40_BOC
+5V
+RCLK40
-RCLK40
TTC1_n
Worst Case Power Estimation for 5V supply = 4,5 Amp.
UD
GND
UD
+3V3
UD
UD
UD
GND
VPC
UD
UD
UD
UD
GND
UD
UD
+3V3
UD
GND
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
GND
UD
UD
UD
GND
UD UD
UD
UD
UD
UD
UD
UD
RETRY*
UD
GND
+3V3
UD
UD
UD
UD
GND
UD
Worst Case Power Estimation for 3V3 supply = 15 Amp.
UD
GND
-RCLK40_BOC
GND
UD
+5V
ROD_Busy_nUD
+5V
TTC0_n
+5V
UD
GND
+3V3
TTC3_n
TTC2_n
D31
GND
+5V
UD
UD
UD
GND
UD
UD
+3V3
UD
GND
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
GND
UD
UD
UD
UD
UD
UD
GND UD
UD
UD
UD
UD
+5V
GND
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
GND
UD
UD
TTC7_n
TTC6_n
TTC5_n
TTC4_n
+5V
UD
UD
GND
UD
GND
UD
UD
+V1
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
GND
UD
UD
UD
UD
+5V
UD
UD
UD
UD
UD
GND
UD
UD
UD
+5V
+3V3
GND
VPC
UD
GND
D10
A24
A25
UD
UD
A28
A29
A30
A31
GND
UD
UD
UD
UD
D19
D20
UD
UD
D23
UD
UD
UD
UD
GND
UD
UD
UD
A08
+12V
+5V
VPC
GND
ACFAIL*
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
UD
+5V
UD
UD
UD
UD
UD
IRQ1*
+5VSTDBY
+5V
D08
D09
D02
GND
UD
A26
A27
GND
UD
GND
UD
GND
+5V
D16
D17
D18
UD
GND
D21
D22
UD
GND
UD
UD
UD
UD
UD
D29
D30
A01
-12V
+5V
BBSY*
BCLR*
MCTL
+V2
RsvU
UD
UD
RsvU
GAP*
GA0*
GA1*
+3V3
UD
UD
UD
UD
GA4*
+3V3
UD
UD
RsvBus
UD
UD
UD
UD
UD
UD
UD
UD
GND
RsvBus
GND
D00
D01
BD11
D12
GND
UD
D15
GND
SYSFAIL*
BERR*
SYSRESET*
UD
GND
UD
GND
A21
A20
UD
GND
A17
GND
D24
D25
D26
D27
D28
GND
UD
GND
MSD
GND
MMD
GND
11
BG0IN*
BG0OUT*
-V1
-V2
BG2IN*
BG2OUT*
BG3IN*
BG3OUT*
BR0*
GA2*
+3V3
GA3*
+3V3
AM1
AM2
RsvBus
+3V3
SERA
+3V3
UD
UD
UD
UD
UD
+3V3
LI/O*
9 10 11 12
A
C
D03
D04
D13
D14
D07
GND
SYSCLK
GND
DS1*
LWORD*
AM5
A23
A22
GND
AS*
A19
A18
IACKIN*
A16
UD
GND
UD
GND
UD
A10
A09
4 5 6 7 8 9
B
C
BG1IN*
BG1OUT*
F
G
GND
RESP*
GND
BR1*
BR2*
BR3*
AM0
RsvBus
GND
AM3
GND
RsvBus
SERB
RsvBus
+3V3
RsvBus
+3V3
LI/I*
IRQ3*
IRQ2*
3 4 5 6 7 8
D
E
D05
D06
L
M
N
c ET-Nikhef Amsterdam
DS0*
WRITE*
GND
DTACK*
Proj: Proj.No:
GND
IACK*
Time
IACKOUT*
A15
A14
A13
A12
A11
A03
A02
S
T
A
1 2 3 10
H
D
E
S
T
O
J
K
RsvBus
GND
RsvBus
P
R
RsvBus
GND
12
GND
RsvBus GND
IRQ7*
IRQ6*
IRQ5*
IRQ4*
GND
RsvBus
GND
RsvBus
GND
RsvBus
1 2
F
G
H
J
NIKHEF1098 SJ AMSTERDAM NEDERLAND
K
P
R
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1:34:31 pm
Ton van Reen
A3 4 1 4 A
297 x 420 mm
15 19
AM4
A07
A06
A05
A04
GND
MCLK
Rev
Date
O
Name
Size
Dim
Page of
MPR
L
M
N
GND
3b
P1 4b
MROD-Out
VME Connectors
MROD-X 38405
Peter Janweijer [email protected]
3 V2
7 Feb 2006
P1 32c
P1 1b
P1 2b
P1
P1 29c
P1 30c
P1 31c
P1 18c
P1 19c
P1 20c
P1 15c
P1 16c
P1 17c
3a
P1 4a
P1 13c
P1 14c
32b
P1 1a
P1 2a
P1
P1 29b
P1 30b
P1 31b
P1
P1 18b
P1 19b
P1 20b
14b
P1 15b
P1 16b
P1 17b
3c
P1 4c
P1 13b
P1
32d
P1 1c
P1 2c
P1
P1 29d
P1 30d
P1 31d
P1
P1 2z
P1 3z
P1 4z
P1 31a
P1 32a
P1 1z
19d
P1 20d
P1 29a
P1 30a
P1 16d
P1 17d
P1 18d
P1
P1 13d
P1 14d
P1 15d
P1 26z
P1 13a
P1 14a
P1 23z
P1 24z
P1 25z
3d
P1 4d
P1 21z
P1 22z
15
P1 1d
P1 2d
P1
4
6
5
13
14
GND GND
0
1
2
3
1
0
5A
F1
21
GND
P3 3b
P3 4b
5
5
4
3
2
1
GND
21
20
3
7
6
P2 29z
P2 30z
23
22
U10
P2 27z
P2 28z
P1 18a
P1 19a
P1 20a
U9
P1 15a
P1 16a
P1 17a
15z
P2 16z
P2 17z
P2 18z
12z
P2 13z
P2 14z
P2
19z
P1 20z
P2 11z
P2
4
3
2
1
0
P1
P2 30a
P2 1z
P2 2z
P2 27a
P2 28a
P2 29a
0
1
2
3
4
4
7
P2 16a
P2 17a
P2 18a
P2 13a
P2 14a
P2 15a
P2 2a
P2 11a
P2 12a
P2 31z
P2 32z
P2 1a
P2 28b
P2 29b
P2 30b
10
9
8
GND
P2 27b
P2 17b
P2 18b
13
12
11
P2 14b
P2 15b
P2 16b
12a
P2 11b
P2 12b
P2 13b
31z
P1 32z
P1 11a
P1
28z
P1 29z
P1 30z
P1
P2 1b
P2 2b
P1 27z
P1
P2 30c
P2 31a
P2 32a
18z
P2 27c
P2 28c
P2 29c
15z
P1 16z
P1 17z
P1
P1 12z
P1 13z
P1 14z
P1
P2 17c
P2 18c
P1 11z
P2 14c
P2 15c
P2 16c
12b
P2 11c
P2 12c
P2 13c
9z
P1 10z
P1 11b
P1
P1 6z
P1 7z
P1 8z
P1
P2 1c
P2 2c
P1 5z
P2 30d
P2 31b
P2 32b
P2 27d
P2 28d
P2 29d
25a
P1 26a
P1 27a
P1 28a
22a
P1 23a
P1 24a
P1
P2 17d
P2 18d
P1 21a
P1
P2 14d
P2 15d
P2 16d
P2 11d
P2 12d
P2 13d
9a
P1 10a
P1 11c
P1 12c
P1 6a
P1 7a
P1 8a
P1
P2 1d
P2 2d
P1 5a
P1 28b
P2 31c
P2 32c
P1 25b
P1 26b
P1 27b
P1 22b
P1 23b
P1 24b
12d
GND GND
P1 21b
P1 9b
P1 10b
P1 11d
P1
P1 6b
P1 7b
P1 8b
P2 31d
P2 32d
P1 5b
P1 26c
P1 27c
P1 28c
P1 23c
P1 24c
P1 25c
P1 21c
P1 22c
P1 8c
P1 9c
P1 10c
GND
P1 5c
P1 6c
P1 7c
P3 8z
P3 9z
P3 10z
P1 27d
P1 28d
P3 7z
23d
P1 24d
P1 25d
P1 26d
24
P1 21d
P1 22d
P1
30
31
26
27
28
29
25
P1 9d
P1 10d
1
2
5d
P1 6d
P1 7d
P1 8d
9a
P3 10a
17
16
P112
P3 7a
P3 8a
P3
6
7
8
9
10
11
P3 28z
P3 29z
P3 30z
5
P3 25z
P3 26z
P3 27z
9z
P2 10z
P3 23z
P3 24z
P3 13z
P3 14z
P2
P3 10c
P3 11z
P3 12z
P3 7c
P3 8c
P3 9c
P3 28a
P3 29a
P3 30a
P3 25a
P3 26a
P3 27a
P2 10a
P3 23a
P3 24a
17
16
15
14
P2 9a
12a
P3 13a
P3 14a
19
18
9d
P3 10d
P3 11a
P3
P2 26z
P3 7d
P3 8d
P3
P2 23z
P2 24z
P2 25z
P2 20z
P2 21z
P2 22z
28c
P3 29c
P3 30c
P2 19z
25c
P3 26c
P3 27c
P3
P2 10b
P3 23c
P3 24c
P3
P2 7z
P2 8z
P2 9b
3z
P2 4z
P2 5z
P2 6z
12c
P3 13c
P3 14c
P2
25a
P2 26a
P3 11c
P3
22a
P2 23a
P2 24a
P2
19a
P2 20a
P2 21a
P2
P3 28d
P3 29d
P3 30d
P2
P3 25d
P3 26d
P3 27d
9c
P2 10c
P3 23d
P3 24d
6a
P2 7a
P2 8a
P2
P2 3a
P2 4a
P2 5a
P2
P3 12d
P3 13d
P3 14d
25b
P2 26b
P3 11d
P2 22b
P2 23b
P2 24b
P2
P2 19b
P2 20b
P2 21b
8b
P2 9d
P2 10d
P2 5b
P2 6b
P2 7b
P2
GND
P2 3b
P2 4b
P2 24c
P2 25c
P2 26c
P2 21c
P2 22c
P2 23c
8c
P2 19c
P2 20c
5c
P2 6c
P2 7c
P2
P2 3c
P2 4c
P2
21b
P3 22b
P3 23b
P3 24b
24d
P2 25d
P2 26d
P3
P2 21d
P2 22d
P2 23d
P2
P3 12b
P2 19d
P2 20d
8b
P3 9b
P3 10b
P3 11b
5b
P3 6b
P3 7b
P3
6d
P2 7d
P2 8d
P3
P2 3d
P2 4d
P2 5d
P2
P3 26b
P3 27b
P3 28b
GND
P3 25b
24
18
19
20
21
GND
25
P3 22z
P3 21z
P3 4z
P3 5z
P3 6z
P3 1z
P3 2z
P3 3z
P3 21a
P3 22a
30
31
22
23
26
27
28
29
100
R721
0E0
R722
100
R719
R720100
P3 4a
P3 5a
P3 6a
P3 1a
P3 2a
P3 3a
P3 31z
P3 32z
19z
P3 20z
P3 21c
P3 22c
16z
P3 17z
P3 18z
P3 0E0
R724
P3 15z
P3
P3 5c
P3 6c
R7230E0
P3 2c
P3 3c
P3 4c
P3 31a
P3 32a
P3 1c
P3 21d
P3 22d
P3 18a
P3 19a
P3 20a
P3 15a
P3 16a
P3 17a
5d
P3 6d
2d
P3 3d
P3 4d
P3
P3 31c
P3 32c
P3 1d
P3
P3 19c
P3 20c
P3 16c
P3 17c
P3 18c
7
6
5
4
P3 15c
P3 31d
P3 32d
GND
GND
P3 19d
P3 20d
15d
P3 16d
P3 17d
P3 18d
P3 31b
P3 32b
P3
P3 29b
P3 30b
F2
21
18b
P3 19b
P3 20b
16A
15b
P3 16b
P3 17b
P3
3
2
P3 13b
P3 14b
P3
GND
P3 1b
P3 2b
5VPOWER_NET_TYPE
VME_5VPOWER_NET_TYPE
POWER_NET_TYPE
VME_3V3 3V3POWER_NET_TYPE
V_TRST_n
DP_P3_RCLK40
-RCLK40_BOCDP_P3_RCLK40_BOC
+RCLK40_BOCDP_P3_RCLK40_BOC
DP_P3_RCLK40
+RCLK40DP_RCLK40
VME_5V VME_5VVME_3V3VME_3V3
V_ROD_Busy_n
V_TTC_n(7:0)
DP_RCLK40
-RCLK40
V_SYSRESET_n
V_LWORD_n
V_BERR_n
VME_5V
GA_n(4:0)
VME_5V VME_5V
V_IACKOUT_n
V_IACK_n
V_IACKIN_n
V_AM(5:0)
V_A(31:1)
VME_12V_Neg
V_IRQ_n(7:1)
GAP_n
VME_3V3
V_TCK
V_TDO
V_TDI
V_TMS
VME_5V VME_5V
V_D(31:0)
V_WRITE_n
V_AS_n
V_DS1_n
V_DS0_n
V_DTACK_n
VME_5V
5 6
Size
Dim
3 4 7 8
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IC3 is SWAP buffer
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1 2 3 4 5 6 7 8 9
NIKHEFc ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
MROD-Out
VME DataBus Buffers
MROD-X 38405
peter Jansweijer [email protected]
3 V2
7 Feb 2006
1:34:59 pm
Ton van Reen
A3 4 1 4 A
297 x 420 mm
16 19
10 11 12
S
D
3
11
22
23
5
13
GND
C893
22n
2
10
25 32 39 46 53
7 22 35 50
22n
C894
15
16
17
IC569
74LVT16543.NH
4 11 18
B534
B633
B7
26CEAB
31CEBA
27LEAB
30LEBA
28OEAB
OEBA29
7
19A3
20A4
21A5
23A6
24A7
42B0
41B1
40B2
38B3
37B4
36
3
11
4
74LVT16543
IC569
15A0
16A1
17A2
GND GND
100n
C899
2
10
11
12
13
14
22n
C897
B114
B216
B317
B419
B520
B622
B723
DIR24
OE25
GND
IC570
A036
A135
A233
A332
A430
A529
A627
A726
B013
22n
C889
4
12
7
8
74LVT16245
17
18
GND
C900
100n
GND
OEAB1
56OEBA
GND
5
6
15
16
B151
B249
B348
B447
B545
B644
B743
CEAB3
CEBA54
LEAB2
LEBA55
IC569
A05
A16
A28
A39
A410
A512
A613
A714
B052
8B4
9B5
11B6
12B7
1DIR
48OE
26
27
74LVT16543
46A1
44A2
43A3
41A4
40A5
38A6
37A7
2B0
3B1
5B2
6B3
8
1
9
IC570
74LVT16245
47A0
14
28
29
30
31
0
GND
4
12
24
25
6
34 39 45
7 18 31 42
C895
100n
21
GND
IC570
74LVT16245.NH
4 10 15 21 28
5
13
6
14
23
22
0
1
2
3
26
27
GND
18
19
20
21
39 46 53
7 22 35 50
GND
C898
22n
29
9
10
74LVT16543.NH
IC5684 11 18 25 32
20
21
GND
C890
22n
28
2
LEBA55
OEAB1
OEBA56
GND
18
19
B052
B151
B249
B348
B447
B545
B644
B743
CEAB3
CEBA54
LEAB
IC568
74LVT16543
A05
A16
A28
A39
A410
A512
A613
A714
38B3
37B4
36B5
34B6
33B7
26CEAB
31CEBA
27LEAB
30LEBA
28OEAB
29OEBA
A016
A117
A219
A320
A421
A523
A624
A7
42B0
41B1
40B2
28
29
30
31
74LVT16543
IC568
15
22
23
24
25
100n
C896
GND
0
8
1
9
19
20
24
25
26
27
100n
C891
GND
C892
100n
GND
30
31
7
15
16
17
LEAB_n
DENO_n
3V3
DENIN0_n
DENIN1_n
R_W_n
SWDEN_n
VME_D(31:0)
V_D(31:0)
12
1 2
signalling, buffer them anyway.
BERR_n is an
DTACK_n is a Recindering
Open Collector signal.
Open Collector signal.
Note: VME signals are 5V.
Most Logic on the MROD is NOT 5V tolerant!
6 7 11 12
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NATIONAAL INSTITUUT VOOR KERN-
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KRUISLAAN 409, 020-592 2000
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Proj.No:
J
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6 7
VME IRQ(7:1) are Open Collector signals.
Although TTC-Bus signals are 3V3
3 4 5
Place termination at the end of the line.
A
10 11
D
9
E
1 2
3
Therefore all VME signals need to be
buffered by a 3V3 (but 5V tolerant) buffer.
Parallel-Terminate due to
Long Board traces from P3 to FPGAs.
F
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8 9 10
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1098 SJ AMSTERDAM NEDERLAND
Proj:
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NIKHEF1917
297 x 420 mm
4 1 4 AA3
Ton van Reen
1:35:25 pm
7 Feb 2006
V2 3
[email protected] Jansweijer
MROD-X
VME Bus Other Buffers
MROD-Out
C
8
5 5
0 0
3 3
7 7
9
GND
1
8
6
13
7
GND
3
GND
16
4
5
12
4
11
14
30
31
GND
0
17
16
10
2
4
15 15
7
18
1
21
2 2
27
GND
23 23
GND
GND
GND
GND
1
21
22
2 2
GND
18
GND
GND
17
GND
22
6 6
GNDGND
1
2
3
GND
GND
GND
A232
A3
25OE
13Y0
14Y1
16Y2
17Y3
1
8
GND
A337
OE48
Y08
Y19
Y211
Y312
74LVT16244
IC576
36A0
35A1
33
43A3
1OE
2Y0
3Y1
5Y2
6Y3
IC576
74LVT16244
A041
A140
A238
A3
48OE
8Y0
9Y1
11Y2
12Y3
74LVT16244
IC576
47A0
46A1
44A2
3
10
2
74LVT16244
IC575
41A0
40A1
38A2
37
26A3
24OE
19Y0
20Y1
22Y2
23Y3
28
29
9
OE25
Y013
Y114
Y216
Y317
74LVT16244
IC572
30A0
29A1
27A2
19 19
11
IC572
74LVT16244
A036
A135
A233
A332
13
GND
GND
24
25
26
3
GND
GND
GND
14
6
100n
C903
GND
C904
100n
3
5
GND
4 4
GND
4
5
6
7
20 20
29
A227
A326
OE24
Y019
Y120
Y222
Y323
GND
A144
A243
A3
1OE
2Y0
3Y1
5Y2
6Y3
IC575
74LVT16244
A030
A1
A238
A337
OE48
Y08
Y19
Y211
Y312
74LVT16244
IC575
47A0
46
27
A326
OE24
Y019
Y120
Y222
Y323
IC574
74LVT16244
A041
A140
1
2
3
0
IC577
74LVT16244
A030
A129
A2
15 21 28 34 39 45
7 18 31 42
100n
C916
GNDGND
74LVT16244.NH IC575
4 10
Y09
Y111
Y212
Y3
30
31
28
29
Y13
Y25
Y36
74LVT16244
IC573
41A0
40A1
38A2
37A3
48OE
8
18 31 42
IC573
74LVT16244
A047
A146
A244
A343
OE1
Y02
74LVT16244.NH
4 10 15 21 28 34 39 45
7
21 28 34 39 45
7 18 31 42
IC574
5
12
4
26
74LVT16244.NH IC573
4 10 15
A041
A140
A238
A337
OE48
Y08
Y19
Y211
Y312
A047
A146
A244
A343
OE1
Y02
Y13
Y25
Y36
IC571
74LVT16244
GND
1 1
IC571
74LVT16244
GND
C905
22n
GND
C907
100n
GND
R73682
R737130
31 42
C902
22n
130
R735
4 10 15 21 28 34 39 45
7 18
5
C926
22n
GND
74LVT16244.NH IC571
4
5
6
7
Y3
100n
C919
GND
C920
100n
GND74LVT16244
IC577
36A0
35A1
33A2
32A3
25OE
13Y0
14Y1
16Y2
17
IC577
74LVT16244
A041
A140
A238
A337
OE48
Y08
Y19
Y211
Y312
74LVT16244
IC577
47A0
46A1
44A2
43A3
1OE
2Y0
3Y1
5Y2
6Y3
A030
A129
A227
A326
OE24
Y019
Y120
Y222
Y323
16
Y317
100n
C924
GNDGND
IC576
74LVT16244
Y36
IC575
74LVT16244
A036
A135
A233
A332
OE25
Y013
Y114
Y2
23Y3
IC574
74LVT16244
A047
A146
A244
A343
OE1
Y02
Y13
Y25
17
74LVT16244
IC573
30A0
29A1
27A2
26A3
24OE
19Y0
20Y1
22Y2
IC573
74LVT16244
A036
A135
A233
A332
OE25
Y013
Y114
Y216
Y3
Y111
Y212
Y3
GNDGND
22n
C914
GND
25
74LVT16244
IC572
41A0
40A1
38A2
37A3
48OE
8Y0
9
GND
22n
C909
GND
27
24
GND
R72682
C910
22n
GND
82
R740
130
R741
GND
GND
22n
C906
GND
22n
C901
GND
C923
100n
GND
GND
GND
20Y1
22Y2
23Y3
C921
22n
GND
14Y1
16Y2
17Y3
74LVT16244
IC574
30A0
29A1
27A2
26A3
24OE
19Y0
GND
74LVT16244
IC574
36A0
35A1
33A2
32A3
25OE
13Y0G
ND
82
R730
130
R731
C918
22n
GND
22n
C917
GND
130
R73282
82
R734
R739130
GND
GND
R733
4K7R725
GND
R73882
34 39 45
7 18 31 42
22n
C925
Y13
Y25
Y36
IC57274LVT16244.NH
4 10 15 21 28
20Y1
22Y2
23Y3
IC572
74LVT16244
A047
A146
A244
A343
OE1
Y02
Y116
Y217
Y3
74LVT16244
IC571
30A0
29A1
27A2
26A3
24OE
19Y0
GND
74LVT16244
IC571
36A0
35A1
33A2
32A3
25OE
13Y0
14
GND
GND
GND
GND
100n
C927
GND
100n
C908
28 34 39 45
7 18 31 42
22n
C922
31 42
GND
IC57674LVT16244.NH
4 10 15 21
4 10 15 21 28 34 39 45
7 18
74LVT16244.NH IC577
100n
C911
GND
C912
100n
C928
100n
C913
22n
GND
C915
100n
GNDGND
82
R728
130
R729
V_BERR_n BERR_n
V_IACKOUT_n
V_DTACK_n
V_DS1_n
IACK_n
DTACK_n
WRITE_n
DS0_n
DS1_n
R727130
IACKIN_n
IACKOUT_n
DTACK_OE_n
AS_n
LWORD_n
V_SYSRESET_n SYSRESET_n
3V3
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
Z50_NET_TYPE
3V3
TTC_n(7:0)
3V3
3V3
VME_IRQ_n(7:1)
V_A(31:1)
V_IRQ_n(7:1)
AM(5:0)
V_DS0_n
V_WRITE_n
V_AS_n
V_IACK_n
V_LWORD_n
V_TTC_n(7:0)
V_AM(5:0)
VME_A(31:1)
V_IACKIN_n
3 8
960 mA peak per ADSP21160N (= 1920 mA total)
21
1V9 @ 2Amp
MROD-In 3 & 4MROD-In 3 & 4
2V5 @ 2Amp
4 5 7
= VDDINT for the ADSP21160N’s of the MROD-Out
MROD-Out
1V9 @ 2Amp
960 mA peak per ADSP21160N (= 1920 mA total)
2V5_MRI_12 serves 2 MROD-Ins = 4 Input
2V5 @ 2Amp
= VCCAUX for Xilinx Virtex-II Pro in the
Input Channels, 250 mA per Channel
13
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
3 145 6 7 8 9
Proj:
1V5 @ 2Amp
MROD-Out
J
K
L
A
B
H
I
J
K
LNIKHEFc ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
C
D
E
F
G
H
F
G
121110
Channels = 4 * 250 mA = 1 A
2V5 @ 2Amp
= VDDEXT for the ADSP21160N’s of the MROD-Out
~100 mA per ADSP21160N (= 200 mA total)
= VCCAUX for Xilinx Virtex-II Pro in the
MROD-Out, 250 mA
6
= VDDINT for the ADSP21160N of MROD-In 3 & 4
= Vccint for configuration devices (XCF08P)
25 mA per device.
15 16 17 18
1
All GND nets on the SHARCs and FPGAs need
9
2
Name
4
Time
Date
Rev
= VCCINT for Xilinx Virtex-II Pro in the
MROD-Out, 600 mA
VCCINT Ramp rate 200 us min. and 50 ms max.
Proj.No:
10 11 12 13 14
16 17 18
A
B
to be connected to golbal GROUND.
1098 SJ AMSTERDAM NEDERLAND
MROD-In 1 & 2
= VDDINT for the ADSP21160N of MROD-In 1 & 2
MROD-Out
Page
Dim
Size
1V9 @ 2Amp
960 mA peak per ADSP21160N (= 1920 mA total)
I
15
2V5_MRI_34 serves 2 MROD-Ins = 4 Input
Input Channels, 250 mA per Channel
= VCCAUX for Xilinx Virtex-II Pro in the
MROD-In 1 & 2
Channels = 4 * 250 mA = 1 A
of
C
D
E
MROD-Out
Power Supplies
MROD-X 38405
Peter Jansweijer [email protected]
3 V2
7 Feb 2006
1:35:57 pm
tonvr
A3 4 1 4 A
420 x 297 mm
18 19
5V
GND
5V_to_2V5_?
2V55V
MBRD835L
D520
5V_to_2V5_?
2V5
5V_to_1V9_?
1V95V
5V_to_1V9_?
1V95V
5V_to_1V9_?
1V95V
5V_to_1V5_?
1V55V
5V_to_2V5_?
2V55V
VDDEXTPOWER_NET_TYPE
3V3
2V5_MRI_12POWER_NET_TYPE
2V5_MRI_34POWER_NET_TYPE
VCCAUXPOWER_NET_TYPE
1V9_MRI_12POWER_NET_TYPE
1V9_MRI_34POWER_NET_TYPE
5V
VCCINTPOWER_NET_TYPE
GNDPOWER_NET_TYPE
POWER_NET_TYPE
1V9
VDDINTPOWER_NET_TYPE
I
J
K
L
1 2 3 4
VME64x VME64x & TTC
16 17 189
Some test traces to verify the impedance on the board.
C
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND of
15 16 17 18
A
B
Clk
Proj: Proj.No:
Rev
Size
Dim
Page
11
H
D
E
F
G
7 8 9
G
Connector
Optional Test
14
E
F
GND
Connector
Optional Test
15
0
Clk
GND
Connector
Optional Test
15
I
5 6 7 8 10
0
Clk
GND
2
11 12 13 14 15
5 64
VME64x SHARCs SHARCs S-LINK Output
NIKHEFc ET-Nikhef Amsterdam
Name
The 0 ohm resistors in the clock lines can be removed
when the test connector is not used. This avoids long
stubs on the clock lines. Note that the resistors
should be placed near the clock source!
NATIONAAL INSTITUUT VOOR KERN-
FYSICA EN HOGE ENERGIE-FYSICA
Connector
GND
Connector
Optional Test
15
0
Clk
GND
10
Optional Test
15
0
Optional Test
15
H
Connector
12 13
C
D
0
Clk
GND
1 3
1919
420 x 297 mm
4 1 4 AA3
tonvr
1:36:13 pm
7 Feb 2006
V2 4
[email protected] Jansweijer
38405MROD-X
Test connectors
MROD-Out
J
K
L
A
B
15
0
Clk
Date
Time
2
7
18
GND
J205 14
J205 1
6
J201 5
J202 17
J202
J205 5
J205 6
J201 7
J201
2
J205 20
J201 4
J202 12
R7891M
1
8
J202 9
J202 10
J202 11
J202 3
J202
3
J203 18
J203 19
J203 20
8
J201 1
J201 2
J201
3
4
0E0
R742
J205 7
J205
7
0
2
1
7
J205 3
R743
0E0
6
6
5
4
0E0
R745
16
J205 2
0
6
1
2
3J202
8
J203 9
J203 10
J205 19
5
13 J203 13
J203
19
J204 20
J203 3
J202 19
J202
J204 16
J204 17
J204 18
J204
J205 17
J205 18
7
GND
16
J203 17
5
4
1
J204 11
J204 12
J204 13
J203
6
J202 7
6
J205 9
GND
4
3
J202 4
J202 5
J202
0E0
R746 R747
0E0
J205
3
J206 2
J206 1
J206 4
6
J205 16
J206
3
4J203 15
GND
J203 5
J203 11
J203 12
2
J203 2
J203 1
J203 4
J202 20
J206 14
J206 15
1
0
1
0
5
15
0E0
R744
2
3
4
J202 14
J202 15 J205
13
J204 9
J204 10
J205 13
2
J202 1
0
7
J206
5
J206 5
J206 6
J202
0E0
R7770E0
GND
GND
0E0
0E0
R778
GND
R780
J206 12
J204 14
J204 15
R779
5J203 14
J206 10
J206 11
1
J206 19
J206 20
4
7
J204 8
J203 6
J203 7
GND
J204 5
J204 6
J204
J201 17
1MR788
R7871M
14
J201 20
J201 19
J201 18
J201 11
J201 16
J201 15
J201
9
J201 8
J201 13
J201 12
J206 9
5
J201 10
J201
J205 11
J205 12
J206 7
J206 8
17
J206 18
J205 10
4
3
2
1
J206 16
J206
3
J204 2
J204 1
J204 4
LWORD_n
VME_A(31:1)
VME_D(31:0)
Clk
Z50_NET_TYPE
Z50_NET_TYPE
UCLK
J204
DENIN1_n
DENIN0_n
BERR_n
DTACK_n
WRITE_n
AS_n
DS1_n
DS0_n
GOL_LVDS
ROCKET_LVDS
DP_TST
GOL_LVDS
ROCKET_LVDS
DP_TST
Z50_NET_TYPE
Z50_NET_TYPE
Flag1a
SWDEN_n
R_W_n
LEAB_n
DENO_n
DMAR2_n
DMAR1_n
MS3_n
MS2_n
MS1_n
MS0_n
SharcWr_n
SharcRd_n
IACK_n
IACKIN_n
IACKOUT_n
REDY_b
CSb_n
REDY_a
CSa_n
LFF_n
URESET_n
LDOWN_n
UCTRL_n
UWEN_n
AM(5:0)
VME_IRQ_n(7:1)
SharcAdr(31:0)
TTC_n(7:0)
UD(31:0)
LRL(3:0)
Sharc_Clk
Flag0a
RstSharcAB_n
RstSharcF_n
RstSharcE_n
RstSharcD_n
RstSharcC_n
IRQ2a_n
IRQ1a_n
IRQ0a_n
HBG_n
HBR_n
ACK
4 5 6 10 11 12 16 17 18
2 3
FYSICA EN HOGE ENERGIE-FYSICA
5 6
Date
Time
Name
7 8 9
of
15 1610 11 12
B
C
D
13 14
L
H
I
J
D
E
F
B
C
=> Ramp rate = 6,6 ms
J
K
L
H
I
Reference C
Input C
Ceramic X7R
1 2 3
Ceramic X7R
Css = 22 nF
Low ESR
7 8 9
AVX
TPSD157K010R0100
2V5 @ 2Amp
13 14 15
c ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
1
NIKHEF
Ceramic X7R
Proj: Proj.No:
Rev
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
4
1
420 x 297 mm
4 1 4 AA3
tonvr
1:36:58 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
5V -> 2V5 @ 2A
Power Supply
Size
Dim
Page
17 18
A
E
F
G
K
Low ESR
A
FBSEL = VCC
Output 2V5G
R750
180K
1
GND
22n
C933
R749
0E0
GND
C931
2u2
C929150u
GND GND
10u
C930
R748
10
GND
470pC932
GND
C934
1u
LX1
LX214
3LX3
15PGND1
PGND213
REF
10
SS5
TOFF
7
12VCC
_SHDN1
GND
IC578
MAX16446COMP
FB8
11FBSEL
9
GND
IN1
2 4
IN216
2V5
5V
GND
C935100u
L534
6u8
4 5 6 10 11 12 16 17 18
2 3
FYSICA EN HOGE ENERGIE-FYSICA
5 6
Date
Time
Name
7 8 9
of
15 1610 11 12
B
C
D
13 14
L
H
I
J
D
E
F
B
C
=> Ramp rate = 6,6 ms
J
K
L
H
I
Reference C
Input C
Ceramic X7R
1 2 3
Ceramic X7R
Css = 22 nF
Low ESR
7 8 9
AVX
TPSD157K010R0100
2V5 @ 2Amp
13 14 15
c ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
1
NIKHEF
Ceramic X7R
Proj: Proj.No:
Rev
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
4
1
420 x 297 mm
4 1 4 AA3
tonvr
1:36:58 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
5V -> 2V5 @ 2A
Power Supply
Size
Dim
Page
17 18
A
E
F
G
K
Low ESR
A
FBSEL = VCC
Output 2V5G
R753
180K
1
GND
22n
C940
R752
0E0
GND
C938
2u2
C936150u
GND GND
10u
C937
R751
10
GND
470pC939
GND
C941
1u
LX1
LX214
3LX3
15PGND1
PGND213
REF
10
SS5
TOFF
7
12VCC
_SHDN1
GND
IC579
MAX16446COMP
FB8
11FBSEL
9
GND
IN1
2 4
IN216
2V5
5V
GND
C942100u
L535
6u8
16 17 18
D
E
F
J
Low ESR
L
FBSEL = REF
Output Adjustable (1V9)
F
Ceramic X7R
Input C
L
1 2
Ceramic X7R
Ceramic X7R
Css = 22 nF
6 7 8
Low ESR
AVX
TPSD157K010R0100
12 13 14
NIKHEFc ET-Nikhef Amsterdam
18
1V9 @ 2Amp
1
1098 SJ AMSTERDAM NEDERLAND
Proj: Proj.No:
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
4
Name
Size
Dim
Date
Time
7 8 9
Page of
1510 11 12
A
B
C
13 14
K
G
H
I
C
D
E
A
B
=> Ramp rate = 6,6 ms
I
J
K
G
H
Reference C
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:39:18 pm
tonvr
A3 4 1 4 A
420 x 297 mm
1 1
3 4 5 9 10 11 15 16 17
2 3
NATIONAAL INSTITUUT VOOR KERN-
5 6
Rev
220K R756
Power Supply
5V -> 1V9 @ 2A
MROD_X 38405
48K7 R758
22n
C947
R755
0E0
C943150u
GND
R757
34K8
2%
2%
10
GND
GND
C945
2u2
GND GND
10u
C944
R754
GND
470pC946
GND
C948
1u
16LX1
LX214
3LX3
15PGND1
PGND213
REF
10
SS5
TOFF
7
12VCC
_SHDN1
GND
IC580
MAX16446COMP
FB8
11FBSEL
9
GND
IN1
2 4
IN2
1V9
5V
GND
C949100u
L536
6u8
16 17 18
D
E
F
J
Low ESR
L
FBSEL = REF
Output Adjustable (1V9)
F
Ceramic X7R
Input C
L
1 2
Ceramic X7R
Ceramic X7R
Css = 22 nF
6 7 8
Low ESR
AVX
TPSD157K010R0100
12 13 14
NIKHEFc ET-Nikhef Amsterdam
18
1V9 @ 2Amp
1
1098 SJ AMSTERDAM NEDERLAND
Proj: Proj.No:
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
4
Name
Size
Dim
Date
Time
7 8 9
Page of
1510 11 12
A
B
C
13 14
K
G
H
I
C
D
E
A
B
=> Ramp rate = 6,6 ms
I
J
K
G
H
Reference C
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:39:18 pm
tonvr
A3 4 1 4 A
420 x 297 mm
1 1
3 4 5 9 10 11 15 16 17
2 3
NATIONAAL INSTITUUT VOOR KERN-
5 6
Rev
220K R761
Power Supply
5V -> 1V9 @ 2A
MROD_X 38405
48K7 R763
22n
C954
R760
0E0
C950150u
GND
R762
34K8
2%
2%
10
GND
GND
C952
2u2
GND GND
10u
C951
R759
GND
470pC953
GND
C955
1u
16LX1
LX214
3LX3
15PGND1
PGND213
REF
10
SS5
TOFF
7
12VCC
_SHDN1
GND
IC581
MAX16446COMP
FB8
11FBSEL
9
GND
IN1
2 4
IN2
1V9
5V
GND
C956100u
L537
6u8
4 5 6 10 11 12 16 17 18
2 3
FYSICA EN HOGE ENERGIE-FYSICA
5 6
Date
Time
Name
7 8 9
of
15 1610 11 12
B
C
D
13 14
L
H
I
J
D
E
F
B
C
=> Ramp rate = 6,6 ms
J
K
L
H
I
Reference C
Input C
Ceramic X7R
1 2 3
Ceramic X7R
Css = 22 nF
Low ESR
7 8 9
AVX
TPSD157K010R0100
2V5 @ 2Amp
13 14 15
c ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
1
NIKHEF
Ceramic X7R
Proj: Proj.No:
Rev
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
4
1
420 x 297 mm
4 1 4 AA3
tonvr
1:36:58 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
5V -> 2V5 @ 2A
Power Supply
Size
Dim
Page
17 18
A
E
F
G
K
Low ESR
A
FBSEL = VCC
Output 2V5G
R766
180K
1
GND
22n
C961
R765
0E0
GND
C959
2u2
C957150u
GND GND
10u
C958
R764
10
GND
470pC960
GND
C962
1u
LX1
LX214
3LX3
15PGND1
PGND213
REF
10
SS5
TOFF
7
12VCC
_SHDN1
GND
IC582
MAX16446COMP
FB8
11FBSEL
9
GND
IN1
2 4
IN216
2V5
5V
GND
C963100u
L538
6u8
16 17 18
D
E
F
J
Low ESR
L
FBSEL = REF
Output Adjustable (1V9)
F
Ceramic X7R
Input C
L
1 2
Ceramic X7R
Ceramic X7R
Css = 22 nF
6 7 8
Low ESR
AVX
TPSD157K010R0100
12 13 14
NIKHEFc ET-Nikhef Amsterdam
18
1V9 @ 2Amp
1
1098 SJ AMSTERDAM NEDERLAND
Proj: Proj.No:
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
4
Name
Size
Dim
Date
Time
7 8 9
Page of
1510 11 12
A
B
C
13 14
K
G
H
I
C
D
E
A
B
=> Ramp rate = 6,6 ms
I
J
K
G
H
Reference C
Peter Jansweijer [email protected]
2 V2
7 Feb 2006
1:39:18 pm
tonvr
A3 4 1 4 A
420 x 297 mm
1 1
3 4 5 9 10 11 15 16 17
2 3
NATIONAAL INSTITUUT VOOR KERN-
5 6
Rev
220K R769
Power Supply
5V -> 1V9 @ 2A
MROD_X 38405
48K7 R771
22n
C968
R768
0E0
C964150u
GND
R770
34K8
2%
2%
10
GND
GND
C966
2u2
GND GND
10u
C965
R767
GND
470pC967
GND
C969
1u
16LX1
LX214
3LX3
15PGND1
PGND213
REF
10
SS5
TOFF
7
12VCC
_SHDN1
GND
IC583
MAX16446COMP
FB8
11FBSEL
9
GND
IN1
2 4
IN2
1V9
5V
GND
C970100u
L539
6u8
15 16 17
c ET-Nikhef Amsterdam
NATIONAAL INSTITUUT VOOR KERN-
6
A
7 8
Dim
Page
2 3
of
15
A
B
C
G
H
I
G
B
C
10 11 12
D
13 144 52 3 9 10 11
Output Adjustable (1V5)
12
J
Low ESR
L
1
K
L
Rev
Size
Ceramic X7R
Ceramic X7R
=> Ramp rate = 6,6 ms
FYSICA EN HOGE ENERGIE-FYSICA
KRUISLAAN 409, 020-592 2000
1098 SJ AMSTERDAM NEDERLAND
Low ESR
Proj: Proj.No:
Reference C
Ceramic X7R
Input C
18
1V5 @ 2Amp
1 9 13 16 17 184 5
tonvr
1:38:24 pm
7 Feb 2006
V2 2
[email protected] Jansweijer
38405MROD-X
5V -> 1V5 @ 2A
Power Supply
AVX
TPSD157K010R0100
Date
Time
Name
Css = 22 nF
H
I
E
F
14
K
D
E
F
J
6 7 8
NIKHEF
FBSEL = REF
270K
11
420 x 297 mm
4 1 4 AA3
22n
C975
R773
0E0
R774
R775
17K8
2%
2%48K7 R776
C973
2u2
C971150u
GND
10u
C972
R772
10
GND
GND
GND
C976
1u
GND GND
TOFF
7
12VCC
_SHDN1
GND
GND
470pC974
FBSEL
9
GND
IN1
2 4
IN216
LX1
LX214
3LX3
15PGND1
PGND213
REF
10
SS5
L540
6u8
IC584
MAX16446COMP
FB8
11
5V
1V5
GND
C977100u