using spectre rf noise-aware pll methodology to predict pll behavior accurately

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Using Spectre RF Noise-Aware PLL Methodology to Predict PLL Behavior Accurately

Helene ThibierozCustomer Support CIC

September 17, 20072


•

Introduction

•

Spectre RF Noise-Aware PLL Flow and Non-Linear VCO Modeling

•

Advantages of this flow versus other commercial approaches

•

Experimental results

•

Conclusion

September 17, 20073

Introduction

•

Phase locked loops are essential blocks in most analog mixed-

signal and radio frequency (RF) applications today. •

Because of the complexity of PLLs, the different time constants involved (two widely-spaced time constants), and the fact that the voltage-controlled oscillator (VCO) frequency often oscillates several order of magnitude faster than the reference frequency, simulating PLLs at a transistor level presents multiple challenges and is extremely time demanding.

•

Cadence SpectreRF Noise-aware PLL flow enables designers to efficiently and accurately predict PLL response using a non-linear model approach to capture the VCO dynamic behavior

September 17, 20074

Challenges of PLL Simulation

•

PLL are “stiff”

circuits–

Contain two widely-spaced time constants–

For wireless systems, the VCO often oscillates orders of magnitude faster than the reference frequency

fref

fref

PFD LPF VCO

Divide by NN * fref

CPRef

Div

Out

September 17, 20075

Challenges of PLL Simulation

•

Behavioral model based simulation approaches accelerate simulation speed, allowing designers to trade-off block characteristics and PLL performance.

•

Cadence has developed a new non-linear model that allows designers to accurately simulate the dynamic behavior of the VCO, such as injection locking and power-supply interference.

fref

fref

PFD LPF VCO

Divide by NN * fref

CPRef

Div

Out

September 17, 20076


Introduction




Conclusion

September 17, 20077

Spectre RF Noise-Aware PLL Simulation

V R

PFD CP VCO

N÷

V F

Closed Loop PLL Noise

100 nV/√Hz

200 nV/√Hz

500 nV/√Hz

1 μ V/√Hz

2 μ V/√Hz

5 μ V/√Hz

10 μV/√Hz

20 μV/√Hz

50 μV/√Hz

1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHzVerilog-A –

Transient Analysis

Automatically generate model

ComputePSS-PNoise

ADE Test Bench and Analysis

•

Automated flow for closed loop PLL noise analysis

•

ADE test bench and analysis for all PLL blocks

•

Automatic generation of behavioral models

•

Spectre RF enhanced direct integration

September 17, 20078

Spectre RF Noise-Aware PLL Simulation Flow

1.

In SpectreRF, a PLL circuit is partioned as a PFD block and a VCO block since they have different work frequencies (Other blocks such as CP, LPF and DIVIDER are being merged in those two blocks).

2.

SpectreRF solves the two test benches at different frequencies with PSS (using either time domain and harmonic balance solvers) and get the large signal operation points.

3.

The Perturbation Projection Vector (PPV) is extracted in the VCO test bench. Then a PLL test bench combines the PFD and VCO macro models.

4.

PLL behavior is then simulated with a TRAN analysis. Since PPV is used to provide the phase changes, the output of VCO/DIVIDER is tracing the reference frequency. Also noise information (represented by Jitter) could be added and simulated with the same test bench.

September 17, 20079

PLL Model Extraction Flow•

Place the block to be tested into the testbench schematic

•

Invoke ADE, setup simulation and enable model extraction

•

Run PSS and PNOISE analysis–

PSS calculates the PPV of the VCO and the transfer function of the other blocks

–

PNOISE calculates the noise characteristics of the block

•

Spectre automatically generates the model –

Model is generated in two formats: CMI and Verilog-A models

Place DUT in Testbench

Start ADE and Setup Test

Simulate

PSS/PNOISE

Automatically Generate Model

September 17, 200710

PLL Simulation Flow

•

Create new PLL Testbench by placing the extracted models in a PLL testbench

•

Start ADE and setup test simulation•

Run Transient Analysis–

Designers have an option to simulate either with or without noise

–

Simulate without noise for PLL large signal characteristics such as lock Time

–

Simulate with noise for phase noise and jitter

Create PLL

Testbench

Start ADE and Setup Test

Simulate

Transient

Analyze Results


PLL testbench using the PPV model

Cell: pll_bench

(custom veriloga) (PPV model)

(schematic)

(utility for freq output and saving periods.txt for phase noise/jitter calculation)

(power supply noise injection)

(LC tanknoise injection)


Model Overview

•

Noise-Aware PLL flow supports extraction and modeling of Voltage Controlled Oscillator, Phase/Frequency Detector, Charge Pump, Divider

•

VCO Model supports –

Single-ended VCO outputs.–

Sensitivity to Tuning Voltage, Positive Power Supply, and Negative Power Supply.

•

Phase/Frequency Detector and Charge Pump–

P/FD and CP are merged. .•

Divider model–

Divider noise is not extracted.–

The divider is merged into the VCO for faster simulation.•

Models are single-ended, voltage output levels•

Two types of models are generated–

CMI model will not be editable.–

Verilog-A model will be editable and designers will be able to extend the model themselves.


Non-Linear VCO Modeling

•

Why do we need nonlinear oscillator models?–

Oscillators are fundamentally nonlinear systems.–

Linear oscillator models often fail to accurately predict oscillation amplitude and phase

deviations under perturbations [1].

•

Nonlinear oscillator models

can capture the nonlinear dynamics of oscillators

such as injection locking, power supply interference, cycle slipping, …


Non-Linear VCO Modeling

•

Two main approaches are available and provide the same information:–

Impulse Sensitivity Function ISF ([1], [2], [3]).–

Perturbation Projection Vector PPV ([1], [4]).

•

The two models are tightly related by further observing the definitions of ISF and PPV. ISF defines the phase sensitivity to

state variables. PPV represents the time sensitivity to the state variables ([1], [6]).

•

PPV is a more mathematical and precise method of describing the VCO and is valid for all classes of oscillators contrarily to ISF ([5]).


Effect of Noise and Perturbation on an Oscillator

Steady-State

xs

(t)

Orbital

Deviation

Phase

Deviation

New State

x

(t)


Non-linear VCO PPV Model

•

α(t)

is the phase deviation due to perturbation of the VCO and satisfies the nonlinear differential equation.

•

Owing to the PPV, νT1

(t),

oscillator phase deviations due

to perturbations can be efficiently evaluated by solving the

one–

dimensional nonlinear differential equation (1). The PPV relates the changes in the circuit’s nodes voltages or

currents to the VCO phase.

( ) ( )tnt vT ∗=•

1α (10)


SpectreRF’s PPV-based VCO Model

•

SpectreRF’s PSS analysis calculates and outputs the PPV for an oscillator in a file stored in the simulation results directory.

•

SpectreRF uses the information about a VCO’s PPV to implement a trajectory-piecewise PPV model for the VCO.

[6]



Introduction


Advantages of SpectreRF flow versus other approaches


Conclusion


Strengths of SpectreRF Noise aware PLL flow

•

Significantly decreases simulation time compared to a traditional spice/fast spice transient approach:–

Even simple PLLs can require 2-3weeks when simulating with traditional SPICE simulators.

–

Complex PLLs can easily require 2-3 months.

•

Provides accuracy comparable to a traditional spice transient approach:–

The VCO dynamic behavior is fully captured by using a non linear model based on PPV.

•

Supports both Integer-N and Fractional PLLs


Strengths of SpectreRF Noise aware PLL flow

•

Calibrates the VCO and PFD/CP model automatically–

No behavioral modeling expertise required–

Models automatically generated during SpectreRF noise simulations

•

Provides an option to simulate either with or without noise: Simulate without noise for PLL large signal characteristics (Lock Time) or with noise for phase noise, jitter or injection pulling metrics.

•

Provides an option to look at PLL advanced metrics such as injection pulling or power supply noise rejection through ADE direct plot form.

•

Benefits from a tight SpectreRF integration using our Simulator Kernel Interface (SKI) allowing better simulation performances.



Introduction




Conclusion


Experimental Results using Cadence RFkit database

•

The test circuit used was a N-Integer 2.4 GHz PLL including a PFD, charge pump, VCO and divider available in Cadence RFKit ([8], [9]).

•

Using Cadence SpectreRF PLL flow (versions IC5141/MMSIM611), the phase noise was extracted for the PFD and VCO blocks to generate a phase-domain model for the entire PLL.

•

The closed-loop PLL behavior is then simulated using Spectre TRAN analysis and compared with transistor level simulation.–

Results generated on an IBM MPRO Linux 64 bits OS.

•

Additional metrics (Injection Pulling, power supply rejection) are directly evaluated


PPV versus transistor-level Settling time

Simulationresults

Spectre Transistor level

simulation

SpectrePPV CMI/VerilogA

simulation

Simulation Ratio

PPV Sampling*=1 46 hours(165.08Ks)

10.8 s 15285

PPV Sampling*=50 8 min 35s (515s) 320

*Sampling refers to the number of sample points per period. To calculate the phase accurately, the transient time step is bounded as ((1/(vco frequency)) / sample points per period

Experimental data extracted from PLL test circuit available in Cadence RF kit ([8] and [9])


PLL Noise-Aware Flow Experimental results

Impact on Injection Pulling and Power Noise supply on a N-

Integer PLL performance [10]

Impact of Injection noise pulling on phase noise:

Spurs in phase noise spectrum

Impact of Power Supply Noise rejection on PLL phase noise:No “beat”

freq generated (injection noise at 10M generates spur at 10M)


PLL Noise-Aware Flow Experimental results Same measurements were performed on a fractional PLL [10]. Phase Noise was obtained using ADE Direct Plot form

Impact of Injection noise pulling:Spurs in phase noise spectrum are present after noise injection



Introduction




Conclusion


Conclusions

•

Cadence SpectreRF Noise-aware PLL flow predicts the phase noise of a PLL-based frequency synthesizer using a simulation method that is both accurate and efficient.

•

For each block, the phase noise is extracted and applied to a phase-domain model for the entire PLL.VCO phase noise is accurately characterized using advanced perturbation technology (PPV).

•

Strengths of this flow (automatic calibration, greatly improved simulation time without loss of accuracy, direct plotting capability of PLL metrics) were presented.

•

Compared to traditional approaches, experimental data confirmed a significant speed-up with comparable accuracy.


References•

[1] Emad Hegazi, Jacob Rael, Asad Abidi. The Designer’s Guide to High-Purity Oscillators. Kluwer Academic Publishers, 2005

•

[2] Hajimiri A, Lee T H. A General Theory of Phase Noise in Electrical Oscillators. IEEE Journal of Solid-State Circuits, 1998, 33(2): 179~194

•

[3] Lee T H, Hajimiri A. Oscillator Phase Noise: A Tutorial. IEEE Journal of Solid-State Circuits,2002, 35(3): 326~336

•

[4] Demir A, Liu E W Y, and Sangiovanni-Vincentelli A L. Time-

domain non Monte-Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations. IEEE Transactions for Computer-

Aided Design, 1996, 15(5): 493~505•

[5] Vanassche P, Gielen G and Sensen W. On the Difference between Two Widely Publized Methods for Analyzing Oscillator Phase Noise Behavior. Proceeding IEEE/ACM ICCAD 2002


References•

[6] Automated oscillator macromodelling techniques for capturing

amplitude variations and injection locking “, X. Lai, J. Roychowdhury , ICCAD, 2004, 687-694

•

[7] “TP-PPV: Piecewise Nonlinear, Time-Shifted Oscillator Macromodel Extraction For Fast, Accurate PLL Simulation“, X. Lai, J. Roychowdhury , ICCAD, 2006

•

[8] Cadence RF kit user guide version 5.2.1, February 2007•

[9] Cadence RFIC design methodology kit workshop, version 5.2.1,

February 2007•

[10] SpectreRF Workshop Noise-Aware PLL Design Flow, MMSIM6.2, August 2007

using spectre rf noise-aware pll methodology to predict pll behavior accurately

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