using the sim spi function in the ht67f50 - holtek.com · spia transfer control flowchart sim spi...

Using the SIM SPI Function in the HT67F50

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D/N：AN0252E

Introduction

The HT67F50 includes an internal Serial Interface Module within which is included both

SPI and I2C interface types. There is also an additional SPIA function which is an

independent SPI function module. The following description depicts the way of using the

SPI in the HT67F50 for data transmission and any special considerations that must be

taken into account.

SPI Interface

The SPI is a full duplex synchronous serial data link which was originally developed by

Motorola and which allows communication with external devices. Using a master and

slave technique, only the master can initiate a transmission. A simple four line SPI

interface is used for all communication and all the SPI interface pins are pin-shared with

normal I/O ports.

The SPI in the SIM Module


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The SIM SPI interface is a full duplex synchronous serial data link, and is a four line

interface with pin names SDO (serial data output), SDI (serial data input), SCK (serial

clock) and SCS (slave select) that are pin-shared with the PC1, PC0, PA7 and PA6 I/O

pins. These pins can be changed using the SIMPS1, SIMPS0 bits in the PRM0 register. It

should be noted that the slave select is implemented using the CSEN bit in the SIMC2

register. If the CSEN bit is set, then the SCS pin will be active, otherwise it will be

floating if the CSEN bit is cleared to 0. The following timing figure describes the timing

protocol under the master/slave mode of the SPI bus.


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Independent SPI Module, the SPIA

The SPIA interface is a full duplex synchronous serial data link and has a four line

interface with pin names SDOA (serial data output), SDIA (serial data input), SCKA (serial

clock) and SCSA (slave select), pin-shared with PA3~PA0 I/O pins. It should be noted

that the slave select is determined by the SACSEN bit in the SPIAC1 register. If the

SACSEN bit is high, then SCSA will be active, otherwise SCSA will be floating when

the SACSEN bit is cleared to zero. The following timing figure describes the timing

protocol under the master/slave mode of the SPIA bus.


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Operating Description

SIM Module SPI function

The SPI interface pins in the SIM module are pin-shared with the I/O and I2C pins. The

system recognises that SDO is pin-shared with PC1, SDI with PC0 (or SDA in the I2C

mode) SCK with PA7 (or SCK in the I2C mode) and SCS with PA6. The common shared

I/O pins can be changed using the SIMPS1 and SIMPS0 control bits status in the PRM0

register as shown in the following table:

PRM0 Register

To enable the SPI function first configure the SIM Function as Enable and then setup the

SIMC0 and SIMC2 register values.


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There are three registers in the HT67F50 related to the SIM SPI function, SIMD, SIMC0

and SIMC2.

The SIMD register is the data register and is used to save data that is about to be

transmitted or has just been received. It is used by both the SPI and I2C functions in the

HT67F50 SIM module, either the SPI or I2C can be selected. To write data into the SPI

bus, it should be first placed in the SIMD register before transmission. After the data is

received from the SPI bus, the microcontroller can read it from the SIMD register. Any

transmission or reception of data from the SPI bus must be made via the SIMD register.

SIMD Register

The SIMC0 register is also used by both the SPI and I2C interface to enable or disable

the serial interface function and setup the SPI bus data transmission clock frequency.

SIMC0 Register

SIMEN：This bit is the overall on/off control for the SPI interface. When the SIMEN bit is

cleared to zero to disable the SPI interface, the SDI, SDO, SCK and SCS lines will be

in a floating condition and the SPI operating current will be reduced to a minimum

value. When the bit is 1, the SPI interface is enabled. The SIM configuration option

must have first enabled the SIM interface for this bit to be effective. Note that when the

SIMEN bit changes from 0 to 1, the contents of the SPI control registers will be in an

unknown condition and should therefore be first initialized by the application program. SIM0~SIM2：These bits setup the overall operating mode of the SIM function. As well

as selecting the I2C or SPI interface, they are used to control the SPI master/slave

selection and the SPI master clock frequency. The SPI clock is a function of the system

clock but can also be chosen to be sourced from TM0 CCRP Match divided by two. If

the SPI slave mode is selected then the clock will be supplied by an external master

device. Detailed information is shown as below:


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The PCKEN, PCKP1 and PCKP0 registers are used to control the external clock

outputs in which the PCLK pin is pin-shared with the PA6 port. The details can be

controlled by PCKPS1 and PCKPS0 bit in the PRM0 register as shown below:

PCKEN：This bit is the overall control of the external clock output.

PCKP0, PCKP1：Select the external clock output clock sources as follows:

The SIMC2 register is used both by the SPI and I2C interface. In the I2C mode, it is the

I2C serial transmission address register SIMA. In the SPI mode, it is the SPI serial

transmission control register.

SIMC2 Register

TRF：SPI transmission/receive complete flag. When the transmission or reception is

completed, it is set to “1” automatically but must be cleared by the application program. WCOL：In the master/slave mode, this bit is high if data has been attempted to be

written to the SIMD register during a data transfer and the writing operation will be

ignored. The WCOL bit can be enabled/disabled by configuration options. The WCOL

can be configured by hardware and cleared to zero by the application program.

CSEN：Enable/disable bit for the chip select pin. If CSEN=1, then the SCS chip select

pin will be valid. In the master mode, output a high on the SCS chip select before

issuing the SCK signals. In the slave mode, a data transfer will be disabled/enabled

before/after receiving the SCS signal. If CSEN=0, the SCS pin will be floating and

the pin chip select function invalid. An external pull-high resistor can be connected to

the SCS pin to implement this function. The CSEN bit can be enabled or disabled via

a configuration option. MLS：This selects either the MSB or LSB bit.

CKEG and CKPOLB：These two bits must be configured before any data transfers are

executed otherwise an erroneous clock edge may be generated. The CKPOLB bit

determines the base condition of the clock line, if the bit is high then the SCK line will

be low when the clock is inactive, the opposite is true if the bit is high. The CKEG bit

determines the active clock edge type which depends on the condition of CKPOLB.

The following shows the condition of the combination of the two bits.


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Independent SPI Module – the SPIA

The SPIA interface is pin-shared with the I/O lines. SDOA is pin-shared with PA3, SDIA

with PA2, SCKA with PA1 and SCSA with PA0. To enable the SPIA function, first

configure the SPI1 option as Enable and then setup the SPIAC0 and SPIAC1 register

values.

There are three registers associated with the SPIA function, SPIAD, SPIAC0 and SPIAC1.

These registers are corresponded with the SIM SPI related registers as shown in the

following table:

SIM SPI SPIA

Register Register

SIMD → SPIAD

SIMC0 → SPIAC0

SIMC2 → SPIAC1

The main difference from the SIM SPI registers is that the SPIA registers are independent

and have no connection with the I2C function.

The SPIAD register is used to store the data to be transmitted or data which has just been

received. Data transmitted and received by the SPIA bus must be placed into the SPIAD

register.

SPIAD Register

The SPIAC0 register is used to enable/disable the serial interface function and setup the

SPIA bus data transmission clock frequency.

SPIAC0 Register

SPIAEN

This bit controls the overall on/off function of the SPIA interface. When this bit is

cleared to zero, the SPIA interface will be disabled, which is similar to the SIMEN

control bit in the SIM SPI interface.


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SASPI2~SASPI0

These bits are used to setup the SPIA operation mode by selecting either the master or

slave mode. The master clock frequency can be the system clock or be chosen to be

sourced from the Timer Modules. If the SPI Slave Mode is selected then the clock will

be supplied by an external Master device. Detailed information is shown below:

SPIAC1 is the SPIA serial transmission control register.

SPIAC1 Register

SATRF

Transmission/receive complete flag. When data transmission is completed, it will be

set to 1 automatically but must be cleared to zero by the application software.

SAWCOL

In the master/slave mode, during a data transfers, the SAWCOL bit will be set if write

operations to the SPIAD register are attempted. The SAWCOL function can be

enabled or disabled through a configuration option. It is set high by the microcontroller

firmware but only cleared to zero by the application program.

SACSEN

The serial interface select chip enable/disable bit. If SACSEN=1, then the SCSA pin

is effective. In the master mode, output the SCSA pin should be managed before the

SCK signals are generated, while in the slave mode, a data transfer will be

disabled/enabled before/after the SCSA signals are received. If SACSEN=0, the

SCSA pin will be placed into a floating state and the function disabled. A pull-high

resistor should be connected to the SCSA pin to implement this function. The

SACSEN bit can be enabled or disabled via a configuration options.

SAMLS

Selects either MSB or LSB.

SACKEG and SACKPOL

These two bits must be configured before any data transfers are executed otherwise

an erroneous clock edge may be generated. The SACKPOL bit determines the base

condition of the clock line, if the bit is high then the SCK line will be low when the clock

is inactive, the opposite is true if the bit is high. The SACKEG bit determines the active

clock edge type which depends on the condition of SACKPOL. The following shows

the condition of the combination of the two bits.


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S/W Flowchart

SIM SPI Transmission Control Flow:

SPI Transfer Control Flowchart


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SPIA Transmission Control Flow:

SPIA Transfer Control Flowchart

SIM SPI Operation

In the Master/Slave Mode, all communication can be implemented by the SPI function.

The timing figure depicts the basic operation of the SPI function. During an SPI transfer,

the Master device, before sending an SCK signal, will select a Slave device by sending

an SCS signal. When CSEN=0, an external pull-high resistor should be added to the

SCS line. In the Slave Mode when SCS =1, SDO will be in a floating condition and when

SCS =0, SDO will be effective. When CSEN=0, whatever condition the SCS is in (high

level or low level) as long as SIMEN=1, the SPI will be effective. Setting the SIMEN bit in

the SIMC0 register high will force the SDI pin to a floating condition and the SDO pin high.

The SCK pin will be in a floating condition in the Slave Mode. If the SIMEN bit is cleared

to 0, then the SPI bus will be disabled, and the SCS , SDI, SDO and SCK pins will all be

placed into a floating condition. In the Master Mode, the clock signal is always generated

by the master device. Clock and data transfers will be activated after data is written to the

SIMD register. In the Slave Mode, data transmission/reception will be enabled by the

clock signal of the external master device. The following steps show the data transfer

order in the Master/Slave Mode.


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Master Mode

Step 1

Initialize the program. Set the SIM0~SIM2 bits in the SIMC0 register to select the

Master Mode and the required serial transmission rate.

Step 2

Set the CSEN and use MLS bits to decide whether the data starts from the low or high

bit. The Slave must correspond with the master device.

Step 3

Set the SIMEN bit in the SIMC0 register to enable the SPI interface.

Step 4

Write data to the SIMD and check WCOL. If WCOL=1 then a collision has occurred and

jump to Step 4. If WCOL=0 then jump to Step 5.

Step 5

Output CLK signal and SIMD data signal→ use SDO pin for data output→ jump to Step

6

Step 6

Check TRF or wait for SPI serial function interrupt.

Step 7

Read data from the SIMD register.

Step 8

Clear TRF

Step 9

Return to Step 4

Slave Mode

Set the SIM0~SIM2 bit to 101 to select the Slave Mode

Step 2

Set the CSEN and use MLS to decide whether the data starts from the low or high bit.

The slave should correspond with the master device.

Step 3

Set the SIMEN bit in the SIMC0 register to enable the SPI interface.

Step 4

Write data to SIMD, check if WCOL. If WCOL=1 then a collision has occurred and jump

to Step 4. If WCOL=0 then jump to Step 5

Step 5

Wait for master clock and SCS signal→ use the SDO pin for data output → jump to

Step 6

Step 6

Check TRF or wait for the SPI serial function interrupt

Step 7

Read data from the SIMDR register.

Step 8

Clear TRF

Step 9

Return to Step 4


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SPIA Operation

The SPIA and SIM SPI operation are similar and no further description is provided here.

SPI Configuration Option

Some configuration options must be set to enable certain register bits for the SPI

interface function. One option in the SIM SPI configuration is to enable the WCOL bit

which is the data collision bit in the SIMC2 register. The other is used to disable or enable

the CSEN bit in the SIMC0 register. If the CSEN bit is disabled by configuration option,

none of the SPI function control will be affected by the CSEN register bit. The WCOL bit

in the SIMC2 register is used to detect data collisions during data transfer. During data

transmission if any attempt is made to write data to the SIMD register, the WCOL bit will

indicate a data collision and disable further write operations. The WCOL bit will be set by

the hardware but should be cleared to zero by the application program. The WCOL bit

can be disabled or enabled by a configuration option.

Similarly, when using the SPIA, the corresponding line select should be all enabled.

Special Notes for the Program

When using the SIM SPI, the common pin configuration should be noted. For example,

when using the four line transmission SPI pins, the SDI and SDO pins are pin-shared

with PC0 and PC1, while they are also shared with TP1B0 and TP1B1. Set

TP1B1PS~TP1B0PS=11 for TP1B0, TP1B1 to be pin-shared with PD4, PD3 and thus

implement the SPI data transmission function. When using the SPIA, set C0SEL=0,

C0OS=1 to implement the SPIA data transmission.

Program Description

The example here uses two HT67F50 ICs to implement the SPI full duplex data

transmission by individually setting the SIM SPI and SPIA as the master and slave

devices. The master/slave device is determined by the I/O status as shown in the

following table:

I/O Status I/O Status

HT67F50 SIM-SPI

HT67F50 SPIA

HT67F50 SIM-SPI or SPIA

PB7 PB7

Master/Slave Transmission Status

PE Port PF Port

1 0 SIM SPI as master, SPIA as slaveTransmitted data

input port Received data

output port

0 1 SIM SPI as master, SPIA as slaveTransmitted data

input port Received data

output port


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The example here is composed of a main program and an SPI service program. The

main program will initialize the MCU, especially the initialization of the relevant SPI

registers.

The spi_Transmission in the SPI service program will send data in PE to the SPI bus and

save data from the SPI bus to PF for users to modify. The spia_Transmission subroutine

in the SPIA will send data in PE to the SPIA bus and then save it to the PE for the users to

modify.

In the configuration options, enable the SIM function, WOCL and CSEN bits before using

the SIM SPI bus. Enable SPI1, SPI1 WOCL and SPI1 CSEN bits before using the SPIA

bus. Other options depend on the actual requirements of the user.

Program Example

SIM SPI Master/Slave Input/Output Program Configuration Option： OSC: HIRC, Filter OFF Internal RC： 4M@Vdd= 5V SIM Function: SIM enable(SPI/I2C) SPI S/W WCOL: Enable SPI S/W CSEN : Enable ;other option select by user.

Program code and description: see the attached file.

The corresponding SPIA Master/Slave Input/Output Program Configuration Option： OSC: HIRC, Filter OFF Internal RC： 4M@Vdd= 5V SPI1: Enable SPI1 WCOL: Enable SPI1 CSEN : Enable ;other option select by user.

Program code and description: see the attached file.

Conclusions

This application has provided an operational description and special considerations

regarding the SPI in the HT67F50 using the HT67F50 SIM SPI and HT67F50 SPIA setup

as master and slave devices for a SPI full duplex data transmission link. Users may insert

the related IP directly into their own programs and modify the program according to their

actual requirement with the description provided above. The SIM SPI and SPIA programs

are enclosed.

using the sim spi function in the ht67f50 - holtek.com · spia transfer control flowchart sim spi...

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