HW/SW Co-design

Design of Embedded SystemsJaap HofstedeVersion 3, September 1999

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Embedded Systems

Embedded system is a computer system (combination of hardware and

software) is part of a larger system (that may or may not be a

computer)performs a fixed function for that system

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SW or HW?

Software

FlexibilityLate design changes

FeaturesReuse

Reduced time to market

Hardware

PerformanceLow power(Security)

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Applications

Relatively small systemsConsumer electronicsConsumer productsAutomobilesTelecommunicationComputer peripheralsCopiers, FAX machinesMultimedia systems

Relatively large systemsAirplanesIndustry

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Classes of embedded systems

Reactive(Control Dominated)

State

Real-time

Transforming(Data Dominated)

Digital Signal Processing(DSP)

Limited functionality, butvery fast

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Cost

Main parts of cost

Initial costProduct costTime to market

Design is a trade-off

CostDesign timePerformance

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Technological developments

Number of transistors: 35%Clock speed: 25%Processor performance: 50%

Design Capacity: only about 20%

What to do with all those transistors?Integrate several functionsProgrammable processorsROM for Programs for these processors

Gap is growing

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Classes of embedded systems

Standard microprocessor or DSP with separate RAM,ROM and interfaces

Standard microprocessor or DSP with ASIC or FPGAProcessor core integrated on ASIC or FPGAASIP

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Traditional design

To manage complexitySW and HW partitioning at an early stageHW and SW designed separately

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HW/SW Co-design

Specify, explore, refineFlexible design strategyHierarchy of models at

different abstractionlevels

HW and SW designedwith interaction andfeedback

Final partitioning afterevaluation of trade-offs

RequiresCo-specificationCo-development (Co-

synthesis)Co-verification

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Goals

Reduced time to marketBetter productsLower development costsLower number of design cyclesHigher level of abstractionVolume specific targets

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Tools

Design frameworkCommon specificationsSilicon compilersSoftware compilersReal-time kernelsSimulatorsAnalysis tools

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Disciplines

Application domainSpecification and programming languagesCompilers (!)VLSI designParallel/distributed systemsReal-time systemsFormal methods(Performance) analysis

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Specification

Provide clear and unambiguous descriptionAllow CAD toolsShould not constrain implementation in either SW or HWTo be compiled to other languages for HW (VHDL) or

SW (C)Executable to verify if requirements are met

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Computation models

Control dominatedFinite State Machines

(FSM)Communicating

Sequential Processes(CSP)

Discrete event models(VHDL)

Petri nets

Data dominatedControl flow graphsData flow graphsControl/Data flow graphs

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Co-simulation

Simulation of systems witha mix of different kinds ofSW and HW components

LevelsHigh abstractionInstructionsASIC modelsGateSwitchAnalogue

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Compilers

Front-end(target independent)

ScanningParsingStatic semantic analysisOptimization

Back-end(source independent)

OptimizationCode generation

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Code generation

Currently often separateCharacteristics of DSPs and ASIPs make these three

subtasks mutually dependentCoupling necessary for generation of optimal code

1. Instruction selection2. Register allocation3. Instruction scheduling

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Characteristics of DSPs

HarvardMultiple busses with restricted connectivityHigh I/O-rateIrregular register sets of different sizesSpecial purpose registersSpecial registers for zero-overhead loopsMultiply-add-accumulate in one instructionFixed-point operationsHardware supported addressing modes

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Example: Data path ADSP210x

MR

MFMX MY

*+,-

AR

AFAX AY

+,-,..

DP

yi-1[j]

x[j-i]

x[j-i]*a[i]

a[i]

Addressgeneration unit(AGU)

Address-registersA0, A1, A2 ..i+1, j-i+1

ax

i: 0i n: yi[j] = yi-1[j] + x[j-i]*a[i]

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Compiler back-ends for DSPs

Very hard to generate sufficiently efficient code

Intensive optimization requiredCoupling of three subtasksLong compilation time acceptable

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Compiler back-ends for ASIPs

ASIPs often have characteristics of DSPsSpecific code generator requiredRetargetable code generatorsCode generator must be generated automatically from

description of processorFrom register description and instruction set (behavior)From structure of ASIP data path as generated by high level

synthesis (structure)