FPGA PIANO USING VHDL On Xilink Sparta Board

Jasmine A. Roberts Columbia University, Electrical Engineering

Roberts, FPGA Piano Using VHDL

ABSTRACT

The main intention of the project was to implement an electric piano on a Spartan 3 development board using Xilinx Integrated Software Environment. The hardware was done using VHDL encoding. By use of a piezoelectric speaker with moderately high impedance, the piano was driven directly from the FPGA. Switches output four-bit digital logic code transferred to FPGA. The VHDL description is synthesized to logic and the 8 notes corresponding to the C scale in global music theory, and mapped to the gates of the FPGA.

INTRODUCTION

The notes are encoded on switches by the following segment of code:

when "10000000" -- C when "01000000" -- D when "00100000" -- E when "00010000" -- F when "00001000" -- G when "00000100" -- A when "00000010" -- B

when others none

The clock used is a 50 MHz input clock, the following are the waveforms on CLK_OUT and ONE_SHOT for EN = '1' and DIV = X"32". The toggle and trigger waveforms are also presented

Frequency =CLK

DIV 5

DIV=X32=50, CLK=50MHz, f=0.5 MHz

With a frequency of 0.5 MHz for CLK_OUT

CLK_OUT ________________ _________ TRIGGER ____-___-____-___-____-___-____-___-____-___-____-___

TOGGLE ________________ _________ ONE_SHOT ________-________-_______-________-_______-________

For a 1MHz input, the output frequency as a function of divider value is . These values were verified with the values used for the note decoder to define the notes of the piano.

f = CLK / DIV * .5 ONE_SHOT frequency = F/2

when "00001" => next_div next_div next_div next _div next_div next_div next_div next_div next_div next_div next_div

Roberts, FPGA Piano Using VHDL

when " 01100" => next_div next_di v next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div

Roberts, FPGA Piano Using VHDL

Roberts, FPGA Piano Using VHDL

This design plays a few measures of Part of Your World from Disneys The Little Mermaid. The user interface was deleted (commented out so it could still be referenced to the encode notes) and played the output note from play_position to the signal note_select in piano.vhd.

The notes are played at the latch output in note_play.vhd. A cascade of elseif statements executes the notes. Contained within the elsif statement are pointers to the notes found in the note lookup table. The tempo of the song was controlled by the frequency in hexadecimal. A half-note is one second, and is implemented by adding 50MHz to the previous signal. A quarter-note is implemented by adding 25MHz, a whole-note by adding 100MHz.

Ideally, quarter-note triplets should be executed by incrementing by 16 ( 50/3), unfortunately, when a design using quarter-note triplets was implemented, the output was muddled. Therefore, an easier tempo was implemented. The solution would be to increase the speed of the clock used to count through the notes. The notes corresponding to the measure played are B A F C B A F C C E F.

CODE

PIANO.VHD -- -- piano.vhd - FPGA Piano -- library IEEE; use IEEE.STD_LOGIC_ 1164 .ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.a ll; entity piano is port ( CLK_IN : in std_logic; pb_in : in std_logic_vector(3 downto 0); switch_in : in std_logic_vector( 7 downto 0); SPK_N : out std_logic; SPK_P : out std_logic; led_out : out std_logic_vector( 7 downto 0); digit_out : out std_logic_vector( 3 downto 0); seg_out : out std_logic_vector(7 downto 0)

Roberts, FPGA Piano Using VHDL

); end piano; architecture Behavioral of piano is -- Xilin x Native Components component BUFG port ( I : in std_logic; O : out std_logic); end component; component IBUFG port ( I : in std_logic; O : out std_logic); end component; component IBUF port ( I : in std_logic; O : out std_logic); end component; component OBUF port ( I : in std_logic; O : out std_logic); end component; component DCM port ( CLKIN : in std_logic; CLKFB : in std_logic; RST : in std_logic; PSEN : in std_logic; PSINCDEC : in std_logic; PSCLK : in std_logic; DSSEN : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLKDV : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; STATUS : out std_logic_vector ( 7 downto 0); LOCKED : out std_logic; PSDONE : out std_logic); end component; -- My Components: -- Clock Divider component clk_dvd port ( CLK : in std_logic; RST : in std_logic; DIV : in std_logic_vector( 15 downto 0); EN : in std_logic; CLK_OUT : out std_logic; ONE_SHOT: out std_logic ); end component; -- Note decoder component note_gen port ( CLK : in std_logic; RST : in std_logic; NOTE_IN : in std_logic_vector( 4 downto 0); DIV : out std_logic_vector( 15 downto 0) ); end component;

Roberts, FPGA Piano Using VHDL

-- 7-Segment Display for Notes component seven_seg port ( CLK : in std_logic; RST : in std_logic; NOTE_IN : in std_logic_vector( 4 downto 0); SCAN_EN : in std_logic; DIGIT : out std_logic_vector( 3 downto 0); SEG : out std_logic_vector( 7 downto 0) ); end component; -- Signals signal CLK : std_logic; -- 50MHz clock after DCM and BUFG si gnal CLK 0 : std_logic; -- 50MHz clock from pad signal CLK_BUF : std_logic; -- 50MHz clock after IBUF signal GND : std_logic; signal RST : std_logic; signal PB : std_logic_vector( 3 downto 0); -- Pushbuttons after ibufs signal digit_l : std_logic_vector( 3 downto 0); -- 7-seg digit MUX before obuf signal switch : std_logic_vector(7 downto 0); -- Toggle switches afte r ibufs signal led : std_logic_vector( 7 downto 0); -- LEDs after ibufs signal seg_l : std_logic_vector( 7 downto 0); -- 7-seg segment select before obuf. signal one_mhz : std_logic; -- 1MHz Clock sig nal one_mhz_ 1 : std_logic; -- pulse with f= 1 MHz created by divider signal clk_ 10k_ 1 : std_logic; -- pulse with f= 10kHz created by divider signal div : std_logic_vector(15 downto 0); -- variable clock divider for loadable counter signal note_in : std_logic_vector( 4 downto 0); -- output of user interface. Current Note signal note_next : std_logic_vector( 4 downto 0); -- Buffer holding current Note signal note_sel : std_logic_ve ctor( 3 downto 0); -- Encoding of switches. signal div_ 1 : std_logic; -- 1MHz pulse signal sound : std_logic; -- Output of Loadable Clock Divider. Sent to Speaker if note is playing. signal SP K : std_logic; -- Output for Speaker fed to OBUF begin GND

Roberts, FPGA Piano Using VHDL

process (div, sound) begin if (div = x"0000 ") then SPK SPK_N); SPK_P pb_in(i), O => PB(i)); dig_obuf : OBUF port map(I => digit_l(i), O => digit_out(i)); end generate ; loop 1 : for i in 0 to 7 generate swt_obuf : IBUF port map(I => switch_in(i), O => switch(i)); led_obuf : OBUF port map(I => led(i), O => led_out(i)); seg_obuf : OBUF port map(I => seg_l(i), O => seg_out(i)); end generate ; -- Global Clock Buffers -- Pad -> DCM CLKIN_IBUFG_INST : IBUFG port map (I=>CLK_IN, O=>CLK0); -- DCM -> CLK CLK0_BUFG_INST : BUFG port map (I=>CLK_BUF, O=>CLK); -- DCM for Clock deskew and frequency synthesis DCM_INST : DCM port map (CLKFB=>CLK, CLKIN=>CLK0, DSSEN=>GND, PSCLK=>GND, PSEN=>GND, PSINCDEC=>GND, RST=>RST, CLKDV=>open, CLKFX=>open, CLKFX180 =>open, CLK0=>CLK_BUF, CLK2X=>open, CLK2X180=>open, CLK90=>open, CLK180 =>open, CLK270 =>open, LOCKED=>led( 0), PSDONE=>open, STATUS=>open );

Roberts, FPGA Piano Using VHDL

-- Divide 50Mh z to 1Mhz clock DIV_ 1M : clk_dvd port map ( CLK => CLK, RST => RST, DIV => x"0019 ", -- 25 EN => 1, CLK_OUT => one_mhz, ONE_SHOT => one_mhz_1 ); -- Divide 1Mhz to Various frequencies for the notes. DIV_NOTE : clk_dvd port map ( CLK => CLK, RST => RST, DIV => div, EN => one_mhz_ 1, CLK_OUT => sound, ONE_SHOT => div_ 1 ); -- Divide 1Mhz to 10k DIV_ 10k : clk_dvd port map ( CLK => CLK, RST => RST, DIV => x" 0032 ", -- 50 EN => one_mhz_ 1, CLK_OUT => open, ONE_SHOT => clk_ 10k_ 1 ); -- Translate Encoded Note to clock divider for 1MHz clock. note_g en_inst : note_gen port map ( CLK => CLK, RST => RST, NOTE_IN => note_in, DIV => div ); -- Wire up seven -seg controller to display current note. seven_se g_inst : seven_seg port map ( CLK => CLK, RST => RST, NOTE_IN => note_in, SCAN_EN => clk_ 10k_ 1, DIGIT => digit_l, SEG => seg_l ); -- User Interface note_in note_sel note_sel

Roberts, FPGA Piano Using VHDL

when " 00100000 " => note_sel note_sel note_sel note_sel note_sel note_sel note_sel

Roberts, FPGA Piano Using VHDL

DIV

Roberts, FPGA Piano Using VHDL

end if; end process; -- Lookup Table process (NOTE_IN) begin case NOTE_IN is when " 00000 " => next_div next_div next_div next_div next_div next_ div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div next_div