virtual prototyping and electrical signoff for the pcb ...mentorg.com.cn/download/2015/05 - virtual...
TRANSCRIPT
Virtual Prototyping And Electrical Signoff For The PCB Engineer
www.mentor.com © Mentor Graphics Corp. Company Confidential
Agenda
The electrical signoff challenge
Optimizing a virtual prototype process
2
www.mentor.com © Mentor Graphics Corp. Company Confidential
High-speed Design Trends
TLA2014 snapshot — 86% designed for SI
– 92% of winning designs – All computer, consumer,
telecoms designed for SI — 74% designed for PI — Largest % nets high-speed: 97% — SI up 5%; PI up 15% over 2010
3
www.mentor.com © Mentor Graphics Corp. Company Confidential
Signoff is a process of verification that a design must complete before it can be sent to manufacturing
What Is Electrical Signoff?
Terminology used in the IC space for years
Increasing use in the PCB domain
4
www.mentor.com © Mentor Graphics Corp. Company Confidential
Your Design Likely Has a Problem (How do you find it?)
Even If You Simulate…
• Do you simulate every net? • Do you consider EMI? • Do you analyze the PDN?
5
www.mentor.com © Mentor Graphics Corp. Company Confidential
Design Guideline Compliance the Hard Way
Visual Inspection
Design guideline interpretation Design guideline deviations
Low coverage Time consuming Error prone
Final Signoff
SI/EMC Expert
6
Bottleneck
www.mentor.com © Mentor Graphics Corp. Company Confidential
High Speed Design Paradigm Shift Everything Must be Verified
Need improved electrical signoff process
– Remove signoff bottleneck
– Better design guideline compliance checking
– Higher analysis coverage
– Higher percentage of nets
– Details that cannot be simulated
―At 28gbps the domain is the entire board... everything messes with everything else‖
Scott McMorrow, Teraspeed Consulting Group From DesignCon 2014 Panel
7
www.mentor.com © Mentor Graphics Corp. Company Confidential
Automating Electrical Signoff Encapsulate and Deploy Design Guidelines and Expert Know-How
Out-of-the-box and/or custom
rules
Secure Deployment
Encrypted HL DRC rule set
• Reliable • Reusable • Repeatable
Implementation, checking & signoff
PCB/HW Designers
SI/EMC Expert
8
www.mentor.com © Mentor Graphics Corp. Company Confidential
HyperLynx DRC - Electrical Rule Checking
Design rule checks
– Automates design checks, eliminating errors from manual inspection
– Reduces days of manual design checks to a few hours
Includes built-in rules
– Design rule checks for EMI, SI, PI
– Items not quickly/easily simulated
Allows for rule customization
– Easily access database objects through automation
– Advanced geometric operations
– Script writing/debugging environment
9
www.mentor.com © Mentor Graphics Corp. Company Confidential
HyperLynx DRC Driven Electrical Signoff
Design Entry
SI/PI Analysis Constraints Entry
Minimize problems found in signoff
Minimize signoff bottleneck
Layout
EMI/EMC errors
Signoff
PI errors
SI errors SI simulation
Rule Set
PI simulation
In Process Checking
Existing Constraints
HyperLynx DRC
10
www.mentor.com © Mentor Graphics Corp. Company Confidential
HyperLynx DRC Built-in DRCs
23 built-in DRCs included
– With editable parameters
– Adaptable to any design
EMI examples
– Traces crossing splits, reference plane changes
– Nets near edge, coupling to I/O nets
SI examples
– Long nets (SI risk), termination check
– Impedance changes on net
PI examples
– Power net width
– Decoupling cap proximity
11
www.mentor.com © Mentor Graphics Corp. Company Confidential
Concurrent Electrical Rule Check in Layout
Subject matter experts create their own rule sets
– Using built-in/custom rules
– Appropriately adjust parameters
– Encapsulating their design expertise
HyperLynx DRC launched remotely using experts’ setup
HyperLynx DRC feeds hazards back into layout
– Necessary layout changes are highlighted and can be corrected
12
www.mentor.com © Mentor Graphics Corp. Company Confidential
Mentor has the Total Signoff Solution
Layout rules validation (HyperLynx DRC)
– Mitigate SI/PI/EMI issues early-on, accelerate the design cycle
Electromagnetic compatibility (HyperLynx DRC)
– Product will not radiate excessively or be overly sensitive to external radiation
Signal integrity and timing
– High-speed signaling (HyperLynx GHz, Nimbic, DRC)
– Memory (HyperLynx DDR Wizard)
Power integrity (HyperLynx PI, DRC)
– PDN effectively and efficiently delivers required power
Manufacturability (Valor)
– Product can be physically produced with high yield
Thermal compliance
– Fast thermal analysis (HyperLynx Thermal)
– Detailed thermal w/enclosure (FloTHERM)
13
www.mentor.com © Mentor Graphics Corp. Company Confidential
Electrical Signoff Flow
Design Entry
SI/PI Analysis Constraints Entry
Minimize problems found in signoff
Minimize signoff bottleneck
Layout
EMI/EMC errors
Signoff
PI errors
SI errors SI simulation
Rule Set
PI simulation
In Process Checking
Existing Constraints
HyperLynx DRC
14
HyperLynx - Nimbic
www.mentor.com © Mentor Graphics Corp. Company Confidential
3D Electromagnetic Field Solver Modeling
Intuitive, scripted GUI specifically for die/package/PCB structures
Direct import of all major layout databases
Automated cropping and simplified port setup
Powerful reporting and viewing of results
Package / PCB Design Entry
Electric / Magnetic Field Current Density
Extracted Circuit S-parameters
Electromagnetic Simulation
SPICE
Waveforms, Eye Diagram
Chip Design
www.mentor.com © Mentor Graphics Corp. Company Confidential
Vias, multi-Gbps interconnect, and EMI: Full-wave
Fast full package model: Quasistatic
Power delivery network and power-aware SI: Hybrid SI/PI
Nimbic Solver Technologies
16
www.mentor.com © Mentor Graphics Corp. Company Confidential
Nimbic 3D Full-wave Broadband Solver 40 GHz Correlation
• 8 Layer PCB
• Published measurement data for Via Transitions up to 40 GHz, hard to model via/plane interaction
• Excellent correlation with Measurement data [Ref] of (a) S11 (b) S12 for 1000 frequency points
[Ref] G. Selli, C.Schuster, Y.H.Kwark, M.B. Ritter and J.L. Drewniak, "Developing a Physical Model for Vias - Part II: Coupled and.Ground Return Vias", Proc. of DesignCon 2007, Jan.29-Feb.1 2007, Santa Clara.
17
www.mentor.com © Mentor Graphics Corp. Company Confidential
Nimbic Quasistatic Fast Package Extraction
• 16 level stacked-die complex package
• S-parameter extraction with full-wave and quasistatic
• Excellent correlation (quasistatic to 2GHz)
Reference Solution
Nimbic Full-wave
Nimbic Quasistatic
Time 80h 20h 9 min
Memory 120GB 40GB 6GB
18
www.mentor.com © Mentor Graphics Corp. Company Confidential
Integration with HyperLynx SI/PI
2H2015
HyperLynx 9.3 • HyperLynx LineSim Ghz
• 3D Via Solver • HyperLynx BoardSim
• Export 3D extracted model to LineSim • Series component support • Export area to Nimbic
HyperLynx 9.3/9.4 • HyperLynx PI
• Trace routed power • Improved capture of 3D effects
Powered by
19
www.mentor.com © Mentor Graphics Corp. Company Confidential
HyperLynx LineSim – Nimbic Integration
Integrated 3D full wave via solution
View 3D model in Nimbic full-wave
20
www.mentor.com © Mentor Graphics Corp. Company Confidential
HyperLynx BoardSim – Nimbic Integration
Select/filter for nets of interest
Create target 3D area
21
www.mentor.com © Mentor Graphics Corp. Company Confidential
HyperLynx BoardSim – Nimbic Integration
Port names automatically created
Choose ports
22
www.mentor.com © Mentor Graphics Corp. Company Confidential
HyperLynx BoardSim – Nimbic Integration
Export 3D circuit to Nimbic
23
www.mentor.com © Mentor Graphics Corp. Company Confidential
HyperLynx BoardSim – Nimbic Integration
Ports automatically created
– Based on HyperLynx BoardSim assignments
24
www.mentor.com © Mentor Graphics Corp. Company Confidential
HyperLynx BoardSim – Nimbic Integration
Solve the structure
25
www.mentor.com © Mentor Graphics Corp. Company Confidential
HyperLynx BoardSim – Nimbic Integration
Detailed debug in HyperLynx LineSim
– Includes 3D circuit s-parameter model
26
www.mentor.com © Mentor Graphics Corp. Company Confidential
27
www.mentor.com © Mentor Graphics Corp. Company Confidential
28
www.mentor.com © Mentor Graphics Corp. Company Confidential
29
www.mentor.com © Mentor Graphics Corp. Company Confidential
HyperLynx PI Decoupling – Nimbic Integration (9.4)
Trace routed power support for AC analysis
Improved capture of 3D effects
Coplanar coupling between power nets
30
www.mentor.com © Mentor Graphics Corp. Company Confidential
HyperLynx Accuracy & Performance
31
20X faster with same accuracy as H-Spice
Fujitsu recommends HyperLynx with design kits
– DDR4 power-aware models, reference boards
―We validated Mentor’s power-aware SI solution with a complex DDR4 system design using IBIS 5.0 models. We were able to achieve excellent correlation with transistor-level model with a 95% reduction in simulation time.‖ Atsushi Sato, Fujitsu Semiconductor
www.mentor.com © Mentor Graphics Corp. Company Confidential
Introducing HyperLynx DRC Into Ecosystems
32
– Cell phone chipset leader
– Reference designs
– Design verification services
Automates design verification
– Intelligent design guidelines
– Eliminated manual checking
– 40+ custom rules
Reduces verification time
– Eliminates bulk simulation
– Reduces results interpretation
www.mentor.com © Mentor Graphics Corp. Company Confidential
Signoff Summary
PCB design needs to be done right the first time
Compliance with requirements is the way to validate a successful PCB design
The ―signoff‖ concept has been used to reduce risk in IC design
PCB signoff is here today
– HyperLynx SI/PI simulation
– With Nimbic solver technology
– HyperLynx DRC verification
33
www.mentor.com © Mentor Graphics Corp. Company Confidential
HyperLynx Based Electrical Signoff
Accelerate Time to Electrical Performance Sign-off
– Reduce Time to Complete Final Design, Check, Signoff
– Reduce/Eliminate Design Iterations
– Find and Fix Hard to Locate Design Flaws
Improve overall design quality
– 100% Coverage for Catastrophic Errors
– Improved Design Margins Reduces Field Failure Rates
– Elevates Novice Engineers Results to Expert Levels
Lower Development Cost Structure
– Minimize Manual Checking Costs
– Minimize Design Respin Costs
– Minimize Engineering Costs due to Schedule Delays
– Reduced Field Failures Lowers Support/Debug Costs
34