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Virtuoso Multi-Mode Simulation comprises the following simulation engines:

• Virtuoso Spectre® Circuit Simulator

• Virtuoso Accelerated Parallel Simulator

• Virtuoso UltraSim Full-Chip Simulator

• Virtuoso AMS Designer

Cadence® Virtuoso® Multi-Mode Simulation combines industry-leading simulation engines to deliver a complete design and verification solution. It meets the changing simulation needs of designers as they progress through the design cycle—from architecture exploration to analog and RF block-level development and to final analog and mixed-signal full-chip verification.

V IRTUOSO MULTI-MODE SIMULATION

Figure 1: Virtuoso Multi-Mode Simulation offers complete SoC verification

Virtuoso Multi-Mode Simulation 7.1

MixedSignal

AMSDesigner

UltraSim APS

RF Analog

Spectre

Infrastructure Device Models MMSIM Tokens

http://www.cadence.com

2www.cadence.com VIRTUOSO MULTI-MODE SIMULATION

VIRTUOSO MULTI-MODE SIMULATIONVirtuoso Multi-Mode Simulation is a comprehensive design and verification solution that combines SPICE, RF, FastSPICE and mixed-signal simulators in a unique shared licensing package. This unified environment not only aids in the design and verification of analog, RF, memory, custom digital and mixed signal SoCs but also address the simulation requirements for all application ICs.

Virtuoso Multi-Mode Simulation delivers a variety of analysis and measurements in a flexible access model to provide designers with the appropriate technology tailored for each phase of their design flow (see Table 1 for details):

• VirtuosoSpectreCircuitSimulatorLforblock-level analysis that includes, accurate transient, DC, AC, noise, S-parameters, and statistical analysis

• VirtuosoSpectreCircuitSimulatorXLfor analog turbo simulation of pre-layout designs, RF steady state, periodic noise and envelope analysis and Noise-Aware PLL analysis

• VirtuosoSpectreCircuitSimulatorGXLfor RF simulation with “Turbo” technology and turbo post-layout verification

• VirtuosoParallelAcceleratorSimulatorfor complex and large post-layout analog/RF designs

• VirtuosoUltraSimFull-ChipSimulatorLfor block-level FastSPICE verification

• VirtuosoUltraSimFull-ChipSimulatorXLforfullchip-levelFastSPICEverification

• VirtuosoAMSDesignerformixed-signaldesign and verification

These simulation engines support a common syntax, use common device model equations, and are fully integrated into the Virtuoso Analog Design Environment and the Cadence Incisive® Logic Design and Verification flow. The complementary feature sets

L XL GXL

Virtuoso Accelerated Parallel Simulator

Large and complex analog/RF and mixed signal blocks and subsystem SPICE simulation

Analog/RF and mixed signal post-layout verification

Multi-threading on multi-core machines

Virtuoso Spectre Circuit Simulator

Analog/Mixed signal block designs

Comprehensive Analysis

RF analysis verification

MATLAB Interface

Analog Turbo functionality

Analog Turbo Postlayout verification

RF Turbo functionality

Virtuoso Ultrasim Full-chip Simulator

Analog/Mixed Signal Verification

Full-Chip Verification

•CustomDigital

•Postlayout

•RelabilityAnalysis

Virtuoso AMS Designer with Flexible Analog Simulation


and

Virtuoso Spectre L or Virtuoso Ultrasim L


and

VirtuosoSpectreXLor Virtuoso Ultrasim XL

Table 1: Virtuoso Multi-Mode Simulation features

of these simulators not only improve productivity but also facilitate adoption as designs move through the architecture, implementation, and verification stages—and as simulation needs change (refer to Figure 1).

BENEFITS • Increasesdesignqualityusingsilicon-

accurate device models shared by all simulators and universally supported by all foundry process design kits

• Sharedsyntaxacrossallenginesminimizes translation when moving between design domains

• TightVirtuosoAnalogDesignEnvironment interfaces—with common use model, cross-probing, and back-annotation capabilities—ensure fast adoption

• TightIncisiveLogicDesignEnvironmentinterfaces—with common use model, debugging, waveform viewing, and language support—ensure fast adoption

• OptimizesanalogandRFsimulation

– Accurate SPICE-level simulations with Virtuoso Spectre Circuit Simulator L

– Turbo pre-layout simulation with multi-threading for a significant performance gain over traditional



SPICE-level simulators using Virtuoso SpectreCircuitSimulatorXL

– High-performance silicon accurate simulationofRFandhigh-frequencycircuits—from simple blocks to complete system—using Spectre CircuitSimulatorXL

– Turbo RF analysis with multi-threading for a notable performance gain over traditional steady-state analysis (Shooting Newton and Harmonic Balance) using Virtuoso SpectreCircuitSimulatorGXL

– Turbo analog and RF parasitic reduction with considerable performance gain using Virtuoso SpectreCircuitSimulatorGXL

– High performance and capacity SPICE-accurate simulation, harnessing the power of multi-processing compute platforms core machines for analog/RF designs with thousands of devices, both including active and passive devices using Virtuoso Accelerated Parallel Simulator

• Optimizesfull-chipFastSPICEsimulation

– High-performance and high-capacity transistor-level verification of a wide range of analog and mixed-signal applications at the sub-system level using Virtuoso UltraSim Full-Chip Simulator L

– High performance and high capacity for full-chip transistor-level verification—from blocks to complete SoCs—using Virtuoso UltraSim Full-ChipSimulatorXL

• AccuratedynamicIRdropandElectro-migration analysis

• Detailedreliabilityanalysiscoveringhotcarrier injection (HCI) and Negative Bias Temperature Instability (NBTI)

– Fast and comprehensive static & dynamic circuit and device diagnostic checks

• Optimizesmixed-signalsimulation

– High-performance mixed-signal simulation with Virtuoso AMS Designer based on proven Virtuoso and Cadence Incisive® simulation engines

– Comprehensive support for mixed-signal hardware description languages covering top-down and bottom-up design methodologies

– Common set-up and use model for analog and FastSPICE analysis using Virtuoso Spectre and Virtuoso UltraSim

– Flexible analog-centric and digital-centric mixed-signal verification flows

FEATURES

SILICON-ACCURATE MODELING

All Virtuoso Multi-Mode Simulation engines use the same device model equations, eliminating model correlation issues among the simulation results. Common equations also ensure that new device model updates are available with all the simulators at the same time.

GREATER PERFORMANCE AND CAPACITY

Virtuoso Multi-Mode Simulation engines provide the best combination of performance and capacity without sacrificing accuracy.

LANGUAGE AND NETLIST SUPPORT

Virtuoso Multi-Mode Simulation is compatible with most commonly used SPICE input decks for both pre- and post-layout. It can natively read Spectre, SPICE, and Verilog-A netlist formats and device models. It also supports standard language inputs in Verilog-AMS, VHDL-AMS, Verilog-A, Verilog®, and VHDL formats.

POST-LAYOUT SIMULATION

Verification for post-layout designs has become increasingly important with advanced nanometer processes. For larger designs such as analog subsystems and full SoC designs, the post-layout parasitics data is growing exponentially at 65nm and below.

Virtuoso MMSIM offers flexible solutions for SPICE-level post-layout simulations: Spectre Circuit Simulator GXL addresses the analog and RF sub-system design verification challenge with the turbo

analog and RF post-layout functionality, encompassing high-performance post-layout verification for parasitic-dominant designs. It uses a conservative parasitic reduction algorithm to deliver the performance and capacity required, giving designers the option to make accuracy and performance trade-offs. Virtuoso Accelerated Parallel Simulator delivers a SPICE-accurate, advanced scalable performance and capacity simulation capability for post-layout designs, with tens of thousands of devices dominated by parasitics.

Virtuoso UltraSim Full-Chip Simulator XL meets the SoC design verification challenge with a combination of unique hierarchical parasitic stitching techniques and an accurate frequency-based parasitic reduction algorithm. This approach delivers the performance and capacity for post-layout verification of large designs. It also provides an optimized power net simulation technique and methodology for analysis of effects such as IR drop, signal integrity, timing, and substrate degradation.

DESIGN RELIABILITY

As gate oxide thickness and dimensions of scale shrink in IC design, reliability problems occur and need to be considered early in the design process. Some of the more problematic issues include negative bias temperature instability (NBTI) and hot carrier injection (HCI). These can lead to problems such as performance degradation, burn-in yield loss, leakage current increase leading to increased power consumption, and even functional failure of ICs.

Virtuoso UltraSim Full-Chip Simulator XL provides a full-chip reliability simulation and analysis solution, enabling designers to consider reliability effects in the early stages of design and ensure that circuits have sufficient margins to function correctly over their entire lifetimes.



ADVANCED ANALOG AND RF CIRCUIT ANALYSIS TECHNIQUES

The advanced architecture of Virtuoso Multi-Mode Simulation uses proprietary techniques—including adaptive time step control, sparse matrix solving and multi-threading—to provide high performance while maintaining sign-off accuracy. It bridges the gap between manufacturability and time to market at advanced process nodes by providing a comprehensive set of statistical analysis tools tailored to IC design. Tight integration with Virtuoso Analog Design Environment (ADE) enables user friendly interactive setup and advanced visualization of statistical results.

Virtuoso AMS Designer provides the flexibility to combine design intellectual property (IP) from different sources and in different formats necessary for the design and verification of today’s mixed-signal SoC. It accepts designs in combinations of hardware description languages allowing analog bottom-up and digital top-down design methodologies to link and enable a complete analog mixed-signal full-chip verification.

SPECIFICATIONS

COMPREHENSIVE DEVICE MODELS

• MOSFETmodels,includinglatestversions of BSIM3, BSIM4; PSP, HISIM, high-voltage MOS (HVMOS), MOS9, MOS11 and EKV

• Silicon-on-insulator(SOI)includinglatest versions of BTASOI, SSIMSOI BSIMSOI and BSIMSOI PD

• Bipolarjunctiontransistor(BJT)models,including latest versions of VBIC, HICUM ,HICUM ,Mextram, HBT and Gummel-Poonmodels

• Diode,JFETandGaASMESFETmodels

• RensselaerPolytechnicInstitute’s(RPI)Poly and Amorphous Silicon Thin-Film models

• Verilog-Acompactdevicemodels

• Specializedreliabilitymodels(AgeMOS)for Hot Carrier Injection (HTI) and Negative Bias Temperature Instability (NBTI) analysis

PLATFORM SUPPORT :

• SunSolaris9and10

• HP-UX11

• IBMAIX

• LinuxRedhat,EnterpriseV4

• SUSELinux9and10

CADENCE SERVICES AND SUPPORT

• Cadenceapplicationengineerscanansweryourtechnicalquestionsbytelephone, email, or Internet—they can also provide technical assistance and custom training

• Cadencecertifiedinstructorsteachmorethan70coursesandbringtheirreal-world experience into the classroom

• Morethan25InternetLearningSeries(iLS) online courses allow you the flexibility of training at your own computer via the Internet

• SourceLink® online customer support gives you answers to your technical questions—24hoursaday,7daysaweek—includingthelatestinquarterlysoftware rollups, product change release information, technical documentation, solutions, software updates, and more



To meet the diverse needs for block-level circuit simulation, Virtuoso Spectre Circuit Simulator is available in tiered configurations of L, XL, and GXL, which provide multiple levels of technology tailored to specific levels of design complexity and applications.

FEATURES OF VIRTUOSO SPECTRE SIMULATOR L

PRODUCTION-PROVEN CIRCUIT SIMULATION TECHNIQUES

Virtuoso Spectre Circuit Simulator L uses proprietary techniques—including adaptive time step control, sparse matrix solving, and multi-threading of MOS models—to provide high performance while maintaining signoff accuracy. It includes native support for both Spectre and SPICE syntax, giving users the

flexibility to use the L configuration in any design flow, without worrying about the design format. Additionally, it provides results that are “silicon-accurate” by modeling extensive physical effects in devices for deep sub-micron processes.

COMPREHENSIVE STATISTICAL ANALYSIS

Virtuoso Spectre Circuit Simulator L bridges the gap between manufacturability and time to market at advanced process nodes by providing a comprehensive set of statistical analysis tools tailored to IC design. Advanced Monte Carlo algorithms enable smart selection of process and design parameters to characterize the yield in one-tenth of the required simulation runs (see Figure 2). The L configuration’s DC Match efficiently analyzes local process mismatch effects and identifies the yield-

The Virtuoso Spectre Circuit Simulator provides fast, accurate SPICE-level simulation for tough analog, radio frequency (RF) and mixed-signal circuits. It is tightly integrated with the Virtuoso custom design platform and provides detailed transistor-level analysis in multiple domains. Its superior architecture allows for low memory consumption and high-capacity analysis.

BENEFITS • Provideshigh-performance,high-

capacity SPICE-level analog and RF simulation with out-of-the-box tuning for accuracy and convergence

• Facilitatesthetradeoffbetweenaccuracy and performance through user-friendly simulation setup applicable to the most complex analog and custom-digital ICs

• Enablesaccurateandefficientpost-layout simulation with parasitics, S-Parameter models (n-port), and lossy coupled transmission lines (mtline)

• Performsapplication-specificanalysisofRF performance parameters (spectral response, gain compression, inter-modulation distortion, impedance matching, stability, isolation)

• Includesadvancedstatisticalanalysis(Smart, MonteCarlo, DCmatch) to help design companies improve the manufacturability and yield of ICs at advanced process nodes without sacrificing time to market

• Deliversfastinteractivesimulationset-up, cross-probing, visualization, and post-processing of simulation results through tight integration with Virtuoso Analog Design Environment

• Ensureshigherdesignqualityusingsilicon-accurate, foundry-certified device models shared within Virtuoso Multi-Mode Simulation

V IRTUOSO SPECTRE CIRCUIT S IMULATOR

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20 50 100 200 500 1000 2000 500010

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Standard Sampling Smart Monte Carlo analysis Sampling

Figure 2: Virtuoso Spectre simulator offers faster statistical analysis with smart Monte Carlo analysis



limiting devices and parameters. Tight integration between Virtuoso Spectre Circuit Simulator L and Virtuoso Analog Design Environment enables user-friendly interactive setup and advanced visualization of statistical results.

TRANSIENT NOISE ANALYSIS

Virtuoso Spectre Circuit Simulator L leveraging the production proven transient analysis capability provides Transient Noise Analysis including large signal and non-periodic noise analysis

BENEFITS:• FullSpectreaccuracy

• Supportsallnoisetypes–thermal,shotand flicker

• Statisticalpost-processingwithAnalogDesign Environment in Virtuoso Platform

BUILT-IN VERILOG-A AND MDL

Virtuoso Spectre Circuit Simulator L includes behavioral modeling capabilities in full compliance with Verilog-A 2.0. The compiled Verilog-A implementation is optimized for compact device models offering comparable performance to built-in device models.

In addition to supporting standard SPICE measurement functions (.measure), the L configuration includes a measurement description language (MDL) to automate cell and library characterization. Virtuoso Spectre MDL not only post-processes the results but also tunes the simulator to provide the best performance/accuracy tradeoff for a specific measurement.

ADVANCED DEVICE MODELING AND SUPPORT

Virtuoso Spectre Circuit Simulator L supports MOS, BJT, specialty transistor models, resistors, capacitors, inductors, transformers and magnetic cores, lossy and lossless transmission lines, independent and controlled voltage and current sources, and Z and S domain sources.

The user-defined model interface includes a compiled model interface (CMI) that is shared across all platform simulators. It allows for the rapid inclusion of user-defined models for a “model once, use everywhere” capability. The L configuration also provides a curve tracer analysis capability for rapid model development and debugging.

FEATURES OF VIRTUOSO SPECTRE CIRCUIT SIMULATOR XL

RF ANALYSIS

• Periodicandquasi-periodicsteady-stateanalysis based on harmonic balance technology, optimized for high dynamic range, high-capacity RF circuits with distributed components

• Periodicandquasi-periodicsteady-stateanalysis based on the Cadence patented time-domain shooting Newton algorithm, optimized for strongly non-linear circuits

• Envelopefollowinganalysissupportingall analog and digital modulation techniques

• RapidIP2andIP3calculationbasedonperturbation technology

• Periodicnoiseanalysisfortheaccuratecalculation of noise in non-linear time variant circuits with detailed analysis options (modulated noise, sampled noise, jitter)

• Noiseanddistortionsummarytoidentify the contribution of each device to the total output noise, harmonic, or inter-modulation distortion

• Smallsignalanalysis:ac,transferfunction, S-Parameters, and stability basedonaperiodicorquasi-periodicoperating point

• MonteCarlo,corner-case,andparametric sweep analysis

NOISE-AWARE PLL ANALYSIS

An automated flow for time-domain and jitter analysis of integer-N and fractional-N phase locked loops (PLL) blocks. The flow speeds up PLL verification by significantly using transistor-calibrated nonlinear models. The flow enables PLL designers to capture the effect of circuit nonlinearity on closed-loop PLL noise and test for complicated performance parameters such as injection pulling.

Figure 3: Virtuoso Spectre simulator XL offers fast sign-off accurate analysis of Voltage-controlled oscillators



RF MEASUREMENT LIBRARYMEASUREMENT

The library consists of RF measurements such as noise figure and inter-modulation distortion tailored for specific RF blocks (amplifiers, mixers, oscillators). Designers can insert the measurements directly on the schematics simplifying simulation setup and post-processing. The measurement element will automatically set up the simulation, perform any necessary post-processing and plot the required waveforms. Users can augment the library by defining their own measurements.

ANALOG TURBO FUNCTIONALITY

Turbo functionality in Virtuoso Spectre Circuit Simulator XL provides a considerable performance boost over the traditional SPICE-level analog simulation with full SPICE accuracy. The proprietary techniques in the L configuration have been extended to address the challenges designers face with tough complex analog and mixed-signal circuits. Turbo multi-threading allows designers to leverage multi-core machines to achieve additional performance speedup. The use model in turbo mode is identical to SPICE-level simulation offered with the L configuration, enabling designers to preserve their existing setup and methodology.

CO-SIMULATION WITH SIMULINK

The MathWorks Simulink interface to Virtuoso Spectre XL offers system and circuit designers a unique integrated environment for design and verification. Designers can insert their analog and RF schematics and post-layout netlist directly in the system-level block diagram and run

a co-simulation between Simulink and Virtuoso Spectre technologies. Designers can reuse the same Simulink testbench from system-level design to post-layout verification, thereby minimizing the unnecessary format conversion while maintaining accuracy throughout the design flow.

VIRTUOSO MULTI-MODE SIMULATION TOOLBOX FOR MATLAB

The Virtuoso Multi-Mode Simulation toolbox for MATLAB reads PSF and SST2 files directly in MATLAB. Users benefit from the rich set of MATLAB mathematical functions to post-process simulation results from Virtuoso Spectre Circuit Simulator L and XL, Virtuoso UltraSim Full-Chip Simulator, and Virtuoso AMS Designer with Flexible Analog Simulation. All sweep types are supported in the toolbox including Monte Carlo and parametric. Special data structures are used to store RF signals and harmonics resulting from PSS and QPSS analysis. Furthermore, the Virtuoso Multi-Mode Simulation toolbox complements the rich MATLAB libraries with communication product-specific post-processing functions such as Fast Fourier Transform, third-order intercept point, and 1-dB gain compression point.

FEATURES OF VIRTUOSO SPECTRE CIRCUIT SIMULATOR GXL

RF ANALYSIS WITH “TURBO” TECHNOLOGY

RF analysis with “Turbo” technology provides increased performance enhancement over traditional steady state (Harmonic Balance and shooting Newton) and envelope analysis techniques with full SPICE accuracy. The technology enables complete analysis and verification of large RF circuits designed for advanced CMOS process nodes through better device model manipulation and multi-threading. The “Turbo” use model is identical to RF analysis offered with the XL configuration, enabling designers to preserve their existing setup and methodology.

TURBO POST LAYOUT

Turbo post-layout enables analog and RF block and subsystem post-layout verification at near the speed of pre-layout simulation. An accurate parasitic reduction technique enhances the simulation performance of parasitic-dominant circuits significantly over traditional SPICE-level simulation. The technology enables designers to trade-off accuracy and performance using simple user-friendly setup.

Figure 4: RF analysis with “Turbo” technology enables fast transceiver verification



SPECIFICATIONS




• Bipolarjunctiontransistor(BJT)models,including latest versions of VBIC, HICUM, HICUM, Mextram, HBT and Gummel-Poonmodels





COMPREHENSIVE CIRCUIT ANALYSIS

Virtuoso Spectre Circuit Simulator L

• DC,AC,andtransientanalysis

• Noise,transferfunction,andsensitivityanalysis

• Transientnoiseanalysis

• MonteCarloandparametricstatisticalsupport

• Fullsupportforsweepinganalysisandcircuit parameters

• Built-inmeasurementdescriptionlanguage

Virtuoso Spectre Circuit Simulator XL

• Periodicandquasi-periodicsteadystateanalysis (PSS and QPSS) based on harmonic balance and shooting Newton

• Periodicandquasi-periodicnoiseanalysis (PNoise, QPNoise)

• Periodicandquasi-periodicsmallsignalanalysis(PAC,PXF,PSP,QPAC,QPSF,QPSP)

• Periodicstabilityanalysis(PSTB)

• Time-domainandfrequency-domainenvelope analysis

• Perturbation-basedrapidIP2andIP3

• Noiseanddistortionsummaries

• Co-simulationwithSimulinkfromTheMathWorks

• VirtuosoMulti-ModeSimulationtoolbox for MATLAB from the MathWorks

• Analogsimulationwith“Turbo”Technology

Virtuoso Spectre Circuit Simulator GXL

• RFSimulationwith“Turbo”Technology

• Accurateparasiticreductionforanalogand RF post-layout block verification

DESIGN INPUTS/OUTPUTS

• VirtuosoSpectrenetlistformat

• HSPICE

• SPICE2/3

• Verilog-A2,0

• S-Parameterdatafiles

• PSFwaveformformat

PLATFORM SUPPORT


• HP-UX11

• IBMAIX


• SUSELinux9and10



V IRTUOSO ACCELERATED PARALLEL S IMULATOR

Virtuoso Accelerated Parallel Simulator, a part of the Virtuoso Multi-mode Simulation Platform, provides the next generation analog simulation, with significant scalable performance and capacity at full Spectre accuracy, for a broad class of complex analog, RF and mixed-signal blocks and sub-systems with ten thousands of devices. It is tightly integrated with the Virtuoso custom IC design platform and provides all the transistor-level analysis capabilities as in Virtuoso Spectre Simulator. The proprietary parallel simulation technology delivers complete and scalable multi-threading capability on modern multi-processing compute platforms machines.

BENEFITS• Providessignificantsingle-thread

performance with full Spectre accuracy

• Enableshigh-precisionsimulationforlarge post layout analog designs and subsystems dominated by parasitic devices

• Deliversscalableperformanceleveraging machines with multi-processing architectures allowing higher levels of analog design integration and verification.

• ProvidesidenticalusemodeltoVirtuosoSpectre Circuit simulator

SPECIFICATIONS









CIRCUIT ANALYSIS

• DC,AC,andtransientanalysis

LANGAUGE SUPPORT

• BehavioralVerilogA

• AMSVerilog

• VerilogCompactDeviceModels

PLATFORM SUPPORT :


• HP-UX11

• IBMAIX


• SUSELinux9and10



V IRTUOSO ULTRASIM FULL-CHIP S IMULATOR

VIRTUOSO ULTRASIM FULL-CHIP SIMULATOR The Virtuoso UltraSim Full-Chip Simulator is a high-performance transistor-level FastSPICE circuit simulator for verifying large custom, analog/mixed-signal, RF, memory and SoC designs. It uses true hierarchical simulation with patented isomorphic and adaptive partitioning algorithms to provide the capacity, accuracy, and speed required for design and verification, regardless of design type or stage in the design cycle.

BENEFITS • Acceleratespre-andpost-layout

simulation for a wide range of applications from blocks to full-chip SoCs (see Figure 3)

– Basic and advanced circuit diagnostics

– Advanced parasitic reduction algorithm

– Advanced algorithm for custom digital verification

• Offersdesignverificationflexibilitythrough various modes

• Deliverssilicon-accuratesimulation

• Hastheflexibilitytoswitchbetweenenvironments for different design stages via integration with Virtuoso Analog Design Environment

• Delivershighanalogcapacityandsimulation speed for AMS simulation solutions for block authoring and final verification

Design DataSPICE + DSPF

ParasiticExtraction

PhysicalVerification

VirtuosoSchematicLayout

Viewing & Analysis

IR drop & EMviolations

Virtuoso UltraSimFast SPICE

Figure 5: Virtuoso UltraSim electrical verification flow addresses electrical verification requirements for voltage drop and electrical migration analysis of large designs

FEATURES

COMPATIBLE WITH SPICE, SPECTRE, VERILOG-A, DSPF, AND SPEF

Virtuoso UltraSim Full-Chip Simulator is compatible with most types of SPICE input decks for both pre- and post-layout. Additionally, it can natively read Virtuoso Spectre format netlists and models, and uses the same views within Virtuoso Analog Design Environment, making it easy to adopt in Virtuoso Spectre-based design flows.

POST-LAYOUT SIMULATION

When used in conjunction with Cadence post-layout products, Virtuoso UltraSim Full-Chip Simulator provides a means for exploration and validation of such effects as electromigration, IR drop, signal integrity, and substrate degradation. It also has built-in, state-of the-art, S-Parameter–based parasitic reduction for faster simulation with minimal loss in accuracy.

DESIGN RELIABILITY SIMULATION

Virtuoso UltraSim Full-Chip Simulator provides a robust set of analyses capable of predicting and validating timing, power, and reliability. It is the only FastSPICE simulator capable of simulating hot carrier injection (HCI) and negative bias temperature instability (NBTI)—key stress effects that must be taken into account for either high-performance or DSM designs.



SPECIFICATIONS

DESIGN INPUTS

• SPICEnetlist

• VirtuosoSpectrenetlist

• DSPF/SPEF

• Verilog-A

• VirtuosoUltraSim/Verilog

– Verilog-HDL IEEE 1364

- PLI1.0,VPI(PLI2.0)

- SDF

• AMS-VirtuosoUltraSim

– Verilog-HDL IEEE 1364

– VHDLIEEE1076

– Verilog-AMS

– PLI1.0,VPI(PLI2.0)

– SDF

– SystemC®, SystemVerilog









INPUT AND OUTPUT FORMATS

• SST2waveformformat

• PSFandPSFXLwaveformformat

• FSDBformat

• VeritoolsUT7.2.5support

• ASCIItext

PLATFORM SUPPORT :


• HP-UX11

• IBMAIX


• SUSELinux9and10



Virtuoso AMS Designer

AMS Block & Top-Down Verification

Virtuoso Spectre L/LX

Incisive DesignTeam Simulator

Virtuoso AMS Designer

AMS Full-chip Verification

Multi-Language DebuggingUnified Waveform

VirtuosoUltraSim X/XL

Incisive DesignTeam Simulator

VIRTUOSOAMSDESIGNERSIMULATOR

Figure 6: Virtuoso AMS Designer verification flow addresses AMS verification needs throughout the design cycle

Virtuoso AMS Designer is a mixed-signal simulation solution for the design and verification of analog, RF, memory, and mixed-signal SoCs. It is integrated with the Virtuoso full-custom environment for mixed-signal design and verification. It is also integrated with the Cadence Incisive functional verification platform for mixed-signal verification within the digital verification environment (see Figure 6).

Virtuoso AMS Designer with Flexible Analog Simulation provides a single executable language-based mixed-signal simulation solution with support for the standard mixed-signal languages, Verilog-AMS and VHDL-AMS. As the bridge from the analog domain to the digital domain, it enables users to choose the right analog solver for the right design or verification task. Users can choose Virtuoso Spectre Circuit Simulator L, XL and GXL for accurate block-level analog and RF designs or Virtuoso UltraSim Full-Chip Simulator L and XL for full-chip verification tasks.

Virtuoso AMS Designer is fully configurable across design and verification domains offering the right simulation technology and environment for every stage in the design and verification cycle

BENEFITS • Ensuresdesignqualitywithproven

Virtuoso analog and Incisive digital simulation technologies

• Supportsbothanalogdesignflowusemodel in Virtuoso Analog Design Environment as well as digital verification use model in Incisive Environment

• Supportstop-downmethodologytoquicklydetectdesignfailuresearlyinthe design cycle to make sure the design is ready for tape-out, right on time

• Acceleratessimulationwithmixed-signal hardware description language support

• AcceleratessimulationofRFcircuitsatfull SPICE accuracy by combining envelope analysis of RF transceivers with digital baseband simulation

FEATURES

“MEET-IN-THE-MIDDLE” DESIGN METHODOLOGY

Virtuoso AMS Designer with Flexible Analog Simulation provides the flexibility to combine IP from different sources and in different formats for today’s SoC designs. It does more than just co-simulate analog and digital blocks. By treating Virtuoso Schematic Editor blocks and textual descriptions equally, Virtuoso AMS Designer with Flexible Analog Simulation allows different points of data entry. It is multi-lingual and accepts

descriptions in the standard language formats of Verilog-AMS, VHDL-AMS, Verilog-A, Verilog, VHDL, and SystemC, as well as SPICE and Virtuoso Spectre simulation, or any combination of these languages. This multi-lingual approach allows bottom-up and top-down design methodologies to meet in the middle.

Different levels of abstraction, like Verilog-AMS or VHDL-AMS behavioral models and schematic representation, are easily interchangeable to allow the design to change over time from full behavioral to full transistor. The entire design is configured using the hierarchy editor, which facilitates the viewing and design preparation of a complex mixed-signal design. Automatically inserted interface elements are used to translate signals from one domain to the next, leaving the user free to simulate with different design configurations to easily trade off simulation speed for simulation accuracy.



Virtuoso AMS Designer with Flexible Analog Simulation also supports IP encryption using RSA technology, which allows the user to establish both IP reuse and virtual prototyping methodologies.

INTEGRATED WITH PROVEN VIRTUOSO AND INCISIVE SIMULATION TECHNOLOGIES

Virtuoso AMS Designer is a single executable mixed-signal simulator based on the proven technology of Virtuoso Spectre Circuit Simulator, Virtuoso UltraSim Full-Chip Simulator, and the Incisive digital simulation capabilities.

Using Virtuoso AMS Designer with Virtuoso Spectre Circuit Simulator ensures that the user gets golden simulation results for performance measurements. In the verification flow, the Virtuoso UltraSim Full-Chip Simulator is used as the built-in analog simulation engine. This enables final verification of the largest mixed-signal SoCs and multi-chip designs. The Incisive digital simulation engine inside of Virtuoso AMS Designer delivers high-performance native Verilog, SystemVerilog, VHDL, SystemC and e simulation.

Virtuoso AMS Designer also supports IP encryption using RSA technology, which allows the user to establish both IP reuse and virtual prototyping methodologies.

ANALOG-CENTRIC AND DIGITAL-CENTRIC FLOWS

Virtuoso AMS Designer is tightly integrated with Virtuoso Analog Design Environment for mixed signal block design. It uses native ADE netlisting technologies to combine schematics and behavioral views enabling users to independently manage the level of abstraction of each block. The entire design is configured using the hierarchy editor, which facilitates the viewing and design preparation of a complex mixed-signal design.

AMS Designer works natively in the Incisive environment for digital-centric verification. A single control file is used to

define how analog blocks are integrated into the digital SoC. Analog and RTL blocks can be easily interchanged to trade-off accuracy and performance. It supports all features in the Incisive environment like test bench analysis, Specman and verification planning.

Automatically inserted interface elements are used to translate signals from one domain to the next, leaving the user free to simulate with different design configurations to easily trade off simulation speed for simulation accuracy.

AMS DESIGNER VERIFICATION OPTION

AMS Designer Verification Option provides a complete solution for mixed-signal SoC verification. It enhances the performance and capacity of analog/mixed-signal block-level simulation using multi-threading technology, The Verification Option also enables cross domain connectivity between test benches and design IP blocks from multiple vendors by providing native connectivity between VHDL or SystemVerilog and SPICE. The solution also extends mature digital verification methodologies such as low-power to the analog domain.

SPECIFICATIONS



• Silicone-on-insulator(SOI)includinglatest versions of BTASOI, SSIMSOI BSIMSOI and BSIMSOI PD





• Specializedreliabilitymodels(AgeMOS)for Hot Carrier Injection (HTI) and NegativeBiasTemperatureInstability (NBTI) analysis

VIRTUOSO ENVIRONMENT

• DirectVerilog-AMSnetlisting

• HierarchyeditorAMSplug-in

• Hierarchyeditorconfiguration

• Supportforglobaldesignvariablesandglobal signals

• Inheritedconnections

AMS SIMULATOR

• Singleexecutablemixed-signal/mixed-language simulator

• Built-inVirtuosoSpectreorVirtuosoUltraSim simulators and Incisive digital engines

• DigitalandRealnumbermodelingcapabilities

• System-levelsimulationswithlinkstoSimulink from the MATHWORKS

• Save/restart

• Commonmixed-signalwaveformdatabase

INCISIVE ENVIRONMENT

• Mixed-signaldebugger

• Breakpointsontime,position,condition

• Debugsteppingthroughbehavioralcode, analog, and digital

• SourceviewerwithVerilog-AMS/VHDL-AMS syntax highlighting

• Directvalueaccessinsourceviewer

• Waveformwindow

• Registerwindow

• Calculator

• Schematictracer

• Signalflowbrowser

• Errorbrowser

• Digitaltransactionsupport


© 2008 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Incisive, Spectre, Verilog, and Virtuoso are registered trademarks of Cadence Design Systems, Inc. OSCI and SystemC are registered trademarks of the Open SystemC Initiative, Inc., in the U.S. and other countries and is used with permission. All others are properties of their respective holders.

20828/20588A 12/08 MK/MVC/CS/PDF

AMS DESIGNER VERIFICATION OPTION

• Analogmulti-threading

• NativeVHDL-SPICEconnectivity

• NativeSystemVerilogtoSPICEandAMSconnectivity

• Power-SmartconnectmodulesforCPF

DESIGN INPUTS

• CadenceCDBAdatabaseorOpenAccess database

• Verilog-AMS2.0

• VHDL-AMS1076.1

• Verilog(IEEE1364-1995,IEEE1364-2001extensions)

• VHDL(IEEE1076-1987,IEEE1076-1993,IEEE1076.4-2000[VITAL2000])

• Spectre,SPICE2G6,HSPICEnetlistformats

• SystemVerilog(IEEE-1800)

• CommonPowerFormat(CPF)

• WithinIncisiveplatform:SystemC(OSCI®SystemCv2.01),SystemCVerificationLibrary(OSCISCV1.0),Specman e

For more information, contact Cadence sales at:

1.800.746.6223

or log on to:

www.cadence.com

DESIGN OUTPUTS

• SST2waveformformatanaloganddigital data

• PSFwaveformformatforanalogdata

• Verilog-AMSnetlistformat

PLATFORM SUPPORT :


• HP-UX11

• IBMAIX


• SUSELinux9and10




virtuoso multi-mode simulation - integrity · pdf file virtuoso multi-mode simulation 4...

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