vlsi consolidated v1 16.7
TRANSCRIPT
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LOGIT(P)LTD.,Varatharajamills,nearhopes,Coimbatore,9597388388,8122044220,9003667666
Welcome to VLSI world!
Here we listed out a number of titles as per industry requirement and latest
development. These titles are purely based upon IEEE Transactions only.
VLSI is ever growing research field, and it leads the world always.
The following table shows the IEEE titles in various domains like signal processing,
communication Systems, cryptography, audio signal processing, image processing and
power electronic controls.
The following titles are always simulatable and for hardware details consult our
coordinators, since every title has its own hardware setup.
For simulation - ModelSim 6.5 or later
For synthesis and implementation - Xilinx 12.1 or later
For inter verification (Miscellaneous) - MATLAB R2009a or later
Our projects are vendor independent, which means that we can use any FPGA or CPLD as
per project requirement.
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1. Cognition and Removal of Impulse Noise WithUncertainty_jul2k12
July 2012
2. Fast Higher-Order MR Image Reconstruction Using Singular-Vector Separation_Jul2k12
July 2012
3. Image Deblurring Using Derivative Compressed Sensing forOptical Imaging Application_Jul2k12
July 2012
4.New Families of Fourier Eigen functions for Steerable
Filtering_jun2k12 June 2012
5. Scalable Coding of Encrypted Images_Jun2k12 June 20126. A Pipeline VLSI Architecture for Fast Computation of the 2-D
Discrete Wavelet Transform2012
7. An Efficient Denoising Architecture for Removal of ImpulseNoise in Images
2012
8. Design and Implementation of a Pipelined Datapath for High-
Speed Face Detection Using FPGA 2012
9. An Efficient VLSI Architecture for Lifting-Based DiscreteWavelet Transform
2012
10. Chaos-Based Security Solution for Fingerprint Data DuringCommunication and Transmission
2012
11. An FPGA-Based Hardware Implementation of ConfigurablePixel-Level Color Image Fusion
2012
12. An Improved Multiplicative Spread Spectrum EmbeddingScheme for Data Hiding
2012
13. Interference Removal Operation for Spread SpectrumFingerprinting Scheme
2012
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14. Robust Watermarking of Compressed and EncryptedJPEG2000 Images
2012
15. Spread Spectrum Magnetic Resonance Imaging 201216. VLSI Architecture of Arithmetic Coder Used in SPIHT 201217. Digital Signal Processing Techniques to Improve Time
Resolution in Positron Emission Tomography2011
18. A New Supervised Method for Blood Vessel Segmentation inRetinal Images by Using Gray-Level and Moment Invariants-Based Features
2011
19. High-Accuracy Fixed-Width Modified Booth Multipliers forLossy Applications
2011
20. Optimal Design of FIR Triplet Halfband Filter Bank andApplication in Image Coding
2011
21. Memory Efficient Modular VLSI Architecture forHighthroughput and Low-Latency Implementation ofMultilevel Lifting 2-D DWT
2011
22. A Self-Configurable Systolic Architecture for Face RecognitionSystem Based on Principal Component Neural Network
2011
23. Time Multiplexed VLSI Architecture for Real-Time BarrelDistortion Correction in Video-Endoscopic Images 201124. Blind Methods for Detecting Image Fakery(any one method) 201025. FPGA implementation of adaptive segmentation for non-
stationary biomedical signals2010
26. Implementation of a New Contrast Enhancement Method forVideo Images
2010
27. Medical image enhancement algorithm based on wavelettransform 201028. Message Encoding in Images Using Lifting Schemes 201029. P-step Unbiased FIR Filter to the Ultrasound Image
Processing2010
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30. Investigating the Impact of Logic and Circuit Implementationon Full Adder Performance_Jul2k12
July 2012
31. Optimizing Floating Point Units in Hybrid FPGAs_Jul2k12 July 201232. Low-Power and Area-Efficient Carry Select Adder 201233. Design Issues and Implementations for Floating Point
DivideAdd Fused2010
34. FPGA Designs with Optimized Logarithmic Arithmetic 2010
35. A Highly-Integrated 38 GHz Ultra-Wideband RF TransmitterWith Digital-Assisted Carrier Leakage Calibration andAutomatic Transmit Power Control_Aug2k12
August 2012
36. High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm_Jul2k12
July 2012
37. Novel Interpolation and Polynomial Selection for Low-Complexity Chase Soft-Decision Reed-SolomonDecoding_Jul2k12
July 2012
38. Power Management of MIMO Network Interfaces on MobileSystems_Jul2k12
July 2012
39. Unified Architecture for Reed-Solomon Decoder CombinedWith Burst-Error Correction_Jul2k12
July 2012
40. A Fourier Based Method for Approximating the JointDetection Probability in MIMO Communications_Jun2k12
June 2012
41. Low Complexity Transmitter Architectures for SFBC MIMO-OFDM Systems_Jun2k12
June 2012
42. On the Reduction of Additive Complexity of CyclotomicFFTs_Jun2k12
June 2012
43. A Mutual Distortion and Impairment Compensator forWideband Direct-Conversion Transmitters Using Neural
June 2012
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Networks_Jun2k12
44. Segmentation of Source Symbols for Adaptive ArithmeticCoding_Jun2k12
June 2012
45. Cooperative Beamforming for Cognitive Radio Networks-ACross-Layer Design_May2k12 May 201246. Dynamic Resource Allocation in MIMO-OFDMA Systems with
Full-Duplex and Hybrid Relaying_May2k12May 2012
47. Good Synchronization Sequences for PermutationCodes_May2k12
May 2012
48. Low Latency Coding- Convolutional Codes vs. LDPCCodes_May2k12
May 2012
49. Low-Complexity Iterative Channel Estimation for TurboReceivers_May2k12
May 2012
50. Spectrum Sensing in the Presence of Multiple PrimaryUsers_May2k12
May 2012
51. The Design of Hybrid Asymmetric-FIR_Analog Pulse-ShapingFilters Against Receiver Timing Jitter_May2k12
May 2012
52. Uncoordinated Beamforming for CognitiveNetworks_May2k12
May 2012
53. 3D MIMO-OFDM Channel Estimation_Apr2k12 April 201254. Interleaved Product LDPC Codes_Apr2k12 April 201255. Secure Communication in the Low-SNR Regime_Apr2k12 April 201256. Blind Signal Processing for Impulsive Noise
Channels_Feb2k12February 2012
57.Curvature Based ECG Signal Compression for Effective
Communication on WPAN_Feb2k12 February 2012
58. Distributed Coordination Protocol for Ad Hoc Cognitive RadioNetworks_Feb2k12
February 2012
59. A CMOS Low-Power Digital Polar Modulator System 2012
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Integration for WCDMA Transmitter
60. A High-Speed Low-Complexity Modified(Radix_2pow5) FFTProcessor for High Rate WPAN Applications
2012
61. A Wideband Digital RF Receiver Front-End Employing a NewDiscrete-Time Filter for m-WiMAX 201262. A Novel Filter-Bank Multicarrier Scheme to Mitigate the
Intrinsic Interference Application to MIMO Systems2012
63. Differential Coding for MAC Based Two-User MIMOCommunication Systems
2012
64. High-Speed Low-Power Viterbi Decoder Design for TCMDecoders
2012
65. MDC FFT_IFFT Processor With Variable Length for MIMO-OFDM Systems
2012
66. New S-Band Bandpass Filter (BPF) With Wideband Passbandfor Wireless Communication Systems
2012
67. Reconfigurable Adaptive Singular Value DecompositionEngine Design for High-Throughput MIMO-OFDM Systems
2012
68. Synthesis and Array Processor Realization of a 2-D IIR BeamFilter for Wireless Applications
2012
69. Transmission of 4-ASK Optical Fast OFDM With ChromaticDispersion Compensation
2012
70. VLSI Architecture for a Reconfigurable Spectrally EfficientFDM Baseband Transmitter
2012
71. A Two-Level FH-CDMA Scheme for Wireless CommunicationSystems over Fading Channels
2011
72. Differential Encoding by a Look-Up Table for Quadrature-Amplitude Modulation 2011
73. Timing accuracy of self-encoded spread spectrum navigationwith communication
2011
74. A Low-Complexity Viterbi Decoder for Space-Time Trellis 2010
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Codes
75. Adaptive Design of Digital FIR Filter for Beamforming with ItsApplication in PSK UWA Communication
2010
76. Coding Schemes for Noiseless and Noisy AsynchronousCDMA Systems 201077. Design Space Exploration of Hard-Decision Viterbi Decoding-
Algorithm and VLSI Implementation2010
78. FPGA Implementation of Digital Up_Down Convertor forWCDMA System
2010
79. Performance of MC-CDM Systems With MMSEC Over RayleighFading Channels
2010
80. Video Encoder Design for High-Definition 3D VideoCommunication Systems
2010
81. A CMOS Low-Power Digital Polar Modulator SystemIntegration for WCDMA Transmitter
2012
82. Enhancement of Single-Channel Periodic Signals in the Time-Domain_Sep2k12
Septembe
r2012
83. Multi-View and Multi-Objective SemiSupervised Learning forHMM-Based Automatic Speech Recognition_Sep2k12
Septembe
r2012
84. Musical-Noise-Free Speech Enhancement Based onOptimized Iterative Spectral Subtraction_Sep2k12
Septembe
r2012
85. Robustness and Regularization of Personal AudioSystems_Sep2k12
Septembe
r2012
86. Speaker and Noise Factorization for Robust SpeechRecognition_Sep2k12
Septembe
r
2012
87. State-Space Frequency-Domain Adaptive Filtering forNonlinear Acoustic Echo Cancellation_Sep2k12
Septembe
r2012
88. Vocal Tract Length Normalization for Statistical Parametric Septembe 2012
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Speech Synthesis_Sep2k12 r
89. A Dual-Channel Time-Spread Echo Method for AudioWatermarking
2012
90. A Low-Complexity Design for an MP3 Multi-Channel 2012
91. Telephone Channel Compensation in Speaker VerificationUsing a Polynomial Approximation in the Log-Filter-BankEnergy Domain
2012
92. Enhancement of Residual Echo for Robust Acoustic EchoCancellation
2012
93. A Wiener Filter Approach to Microphone Leakage Reductionin Close-Microphone Applications
2012
94. Robust Patchwork-Based Embedding and Decoding Schemefor Digital Audio Watermarking
2012
95. Stereo Acoustic Echo Cancellation Employing Frequency-Domain Preprocessing and Adaptive Filter
2011
96. Efficient FPGA Implementations of Point Mult on BinaryEdwards & Generalized Hessian Curves Using_Aug2k12
August 2012
97. Construction of Optimum Composite Field Architecture forCompact High-Throughput AES S-Boxes_Jun2k12
June 2012
98. Secure Multipliers Resilient to Strong Fault-Injection AttacksUsing Multilinear Arithmetic Codes_Jun2k12
June 2012
99. A Formal Approach to Designing Cryptographic ProcessorsBased on GF(2^m) Arithmetic Circuits
2012
100. Efficient Implementation of Elliptic Curve Cryptography UsingLow-power Digital Signal Processor
2010
101. A Highly-Digital VCO-Based ADC Using Phase Interpolator &Digital Calibration_Aug2k12
August 2012
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102. Area-Time Efficient Scaling-Free CORDIC Using GeneralizedMicro-Rotation Selection_Aug2k12
August 2012
103. Jitter Analysis of Polyphase Filter-Based Multiphase Clock inFrequency Multiplier_Aug2k12
August 2012
104. Resource-Efficient FPGA Architecture and Implementation ofHough Transform_Aug2k12
August 2012
105. A Low-Power Low-Cost Design of Primary SynchronizationSignal Detection_Jul2k12
July 2012
106. A Multi-Resolution Fast Filter Bank for Spectrum Sensing inMilitary Radio Receivers_Jul2k12
July 2012
107. Hardware Implementation of Nakagami and Weibull VariateGenerators_Jul2k12
July 2012
108. Pipelined Parallel FFT Architectures via FoldingTransformation_June2k12
June 2012
109. A Novel Approach for Motion Artifact Reduction in PPGSignals Based on AS-LMS Adaptive Filter
2012
110. A Single-Pass-Based Localized Adaptive Interpolation Filterfor Video Coding
2012
111. A Very Linear Low-Pass Filter with Automatic FrequencyTuning 2012
112. An Optimization-Based Parallel Particle Filter for MultitargetTracking
2012
113. Area-Efficient Parallel FIR Digital Filter Structures forSymmetric Convolutions Based on Fast FIR Algorithm
2012
114. Area-Efficient VLSI Implementation for Parallel Linear-PhaseFIR Digital Filters of Odd Length Based on Fast FIR Algorithm
2012
115. Design of Digit-Serial FIR Filters Algorithms, Architectures,and a CAD Tool
2012
116. Hierarchical Design of an Application-Specific Instruction SetProcessor for High-Throughput and Scalable FFT Processing
2012
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117. Non-Causal Time-Domain Filters for Single-Channel NoiseReduction
2012
118. On the BIBO Stability Condition of Adaptive Recursive FLANNFilters With Application to Nonlinear Active Noise Control
2012
119. Pipelined Parallel FFT Architectures via FoldingTransformation
2012
120. The Design of Hybrid Symmetric-FIR_Analog Pulse-ShapingFilters
2012
121. Universal Switching FIR Filtering 2012122. Energy-Efficient Low-Latency 600 MHz FIR With High-
Overdrive Charge-Recovery Logic2012
123. Fixed-Point Implementation of Cascaded ForwardBackwardAdaptive Predictors
2012
124. Radix-2 Fast Algorithm for Computing Discrete HartleyTransform of Type III
2012
125. A Reconfigurable FIR Filter Architecture to Trade Off FilterPerformance for Dynamic Power Consumption
2011
126. An Adaptive Kalman Filter for ECG Signal Enhancement 2011127. Analysis and Compensation of the Effects of Analog VLSI
Arithmetic on the LMS Algorithm2011
128. Design of Linear Phase FIR Filters With High Probability ofAchieving Minimum Number of Adders
2011
129. Implementation of Linear-Phase FIR Filters for a RationalSampling-Rate Conversion Utilizing the Coefficient Symmetry
2011
130. Pipelined Parallel FFT Architectures via FoldingTransformation
2011
131. A Quaternion Widely Linear Adaptive Filter 2010132. An Adaptively Pipelined Mixed Synchronous-Asynchronous
Digital FIR Filter Chip Operating at 1.3 Gigahertz2010
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133. First Order Complex Adaptive FIR Notch Filter 2010134. Modulated Wideband Converter with Non-Ideal Lowpass
Filters2010
135. New Approach to Look-Up-Table Design and Memory-BasedRealization of FIR Digital Filter 2010136. New Reconfigurable Architectures for Implementing FIR
Filters with Low Complexity2010
137. Design and Implementation of a New Multilevel InverterTopology_Nov2k12
November 2012
138. Digital Filters for Fast Harmonic Sequence ComponentSeparation 3Ph_Oct2k12 October 2012
139. Spread Spectrum Modulation by Using Asymmetric-CarrierRandom PWM_Oct2k12
October 2012
140. A Fast-Response Pseudo-PWM Buck Converter With PLL-Based Hysteresis Control_Jul2k12
July 2012
141. Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic_Jun2k12
June 2012
142. A Filter Bank and a Self-Tuning Adaptive Filter for theHarmonic and Inter harmonic Estimation in Power Signals
2012
143. A Shifted SVPWM Method to Control DC-Link ResonantInverters and Its FPGA Realization
2012
144. Fully FPGA-Based Sensorless Control for Synchronous ACDrive Using an Extended Kalman Filter
2012
145. Synchronous FPGA-Based High-Resolution Implementationsof Digital Pulse-Width Modulators
2012
146. High Resolution FPGA DPWM Based on Variable Clock PhaseShifting
2010
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147. Dual-Layer Adaptive Error Control for Network-on-ChipLinks_Jul2k12
July 2012
148. Return Data Interleaving for Multi-Channel Embedded CMPsSystems_Jul2k12
July 2012
149. A Reconfigurable Clock Polarity Assignment Flow for ClockGated Designs_Jun2k12
June 2012
150. Parallel Architecture for Hierarchical Optical Flow EstimationBased on FPGA_Jun2k12
June 2012
151. A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing
2012
152. Viterbi-Based Efficient Test Data Compression 2012153. Effective and Efficient Approach for Power Reduction by
Using Multi-Bit Flip-Flops2012
154. A Low-Cost HighQuality Adaptive Scalar for Real-TimeMultimedia Applications
2011
155. A Low-Power High-Performance H.264_AVC Intra-FrameEncoder for 1080pHD Video
2011
156. A VLSI Architecture and the FPGA Prototype for MPEG-2Audio_Video Decoding
2011
157. Development and Implementation of Parameterized FPGA-Based General Purpose Neural Networks for OnlineApplications
2011
158. A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing
2012