vlsi projects

Contact: +91 9158547792

Email: [email protected], [email protected], www.candorminds.com

CODE TITLE DESCRIPTION

IE

EE 2

013

- VLS

I

VL01

Area-Delay Efficient Binary Adders

in QCA

Area Efficient, Quantum-Dot Cellular Automaton, Low-Power

High- Performance Digital Circuits, Low-Area Adders, DSP

VL02

Parallel AES Encryption Engines for

Many-Core Processor Arrays

Area Efficient, Rijindael Algorithm, Mobile Phones, Encryption Decryption

Circuits, Image Processing, Satellite Communication.

VL03

L o w - C o m p l e x i t y M u l t i p l i e r fo r

GF(2m) Based on All-One Polynomials

Area Efficient, Novel Cut-Set Retiming, RS code Encoder and Decoder,

Register Sharing Technique, Storage Devices,

VL04

Split Radix Algorithm for Length 6m

DFT

Area Efficient, Split Radix 3/6 Algorithm, DCT Applications, Spectral

analysis, Data compression, Polynomial multiplication.

VL06

A Novel modulo Adder for 2n-

2k-1 Residue Number System

Low Power, Parallel Prefix Algorithm, Carry Correction Technique,

Arithmetic High-Speed Systems, FIR Filtering

VL07

Low-Power, High-Throughput, and

Low-Area Adaptive FIR Filter Based

on Distributed Arithmetic

Low Power, LMS (least mean square) Adaptive Algorithm, DA- based

technique, Digital radio receivers, Down converts, Software Radio.

VL12

CORDIC Based Fast Radix-2 DCT

Algorithm

High Speed, DCT Algorithm, Fast Radix-2 FFT Technique, Mobile

Multimedia Devices, Signal & Image Processing, Digital Cameras, HDTV.

VL13

Low Latency Systolic Montgomery

Multiplier for Finite Field GF (2m)

Based on Pentanomials

High Speed, Montgomery Multiplication algorithm, Error control coding

systems Elliptic curve cryptography (ECC). RS Transmitter Receiver, AES

Encryption Decryption Design.

VL14

Design of Digit-Serial FIR Filters:

Algorithms, Architectures and a CAD

Tool

High Speed, Exact CSE Algorithm, GB Algorithm, Fourier transforms,

Discrete Cosine Transforms, Error- Correcting Codes, video processing.

mailto:[email protected]


Contact: +91 9158547792



IE

EE 2

013

- VLS

I

VL15

R e d u c e d - C o m p l e x i t y L C C

Reed–Solomon Decoder Based on

Unified Syndrome Computation

High Speed, The Low-Complexity Chase (LCC) Decoding Algorithm, Reed

Solomon Transmitter and Receiver, Storage systems.

VL19

D e s i g n o f Te s t a b l e R e v e r s i b l e

Sequential Circuits

Testing, Conservative Logic Reversible QCA Gate Technique, Fault

coverage for single missing/additional cell, Testing a sequential Circuits.

VL20

Test Patterns of Multiple SIC Vectors:

Theory and Application in BIST

Schemes

Testing, MSIC-TPG Scheme, Built-In Self-Test (BIST) Technique, Circuit

verification section, Electronic system design.

VL21

Gate Mapping Automation for

Asynchronous NULL Convention Logic

Circuits

Testing, Multi-Rail Logic Expression Mapping Algorithm, Industrial

Designs, Encryption Decryption circuits,

VL25

Improvement of the Security of

Zigbee by a New Chaotic Algorithm

VLSI With MATLAB, RFCA (Robust and Fast Chaotic Encryption)

algorithm, Industrial & Medical Applications, Network Security.

VL26

High-Throughput Multi standard

T r a n s f o r m C o r e S u p p o r t i n g

MPEG/H.264/VC-1 Using Common

Sharing Distributed Arithmetic

VLSI With MATLAB, Common Sharing Distributed Arithmetic (CSDA)

algorithm, Digital Cinema, Video And Image Applications, DCT

Compression Application. HDTV broadcast and Digital Cinema

applications.

VL27

Multicarrier Systems Based on

Multistage Layered IFFT Structure

VLSI With MATLAB, IFFT algorithms, Radix-2 Technique, Multiple access

communications, Satellite Communication, Mobile Communication &

OFDM.

VL28

H i g h P e r f o r m a n c e H a r d w a r e

Implementation of AES Using Minimal

Resources

Several cryptographic algorithms, Advanced Encryption Standard (AES)

algorithm, Xilinx– virtex5 Field Programmable Gate Array (FPGA)

VL29

Low-Cost FIR Filter Designs Based on F

a i t h f u l l y R o u n d e d Tr u n c a t e d

multiple constant Multiplication

/Accumulation

Low-cost finite impulse response (FIR), Digital signal processing (DSP),

best area and power results FIR design



Contact: +91 9158547792



IEEE

201

3

VLSI

VL30

VLSI implementation of Fast Addition

u s i n g Q u ate r n a r y S i g n e d D i g i t

Number System

QSD number system, Signed Digit number system one may perform carry

free addition

VL01

Accumulator Based 3-Weight Pattern

Generation

The proposed scheme generates set Pattern Generation of patterns

with weights 0, 0.5, and 1. This scheme can be efficiently utilized to drive

down the hardware of BIST pattern generation. Comparisons with

previously presented schemes indicate that the proposed

scheme compares Favorably with respect to the Required hardware.

IE

EE 2

012

- VLS

I

VL02

An On-Chip Delay Measurement

Technique Using Signature Registers

for Small-Delay Defect Detection

This paper presents a delay measurement technique using

signature analysis, and a scan design for the proposed delay

measurement technique to detect small-Delay defects. The proposed

measurement technique measures the delay of the explicitly sensitized

paths with the resolution of the on-chip variable clock

VL03

Period Extension and Randomness

E n h a n c e m e n t U s i n g H i g h -

Throughput Reseeding-Mixing PRNG

In this paper we present a new reseeding- mixing method to extend

the system period length and to enhance the statistical properties of a

chaos- based logistic map Pseudo random number generator

(PRNG). The reseeding method removes the short periods of the

digitized logistic map and the mixing method extends the system period

length to 2256 by “X Oring” with a DX generator.

VL04

Single Cycle Access Structure for Logic

Test

Eliminates the peak power consumption problem of conventional

shift- based scan chains and reduces the activity during shift and capture

cycles. This leads to more realistic circuit behavior during stuck-at and

at-speed tests.

VL06

Low-Power and Area-Efficient Carry

Select Adder

In this paper we uses a simple and efficient gate-level modification to

significantly reduce the area and power of the CSLA. Architecture have

been developed and compared with the regular SQRT CSLA Architecture.

IE

EE 2

012-

LOW

PO

WER

VL07

A Low-Power Single-Phase Clock

Multiband Flexible Divider

A frequency synthesizer is proposed based on pulse-swallow

topology. The multiband divider consists of a proposed wideband

multi modulus

32/33/47/48 pre scalar and an improved bit-cell for swallow (S) counter.

VL08

On Modulo 2n

+1 Adder Design The first one is built around a sparse carry Computation unit

that computes only some of the carries of the modulo 2n

+1

addition. The second architecture unifies the design of modulo 2n

± 1

adders.

VL09

Measurement and Evaluation of

P o w e r A n a l y s i s A t t a c k s o n

Asynchronous S-Box

In this paper demonstrates the hardware implementation of a

recently proposed low-power asynchronous Advance Encryption

Standard substitution box (S-Box) design that is capable of being

resistant to side channel attack



Contact: +91 9158547792



VL11

Design of an Error Detection and Data

Recovery Architecture for Motion

Estimation Testing Application

In this paper we are presents an error detection and data recovery

(EDDR) design, based on the residue-and-quotient (RQ) code, to embed

into ME for video coding testing applications

VL12

H i g h - T h r o u g h p u t I n t e r p o l a t o r

Architecture for Low-Complexity

Chase Decoding of Rs codes

In this paper, high-throughput interpolator architecture for soft-

decision decoding of Reed–Solomon (RS) codes based on low-

complexity chase (LCC) decoding is presented

VL13

Construction of Optimum Composite

Field Architecture for Compact High-

Throughput AES S-Boxes

In this work, we derive three novel composite field arithmetic (CFA)

Advanced composite field Encryption Standard (AES) S-boxes of the field

GF(22)2)2). The best construction is selected after a sequence of

algorithmic and architectural optimization processes.

VL14

Re d u c e d - C o m p l ex i t y L C C Re e d

–Solomon Decoder Based on Unified

Syndrome Computation

In this paper, a unified syndrome computation algorithm and the

corresponding architecture are proposed. Cooperating with the KES in

the reduced inversion-free Berlekamp-Messy algorithm, the reduced

complexity

VL16

A H i g h - A c c u r a c y A d a p t i v e

Conditional-Probability Estimator for

Fixed-Width Booth Multipliers

In this paper, a single compensation formula of adaptive conditional-

probability estimator (ACPE) applied to fixed-width Booth multiplier is

proposed. Based on the conditional- probability theory, the ACPE can be

easily applied to large length Booth multipliers

VL17

Low-Complexity Multiplier for GF(2m)

Based on All-One Polynomials

This paper presents an area-time-efficient systolic structure for

multiplication over based on all-one polynomial (AOP). We have used a

cut-set retiming to reduce the duration of the critical-path to one XOR

gate delay

VL22

A High Performance Video Transform

E n g i n e b y U s i n g S p a c e - T i m e

Scheduling Strategy

The proposed spatial scheduling strategy includes the ability to

choose the distributed arithmetic (DA)-precision bit length, a hardware

sharing architecture that reduces the hardware cost, and the

proposed time scheduling strategy.

VL23

Precision-Aware Self-Quantizing

Hardware Architectures for the

Discrete Wavelet Transform

This paper presents designs for both bit- parallel (BP) and digit-serial (DS)

precision optimized implementations of the discrete wavelet

transform (DWT), with specific consideration given to the impact of

depth on the overall computational accuracy.

VL24

Area-Efficient Parallel FIR Digital Filter S

t r u c t u r e s f o r S y m m e t r i c

Convolutions Based on Fast FIR

Algorithm

The proposed parallel FIR structures exploit the inherent nature of

symmetric coefficients reducing half the number of multipliers in sub filter

section at the expense of additional adders in Preprocessing and

post processing blocks.

VL25

Quantization Noise Suppression in

Fractional-PLLs Utilizing Glitch-Free

Phase Switching Multi-Modulus N-

Frequency Divider

The proposed phase switching multi- modulus frequency divider (PS-

MMFD) utilizes a novel glitch-free phase switching (PS) divide-by-

0.5/1/1.5/2 cell to reduce the frequency division step to 0.5.



vlsi projects

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