VLSI: SYSTEMS ON A CHIP

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VLSI: SYSTEMS ON A CHIP

IFlP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI December 1-4, 1999, Lisboa, Portugal

Edited by

Luis Miguel Silveira INESC Portugal

Srinivas Devadas Massachusetts Institute of T echnology USA

Ricardo Reis Universidade Federal do Rio Grande do Sul Brazil

,. SPRINGER SCIENCE+BUSINESS MEDIA, LLC

Library of Congress Cataloging-in-Publication Data

IFIP TCl O/WGl 0.5 International Conference on Very Large Scale Integration (lOth : 1999 : Lisbon, Portugal)

VLSI: systems on a chip: IFIP TClO WGI0.5 Tenth International Conference on Very Large Scale Integration (VLSI'99), December 1-4, 1999, Lisboa, Portugal 1 edited by Luis Miguel Silveira, Srinivas Devadas, Ricardo Reis.

p. cm. - (International Federation for Information Processing; 34) Includes bibliographical references and index. ISBN 978-1-4757-1014-4 ISBN 978-0-387-35498-9 (eBook) DOI 10.1007/978-0-387-35498-9 1. Integrated circuits-Very large scale integration-Design and construction­

Congresses. 2. Integrated circuits-Very large scale integration---Computer-aided design­Congresses. 3. Embedded computer systems-Design and construction---Congresses. 4. Computer storage devices-Design and construction---Congresses. I. Silveira, Luis Miguel. 11. Devadas, Srinivas. III. Reis, Ricardo A.L. (Ricardo Augusto da Luz). IV. Title. V. International Federation for Information Processing (Series); 34. TK7874.I328 1999 621.39'5-dc21 99-049486

Copyright @ 2000 by Springer Science+Business Media New York

Origina1ly published by International Federation for Information Processing in 2000

Softcover reprint ofthe hardcover 1st edition 2000

All rights reserved. No part ofthis publication rnay be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission ofthe publisher, Springer Science+Business Media, LLC.

Printed on acid-free paper.

by IFIP International Federation for Information Processing

The original version of the book frontmatter was revised: The copyright line was incorrect. The Erratum to the book frontmatter is available at DOI: 10.1007/978-0-387-35498-9_57

TABLE OF CONTENTS

Preface ........................................................................................................ xi

Conference Committees .......................................................................... xv

Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application Shenggao Li,Yue Wu, Chunlei Shi, Mohammed Ismail.. ........................... 1

An Analog Non-Volatile Storage System for Audio Signals with Signal Conditioning for Mobile Communication Devices G. B. Jackson, S. V. Awsare, L. D. Engh, M. A. Hemming, P. Holzmann, O. C. Kao, C. Mai-Liu, C. R. Palmer, A Raina ...................... 11

A Design of Operational Amplifier for Sigma Delta Modulators Using O.35um CMOS Process Bingxin Li, Hannu Tenhunen ..................................................................... 23

A Low Power CMOS Micromixer for GHz Wireless Applications Yue Wu, Shenggao Li, Mohammed Ismail, Hakan Olsson ...................... 35

High Current, Low Voltage Current Mirrors and Applications S. S. Rajput, S. S. Jamuar ........................................................................... 47

Nonlinearity Analysis of a Short Channel CMOS Circuit for RFIC Applications Yue Wu, Hong-sun Kim, Fredrik Jonsson, Mohammed Ismail, Hakan Olsson .............................................................................................. 61

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VI Table ofContents

A Fast Parametrie Model for·Contact-Substrate Coupling Nasser Masoumi, Mohamed I. Elmasry, Safeiddin Safavi-Naeini.. ...... 69

A Feature Associative Processor for Image Recognition Based on A-D merged Architecture Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Hornrna, Hiroto Higashi, Takashi Morie .................... 77

Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications A.M.Rassau, G.Alagoda, D.Lucas, J.Austin-Crowe, K.Eshraghian ...... 89

Implementation of a Wavelet Transform Architecture for Image Processing Camille Diou, Lionel Torres, Michel Robert ......................................... 101

Scalable Run Time Reconfigurable Architecture Abdellah Touhafi, Wouter Brissinck, Erik Dirkx .................................. 113

Frontier: A Fast Placement System For FPGAs Russell Tessier ......................................................................................... 125

Dynamically Reconfigurable Implementation of Control Circuits Nuno Lau, Valery Sklyarov .................................................................... 137

An IEEE Compliant Floating Point MAF R.V.K.Pillai, D.AI-Khalili, A.J. AI-Khalili ............................................ 149

Design and Analysis of On-Chip CPU Pipelined Caches C. Ninos, H. T. Vergos, D. Nikolos ........................................................ 161

Synchronous to Asynchronous Conversion - A Case Study: the Blowfish Aigorithm Implementation Joao M. S. Alcantara, Sergio C. Salomao, Edson do Prado Granja, Vladimir C. Alves, Felipe M. G. ......................... 173

Clock Distribution Strategy for IP-based Development Rui L. Aguiar, Dinis M. Santos .............................................................. 181

An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures David H. Albonesi ................................................................................... 192

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Table ofContents

Single Ended Pass-Transistor Logic - A Comparison with CMOSandCPL Mihai Munteanu, Peter A. Ivey, Luke Seed, Marios

vii

Psilogeorgopoulos, Neil Powell, Istvan Bogdan .................................... 206

Multithreshold Voltage Technology for Low Power Bus Architecture A. Rjoub, O. Koufopavlou ...................................................................... 219

Integrating Dynamic Power Management in the Design Flow Antönio Mota, Nuno Ferreira, Arlindo Oliveira, Jose Monteiro .......................................................................................... 233

Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI Stefan Lachowicz, Kamran Eshraghian, Hans-J'rg Pfleiderer .................................................................................................. 245

On Defect-Level Estimation and the Clustering Effect Jose T. de Sousa ...................................................................................... 257

FASTNR: an Efficient Fault Simulator for Linear and Nonlinear DC Circuits J. Soares Augusto and C. F. Beltran Almeida ........................................ 269

Design Error Diagnosis in Digital Circuits without ErrorModel Raimund Ubar, Dominique Borrione ...................................................... 281

Efficient RLC Macromodels for Digital IC Interconnect Bogdan Tutuianu, Daksh Lehther, Madhulima Pandey, Ross Baldick ............................................................................................ 293

A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications Alex Doboli, Ranga Vemuri ................................................................... 305

A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements Adrian Nunez-Aldana, Ranga Vemuri... ................................................. 318

RF Interface Design Using Mixed-Mode Methodology A. Gallegos, P. Silvestre, M. Robert, D. Auvergne ................................ 326

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History-Based Dynamic Minimization During BDD Construction

Table ofContents

Rolf Drechsler, Wolfgang Günther ......................................................... 334

Aura 11: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems Luca P. Carloni, Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli ....................... 346

Satisfiability-Based Functional Delay FauIt Testing Joonyoung Kirn, Joao Silva, Karern Sakallah ........................................ 362

Verification of Abstracted Instruction Cache of TIT AC2: A Case Study Tornohiro Yoneda .................................................................................... 373

Speeding Up Look-up-Table Driven Logic Simulation Rajeev Murgai, Furniyasu Hirose, Masahiro Fujita ............................... 385

Efficient Verification ofBehavioral Models Using Sequential Sampling Technique Tom Chen, Isabelle Munn, Anneliese von Mayrhauser, Arnjad Hajjar ........................................................................................... 398

Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies S. Rairnbault, G. Sassatelli, G. Carnbon, M. Robert, S. PilIernent, L. Torres ................................................................................. 407

A Virtual CMOS Library Approach for Fast Layout Synthesis F. Moraes, M.Robert, D.Auvergne, ........................................................ 415

RT-Ievel Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime Ananth Durbha, Srinivas Katkoori ......................................................... 427

Designing a Mask Programmable Matrix for Sequential Circuits Femanda Lirna, Marcelo Johann, Jose Güntzel, Eduardo D'Avila, Luigi Carro, Ricardo Reis ........................................................ 439

Placement Benchmarks for 3-D VLSI Stefan Thornas Obenaus, Ted H. Szyrnanski ......................................... 447

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Substrate Noise: Analysis, Models, and Optimization Edoardo Charbon, Joel Phillips ............................................................... 456

Arcbitectural Transformations for Hierarcbical Aigoritbmic Descriptions Marcio Yukio Teruya, Marius Strum and Wang Jiang Chau ............................................................................................... 473

An Enbanced Static-List Scbeduling Aigoritbm for Temporal Partitioning onto RPUs Joao M P Cardoso, Horacio C Neto ........................................................ 485

Object-Oriented Modeling and Co-Simulation of Embedded Systems Flavio Rech Wagner, Marcio Oyamada, Luigi Carro, Marcio Kreutz .......................................................................................... 497

Arcbitectural Syntbesis witb Interconnection Cost Control C. Jego, E. Casseau, E. Martin ................................................................ 509

CAE Environment for Electromecbanical Microsystems R. Lerch, M. Kaltenbacher, H. Landes ................................................... 521

Cost Consideration for Application Specific Microsystems Pbysical Design Stages - A New Approacb for Microtecbnological Process Design R. Brück, A. Priebe, K. Hahn .................................................................. 533

Moving MEMS into Mainstream Applications : Tbe MEMSCAP Solution K. Liateni, D. Moulinier, B. Affour, A. Delpoux, J.M. Karam ............. 544

Trends in RF Simulation Aigoritbms Joel Phillips, Dan Feng ............................................................................ 557

Device Modeling and Measurement for RF Systems Franz Sischka ........................................................................................... 569

Reconfigurable Computing: Viable Applications and Trends Alexandro M. S. Adario, Sergio Bampi ................................................ 583

Hardware Syntbesis from Term Rewriting Systems James C. Hoe and Arvind ........................................................................ 595

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Preface

For over three decades now, silicon capacity has steadily been doubling every year and a half with equally staggering improvements continuously being observed in operating speeds. This increase in capacity has allowed for more complex systems to be built on a single silicon chip. Coupled with this functionality increase, speed improvements have fueled tremendous advancements in computing and have enabled new multi-media applications. Such trends, aimed at integrating higher levels of circuit functionality are tightly related to an emphasis on compactness in consumer electronic products and a widespread growth and interest in wireless communications and products. These trends are expected to persist for some time as technology and design methodologies continue to evolve and the era of Systems on a Chip has definitely come of age.

While technology improvements and spiraling silicon capacity allow designers to pack more functions onto a single piece of silicon, they also highlight a pressing challenge for system designers to keep up with such amazing complexity. To handle higher operating speeds and the constraints of portability and connectivity, new circuit techniques have appeared. Intensive research and progress in EDA tools, design methodologies and techniques is required to empower designers with the ability to make efficient use of the potential offered by this increasing silicon capacity and complexity and to enable them to design, test, verify and build such systems.

Solutions to improving designer productivity include the development of new tools and techniques, increasing the abstraction level of designs and introducing reuse of components and systems parts. This book contains a set of papers, which address various subproblems arising in VLSI design, that were presented at the tenth IFIP Very Large Scale Integrated Systems

xii Preface

conference, VLSI'99. This conference is organized biannually by IFIP Working Group 10.5. Previous conferences in this series have taken place in Edinburgh, Trondheim, Vancouver, Munich, Grenoble, Tokyo and Gramado. This conference, at the tuming point of the millenium and in an atmosphere of rapid and exciting change, took place at the Hotel Meridien Park Atlantic, in Lisbon, Portugal, from 1-4 December 1999.

The current trend towards the realization of complex and versatile Systems on a Chip requires the combined efforts and attention of experts in a wide range of areas including microsystems, embedded hardware/software systems, dedicated ASIC and programmable logic hardware, reconfigurable computing, wireless communications and RF issues, video and image processing, memory systems, low power design techniques, design, test and verification algorithms, modeling and simulation, logic synthesis, and interconnect analysis. Thus, the papers presented at VLSI'99 address a wide range of Systems on a Chip problems.

Traditionally, the conference has been organized around two parallel tracks, one dealing with VLSI Systems Design and Applications and the other discussing VLSI Design Methods and CAD. In this context the following topics were addressed:

VLSI Systems Design and Applications • Analog Systems Design • Analog Modeling and Design • Image Processing • Reconfigurable Computing • Memory and System Design • Low Power Design

VLSI Design Methods and CAD • Test and Verification • Analog CAD and Interconnect • Fundamental CAD Algorithms • Verification and Simulation • CAD for Physical Design • High-level Synthesis and Verification ofEmbedded Systems

Additionally a number of special sessions and embedded tutorials were organized by experts in their respective fields. These include:

• Design methodologies for Microsystems • RF Design and Analysis • FPGA's and reconfigurable hardware

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Preface Xl1l

• Architectural Synthesis and Verification • Timing and Verification • CAD for Microelectromemchanical systems • Interconnect Process Parametrization • Design of Multimedia Systems on Chip

We hereby would like to thank IFIP and more specifically IFIP TCI0 and IFIP WG 10.5 for the support of this event, the members of the Organizing Committee and the reviewers that had the daunting task of carefully selecting and providing feedback for the papers submitted. Most of all however, we would like to thank all the researchers and authors that submitted papers to the conference and presented their work there, thus contributing decisively to its success!

Luis Miguel Silveira, Lisboa, Portugal Srinivas Devadas, Cambridge, MA, U.S.A.

Ricardo Reis, Porto Alegre, RS, Brazil

December, 1999

xv

Conference Committees

GENERAL CHAIR: Luis Miguel Silveira, - Systems and Computers Research Institute (INESC) and

Cadence Europeans Laboratories (CEL), Dept. 0/ Electrical and Computer Engineering, Instituto Superior TIJcnico (IST), Technical University 0/ Lisbon,

Lisbon, Portugal, lms@inesc.pt

GENERAL VICE-CHAIR: Jose Carlos Monteiro - Systems and Computers Research Institute (INESC), Dept. 0/

In/ormatics, Instituto Superior TIJcnico (IST), Technical University 0/ Lisbon, Lisbon, Portuga, jcm@inesc.pt

TECHNICAL PRO GRAM COMMITTEE CHAIR: Srinivas Devadas - Laboratory /or Computer Science, Dept. 0/ Elect. Eng. and Comp.

Science Massachusetts Institute 0/ Technology, Cambridge, MA USA, devadas@lcs.mit.edu

VICE CO-CHAIRS OF TECHNICAL PROGRAM COMMITTEE: Systems Design Track:

Prof. Peter Ivey - University o/Sheffield, UK,p.iveY@Sheffield.ac.uk Design Methods Track:

Joao Marques-Silva - INESC/IST/CEL, Lisbon, Portugal,jpms@inesc.pt

FINANCE CHAIR: Arlindo Oliveira - INESC/IST/CEL, Lisbon, Portugal, aml@inesc.pt

xvi Conference Committees

TUTORIALS CHAIR: Luciano Lavagno - DIEGM, Universita di Udine, Udine, Italy,

luciano.lavagno@diegm.uniud.it

PUBLICATIONS CHAIR: Ricardo Reis - Instituto de Informatica, Universidade Federal do Rio Grande do Sul,

Porto Alegre, Brazil, reis@infufrgs.br

PUBLICITY CHAIR: Bemard Courtois - TIMA, Grenoble, France, Bernard.Courtois@imagfr

TECHNICAL PROGRAM COMMITTEE: Adam Postula, Royal Inst. ofTech., S

Anton Chichkov, Alcatel, BE

Antönio Ferrari, Univ. Aveiro, P

Antönio Leal, ISTIINESC, P

Arlindo Oliveira, ISTIINESCICEL, P

Bemard Courtois, TIMAlIMAG, FR

Dominique Borrione, TJMAlIMAG, FR

Donnatella Sciuto, PoUt. Milano, IT

Eduard Cemy, University of Montreal, CA

Flavio Rech Wagner, Univ. Rio Grande do Sul, BR

Franz J. Rammig, Univ. Paderborn, D

George Milne, Univ. ofSouthAustralia, AU

Gerd J.E. Schell er, Philips AG

Grant Martin, Cadence, USA

Hannu Tenhunen, KTH, S

Hans Eveking, Univ. Darmstadt, D

Horacio Neto, ISTIINESC, P

Irith Pomeranz, Univ. Iowa, USA

Joan Figueras, UPC, ES

Joao Marques-Silva, ISTIINESCICEL, P

JoaO Paulo Teixeira, ISTIINESC, P

Joao Vital, ISTIIT, P

Jochen Jess, Tech. Univ. Eindhoven, NL

John Hayes, Univ. Michigan

Jose Carlos Monteiro, ISTIINESC, P

Jose de Sousa, Bell Labs, Lucent

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Conference Committees

Jose Epif'nio da Franca, IST/IT, P

Jose Huertas, Univ. Sevilla, ES

Karem Sakallah, Univ. Michigan, USA Karl-Heinz Diener, Fraunhofer Inst., D

Leonel Sousa, IST/INESC, P

Luciano Lavagno, Polit. Torino, IT

Luis Miguel Silveira, IST/INESC/CEL, P

M. Helena Sarmento, IST/INESC, P

Maciej 1. Ciesielski, Univ. Massachusetts, USA

Manfred Glesner, Univ. Darmstadt, D

Manuel Medeiros Silva, IST/INESC, P

Martyn Edwards, UMIST, UK

Masahiro Fujita, Fujitsu Labs, USA

Mattan Kamon, Microcosm Technologies, MA, USA

Michel Robert, Univ. Montpellier, FR

Neil Weste, Radiata Communications, AU Odysseas Koufopavlou, University of Patras

Pasupathi A. Subrahmanyam, Bell Laboratories, Holmdei, USA

Paul Jespers, Univ. Catholique de Louvain, BE

Pedro Guedes de Oliveira, DEECIFEUP

Peter A. Ivey, University ofSheffield, UK

Pranav Ashar, NEC, USA Przemyslaw Bakowski, IRESTE Nantes, FR

Ricardo Reis, Univ. Rio Grande do Sul, BR

Roger Woods, The Queen's Univ. ofBelfast, UK

Rolf Becker, Philips

RolfDrechsler, Univ. Freiburg, D Stephane Donnay, IMEC, BE

Steve Furber, Manchester Univ., UK

Tiziano Villa, Parades, IT

Tsutomu Sasao, Kyushu Institute ofTechnology, JP Vigyan Singhal, Cadence Berkeley Labs, CA

Warren A. Hunt, Jr., IBMCorporation

Wayne Burleson, Univ. Massachusetts, USA Wemer Grass, Univ. Passau, D

Wolfgang Kunz, Univ. Frankfurt, D

Wolfgang Nebel, Univ. Oldenburg, D

Wolfgang Rosenstiel, Univ. Tuebingen, D

Yusuke Matsunaga, Fujitsu, JP

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SPECIAL SESSION CHAIRS: Jaijeet Roychowdury, Bell Labs, USA

Karem Sakallah, u. Michigan

Klaus Mueller-Glaser, TU Karlsruhe, Germany

Manfred Glesner, TU Darmstadt, Germany

Marios Papaefthymiou, u. Michigan

Sergio Bampi, URFGS, Brazil

Srinivas Devadas, MIT, USA

ORGANIZING COMMITTEE: Luis Miguel Silveira, INESCIISTICEL, Lisboa, Portugal

Jose Carlos Monteiro, INESCIIST, Lisboa, Portugal

Joao Marques-Silva, INESCIISTICEL, Lisboa, Portugal

Arlindo Oliveira, INESCIISTICEL, Lisboa, Portugal

Ana Teresa Freitas, INESCIIST, Lisboa, Portugal

Ricardo Reis, UFRGS, Porto Alegre, Brazil

Conference Committees

Ana Cristina Medina Pinto, UFRGS, Porto Alegre, Brazil

Flavio Luiz de Oliveira Zimmermann, , UFRGS, Porto Alegre, Brazil

Luciano Volcan Agostini, UFRGS, Porto Alegre, Brazil

SECRETARIAT: Ana Cardoso, INESC, Lisboa, Portugal

Ana de Jesus, INESC, Lisboa, Portugal

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