VLSI Technology12MEVL_E18Course Plan

Lecturer: Mahendra Babu.G.RSemester : 3 2013-14Number of Credits: 3Course Type: ElectiveCourse Synopsis:

This course is designed to introduce the basic concepts of VLSI technology and provide an understanding of the VLSI manufacturing process of different methods. The course also helps the students to develop the skills in VLSI technology for various applications.Course Outcomes (C.O)C.O.1: Ability to understand the initial processes crystal growth, wafer preparation etc in IC manufacturing. C.O.2: Ability to interpret, discuss and apply deposition, duffusion, Ion implementation and metallization. C.O.3: Ability to interpret, discuss and apply process simulation and process integration. C.O.4: Ability to interpret, discuss and apply concepts of analytical, assembly techniques and packaging of VLSI devices. Course SyllabusUNIT I CRYSTAL GROWTH, WAFER PREPARATION, EPITAXY AND OXIDATION [Lecture 1, 2 & 3]Electronic Grade Silicon, Czochralski crystal growing, Silicon Shaping, processing consideration, Vapor phase Epitaxy, Molecular Beam Epitaxy, Silicon on Insulators, Epitaxial Evaluation, Growth Mechanism and kinetics, Thin Oxides, Oxidation Techniques and Systems, Oxide properties, Redistribution of Dopants at interface, Oxidation of Poly Silicon, Oxidation inducted Defects.

UNIT II LITHOGRAPHY AND RELATIVE PLASMA ETCHING [Lecture 4]Optical Lithography, Electron Lithography, X-Ray Lithography, Ion Lithography, Plasma properties, Feature Size control and Anisotropic Etch mechanism, relative Plasma Etching techniques and Equipments,UNIT III DEPOSITION, DIFFUSION, ION IMPLEMENTATION AND METALISATION [Lecture 5 & 6]Deposition process, Polysilicon, plasma assisted Deposition, Models of Diffusion in Solids, Flicks one dimensional Diffusion Equation Atomic Diffusion Mechanism Measurement techniques Range theory- Implant equipment. Annealing Shallow junction High energy implantation Physical vapour deposition Patterning.UNIT IV PROCESS SIMULATION AND VLSI PROCESS INTEGRATION [Lecture 7 & 8]Ion implantation Diffusion and oxidation Epitaxy Lithography Etching and Deposition- NMOS IC Technology CMOS IC Technology MOS Memory IC technology - Bipolar IC Technology IC Fabrication.UNIT VANALYTICAL, ASSEMBLY TECHNIQUES AND PACKAGING OF VLSI DEVICES [Lecture 9]Analytical Beams Beams Specimen interactions - Chemical methods Package types banking design consideration VLSI assembly technology Package fabrication technology.

WEEKLECTURE DATESLECTURETEST / EXAMASSIGNREMARKS

117,19,20,21 JuneLecture 1: Electronic Grade Silicon, Czochralski crystal growing, Silicon Shaping, processing consideration, Vapor phase EpitaxyCIA T1 Q1 ESE Q1Wednesday Student Seminar

224,26,27,28 JuneLecture 2: Molecular Beam Epitaxy, Silicon on Insulators, Epitaxial Evaluation, Growth Mechanism and kineticsCIA T1 Q1 ESE Q1

31,3,4,5 JulyLecture 3: Thin Oxides, Oxidation Techniques and Systems, Oxide properties, Redistribution of Dopants at interfaceCIA T1 Q2 ESE Q1Seminar

48,10,11,12 JulyLecture 3: Oxidation of Poly Silicon, Oxidation inducted DefectsCIA T 1 Q2 ESE Q1Seminar

515,17,18,19 JulyLecture 4: Optical Lithography, Electron Lithography, X-Ray Lithography, Ion Lithography, Plasma propertiesCIA T1 Q3 ESE Q2Seminar

622,24,25,26 JulyLecture 4: Feature Size control and Anisotropic Etch mechanism, relative Plasma Etching techniques and EquipmentsCIA T1 Q4 ESE Q2Seminar

729,31 July

1,2 AugLecture 5: Deposition process, Polysilicon, plasma assisted Deposition, Models of Diffusion in Solids, Flicks one dimensional Diffusion EquationCIA T1 Q5 ESE Q3Seminar

85,7,8,9 AugLecture 5: Atomic Diffusion Mechanism Measurement techniques Range theory- Implant equipment.CIA T1 Q5 ESE Q3Seminar

919,21,22,23 Aug Topics: Week 1 to Week 8 TEST I

2,4,5,6 SepLecture 6: Annealing Shallow junction High energy implantation Physical vapour deposition Patterning.CIA T2 Q1 ESE Q3Seminar Wednesday Student Seminar

PBL: Problem Based Learning

119,11,12,13 SepLecture 7: Ion implantation Diffusion and oxidation Epitaxy Lithography Etching and DepositionCIA T2 Q2 ESE Q4Seminar

1216,18,19,20 SepLecture 7: NMOS IC Technology CMOS IC Technology MOS Memory IC technologyCIA T2 Q3 ESE Q4Seminar

1323,25,26,27 SepLecture 8: Bipolar IC Technology IC Fabrication.CIA T2 Q3 ESE Q4Seminar

1430 Sep, 2,3,4 OctLecture 9: Analytical Beams Beams Specimen interactions - Chemical methodsCIA T2 Q4 ESE Q5Seminar

157,9,10,11 OctLecture 9: Package types banking design consideration VLSI assembly technology Package fabrication technology.CIA T2 Q5 ESE Q5Seminar

1621,23,24,25 OctRevision Clinic (Unit 1 to 5)

1728,29,30 OctTopics: Week 11 to Week 16 TEST II

REFERENCE BOOKS1. S.M.Sze, 1998, VLSI Technology, Mc.Graw.Hill, New Delhi. 2. Amar mukherjee, 2000, Introduction to NMOS and CMOS VLSI System design, Prentice Hall India3. James D Plummer, Michael D. Deal, Peter B.Griffin, 2000, Silicon VLSI Technology: fundamentals practice and Modeling, Prentice Hall India4. Wai Kai Chen, 2003, VLSI Technology, CRC PressCONTINOUS INTERNAL ASSESSMENT

Test 1 & 2

: 30 marksSeminar (assgn)

: 5 marks Attendance

: 5 marksSEMESTER EXAMS

: 60 marks Total

100 marks SEMINAR (ASSIGNMENT)

Each student will have to give a seminar presentation on any one of the following topics according to roll no. in the form of PPT presentation for 20 minutes (three students per week)Seminar Evaluation (communication skill: 2 marks; presentation: 2 marks; attitude: 1 mark)Seminar Topics1. Introduction to VLSI manufacturing process2. Silicon on Insulators3. Epitaxial Evaluation4. Growth Mechanism and kinetics,5. Oxidation inducted Defects 6. Feature Size control and Anisotropic Etch mechanism7. Relative Plasma Etching techniques and Equipments8. Measurement techniques Range theory- 9. Implant equipment. 10. Physical vapour deposition Patterning.11. MOS Memory IC technology 12. Bipolar IC Technology

13. IC Fabrication14. Banking design consideration

15. VLSI assembly technology

16. Package fabrication technology