w. g. oldham and s. rosseecs 40 fall 2002 lecture 6 1 circuits, nodes, and branches last time:...

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W. G. Oldham and S. Ro EECS 40 Fall 2002 Lecture 6 1 CIRCUITS, NODES, AND BRANCHES Last time: • Looked at circuit elements, used to model the insides of logic gates • Saw how the resistor and capacitor in the gate circuit model make the change in output voltage gradual • Looked at the mathematical equations that describe the output voltage Today: Derive the mathematical equation for the change in gate output voltage Practice an easy method used to graph and write the equation for the changing output voltage Look at how R and C affect the rate of change in output voltage Look at how R and C affect how quickly we can put new signals through Review ideas we will need to understand Kirchoff’s laws

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W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

1

CIRCUITS, NODES, AND BRANCHES

Last time:

• Looked at circuit elements, used to model the insides of logic gates

• Saw how the resistor and capacitor in the gate circuit model make the change in output voltage gradual

• Looked at the mathematical equations that describe the output voltage

Today:

• Derive the mathematical equation for the change in gate output voltage

• Practice an easy method used to graph and write the equation for the changing output voltage

• Look at how R and C affect the rate of change in output voltage

• Look at how R and C affect how quickly we can put new signals through

• Review ideas we will need to understand Kirchoff’s laws

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

RC RESPONSE

Vin

RVout

C

Internal Model

of Logic Gate

time

Vout

00

Vout

0

Vin

time0

Vout(t=0) Vin

Vout(t=0)

Behavior of Vout after change in Vin

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

RC RESPONSE

We said that Vout(t) has the general exponential form

Vout(t) = A + Be-t/

Initial value Vout(t=0) = A + B Final value Vout(t→∞) = A

But we know Vout(t→∞) = Vin so rewrite

Vout(t) = Vin + [Vout(t=0)-Vin]e-t/

We will now prove that time constant is RC

Remember, Vout(t) has gone 63% of the way from initial to final value after 1 time constant.

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

RC RESPONSE: Proof of Vout equation

law) ce(capacitan dt

dVCi law) s(Ohm'

R

VVi out

Coutin

R

! ii But CR

)VV(RC

1

dt

dV

dt

dVC

R

VV Thus, outin

outoutoutin

or

Vin

RVout

CiCiR

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

RC RESPONSE: Proof

RCt/-outin 0)]e(tV-[V

RC

1

)]]eV-0)(t[V(V-[V RC

1 (t))V-(V

RC

1 RCt/-inoutininoutin

RCt/-outin 0)]e(tV-[V

RC

1

)VV(RC

1

dt

dVoutin

out

Vout(t) = Vin + [Vout(t=0)-Vin]e-t/RC

We know

Is a solution? Substitute:

RC/tinout

RC/tinoutin

out e]V)0t(V[RC

1e]V)0t(V[V

dt

d

dt

dV

This is the solution since it has the correct initial condition!

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

Example: Draw graph and write equation

Input node Output node

ground

R

CVin

Vout+

-

Assume Vin has been zero for a long time, and steps up to 10 V at t=0.

Assume R = 1KΩ, C = 1pF .

Ingredients for graph:

time

Vin

0

0

10

Vout

1nsec

6.3V

1) Initial value of Vout is 0

2) Final value of Vout is Vin=10V

3) Time constant RC is 10-9 sec

4) Vout reaches 0.63 X 10 in 10-9 sec

Vout(t) = 10 - 10e-t/1nsecVout(t) = Vin + [Vout(t=0)-Vin]e-t/RC =>

Ingredients for equation:

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

Charging and discharging in RC Circuits(The official EE40 Easy Method)

Input node Output node

ground

R

CVin

Vout+

-

4) Find the asymptotic value Vout(t→∞), in this case, equals Vin after step

5) Sketch the transient period. After one time constant, the graph has passed 63% of the way from initial to final value.

6) Write the equation by inspection.

1) Simplify the circuit so it looks like one resistor, a source, and a capacitor (it will take another two weeks to learn all the tricks to do this.) But then the circuit looks like this:

Method of solving for any node voltage in a single capacitor circuit.

2) The time constant is = RC.

3) Find the capacitor voltage before the input voltage changes. This is the initial value for the output, Vout(t=0).

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

PULSE DISTORTION

What if I want to step up the input,

wait for the output to respond,

then bring the input back down for a different response?

time

Vin

0

0

time

Vin

0

0

Vout

time

Vin

0

0

Vout

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

Input node Output node

ground

R

CVin+

-

OThe pulse width (PW) must be greater than RC to avoid severe pulse distortion.

0

1

2

3

4

5

6

0 1 2 3 4 5Time

Vo

ut

PW = 0.1RC

01

23

45

6

0 1 2 3 4 5Time

Vo

ut

PW = RC

0

1

2

3

4

5

6

0 5 10 15 20 25Time

Vo

ut

PW = 10RC

PULSE DISTORTION

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

EXAMPLE

VinR

Vout

C

Suppose a voltage pulse of width5 s and height 4 V is applied to theinput of the circuit at the right.

Sketch the output voltage.

R = 2.5 KΩC = 1 nF

First, the output voltage will increase to approach the4 V input, following the exponential form. When the input goes back down, the output voltage will decrease back to zero, again following exponential form.

How far will it increase? Time constant = RC = 2.5 sThe output increases for 5s or 2 time constants.It reaches 1-e-2 or 86% of the final value.0.86 x 4 V = 3.44 V is the peak value.

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

EXAMPLE

00.5

11.5

22.5

33.5

4

0 2 4 6 8 10Just for fun, the equation for the output is:

Vout(t) =4-4e-t/2s for 0 ≤ t ≤ 5 s

3.44e-(t-5s)/2.5s for t > 5 s{

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

APPLICATIONS

• Now we can find “propagation delay” tp; the time between the input reaching 50% of its final value and the output to reaching 50% of final value.

• Today’s case, using “perfect input” (50% reached at t=0): 0.5 = e-tp

tp = - ln 0.5 = 0.69It takes 0.69 time constants, or 0.69 RC.

• We can find the time it takes for the output to reach other desired levels. For example, we can find the time required for the output to go from 0 V to the minimum voltage level for logic 1.

• Knowing these delays helps us design clocked circuits.

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

Adding Voltages in Series

In electrical engineering we generally add voltage drops.

Example:

1. Go around the path that comprises Vx. Start at + terminal,end at – terminal.

2. Look at the first sign you encounter at each element. If +, add that voltage. If -, subtract.

3. The final sum is Vx. + 5 – 8 – 6 + 8 = -1 And that’s OK!

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

JUST PICK A POLARITY

• In the last slide, we “guessed Vx wrong”; the bottom end was actually higher potential than the top. WE DON’T CARE!

• If I need to find a voltage or current, I just give it a name and write down a polarity/direction. Whatever I feel like at the time. Then I solve for the unknown. If the voltage/current “doesn’t really go that way”, the answer will be negative. SO WHAT.

• Just remember how to flip things if you need to:

Ix

-Ix

- Vx +

+ -Vx -

Same

Thing!

W. G. Oldham and S. RossEECS 40 Fall 2002 Lecture 6

@#%*ING ASSOCIATED REFERENCE CURRENTS

We only need to worry about associated reference currents in 3 situations (here we need to have associated reference current):

1. Using Ohm’s law in a resistor

2. Using I = C dV/dt in a capacitor

3. Calculating power P=VI

I

+ V -

Otherwise, forget about it! Work with currents and voltage in whatever direction you want!