WaitLess: Changing Restaurants Today for a Better Tomorrow

Probably put a picture here

of like a restaurant or something

also maybe a better subtitle? I'll think on it and maybe delete this before anybody sees it

also a logo would be cool but I doubt we have anyone who could design one, maybe we could steal the Sprint one, who cares about intellectual property rights anyway

Team Members: Jared Dubin, Terry Garove, Alex RunasDesign Manager: Panchalam Ramanujan

Presentation Outline

Marketing Project Description Behavior Description Design Process Floor Plan Evolution Layout Verification Issues Encountered Specifications Conclusions

WaitLess Market Potential

Total Available Market is millions of restaurants worldwide

At one unit per table per restaurant and an estimated 50% gross profit per unit, potential gross is upwards of 50 million dollars

Unit pays for itself in lower wait staff costs almost immediately, not to mention increased restaurant throughput due to smaller wait times and increased desire to dine outSprinkler buddy had a cool picture background, we should try that

Unit Specifics Touchscreen Display Generic processor with software pre-programmed to run a User

Interface that displays the menu Non-volatile memory to store menu items in Wireless Transmitting Unit to send orders to kitchen Payment Acceptor (Cash/Credit) WaitLess Interface chip to store data and provide control signals

Total Estimated Cost of Production: $50 / unit, mostly for display Estimated Packaged Sale Price: $75 / unit, or more Total Cost to a Restaurant with 100 tables: $7500 Gross pay to one single waiter at minimum wage for 9 months:

$10400

Unit Flow Diagram

I'm outta time but we need to dig up that old picture with the flash memory and generic integrated circuit and display with arrows going in between everything

it will go here, it will be fantastic

Top-level Behavioral Description

Control FSM

Inputs from User

Inputs from comparators

Control signals to registers, SRAM

SRAM Item information from off-chip memory

Outputs to bus that runs to transmitter

Adder Multiplier

Price info, cumulative Multiplies tax

Final price

General State Machine Flow

Design Process Overview

Make it dense

Make it small

Make it cheap

Make it work

Design Process - Verilog & Schematic

Verilog Extensive simulations performed (quick and easy at

this stage) Logic refinement, design criteria refined I/O cap (lifted) nearly caused heart-attack

Schematic Several circuit-level changes later in the design cycle

(change to dyanmic logic decoder) Explored feasibility of design choices (slightly less

quick and easy at this stage)

Design Process - Floorplan

Floorplan We screwed this up pretty badly The 29-bit multiplier got a *teensy* bit larger than

we expected

Tearing up the floor boards… Iterative approach?

Yeah, but we never really did get it right

Design Process - Layout

Let the Biggest Blocks prevail

SRAM and Multiplier effectively determined the approximate bounding box for the design

The two blocks accounted for such a high proportion of the overall layout that finding good ways to massage the remaining pieces into place became our primary goal

Floorplan

Layout - Multiplier

Layout - SRAM, drivers&decoder

Layout - Register

Layout - Full Chip

Verification

Verification

(That was some kind of full-chip simulation that I finally got right, there will be better ones when I get a chance to go to the lab because the internet was not being cooperative from home)

Issues Encountered

(Not entirely sure if you want design things that went wrong, ideas that were harder to implement than we originally thought, or size estimates that had to be revised, so here is a selection of all of those)

The SRAM and multiplier dimensions fluctuated, requiring layout changes up until pretty much every module but the complete FSM was added to the full chip layout

Issues Encountered

Layout of FSM modules was inconsistent and required some “creative” routing—luckily (not necessarily for the density) we had some empty space that needed to be filled

Registers are a mess for so many reasons Signal names were sometimes inconsistent,

leading to time-consuming layout mistakes Also many more things

Specifications

Area 326 x 229 = 74,654 um^2 1.42:1 aspect ratio

Transistor Count 21,988 (So close to 22,000 that it’s psychologically

devastating)

Density 0.295 transistor/um^2