Philadelphia University Student Name:Faculty of Engineering Student Number:

Dept. of Communications and Electronics Engineering

Course Title: Digital Electronics & Techniques Course No: 650344, 630330 Lecturer: Dr. Wagah F. Mohammad Section:

Question: This question is general: Tick (√) the correct answer.1- Large scale integration refers to a chip containing

103-104 . 102-103 . 104-105 .

2- Very large scale integration refers to a chip containing 103-104 . 102-103 . 104-105 .

3- - Medium scale integration refers to a chip containing 103-104 . 102-103 . 104-105 .

4- Digital electronics is the branch of electronics concerned with electronic system exhibits: Linear behavior. Switching behavior. Exponential behavior.

5- Periodic pulse waveform is a repetitive pulse with predetermined: Frequency. Voltage. Current

6- If the voltage across the capacitor is constant that means the current through the capacitor is: Constant. Maximum. Zero.

7- The output signal of an RC circuit reaches the steady state at Ts=Tc. Ts= 5Tc. Ts=10Tc.

8- In RC circuit the voltage across the capacitor at t=0 is; Final value. Initial value. Zero.

9- When time constant of the circuit (Tc) is much shorter than signal transion time (Tup) of the input, the circuit output will.

Form No. T651

Little effect. High effect. No effect.

10- When time constant of the circuit (Tc) is larger than signal transion time (Tup) of the input , the circuit output will Attenuated. Has little effect Has very fast transion time.

11- The voltage across the capacitor (Vc) in an RC circuit can be expressed as follow: Vc= Vf+ (Vin-Vf) e-t/RC. Vc= Vf- (Vin-Vf) e-t/RC. Vc= Vf+ (Vin-Vf) e-RC/t.

12- The output of resistive load in an RC circuit tends to : Slow down the output. Attenuate the output. Increase the time constant of the circuit.

13- As the value of the load resistance in RC circuit is decreased the steady state time of the circuit is. Increased. Decreased Not effected

14- The resistance of the forward biased diode is: Very small nearly zero. Medium in KΩ. Very large nearly infinity.

15- Because the capacitance of the diode is very small, the time constant will be: Very short time. Medium time in sec. Very long time.

16- For the transistor in active region, the base –collector junction: Forward biased. Not biased. Reverse biased.

17- For the transistor in saturation region, the base –collector junction: Forward biased. Not biased. Reverse biased.

18- When the transistor is turned off, the delay time (Td) represent the time: To remove the access charges from the base. To add the access charges from the base. To charge the junction capacitors.

19- When the transistor is turned on , the storage time (Ts) represent the time: To remove the access charges from the base. To add the access charges from the base. To charge the junction capacitors.

20- Bipolar transistor operated in saturation region when the base –collector junction is:Reverse biasedForward biased.

Not biased. 21- The reverse diode resistance is: Very low.Medium.Very high.

22- The total turn off time (toff) of the transistor is the sum of: ts + tr.tr + tf.td + tf.23- When the transistor is saturated, any base current above the value of Ibsat, the Icsat will be

Increased. Decreased. Kept constant.

24- When the transistor is saturated, any base current above the value of Ibsat, as a result there is an excess charges in the base will be: Removed. Stored. not effected

25- Faster turn on of the transistor requires the value of Rb to be : Large. Small. Any value.

26- Faster turn off of the transistor requires the value of Rb to be : Large. Small . Any value.

27- Choosing high value of the load resistor (Rc) the rise time of the circuit is; Long. Short. Not effected

28- Choosing high value of the load resistor (Rc) the high output of the circuit is; Higher. Lower. Not changed

29- Choosing small value of the load resistor (Rc), the current that flow through the output transistor is: Large. Small. Not changed

30- Choosing small value of the load resistor (Rc), the noise margins will be : Shallower. Deeper. Not effected

31- High noise margin of any digital circuit is the difference between:VOH - VOL. VIH – VIL.VOH - VIH

32- Fan-out of a digital circuit is defined as:

IO/II.VO/VI.VO/IO.33- When the digital output is low, the current will flow: Outside the circuit (Sourcing current).Inside the circuit (Sinking Current). No current will flow.34- The temperature range of 74 TTL is

0 < ToC<70. 0 < ToC<125. -50< ToC<70

35- The temperature range of 54 TTL is 0 < ToC<70. 0 < ToC<125. -50< ToC<125

36- The propagation delay time of advance shcottky TTL is Very large. Normal. Very small

37- The power dissipation advance low power shcottky TTL is;•Very large.•Normal.•Very small38- At high output TTL too many loads causing larger drop across R2, T3and D thereby Voh is :

Increased Decreased. Not effected

39- At low output TTL too many loads causing larger drop across T4 thereby Vol is : Increased Decreased. Not effected

40- Unused inputs of NOR gates should be connected to the:Power supply. Used input. Left floating.41- One of the following digital outputs cannot be Wired-Anding:Totem-pole output. Open-collector output.

Tri-state output.42- The job of top transistor (T3) in totem pole output is to connect the output to: Vcc.

GND. Neither Vcc nor GND.43- The job of diode (D) in the totem pole output is to make the transistors: T3 is switching faster thanT4. T4 is switching faster than T3. T3 & T4 switches at the same time.44- In order to increase the switching speed of MOSFET logic, the channel length must be: Increased. Decreased. Not changed.45- The number of transistors needed to build n-input of dynamic-NMOS Inverter is:A- 2n .B- n2.

C- n + 2.46- The high output voltage of NMOS Inverter with Depletion load is:A- VOH = VDD - Vt.B- VOH = VDD + Vt.C- VOH = VDD.

47- For the following digital signal: the duty cycle is: ton + toff

ton / toff

ton/ T

48- The time needed for RC circuit to reach a steady state is: T = 0.7 RC T = eRC

T = 5RC49- The junction (s) in Schottky diodes is (are) formed between: Semiconductor-Semiconductor layers. Metal-Semiconductor layers. Metal-Insulator layers. Metal-Insulator-Semiconductor layers.50- Schottky devices reduce the storage time delay (ts) by: Allowing the transistor to go deeply in saturation. Not allowing the transistor to go deeply in saturation. Allowing the transistor to go very fast to cutoff.51- The number of transistors needed to build n inputs of dynamics NMOS gate is: 2n

n+2 2n52- In the logic circuit noise margin diagram: any input voltage lower than VIH and greater than VIL is considered: Logic one (high level). Logic zero (low level). Unpredictable (neither one nor zero).

53- Totem pole output with the presence of D between T3 & T4: the transistors Can't be reverse in the same time. Can't be forward in the same time. Can be forward in the same time.

54- Emitter coupled logic (ECL) is a type of difference amplifier because the output is proportional to the difference between the: a. Two inputs. b. Two outputs. c. Output & input 55- The fastest of logic families is: MOSFETL ECL TTL.56- The advantages of connecting NEMOS & PEMOS in Transmission gate is to transmit: High level voltage. Entire input voltage. Zero level voltage.57- Monostables multivibraters are a digital circuit has: No stable state. One stable state. Two stable states58- ROM digital circuit is composed of two digital arrays: Programmed AND array & fixed OR array. Fixed AND array & programmed OR array. Programmed AND & OR arrays.59- Digital signal vary between two levels; Smoothly (linearly). Continuously (Sine signal). Abruptly (In discrete manner).60- One of the digital family can be utilized in VLSI circuits: TTL. ECL MOSFET.61- If the voltage across the capacitor is constant: the current will be equal to: V/Xc.

Maximum. Zero.62- ECL is the fastest of all logic families due to the eliminating of storage time of the input transistor because they are prevented from going to: Cutoff. Active. Saturation.

63- In order to make the MOSFET logic circuit switching very fast the load should be: Resistive.

Capacitive. Transistor current source.64- The On resistance (Ron) of MOS transistor varies with channel length (L): Linear. Inverse. Exponential.65- The On resistance (Ron) of MOS transistor varies with channel width (W): Linear. Inverse. Exponential.66- MOSFET transistors have very small ON resistance (Ron) at: Cutoff region. Saturation (pinch off) region. Triode (linear or Ohmic) region. 67- In order to make MOSFET transistor switch ON & OFF very fast, the gain must be: Increases. Decreases. Kept constant.68- The use of depletion MOS as the load element makes the noise margins of digital circuits: Wider. Narrower. Not affected.69- Which gate has the biggest area

NEMOS with enhancement load NEMOS with depletion load. CMOS

70- Which gate transmit the total input signal. NEMOS with enhancement load NEMOS with depletion load. CMOS

71- The main disadvantage of dynamic storage cell memory is; Occupy large silicon area. Use complex circuitry. Loose data due to leakage.72- The main disadvantage of static storage cell memory is; Occupy large silicon area. Retain the data. Need refreshment due to data leakage.73- The main advantage of dynamic storage cell memory is. Retain the data for very long time. Occupy small silicon area. Use complex circuitry.74- The main advantage of static storage cell memory is. Retain the data for very long time. Occupy small silicon area. Use very simple circuitry.75- Transmission CMOS gate is created by connecting NEMOS in parallel with PEMOS in order to transmit: The high level voltage.

The low level voltage. The entire level voltage.76- PAL digital circuit is composed of two digital arrays: Programmed AND array & fixed OR array. Fixed AND array & programmed OR array. Programmed AND & OR arrays.77- PLA digital circuit is composed of two digital arrays: Programmed AND array & fixed OR array. Fixed AND array & programmed OR array. Programmed AND & OR arrays.78- The output word width of 210x8 ROM is: 210 bits. 10 bits. 8 bits.79- The number of unique addresses of 210x8 ROM is: 210 bits. 10 bits. 8 bits.80- The number of words of 210x8 ROM is: 210 words. 10 words. 210x8 words.81- The capacity (number of bits) of 210x8 ROM is: 210 bits. 210x8 bits. 8 bits82- The data in Random Access Memory (RAM) can be: Read only. Write only. Read or Write only. Read and/or Write.83- The storage cells in static RAMs are; Flip-Flop cells. Capacitor cells. Mixed Flip-Flops & capacitor cells.84- The storage cells in Dynamic RAMs are; Flip-Flop cells. Capacitor cells. Mixed Flip-Flops & capacitor cells.85- One of the following storage cells need a refresh signal to prevent data leakage: Dynamic storage cell. Static storage cell.86- Monostables multivibraters has: One stable state. Two stable states. No stable state.87- Bistables multivibraters has: One stable state. Two stable states. No stable state.

88- Astables multivibraters has: One stable state. Two stable states. No stable state.89- The duty cycle of monostables output is proportional to: Width of the input signal. External RC circuit. Internal RC circuit.90- Retriggerable monostables respond to the input signal as long as the output in: Stable state. Quisistable state. Both states.91- Nonretriggerable monostables respond to the input signal as long as the output in: Stable state. Quisistable state. Both states.92- The width of hysteresis loop of Schmitt trigger circuit that switch ON at 5V and OFF at 3V is: Two Volts. Three Volts. Five Volts.93- 555 multivibraters can be connected to perform: Monostables multivibraters only. Astables multivibraters only. Monostables & Astables multivibraters.94- The control input of the 555 multivibrator is used to apply a voltage to the control input in order to change: The frequency of the output signal. The duty cycle of the output signal. The amplitude of the output signal.95- One of the disadvantages of binary-weighted Digital to analogue converter is: Non-weighted. Slow speed. Low resolution. High value of input resistances.96- One of the disadvantages of binary-encoded (flash) analogue to digital converter is: Slow speed. Low resolution. High value of input resistances.97- The time needed for RC circuit to reach a steady state is: T = 0.7 RC T = eRC

T = 5RC98- The total effect of the resistance load in RC circuit on the output voltage is to : Decrease it. Increase it No effect.

99- Fan out of digital circuits is defined as: Io/Vo

Io/Vin

Io/Iin

100- In the logic circuit noise margin diagram: any input voltage greater than VIH are considered: Logic one (high level). Logic zero (low level). Unpredictable (neither one nor zero).101- Totem pole output acts as an emitter follower providing very fast switching circuits due to: High output impedance. Low output impedance. Negative output impedance.102- The propagation delay times in Schottky logic circuits are; Nanoseconds. Seconds. Kilo seconds.103- The smallest size logic family is: TTL. ECL MOSFETL.104- The number of transistors needed to build n inputs of dynamics NMOS gate is: 2n

n+2 2n105- Transmission MOS gate is created by connecting nEMOS & pEMOS in: Series. Parallel. Cascade.106- ROM digital circuit is composed of two digital arrays: Programmed AND array & fixed OR array. Fixed AND array & programmed OR array. Programmed AND & OR arrays.107- When a digital circuit output is high (level one), the output current will flow: Outside the circuit (Sourcing Current). Inside the circuit (Sinking Current). No current will flow.108- In the logic circuit noise margin diagram: any input voltage greater than VIL and smaller than VIH is considered: Logic one (high level). Logic zero (low level). Unpredictable (neither one nor zero).109- Totem pole output acts as an emitter follower providing very fast switching circuits due to: High output impedance. Low output impedance. Negative output impedance.110- The propagation delay times in Schottky logic circuits are; Nanoseconds.

Seconds. Kilo seconds.111- The smallest size logic family is: TTL. ECL MOSFETL.112- The number of transistors needed to build n inputs of dynamics NMOS gate is: 2n

2n n+2113- The advantages of connecting nEMOS & pEMOS in Transmission MOS gate is to transmit the:

Entire input voltage. High level voltage. Zero level voltage.

114- Emitter coupled logic (ECL) is the fastest of all logic families because the input transistors are: * Going to saturation. * Not going to saturation.. * Not going to active region115- Enhancement type MOSFET has a: * Short channel. * No physical channel * Long channel.116- The VDS of NMOSFET in triode region is: VDS < VGS – Vt. VDS > VGS+ Vt. VDS = Vt.

117- The power dissipated in CMOS Logic circuits is: Almost zero power. Moderate power. High power.118- The transition region on VTC (P1 to P2) for NMOS Inverter has a slope equal to: -1. -√K1/K2 +1119- The high output voltage of NMOS Inverter with Enhancement load is: VOH = VDD - Vt. VOH = VDD + Vt. VOH = VDD.

120- For the following digital signal: The time for two periods is: 2(T + ton) 2(T+ toff) 2(ton + toff)

121- The voltage across RC circuit can charge or discharge according to the following relation: Vc = VF + (Vo + VF) ( t/RC) Vc = VF+ (Vo + VF) e( t/RC) Vc = VF+ (Vo + VF) ( t/RC)2 122- The total effect of the resistance load in RC circuit on the output duration time is to : Increase it Decrease it. No effect123- When a digital circuit output is high (level one), the output current will flow: Outside the circuit (Sourcing Current). Inside the circuit (Sinking Current). No current will flow.124- In the logic circuit noise margin diagram: any input voltage lower than VIL are considered: Logic one (high level). Logic zero (low level). Unpredictable (neither one nor zero). 90- Totem pole output with the presence of D between T3 & T4: the transistors . Can't be reverse in the same time. Can't be forward in the same time. Can be forward in the same time.

91- The maximum power dissipated in TTL circuits can be estimated in: Megawatts Kilowatts. Mill watts.92- CMOS inverter is composed of two matched EMOS transistors with : N-type channels. P-type channels. Different type channels.93- The number of transistors needed to build n inputs of CMOS gate is: 2n

n2

2n94- The advantages of connecting nEMOS & pEMOS in Transmission MOS gate is to transmit the:95- High level voltage.96- Entire input voltage.97- Zero level voltage.98- Monostables multivibraters is a digital circuit has: No stable state. One stable state. Two stable states.