ECE 353Introduction to Microprocessor Systems

Michael J. Schulte

Week 9

Administrative MattersQuiz #2 is Thursday, April 10th from 7:15 to 8:30 PM Covers modules 3 and 4 (weeks 5-8, hw 3, 4)

Readings for week 9 Textbook 7.5, 9 ADUC 9-10, 33-36, 43-47, 79-82

Discussion section tonight Review for Quiz #2 Problems post on course webpage

TopicsMemory technologiesOrganization and operation of typical SRAM, EPROM and flash memory devicesMemory subsystem designAddress decoder implementationSRAM timing characteristics

Memory TerminologyHow could we classify memory devices?Read-Only Memory (ROM) In common usage, it is memory that is

nonvolatile.

Random-Access Memory (RAM) The time required to access any

memory location is the same – it does not need to be accessed in any order.

In common usage, it is memory that can be read or written with equal ease.

Memory TechnologiesROM (non-volatile) Masked ROM Field programmable

EPROM OTP PROM (fuse or EPROM)

Electrically erasable EEPROM (or E2PROM) Flash memory

RAM (volatile) SRAM DRAM Pseudo-SRAM

Emerging memory technologies

Memory OrganizationLogical organization Organization as seen looking at the

device from the outside Linear array of registers (memory

locations)

Physical organization Different physical organizations can be

used to implement the same logical organization

Physical organization affects performance and cost

SRAM InterfacesRAM with 3 control inputs /CS, /OE, /WE Read Write

RAM with 2 control inputs /CS, /WE (or R/W)

/CS

/WE

/OE

internal write signal

internal read signal

/CS

/WEinternal write signal

internal read signal

SRAM OrganizationLogical Organization Typically 1, 4 , 8 or 16 bit widths

Physical Organization Rectangular bit array Two-level decoding (row and column) Characteristic delays and timing requirements are

specified in memory devices datasheet (Example)

NV-SRAM Uses an alternate power source to maintain SRAM

when system power is off Requires logic to switch power sources and

prevent spurious writes during power-up/power-down

EPROMElectrically programmable, non-volatileRequires UV light to erase Quartz window in package

Floating polysilicon gate avalanche injection MOS transistor (FAMOS) Operation

Programmer loads device out-of-circuitOTP EPROMs eliminate quartz windowEEPROMs are electrically erasable Byte-erasable / writeable Low-density

JEDEC Packages

Flash MemoryActually Flash EEPROM, commonly just called flash memoryCharacteristics Technologies Endurance Blocking, programming and erasing

Applications ROM replacement GP NV-RAM Solid-state disk (flash-disk) Example

Memory Subsystem Design

Memory banks Increasing memory width Increasing memory depth Increasing memory width and depth

Address decoding Boundaries

If address is a 2m boundary, then what is the result of (address AND (2m-1))?

We normally decode memory devices to be aligned on boundaries at least as large as they are

Exhaustive (full) vs. partial (reduced) decoding

Memory ArchitecturesWide (n-byte) buses Addressing effects Byte transfer support

Data lanes Control signals

Bus resizing Static Configurable Dynamic

Memory Subsystems Review

What is the purpose of an address decoder circuit, and where does its output usually get connected?What is exhaustive decoding, and what effects does it have?What is partial decoding, and what effects does it have?

SRAM Timing Characteristics

An SRAM device has key timing parameters specified for the read cycle. tAA – address access time

tRDHA – data valid after address changes tACS – chip select access time

tRHCS – data valid after chip select tCHZ – time until device floats bus after chip select dis-

asserted tOE – output enable access time

tOHZ – time until device floats bus after output enable dis-asserted

tRC – read cycle time

The write cycle has a complementary set of specifications.

Sample Timing Diagram

7C1046SRAM

27C512EPROM

HM624100HCSRAM

SRAM Timing Compatibility

In order to ensure that we will be able to reliably read and write the memory device, we need to ensure that the processor system bus interface is compatible with the memory device.This is accomplished by analyzing the timing for all relevant parameters of both the processor and memory, and ensuring that the operations can be completed reliably.

Wrapping UpQuiz #2 will be held Thursday 4/10/2008 at 7:15-8:30pm Covers educational objectives for

modules 3 and 4 (weeks 5 through 8) Single 3x5 card with original handwritten

notes No calculators Instruction set references and any

needed datasheets will be provided

Reading for next week Supplement #3, review chapter 9 in text

Physical Memory Organization

32K x 8 SRAM

FAMOS Gate Operation

Programming

Erasing

JEDEC

Flash Blocks

Flash Memory Application:Disk-on-Key

Up to 4GB nonvolatile storageNo battery or power supply

Specifications:Data retention up to 10 years Erase cycles: 1,000,000 times Shock resistance: 1000 G (maximum)

RAM Read – 3 control signals

/CS

Dx

Ax

/OE

/WE

RAM Write – 3 control signals

/CS

Dx

Ax

/OE

/WE

Increasing Memory Depth

CE

A0

A15 D7

D0

CE

A0

A14 D7

D0

CE

A0

A14 D7

D0

Extending Depth

Increasing Memory Width

CE

A0

A15 D7

D0

CE

A0

A15 D3

D0

CE

A0

A15 D3

D0

Extending Width

Increasing Memory Depth & Width

CE

A0

A15 D7

D0CE

A0

A14 D3D0

Extending Width and Depth

CE

A0

A14 D3D0

CE

A0

A14 D3D0

CE

A0

A14 D3D0