what are plds? - nchusocdsp.ee.nchu.edu.tw/class/download/verilog_103/day...7 yt hwang pld 1-13...
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![Page 1: What are PLDs? - NCHUsocdsp.ee.nchu.edu.tw/class/download/verilog_103/day...7 YT Hwang PLD 1-13 Field Programmable Gate Array •architecture originates from gate array •2-D array](https://reader030.vdocument.in/reader030/viewer/2022040923/5e9df8a2e30e7a02066f7c25/html5/thumbnails/1.jpg)
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YT Hwang 1
YT Hwang PLD 1-2
What are PLDs?
![Page 2: What are PLDs? - NCHUsocdsp.ee.nchu.edu.tw/class/download/verilog_103/day...7 YT Hwang PLD 1-13 Field Programmable Gate Array •architecture originates from gate array •2-D array](https://reader030.vdocument.in/reader030/viewer/2022040923/5e9df8a2e30e7a02066f7c25/html5/thumbnails/2.jpg)
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YT Hwang PLD 1-3
Programmable Logic Devices
• A pre-fabricated ASIC capable of performing any logic subject to user programming
• compromise between the semi-custom ASICs and standard components
• a collection of logic elements placed in a programmable interconnection framework
• fast design turn around time
• field programmable EPROM, E2PROM, Flash, SRAM based
YT Hwang PLD 1-4
PLD Programmability (1)
• programmable combinational logic PT-based, LUT
LUT(look-up
table)
PT-based building block• 2-level logic, high fan-in
LUT-based building block• 4-5 inputs, fine-grain arch.• ROM like
![Page 3: What are PLDs? - NCHUsocdsp.ee.nchu.edu.tw/class/download/verilog_103/day...7 YT Hwang PLD 1-13 Field Programmable Gate Array •architecture originates from gate array •2-D array](https://reader030.vdocument.in/reader030/viewer/2022040923/5e9df8a2e30e7a02066f7c25/html5/thumbnails/3.jpg)
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YT Hwang PLD 1-5
PLD Programmability (2)
• programmable register register type, register control
YT Hwang PLD 1-6
PLD Programmability (3)
• programmable interconnect routing resources including switching elements,
local/global lines, clock buffers
![Page 4: What are PLDs? - NCHUsocdsp.ee.nchu.edu.tw/class/download/verilog_103/day...7 YT Hwang PLD 1-13 Field Programmable Gate Array •architecture originates from gate array •2-D array](https://reader030.vdocument.in/reader030/viewer/2022040923/5e9df8a2e30e7a02066f7c25/html5/thumbnails/4.jpg)
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YT Hwang PLD 1-7
PLD Programmability (4)
• programmable I/O direction, I/O register, 3-state, slew rate
YT Hwang PLD 1-8
Field Programmability
• can verify designs at any time by configuring the FPGA/ CPLD devices on board via the download cable or hardware programmer
![Page 5: What are PLDs? - NCHUsocdsp.ee.nchu.edu.tw/class/download/verilog_103/day...7 YT Hwang PLD 1-13 Field Programmable Gate Array •architecture originates from gate array •2-D array](https://reader030.vdocument.in/reader030/viewer/2022040923/5e9df8a2e30e7a02066f7c25/html5/thumbnails/5.jpg)
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YT Hwang PLD 1-9
PLD Classifications
• General classification Simple programmable logic device (SPLD) Complex programmable logic device (CPLD) Field programmable gate array (FPGA)
• Classification by programming technology Fuse, anti-fuse (OTP) EPROM, EEPROM, Flash (multiple programming) SRAM (volatile, need configuration when power up)
• Classification by routing structures Segmented (incremental) routing Continuous routing
YT Hwang PLD 1-10
Simple PLD
• Programmable AND/OR array Sum-Of-Product (SOP) to implement Boolean
functions
• facilitated with FFs, output macros, and feedback path
• foldback architecture
• low density, low cost, fixed delay
• examples: PAL, GAL, PEEL, FPLA
![Page 6: What are PLDs? - NCHUsocdsp.ee.nchu.edu.tw/class/download/verilog_103/day...7 YT Hwang PLD 1-13 Field Programmable Gate Array •architecture originates from gate array •2-D array](https://reader030.vdocument.in/reader030/viewer/2022040923/5e9df8a2e30e7a02066f7c25/html5/thumbnails/6.jpg)
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YT Hwang PLD 1-11
PAL Architecture
YT Hwang PLD 1-12
Complex PLD architecture
![Page 7: What are PLDs? - NCHUsocdsp.ee.nchu.edu.tw/class/download/verilog_103/day...7 YT Hwang PLD 1-13 Field Programmable Gate Array •architecture originates from gate array •2-D array](https://reader030.vdocument.in/reader030/viewer/2022040923/5e9df8a2e30e7a02066f7c25/html5/thumbnails/7.jpg)
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YT Hwang PLD 1-13
Field Programmable Gate Array
• architecture originates from gate array• 2-D array of programmable logic blocks (cells)• programmable / incremental interconnect• less predictable timing, place &routing is
crucial• matrix based architecture
Xilinx XC4000, Spartan, Virtex, QuickLogic
• Row based architecture Actel ACT families
• Continuous interconnect architecture Altera Flex 8K/10K, APEX
YT Hwang PLD 1-14
Generic FPGA logic cell
Carrylogic
Look-UpTable(RAM)
Macro-cell
I/Ocells
Mcell
PrimaryInputs
Logic cell
16X1
![Page 8: What are PLDs? - NCHUsocdsp.ee.nchu.edu.tw/class/download/verilog_103/day...7 YT Hwang PLD 1-13 Field Programmable Gate Array •architecture originates from gate array •2-D array](https://reader030.vdocument.in/reader030/viewer/2022040923/5e9df8a2e30e7a02066f7c25/html5/thumbnails/8.jpg)
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YT Hwang PLD 1-15
Continuous v.s. Segmented
CROSSBAR
continuous segmented
YT Hwang PLD 1-16
Rapid Prototyping & System Verification
• To see is to believe
• The ASIC respin cost is too high
• Verification at lower speed
![Page 9: What are PLDs? - NCHUsocdsp.ee.nchu.edu.tw/class/download/verilog_103/day...7 YT Hwang PLD 1-13 Field Programmable Gate Array •architecture originates from gate array •2-D array](https://reader030.vdocument.in/reader030/viewer/2022040923/5e9df8a2e30e7a02066f7c25/html5/thumbnails/9.jpg)
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YT Hwang PLD 1-17
Low cost solution of FPGAs
• Hardcopy technology Reduced die area
Only two mask layer cost
YT Hwang PLD 1-18
Latest FPGA Features
• Advanced process For example, Xilinx Spartan III use 90nm process
Next generation Virtex FPGA will contain 1G transistors in 70nm process
• High logic gate count Up to millions of logic gates
• Large on chip memory From several K bits to several M bits
• On chip processor ARM 7/9, PowerPC
• On chip multiplier/DSP
• High speed I/O Up to 3.125Gbps
![Page 10: What are PLDs? - NCHUsocdsp.ee.nchu.edu.tw/class/download/verilog_103/day...7 YT Hwang PLD 1-13 Field Programmable Gate Array •architecture originates from gate array •2-D array](https://reader030.vdocument.in/reader030/viewer/2022040923/5e9df8a2e30e7a02066f7c25/html5/thumbnails/10.jpg)
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YT Hwang PLD 1-19
What’s inside?
• Altera Excalibur Processor +
Memory +
1,000,000 plus
logic capacity
PLD Area for Customer Design
ARM922TCore
Single-PortRAM
Dual-PortRAM
YT Hwang PLD 1-20
SoPC example
EBI Bridge
SRAM(Single Port)
SDRAMController
DPRAM
SDRAM Interface
FlashInterface
ARMProcessorP
LL
s
Stripe
33-MHz Utopia-2
PHYManager
CustomLogic
AMBABus
Inter-face
Master Port
Slave Port
Dual-Port RAM Interface
Logic
Ethernet Controller
MediaIndependentInterface
AMBABus
Inter-face
AMBABus
Inter-face
ATM Cell ProcessorNios
CPU
PCIController
PCIAMBABus
Inter-face
Bridge