UNIVERSITYOFHOUSTON–CLEARLAKE 

 

 

   

Designofa4– bitALUusingVHDL

LuzOrlandoRamirezandAlfredoNava

CENG3511,Section2,SaurinGanatra 

 

 

 

 

 

   

   4 ‐bit ALU designed using behavioral VHDL coding techniques.  The 4‐bit ALU using the aforementioned coding techniques successfully performed arithmetic, logical, and shifting operations.  The ALU performs a limited number of arithmetic, logical, and shifting operations dependent on the user defined input. 

   CENG 3511    1 

 

ContentsI.  Background ..................................................................................................................................................................... 2 

II.  Project Overview......................................................................................................................................................... 2 

a.  Objective ..................................................................................................................................................................... 2 

b.  Method ........................................................................................................................................................................ 2 

c.  Procedure .................................................................................................................................................................... 2 

III.  Observations ............................................................................................................................................................... 3 

IV.  RTL (Register Transfer Level) schematic and Waveform of ALU ............................................................................ 3 

a.  Top level ..................................................................................................................................................................... 3 

b.  Detailed RTL schematic .............................................................................................................................................. 3 

c.  Waveforms .................................................................................................................................................................. 4 

V.  Conclusion ...................................................................................................................................................................... 4 

VI.  Recommendation ........................................................................................................................................................ 4 

Works Cited ............................................................................................................................................................................. 5 

Appendix ................................................................................................................................................................................. 6 

VHDL Code for ALU ......................................................................................................................................................... 6 

VHDL Code for 4-bit Full Adder ....................................................................................................................................... 9 

VHDL Code for a 1-bit Full Adder ..................................................................................................................................... 9 

Detailed RTL Schematic of designed ALU ...................................................................................................................... 10 

 

   CENG 3511    2 

 

Introduction

The main goal of this experiment is to design a 4-bit ALU using one main VHDL coding technique using XILINX. The 4-bit ALU was implemented using a VHDL coding techniques that model a four bit full adder and numerous MUXes. VHDL coding was primarily done using a student version of XILINX software.

I. Background

ALU’s (Arithmetic Logic Units) are significant in that they primarily perform nearly all arithmetic and logical operations. “The arithmetic logic unit (ALU) is the brawn of the computer, the device that performs the arithmetic operations like addition and subtraction or logical operations like AND and OR” (Patterson, Hennessy C-26). More detailed information about MUXes, Adders, and other devices can be found in the textbook Fundamentals of Logic Design (2010) by Charles H. Roth, JR. and Larry L. Kinney. Also a complete description of ALU’s is provided by the text Computer Organization and Design (2009) by David A. Patterson and John L. Hennessy.

The primary goal and results of the experiment will be discussed in the following sections.

II. Project Overview a. Objective

Build a 4-bit ALU that performs basic arithmetic, logic, increment/decrement and shifting operations using only one VHDL coding technique. The 4-bit ALU will have: 4-bit input, output and operation select lines and 1-bit carry in and carry out lines. In addition, the 4-bit ALU will perform eleven distinct operations.

b. Method

To enter different inputs into the 4-bit ALU to determine if the outputs of the ALU correspond to the predicted function and result. A pre-defined set of Operation Select of 4-bit inputs will aid in the identification in the case that the ALU produces an output that does not agree with the predicted function or outcome.

c. Procedure

Since the ALU is composed of numerous internal components the operation select inputs are a significant role in determining what output the ALU produces. Specifically, there are only two cases in which the carry in line is not treated as a don’t care and does not affect the ALU output, these occur when 4-bit input A needs to be transferred directly onto the 4-bit output G. Although, the design of the 4-bit ALU includes a four-bit full adder the output of the ALU is significantly affected by the numerous MUXes used in the design as defined per the use of “WHEN-ELSE” VHDL statements in main VHDL source file. In respect to the carry out output of the ALU, the ALU was designed so that the carry out retains the previous carry in of a past operation where in the carry in is not in use.

  

 

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   CENG 3511    5 

 

Works Cited 

Roth, Charles H., and Larry L. Kinney. Fundamentals of Logic Design. Stamford, CT: Cengage Learning,  

    2010.   Print. 

  Patterson, David A., and John L. Hennessy. Computer Organization and Design. Boston: Morgan Kaufmann,  

    2009. Print. 

 

  

 

 

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VHDL

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ppendix

Code for AALU

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V

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VHDL Code

HDL Code f

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for 4-bit Fu

for a 1-bit F

ull Adder

Full Adder

 

9 

  

 

Detail

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hematic of ddesigned ALLU

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