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TRANSCRIPT
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Electrical Modelling of RFIC QFN Package
Using HFSS and ANYSYS Designer
Jun Xia and Alan Wong
Toumaz Microsystems
UK HFSS UGM on 13th June, 2013
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OUTLINES
• Products of Toumaz
• Applications of HFSS and ANSYS Products
• Package modelling - Pre-HFSS Process
• Package modelling - Post-HFSS Process
• Conclusions
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WiFi, 3G, 4G
Heart rate monitor with Sensium-2 chip1
Bluetooth Low Energy (BTLE)
Built-in Sensium-2 IC
The Cloud
Products of Toumaz – Professional Healthcare
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Portable Radios
Home audio systems
Handheld & In-car
Clock Radios & Docks
Products of Toumaz – Consumer Semiconductors
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Applications of HFSS and ANSYS
(or Planning Applications)
HFSS
Designer
ECAD
Antenna
Design
IC
Design
Packaging
Signal
Integrity
PCBs
Design
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Package Modelling - Pre-HFSS Process
Products
Chips and PCB Board
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Package Modelling - Pre-HFSS Process
32 pin QFN Package Silicon IC
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Package Modelling - Pre-HFSS Process
32 pin QFN Package
Top view
Bottom view
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Package Modelling - Pre-HFSS Process
• The advantages in portable communication systems
need packages with small size and good
characteristics.
• The QFN package is a near chip scale package
plastic encapsulated package with a coppery
leadframe substrate.
• It provides advantages of miniaturized size, good
electrical performances and excellent thermal
characteristics.
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Package Modelling - Pre-HFSS Process
• However, at high frequencies the electrical parasitic
effects of the packages become significant and
degrade the radio-frequency integrated circuit
(RFIC)'s performance
• System-level signal integrity is a major issue which
must be addressed by electrical simulations during
the design cycle.
• Unfortunately most of package companies do not
provide accurate electrical models for the packages
• 3D EM numerical simulation is one good solution to
be utilized to extract the equivalent circuit parasitic
elements from a model based on the physical
structure of the package
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Package Modelling - Pre-HFSS Process
2D.dxf only from Package Company
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2D.dxf from Package Company
ANSYS Designer 2D LAYOUT (different layers)
Package Modelling - Pre-HFSS Process
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HFSS 3D LAYOUT
ANSYS Designer 2D LAYOUT (layer by layer)
Package Modelling - Pre-HFSS Process
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Package Modelling - Pre-HFSS Process
Add bondwires
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Package Modelling - Pre-HFSS Process
Add Mold and test ports
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Package Modelling - Pre-HFSS Process
Add PCB, PCB ground and Air Box
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Package Modelling - Post-HFSS Process
Inductor of Bondwire 17
Series resistor of Bondwire 17
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Package Modelling - Post-HFSS Process
Export S-parameters
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Package Modelling - Post-HFSS Process
Using ANSYS Designer Optimization
feature to extract lumped model for
the 32pin QFN package
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Package Modelling - Post-HFSS Process
Cross-talk between different Parts of circuits
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Package Modelling - Post-HFSS Process
Export Broadband full-wave
Spice model to Cadence
For Signal integrity analysis
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Package Modelling - Post-HFSS Process
Broadband full-wave Spice model
Imported to Cadence
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Package Modelling - Post-HFSS Process
Test Bench for Cross-talk Analysis
The work is going on!
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Conclusions
• A complete methodology based on broadband 3D EM
simulation by means of powerful Ansys Designer and
HFSS is proposed to establish the electrical models for
RFIC QFN packages.
• The method use the package physical information (dxf or
dwg file) provided by package companies as the starting
point, and the equivalent wideband electrical circuit model
of the package that accounts for the resonance, coupling,
and frequency-dependent losses is developed.
• The methodology proposed improve the performance of
the RFIC design and reduce the cost and time for the
whole design cycle significantly.