www.trusi.com 1 moore’s law – the z dimension sergey savastiouk, ph.d. [email protected] april...
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Moore’s Law – the Z dimensionMoore’s Law – the Z dimension
Sergey Savastiouk, Ph.D.Sergey Savastiouk, [email protected]@trusi.com
April 12April 12, 2001, 2001
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Introduction: The next dimension is the Z dimension
Step 1: Vertical miniaturization – thinning
– Thinner is better
– Thinning and handling problems and solutions
Step 2: Vertical integration – stacking
– Thru-Silicon vias
– 3D stacking for system-in-a-chip (SIP)
Conclusion: 3D Wafer Level Packaging
Presentation Overview Presentation Overview
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Moore’s Law – the X-Y dimensions. Moore’s Law – the X-Y dimensions.
The number of components on a surface of a chip would double every 18 – 24 months.
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?Si
SiSi
Si
Si
Si
Si
Si
Moore’s Law - the Z dimensionMoore’s Law - the Z dimensionThe number of components in 3D space would double every 18 – 24 months.
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PACKAGEPACKAGE
LITHOGRAPHYLITHOGRAPHYDESIGNDESIGNRULERULE
200020001995199519851985 19901990
DIPDIP
CSPCSP
MCMMCM
TCPTCP
STACKSTACKTSOPTSOP
SOPSOP
BGABGAPGAPGA
TQFPTQFPQFPQFP
BARECHIPBARECHIP STACK MEMORY MODULESTACK MEMORY MODULE
SYSTEM ON MODULESYSTEM ON MODULE
SYSTEM ON SILICONSYSTEM ON SILICON
1M1M 4M4M 16M16M 64M64M 256M256M
2000200010001000300300200200
0.8um0.8um 0.5um0.5um 0.35um0.35um 0.25um0.25um 0.18um0.18um
PIN COUNTPIN COUNT
Packaging trendsPackaging trends
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Package and Chip ThicknessPackage and Chip Thickness
0
1000
2000
3000
4000
5000
6000
7000
1981 1986 1992 1996 1999 2002 2006 2012
PackageThicknessBare DieThickness
CSP
DIP
TQFPBGA
PDIP
STACK MODULES
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Wafer and Chip ThicknessWafer and Chip Thickness
0
100
200
300
400
500
600
700
800
900
1960 1970 1980 1990 2000 2010 2020
Year of Significant Production
Wafer Diameter, mm Wafer Thickness, um Chip Thickness, um
DIPPDIP TQFP
BGA
TSSOP
CSPSTACK MODULES
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• Step 1: Vertical miniaturization – thinning Step 1: Vertical miniaturization – thinning
Thinner is betterThinner is better
Why to thin? Why to thin?
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Thinner is betterThinner is better
WHY to thin ?
Better packaging density More flexible More reliable Better thermal resistance Better yields
50 m wafer.
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Reduction of thickness by half provides 50% reduction in height and 30% in footprint of packaging
SiH1
H2
Si
Thinning for smaller space: Why to thin?
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<100 micron thickness for improved
reliability, requires damage-free silicon
Hitachi
Thinning for flexibility: Why to thin ? Thinning for flexibility: Why to thin ?
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Numerical results for reliability: Why to thin ?Numerical results for reliability: Why to thin ?
Thick chip: u = 700 m, b = 1000 m
Thin chip: u = 50 m, b = 200 m
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Thermal Resistance vs. Thickness
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0.045
0.05
50 100 200 300
Chip Thickness (microns)
Thermal Resistance (Deg.C/Watt)
Chip
Adhesive
Chip+Adhesive
Improved Power Dissipation: Why to thin?Improved Power Dissipation: Why to thin?
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• Step 1: Vertical miniaturization – thinning Step 1: Vertical miniaturization – thinning
Thinning and handling problems Thinning and handling problems and solutionsand solutions
How to thin?How to thin?How to handle thinned wafers? How to handle thinned wafers?
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Thinning alternativesThinning alternatives
Grinding (leaves damage) Polishing (leaves some damage) Wet etching (removes damage, but wet) Dry etching (removes damage)
Silicon
Damage
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Si WAFER
•No induced electrical damage
•No vacuum pumps – excellent process control
•Etch rate suitable for mass production
Atmospheric Downstream Plasma: How to thin?Atmospheric Downstream Plasma: How to thin?
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Edge damage yield problems: How to handle?
Damaged edges cause wafers to break
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NoTouch™ wafer holding: How to thin? NoTouch™ wafer holding: How to thin?
Atmospheric Downstream
Plasma
Holding Gas
NoTouch Holder
Wafer Back Side
•Maintains planarity of flexible wafers
•No contact with bumps
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Silicon
Damage
Silicon
No damage
Damage-free wafer surface: How to thin ?Damage-free wafer surface: How to thin ?
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Damage free edges: How to thin? Damage free edges: How to thin?
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After wet spin etchingAfter grinding or polishing
Oldtechnologies
After ADP etchingNew ADP technology
Thinning alternatives: How to thin?Thinning alternatives: How to thin?
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Die strength etching vs. grind & CMP: How to Die strength etching vs. grind & CMP: How to thin?thin?
Front tensile strength Weibull plot
160um thick die (35 mm squared)
1
10
100
0 200 400 600 800 1000 1200
Tensile strength (N/mm2)
Survival probability(%)
Grind & cmp /Front side
Plasma 10um /FS
Plasma 20um /FS
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Wafer warp improvementWafer warp improvement
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Damage Free Dicing (in development)
Step 2. Controlled depth dicing
Step 3. Apply top side tape
Step 1. Grind
Individual diceStep 4. Etch the backside to singulate
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DBG vs. Damage Free DicingDBG vs. Damage Free DicingSawed die showing chipping 40 micron thin ADP etched dice,
rounded and smoothed
Chip Shifts and Cracks No Chip Shifts and Cracks
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Damage Free DicingDamage Free Dicing
SEM picturesof the edges
Die top
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• Step 2: Vertical integration – stacking Step 2: Vertical integration – stacking
How to thin and to bump on a How to thin and to bump on a backside in one step?backside in one step?
How to stack? How to stack?
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Integration: SOC vs. SOB ,SIP ? Integration: SOC vs. SOB ,SIP ?
SIP
SOB
SOC
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ADP Via Etch (continued)
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ADP thinning of via ADP thinning of via (continued)
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Thru-Silicon viaThru-Silicon via
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Back Side of a wafer with contact pad
Thru-Silicon via results
Silicon
MetalSiO2
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Thru-Silicon via resultsThru-Silicon via results
Back side of a wafer with contact pads
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Direct Chip Attach
Solder Paste Or Other Joining Material
Substrate Or PWB
Active Circuitry Front Side Passivation
Exposed ThroughHole Contact
Tru-CSP™ for front side up : project
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Opto-Electronic Devices
Optically Transparent Layer Or Optical Waveguide
Optical Signals Can Be Transmitted And Received From Either Surface
Optical Waveguide Or Other Silicon Device
Tru-CSP™ for opto-electronics: project
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Tru-CSP™ with passive interposer : project
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Tru-CSP™ face-to-face : project
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Tru- 3D Stacking Tru- 3D Stacking : project
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1997, $8m raised, ADP prototyping
1998, Ultra-thin handling prototyping
1999, $10m raised, Product development
2000, System sales and Thru-Silicon dev-t
2001, $18m raised, – Thru-Silicon dev-t hiring
process engineers: [email protected]
Conclusion: History of CompanyConclusion: History of Company
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Thinning by ADP and NoTouch handling:
– enables low cost damage free thinning
– enables low cost damage free dicing
Thinning by ADP with Thru-Silicon vias:
– enables the new generation of low cost 3D stacking
methods of chips and wafers for System-In-a-Package
– brings front-end technologies to back-end applications
Conclusion: OverallConclusion: Overall SummarySummary