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TRANSCRIPT
Enabling success from the center of technology™
Introduction to Xilinx FPGA Design
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
2Goals
Understand basic Xilinx FPGA architecture, families, and tool solutions
Understand the ISE 9.1i design flow for an FPGA design using an HDL
Understand what resources Avnet and Xilinx have to help make your next FPGA design a success
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
3Agenda
Introduction to Xilinx devices and tools
Create and build a design
Where to go from here
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
4Agenda
Introduction to Xilinx devices and tools
Create and build a design
Where to go from here
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
5FPGA and CPLD Overview
Low-cost FPGA
High-performance FPGACPLD
..
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
6Basic FGPA Architecture
Reg
Reg
DDR mux
3-State
Reg
Reg
DDR muxPAD
Reg
Reg
Input
Output
I3I1I2I0
O
D Q
SETRST
CE
D Q
SETRST
CE
0 1
I3I1I2I0
O 0 1
CLKA
DIPA
ADDRA
DOPA
CLKB
ADDRB
DIA DOA
DIPB DOPBDIB DOB
CLKIN CLK0
CLK90
CLKFX
Clocking
Memory
Logic
IO Blocks
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
7Example Product Matrix – Spartan-3A....
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
8Agenda
Introduction to Xilinx devices and tools
Create and build a design
Where to go from here
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
9Xilinx Design Flow
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
10ISE 9.1i Project Navigator
Sourcesin project
Processesfor source
MessageConsole
Viewing Area
....
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
11Demonstration Block Diagram
Counter
XC3S700A
Input_Clock
Counter_Reset
Counter_EnableSwitches
50MHzClock
LEDs
Digital Clock ManagerGC
IOBsIOB
IOB
LED[0..7]
Spartan-3A Starter Board
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
12Demo 1 – Create a New ISE 9.1 Project
Create a new HDL project
Configure the project through the New Project Wizard
Setup the design’s I/O ports
View the generated code skeleton
Examine the Help menu
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
13Design Entry
Enter the “logic” for the designISE Project Navigator features assist with entry– Integrated text editor– Language templates
• Example code
– State machine editor– Cores– Architecture wizards
• Clocks• SERDES
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
14Demonstration 2 – Design Entry
Create the counter using the language template
Create the DCM instantiation using the DCM wizard
Add HDL code to combine the design
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
15Simulation
Test Bench Waveform Generatoror
Text Editor
Simulator
Results(Waveform Viewer)
StimulusTarget System (UUT)Other Models (e.g. Memory)
Testbench
Results (Text)
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
16Demonstration 3 - Simulation
Create stimulus using waveform editor
Run simulation
View waveform
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
17Synthesis
Xilinx Synthesis Tool– Verilog and Verilog 2001– VHDL 1993– Mixed Verilog and VHDL
Plug-in provision for 3rd party synthesizersCheck Syntax– Syntactical Checker
View design content– RTL Viewer– Technology Viewer
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
18Demonstration 4 – Synthesis
Check syntax
Synthesize
Use technology view to show design
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
19User Constraints
User Constraints File (UCF)– File extension is .ucf– Project file for constraints
Pin Location– Assign pin locations using Assign
Package Pins or text editor– Drag and drop capable
Timing– Assign timing constraints using
Create Timing Constraints or text editor
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
20Demonstration 5 – User Constraints
Assign package pins
Create global timing constraint
View UCF file
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
21Implementation
Push button flow works for many designs– Just “double click” to implement
Primary implementation phases– Translate– Map– Place And Route (PAR)– Timing analysis
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
22Design Summary
Build results shown in Design SummaryKey elements– Status– Device utilization– Performance– Reports links
....
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
23Timing Analyzer
Launch after PAR completesView results for each timing constraint– Failing constraints
shown in redInteractive mode– Try different speed
grade– Look for specific
timing paths
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
24Demonstration 6 - Implementation
Run push button flow
Double click implementation
View design summary
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
25
When the FPGA is powered on, it has no identity“Configuration” is the process of loading the FPGA SRAM with an identityThis identity is called a bitstream
Non-volatileMemory
SRAM-basedFPGA
Bitstream
This can be done two ways–PC connection to the FPGA – Good for debug–Non-volatile, on-board memory – Required for
an embedded system
Configuration
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
26Configuration Process
Generate Programming File– Bitstream (.bit) for FPGA– PROM image file (.mcs) for non-volatile memory
Configure Device– Use a JTAG download cable
• Load bitstream directly to FPGA• Load PROM image file to non-volatile memory
– Using a PROM• Serial or Parallel Interface• Xilinx or 3rd party solutions
ISEiMPACT
9.1i JTAGXilinx CableXilinx Cable
PC Board
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
27Demonstration 7 – Configure Device
Create FPGA bitstream
Download bitstream directly to FPGA using JTAG
Verify design is operational
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
28Agenda
Introduction to Xilinx devices and tools
Create and build a design
Where to go from here
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
29Xilinx Available Resources
Documentation– Datasheets– Application
notes– Design
guidelinesSupport databaseReference designsTraining and tutorialsTools to simplify designSoft IP
www.xilinx.com
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
30Avnet Available Resources
Avnet Field Application Engineers– Local Xilinx FAE– Regional Specialists
• I/O, DSP, and embedded processing
Trainings– On-ramps (1-2 hour)– Speedways (1/2 and full day)
Design Resource Center– Development boards
Avnet Engineering Services
www.em.avnet.com/drc
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
31Xilinx Tool Summary
ISE FoundationWindows, Linux, Solaris supportISE Simulator LiteEvaluation versions
ISE WebPACKWindows & Linux supportISE Simulator LiteLimited Virtex series FPGAsFREE Web download or DVD
FPGA real-time debug via
embedded logic analyzer
ModelTechHDL simulator X-Fest Specials
ChipScope ProMXE-III FPGA KitsFor ISE Foundation
HDL simulator
Full ISE Simulator
Optional Accessories
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
32Summary
Xilinx offers multiple FPGA families and tool solutions for your next design
The ISE 9.1i design flow has been explained and demonstrated in a real design
Avnet and Xilinx both have extensive resources to assist with your design efforts
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
33What’s Next?
Contact your FAE
Get Xilinx tools– ISE WebPACK can be downloaded free
Get a development board– Spartan-3A Starter Board highlighted in this session
Create your own design– Or attend an Avnet Speedway workshop in your area
Enabling success from the center of technology™
Thank You!Any Questions?
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
35Third Party Tools
Synthesis– Synplicity– Mentor
Simulation– Mentor– Aldec
JTAG– Universal Scan
… Many more than could be listed
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
36Advanced Capabilities
Tools– ChipScope Pro – XPower– PlanAhead– Embedded Development Kit – Sysgen for DSP
Features– SmartPreview– SmartGuide– Partitions
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
37ChipScope Pro
Real-time verification tools provide on-chip debug Analyze any internal FPGA signal, including embedded processor busses – Reduce overall design time– Access signals and nodes on-chip– Verify design in hardware
• 50X faster than simulation
– Integrated with the Xilinx design flow• Add ChipScope Pro as a project source• Modify signal probes in minutes
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
38ChipScope Pro Interface Makes FPGA Debug Easy
Access ChipScope cores via JTAG or user defined Trace portConfigure FPGA, define trigger conditions, and view data via ChipScope Pro analyzer running on a PC
ChipScope Pro Analyzer functions as a logicanalyzer, bus analyzer, and control console
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
39XPower
XPower provides power and thermal estimates after for FPGA and CPLD designs
Estimates power consumption by net, logic element, or hierarchical block
Verifies junction temperature limits are not exceeded
Included in all ISE configurations
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
40PlanAhead
Hierarchical Design and Analysis – Visually comprehend
design – Correct design issues early
Flexible Floorplanning– Block level implementation
Enables Block-based Methodology– Team design
Powerful Addition to ISE
PlanAhead Flow
RTL
Synthesis
ISE P&R
PlanAhead:Analysis &
Floorplanning
PlanAhead Flow
RTL
Synthesis
ISE P&R
PlanAheadAnalysis &
Floorplanning
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
41Embedded Development Kit (EDK)
Embedded Development Kit– Single development tool for Microprocessor hardware
and software development
Xilinx Platform Studio Integrated Design Environment
• SW Development• Download to Board
• SW Debug
Industry Standard SWDevelopment Flow
Industry Standard HW Development Flow
• Logic Development• Place and Route
• Download to FPGA• HW Debug
Create Processor, Bus & Peripheral Subsystem,
Software Drivers,BSP
Innovative Technology
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
42Xilinx System Generator for DSP
System Generator for DSP– Tightly integrated with
MATLAB and ISE 8.2i– IP Toolbox plug-in for
simulink– Full hardware design
and simulation
MATLABTM
Algorithm Developmentand Analysis
System-Level DesignSimulinkTM
3rd party prototypeand development
boards
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
43SmartCompile - SmartPreview
SmartPreview allows Pause/Resume in PARSaving and viewing of intermediate results– Easily identify timing critical regions within the design
SmartPreview allows users to– Create bitstream for lab debug– Preserve latest results as snapshot
and continue processing– Exit process immediately
• Latest results will be saved
– Cancel current iteration and move to next iterations• Applicable to Multi-Pass Place and Route (MPPR) runs only
Provides Greater Visibility into Implementation
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
44SmartCompile - SmartGuide
When to use SmartGuide?– Minimize impact of a small change– Faster runtime (2X average; up to 4X)
Is it easy to use SmartGuide?– Absolutely, no need for methodology or constraint
changes– Simply turn-on SmartGuide in ISE (Source -> Use
SmartGuide) Why will SmartGuide work?– Synthesis: New algorithms to maximize
naming repeatability and maintain performance– Implementation: New algorithms to maximize
layout preservation while meeting timing goals and ensuring design routability
– Testing: Thorough testing using 150+ customer HDL test cases
Physical Layout
Physical Layout with small design change
SmartGuide
SmallChangeSmall
Change
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
45SmartCompile - Partitions
When to use Partitions?– Want exact preservation of unchanged partitions– Want faster runtime
• 2.5X average; up to 6X– Design has natural hierarchy
Is it easy to use Partitions?– Yes! Simply right-click in ProjNav sources view
Why will Partitions work?– Database copy and paste– Customizable preservation level: just synthesis
or everything down to routing– Automatic dependency management
Top
A1 A2
B C
Logical Design (HDL)
A
Physical Layout after change
Original Physical Layout