xilinx programmable logic development systems foundation ise version 3
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Xilinx Programmable Logic Development SystemsFoundation ISE version 3
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Foundation ISEAn Integrated Synthesis Environment
Complete HDL centric design environment
ISE includes— Xilinx world-class implementation tools— Internet-Enabled project management environment— HDL design and synthesis tools— HDL testbench and simulation tools
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World Class Implementation Tools The industry’s fastest runtimes
— 2 to 10X faster than the competition
The industry’s highest performance— 15 to 25% faster clock rates than the competition
The industry’s leading devices— V2600E and V3200E, V405EM and V812EM, 2S200, Virtex-II
The industry’s most powerful design flows— Fast and efficient design methodologies for up to 10 million
gates
The industry’s most productive partnerships— Partners with over 30 of the industry’s most successful
companies
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The Industry’s Fastest Runtimes Deliver the Fastest Time To Market
Ultrafast place and route runtimes— XCV100: 3-5 minutes (100,000 system gates)— XCV1000: 30-45 minutes (1 million system gates!)— Real PCI design 64/66 in XCV300: ~ 5 minutes
– Consumes ~ 12% of XCV300 BG432
Even faster than our previous release— From 10% to 100% for < 1 million gates— From 2X to 10X for > 1 million gates
Runtime
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Clock speeds >160 MHz when targeting Virtex-E I/O performance >622 MB per second (mbps) when
targeting Virtex-E For existing designs, performance will increase by 10% to
15% from place & route algorithm improvements — Approximately a speed grade— For Virtex, Virtex-E, Spartan-II devices only
The Industry’s Best Performance Accelerates Our Customer’s Success
Performance
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The Industry’s Leading Devices
Extending the lead with Virtex-E— V2600E and V3200E
Unequalled memory and logic with the Extended Memory (EM) family— V405EM and V812EM
Awesome value for high-volume applications— The new Spartan-II family 2S200 device
Reinventing the FPGA, again with Virtex-II
Device Technology
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The Industry’s Most Powerful Design Flows
Incremental synthesis / layout with high-level floorplanning
Efficient methodology for teams using modular design
Advanced debug capabilities using ChipScope ILA
Seamless Integration with Xilinx EDA ALLSTAR products
Design Flows
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Incremental Synthesis through High-Level Floorplanning
Accelerates your time-to- market
Unchanged hierarchical blocks easily guided
Preserves timing for blocks unaffected by HDL design changes
Accelerates timing closure for complete design
Accelerates your time-to- market
Unchanged hierarchical blocks easily guided
Preserves timing for blocks unaffected by HDL design changes
Accelerates timing closure for complete design
Industry First
PCI uProcessor USB Ctrl
Top Level HDL
Floorplan defines layout area of each HDL blocks logic
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How High-Level Floorplanning Works
Incremental synthesis limits the name and logic changes to a single block instead of an entire design
Top
Block BBlock A Xilinx high-level floorplanning isolates the place and
route task to the area of the design that has changed and maintains timing of unchanged hierarchical blocks
Result: Guide easily restores unchanged blocks in the design!
Guide sees this: Instead of this:
Block DBlock C
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Xilinx Modular Design
Improves high-density design flows— Faster time-to-market by enabling multiple designers to work
on the design of a single device— Changes task from high-density device design
to high-performance module design
Improves high-density design performance— Enables more accurate / aggressive timing estimates during
synthesis!— Guaranteed module timing
Enables a more robust incremental design flow— Changes in HDL are retained within a module
Industry First
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Xilinx Modular Design Enabling Autonomous Team Design
Design Flow Define modules In
HDL block diagram
Floorplan area for each design module
Design, synthesize, place and route, and verify each module independently
Run global routing to interconnect modules
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Advanced Debug Capabilities
Solves the debug bottleneck by— Enabling in-system analysis of any internal FPGA signal while
running at full system speed— Easing analysis of any package pins (BGA)
ChipScope ILA— Powerful capture and control ILA cores— Analysis at system speeds— Comprehensive data capture— Flexible trigger conditions— Supports ILA modification without re-layout
Industry Best
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The ChipScope ILA System
Control
USERFUNCTION
ILA
USERFUNCTION
USERFUNCTION
ILA
ILA
Chipscope ILA
MultiLINX
PC with ChipScope
MultiLINX CableJTAGConnection
Target Board
Target FPGAwith up to15 ILA coresper control core
JTAG
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Language TemplatesLanguage Templates
HDL EditorHDL EditorDesign HierarchyDesign Hierarchy
Design ProcessesDesign Processes
Error Navigation to Web SolutionsError Navigation to Web Solutions
ISEThe Next Generation Design Environment
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Context Sensitive Flows Powerful and easy to use
— Only relevant processes are displayed to the user— Guides the user to the “next step” for that source
HDL testbench select
HDL testbench select Only HDL simulation
process is available
Only HDL simulation process is available
HDL module selected
HDL module selected
Process available includes synthesis and place & route
Process available includes synthesis and place & route
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Easy To Use Push Button Flows Simple three step process to process design Design flow control manages dependencies
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Select top levelSelect top level33
Double click desired end point
Double click desired end point
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Add filesAdd files
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Easy to Use Error Navigation to Web
Automatically search solution records at support.xilinx.com
Up-to-date expert answers for errors and warnings
Gets the answers you need quickly!
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ISE Project Snapshots
User created project checkpoints
Easily access any project snapshot
User defined version/ revision scheme
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Integrated Synthesis Environment Integration of two advanced synthesis engines
— Maximize HDL design performance
Synopsys FPGA ExpressOR
Xilinx Synthesis Technology (XST)
Synopsys FPGA ExpressOR
Xilinx Synthesis Technology (XST)
Further optimizes your design’s performance!
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ISE Synthesis Engines
Express
XST
Mixed Lan
guage
RAM Infer
encin
g
Timing D
riven
Synth
esis
4K D
evice
Supp
ort
Schem
atic V
iewer
Fanout C
ontrol
XXXX
XX
XX
SynthesisFlow
Error N
avigati
on
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Xilinx Synthesis TechnologyAn Added Bonus!
Focus on Quality of Results (QoR)— Spartan-II, Virtex / E / EM / II, and 9500 only! — Push-button results
Xilinx speeds innovation with XST— Vehicle to innovate integration with place and route— Share exclusive technology with select partners
Use as a secondary tool— When better QoR is necessary— Try on tough designs
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The ALLSTAR ProgramEDA ALLiance STARter
EDA Alliance partners tools that complement ISE
Product support by ALLSTAR vendor
Products targeted at lower density designs
Functionally equivalent non-limited versions sold and supported by EDA partner
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Synopsys: FPGA Express— FPGA Express version 3.4
Model Technology: ModelSim— MXE starter & MXE delivered by Xilinx— ModelSim PE and SE available from MTI
Visual software solutions: — StateCAD & Statebench — HDL Bencher— Xilinx Editions available in all packages— Standard products available directly from
Visual Software Solutions
Technologies Delivered in ISE
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Synopsys FPGA Express FPGA Express version 3.4 new features
— Schematic Viewer “Find” feature— Block Level Incremental Synthesis (BLIS)
– Xilinx exclusive feature– User defined blocks within the design– Individual netlists for each block only change if the source
HDL has changed– Virtex, VirtexE, Virtex2, Spartan2
— Improved standard I/O support
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Synopsys FPGA Express
QoR— ROM inferencing (implemented with dedicated RAM
resources)– Constant Arrays, certain CASE / if then else
— LUT instantiation — Runtime improvements
Updated Install methodology for OEMs— Addressed issues raised with the 2.1i Foundation
Install methodology