CURRICULUM VITA

Zainalabedin Navabi

Electrical and Computer Engineering

ECE Department, AK319

Worcester Polytechnic Institute

100 Institute Road

Worcester, Massachusetts 01609-2280

Email: navabi@ece.wpi.edu

Tel: 508-831-6663 (W); 508-668-6276 (H); 617-331-0055 (M); Fax: 508-831-5491 (W);

PERSONAL:

Born August 20, 1952

Citizenship: US

EDUCATION:

1978-1981:

Ph.D. in Electrical Engineering, University of Arizona, Tucson, Arizona 85721

Research: VLSI Design Automation Using A Hardware Programming

Language

Minor: Computer Science

1975-1978:

M.S. in Electrical Engineering, University of Arizona, Tucson, Arizona 85721

Research: Digital System Simulation at the Register Transfer Level

Minor: Computer Science

1971-1975:

B.S. in Electrical Engineering, University of Texas, Austin, Texas 78712

Graduated With HIGHEST HONORS with Grade Point Average of 3.9

SPECIALIZATION:

Specialized in Hardware Description Languages, Digital System Simulation,

VLSI Design Automation, Modeling, Digital System Test, Hardware

Generation, and Silicon Compilation. Have developed or directed development

of programs for Register Transfer Level simulation, PAL fuse layout generator,

Minimum complex gate implementation of digital circuits, behavioral and

component synthesis, back annotation and extraction programs, HDL based

tools, data flow and behavioral HDL based synthesis tools, Test generation

programs, and several testable design generation tools.

PROFESSIONAL AFFILIATIONS:

Institute of Electrical and Electronic Engineers (IEEE)

IEEE Computer Society

American Society of Engineering Education (ASEE)

European Association for Microprocessing and Microprogramming

(EUROMICRO)

Association of Computing Machinery (ACM)

HONORS:

Graduated with HIGHEST HONORS, University of Texas at Austin, May '75.

Motorola Merit Scholarship Award, October 1981.

WORK EXPERIENCE:

9/2006-Present:

Adjunct professor, Electrical and Computer Engineering Department,

Worcester Polytechnic Institute, Worcester, Massachusetts, USA. Responsible

for several graduate and undergraduate courses on digital systems. Teaching

graduate courses in RTL and ESL modeling, embedded design, hardware

description languages, and testing and testable design. Responsible for

incorporating design automation techniquies and use of HDLs into digital

design courses. Presently teaching online courses on ESL design, test, and

embedded design. Present research includes study of hardware modeling,

abstract hardware description languages, ESL methodology, RT level testing,

high level synthesis and design at ESL.

8/1992-8/2006:

Adjunct Professor, Electrical and Computer Engineering Department,

Northeastern University, Boston, Massachusetts, USA. Responsible for

teaching HDL and digital systems courses and research in simulation

algorithms. Performs summer NTU courses, as well as several short non- credit

HDL courses. Conducts research on HDL modeling for simulation and test.

8/1991 - 8/1992:

Associate Professor, Electrical and Computer Engineering Department,

Northeastern University, Boston, Massachusetts, USA. Holding the ITC

endowment Chair. Teaching Computer and Digital System, and VLSI Courses.

Responsible for developing a new HDL based graduate course, and for bringing

extensive use of CAD tools in the basic logic course. Courses taught include

undergraduate computer engineering, VLSI design courses; and graduate digital

system design with hardware description languages. Research in Hardware

Description Languages, timing analysis, simulation, modeling, hardware

synthesis, analysis of behavior of hardware, back-annotation, and Silicon

Compilation.

8/1987 - 8/1991:

Assistant Professor, Electrical and Computer Engineering Department,

Northeastern University, Boston, Massachusetts, USA. Teaching Computer

and Digital System, and VLSI Courses. Responsible for bringing extensive use

of CAD tools in the basic logic course. Courses taught include undergraduate

computer engineering, VLSI design courses; and graduate digital system design

with hardware description languages. Research in Hardware Description

Languages, timing analysis, simulation, hardware synthesis, analysis of

behavior of hardware, and Silicon Compilation.

8/86 - 8/87:

Visiting Assistant Professor, Electrical and Computer Engineering Department,

University of Arizona, Tucson, AZ USA. Teaching Computer and Digital

System Courses, including circuit theory, logic design and microprocessor, and

digital circuit design. Research in VLSI Design Automation and Hardware

description Languages.

8/83 - 8/86:

Assistant Professor, Electrical Engineering Department, Sharif University of

Technology, Iran. Teaching circuit theory, microprocessor, logic design, and

computer organization courses. Research in Hardware Description Languages

and Hardware Compilation. Development of the Computer Engineering

Curriculum and Graduate Study Program for the Computer and Electrical

Engineering Department. Developed software for silicon compilation from

AHPL.

1/82 - 6/83:

Visiting Assistant Professor, and Research Associate in the Electrical and

Computer Engineering, University of Arizona, USA. Taught basic Electrical

Engineering and CAD courses. Developed and taught a graduate course on the

computer aided design of digital circuits. Research in Hardware Description

Languages and VLSI Design Automation.

6/79 - 12/81:

Graduate Research Associate, University of Arizona. Major research in

Automation of VLSI Design.

9/78 - 9/79:

Graduate Teaching Associate, University of Arizona. Assisted is teaching

digital system courses. System Programmer, Interactive Graphic Engineering

Laboratory, Aerospace and Mechanical Engineering Department, University of

Arizona. Duties included development of a digitizing program for digitizing two

dimensional structures for finite element analysis, and Interface to Eclipse

computer.

EXPERTISE:

Experienced in interface design and computer graphics. Thorough

understanding of digital system design, microprocessors, compiler design and

language implementation, compiler-compilers, data structures, operating

systems, field programmable devices and related CAD tools, and custom and

semi-custom VLSI chip design and CAD tools. Have worked on Electrical and

Computer Engineering curriculum of several universities and have developed

graduate programs in this field.

JOURNAL PUBLICATIONS:

[1] H. A. Kamel and Z. Navabi, "Digitizing for Computer-Aided Finite Element Model

Generation – Part 1. The Generation Program," Transactions of the ASME, July

1980.

[2] Z. Navabi and H. A. Kamel, "Digitizing for Computer-Aided Finite Element Model

Generation - Part 2. Use of Digitizing in Mesh Generation," Transactions of the

ASME, July 1980.

[3] F. J. Hill, R. Swanson, Z. Navabi and M. Masud "Structure Specification with a

Procedural Hardware Description Language," IEEE Transactions on Computers,

February 1981, pp. 157-161.

[4] F. J. Hill, Z. Navabi, C. H. Chiang, D. P. Chen, and M. Masud "Hardware

Compilation of AHPL Descriptions to an SLA Target," IEEE Transactions on

Computer Aided Design, June 1984.

[5] Z. Navabi, "Generating Gate Level Two Phase Dynamic MOS Logic From

AHPL," EUROMICRO Journal on Microprocessing and Micrprogramming,

September/October 1985.

[6] Z. Navabi and K. Doroudi, "Compiling an RT Level Hardware Description Language

into Layout of NMOS Cells," EUROMICRO Journal on Microprocessing and

Microprogramming, December 1986, Volume 18, Numbers 1-5.

[7] Z. Navabi and Kia Doroudi, "HDL Front End For a Cell Based Silicon Compiler,"

International Journal of Computer Simulation," 1991-1992, Ablex Publishing

Corporation, Norwood, New Jersey.

[8] Z. Navabi, "Compiling Gate RC Models Into a Top Level Simulation Model for

Rough Timing Analysis of VLSI Circuits," Journal of Microprocessors and

Microsystems, Butterworth Heinemann Publishing, July-August 1991.

[9] Z. Navabi, "A High Level Language For Design and Modeling of Hardware," Journal

of Systems and Software, Elsevier Publishing Company, December 1991 or Early

1992.

[10] Z. Navabi and M. Massoumi, "Investigating Back-Annotation of High Level

Descriptions," The International Journal of Simulation, Society of Computer

Simulation, November 1991.

[11] Z. Navabi, "A Description Style for Automatic Hardware Synthesis," Journal of

Computer Applications in Technology.

[12] Z. Navabi and John Spillane, "Synthesis of VLSI Circuits From Behavioral

Descriptions," Microelectronics Journal, Elsevier Advanced Technology

Publishing, December 1991.

[13] Z. Navabi and Mehran Massoumi, "Design and Description of Hardware Using a

Standard Hardware Language," Microelectronics Journal, Elsevier Advanced

Technology Publishing

[14] Z. Navabi and Zahra Razavi, “A Transistor Level Link for VHDL Simulation of

VLSI Circuits”, Simulation Journal, September 1995.

[15] Z. Navabi with Bijan Alizadeh and Mohammad Reza Kakoee, "A New High Level

Model Based on Integer Equations to Check CTL Properties in VHDL Environment",

WSEAS Transactions on Circuits, Issue 1, Volume 2, January 2003

[16] Z. Navabi with Maghsoud Abbaspour, "Architecture Modeling for retargeting a

disassembler Binary Tool", WSEAS Transactions on Computers, Issue 3, Volume 2,

July 2003

[17] Z. Navabi with M. H. Tehranipour, M. Nourani, S. M. Fakhraie, and M. R.

Movahedin, "Embedded Test for Processor and Memory Cores in

System-on-Chips," to appear in International Journal of Science and Technology

(Scientia Iranica), October 2003.

[18] Zainalabedin Navabi with M.H. Tehranipour, S.M. Fakhraei and M.R. Movahedin,

"A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM

Cores", Journal of Electronic Testing: Theory and Applications 20, 155-168, 2004

[19] Zainalabedin Navabi with Farzin Karimi, Waleed M. Meleis and Fabrizio Lombardi,

" Using Data Compression in Automatic Test Equipment for System-on-Chip

Testing", IEEE Transaction on Instrumentation and Measurement, Vol. 53, NO. 2,

April 2004

[20] Zainalabedin Navabi with Mehran Nadjarbashi and Shahrzad Mirkhani, “A Method

of Structural Equivalence Fault Collapsing for HDL Implementation”, Integration,

the VLSI Journal, Submitted.

[21] Zainalabedin Navabi with Shahrzad Mirkhani, Meisam Lavasani, and Fabrizio

Lombardi “Using RT Level Component Descriptions for Single Stuck-at

Hierarchical Fault Simulation”, Journal of Electronic Testing, Kluwer Publishing,

Submitted.

[22] Zainalabedin Navabi with Saeed Shamshiri and Hadi Esmaeilzadeh, “Instruction-

Level Test Methodology for CPU Core Self-Testing”, ACM Transactions on Design

Automation of Electronic Systems, Vol. 10, No. 4, October 2005, pp. 673-689.

[23] Zainalabedin Navabi with Ehsan Atoofian, “A Test Approach for Look-Up Table

Based FPGAs”, Journal of Computer Science and Technology”, Kluwer Boston Inc.,

Vol. 21, NO. 1, pp. 141-146, January 2006.

[24] Zainalabedin Navabi with Sh. Sharifi, J. Jafari, M. Hosseinabady and A. Afzali-

Kusha, “Scan-Based Structure with Reduced Static and Dynamic Power

Consumption”, Journal of Low Power Electronics, Vol. 2, No.3, pp. 477-487, Dec.

2006.

[25] Zainalabedin Navabi with M. Hosseinabady and Pejman Lotfi-Kamran, “Low Test

Application Time Resource Binding for Behavioral Synthesis”, ACM Transactions

on Design Automation of Electronic Systems, Vol. 12, No. 2, Article 16, April 2007.

[26] Zainalabedin Navabi with Ali Shahabi, Nima Honarmand and Hassan Sohofi,

“Degradable mesh-based on-chip networks using programmable routing tables”,

IEICE Electronics Express, Vol. 4, No. 10, pp. 332-339, May 25, 2007.

[27] Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, and

Zainalabedin Navabi, "An RTL Datapath Test Generation Based on Modular

Arithmetic Equations," submitted to the IEE Proc. Computers & Digital Techniques

[28] Mohammad Hosseinabady, Shervin Sharifi, Zainalabedin Navabi, "Reducing Test

Power, Time and Data Volume Using Partially-Specified Test Vectors," submitted to

the Integration VLSI Journal, Elsevier Publishing.

[29] Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, and

Zainalabedin Navabi, “Low Overhead DFT Using CDFG by Modifying Controller,”

Computers & Digital Techniques, IET, Volume 1, Issue 4, Page(s):322-333, July

2007.

[30] Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin

Navabi, “A selective trigger scan architecture for VLSI testing”, IEEE Transaction

on Computers, Volume 57, Issue 3, Page(s):316 – 328, March 2008

[31] M. R. Jamali, M. Dehyadegari, A. Arami, C. Lucas, Z. Navabi, “Real-time Embedded

Emotional Controller”, Neural Computer & Application, Springer, January 2008

[32] M. Saneei, A. Afzali-Kusha, Z. Navabi, “A Low-Power High Throughput Link

Splitting Router for NoCs”, Journal of Zhejiang University-SCIENCE A, Vol. 9, No.

12, Page(s) 1708-1714, 2008

[33] N. Karimi, A. Alaghi, M. Sedghi, Z. Navabi, “Online Network-on-Chip Switch Fault

Detection and Diagnosis Using Functional Switch Faults”, Journal of Universal

Computer Science, Vol. 14, No. 22, Dec. 2008

[34] M. Saneei, A. Afzali-Kusha, Z. Navabi, “Sign Bit Reduction Encoding For Low

Power Applications”, Journal of VLSI Signal Processing Systems, Springer, Vol. 57,

No. 3, Page(s) 321-329, September 2009

[35] M. R. Jamali, A. Arami, M. Dehyadegari, C. Lucas, Z. Navabi, “Emotion on FPGA:

Model driven approach”, Elsevier Publishing, Volume 36, Number 4, May 2009

[36] N. Mahani, P. Mokri, Z. Navabi, “System Level Hardware Design and Simulation

with SystemAda”, Ada Letters, A Publication of SIGAda, the ACM Special Interest

Group on Ada, Volume 29, Number 1, Page(s): 19-22, April 2009

[37] P. Lotfi-Kamran, A. Rahmani, M. Daneshtalab, A. Afzali-Kusha, Z. Navabi, “EDXY

– A Smart Congestion-Aware and Link Failure Tolerant Routing Algorithm for

Network-on-Chips”, Journal of Systems Architecture, ELSEVIER, Vol. 56, No. 7,

Page(s) 256-264, July 2010

[38] S. Sadeghi-Kohan, F. Javaheri, S. Mahmoodi and Z. Navabi, “Multi Level Test

Package”, Journal of Shanghai Normal University (Natural Sciences), Vol. 39, No.

5, Page(s) 472-477, October 2010

[39] A. A. Ghofrani, F. Javaheri, H. Noori and Z. Navabi, “Transaction Level Formal

Verification Using Timed Automata”, Journal of Shanghai Normal University

(Natural Sciences), Vol. 39, No. 5, Page(s) 462-471, October 2010

[40] M. Mirzaei, M. Tabandeh, B. Alizadeh and Z. Navabi, “A New Approach for

Automatic Test Pattern Generation in Register Transfer Level Circuits” , Journal of

Design & Test, IEEE, Vol. 30 , Issue: 4, Page(s) 49-59, 2013

[41] M. Baharani, H. Noori, M. Aliasgari and Z. Navabi, “High-Level Design Space

Exploration of Locally linear Neuro-Fuzzy Models for Embedded Systems”, Journal

of Fuzzy Sets and Systems, ELSEVIER, 2013

[42] H. Sabaghian, A. Shahabi and Z. Navabi, “A Novel Modeling Approach for System-

Level Application Mapping Targetted for Configurable Architecture”, Canadian

Journal of Electrical and Computer Engineering, IEEE Journals and Magazines,Vol

37, No. 4, 2014

[43] S. Sadeghi Kohan and Z. Navabi, “System Level Design: Facilitations and

Utilizations”, Iranian Journal of Engineering Education, No. 62, Vol. 16, Summer

2014

[44] A. Kamran and Z. Navabi, “Hardware Acceleration of Online Error Detection in

Many-Core Processors”, Canadian Journal of Electrical and Computer Engineering,

IEEE Journals and Magazines,Vol 38, No. 2, Jan. 2015

[45] H. Sohofi and Z. Navabi, “System-level assertions: approach for electronic system-

level verification”, IET Computers & Digital Techniques, Vol. 9, Issue 3, May 2015

[46] S. Ghandali, B. Alizadeh, M. Fujita and Z. Navabi, “Automatic High-Level Data-

Flow Synthesis and Optimization of Polynomial Datapaths Using Functional

Decomposition”, IEEE Transactions on Computers, Vol. 64, Issue 6, May 2015

[47] M. Ansari, H. Afzali-Kusha, B. Ebrahimi, A. Afzali-Kusha, M. Pedram and Z.

Navabi, “A near-threshold 7T SRAM cell with high write and read margins and low

write time for sub-20 nm FinFET technologies”, INTEGRATION, the VLSI journal,

ELSEVIER, Page(s) 91-106, June 2015

[48] A. Kamran and Z. Navabi, “Self-Healing Many-core Architecture: Analysis and

Evaluation”, VLSI Design Journal. Volume 2016, Article ID 9767139, 17 pages,

2016.

[49] A. Kamran and Z. Navabi, “Stochastic of Processing Cores in a many-core

Architecture”, ELSEVIER, Integration, the VLSI Journal. Volume 66, page 183-

193, Sep. 2016.

MAGAZINES:

[1] "System Test: What, Why, and How?" A D&T Roundtable for the IEEE Publication,

Design and Test of Computers; August 1990; with Jack Arabian, Robert Rolfe,

Muary Smeyne, Harold Carter, and Ernie Millham.

MANUALS and WORKBOOKS:

[1] Z. Navabi and F. J. Hill, "User Manual for AHPL Simulator (HPSIM2) / AHPL

Compiler (HPCOM)," Published by Engineering Experiment Station, University of

Arizona, December 1, 1988.

[2] Z. Navabi and John Sutter, "User Manual for OCT2HILO Program," Published by

Massachusetts Microelectronics Center, Westboro MA, February 15 1991.

[3] Z. Navabi, "Advanced VHDL for Hardware Design and Modeling," Published by

Okura and Company Ltd. Tokyo, Japan October 1993.

BOOKS:

[1] Z. Navabi, "VHDL: Analysis and Modeling of Digital System," McGraw Hill

Company, N.Y., New York, 1993.

[2] Z. Navabi, "VHDL: Analysis and Modeling of Digital System," Second Edition.

McGraw Hill Company, N.Y., New York, 1998.

[3] Z. Navabi, "Verilog Digital System Design," McGraw Hill Company, N.Y., New

York, 1999, ISBN: 0-07-047164-0.

[4] Z. Navabi, "Verilog Computer-Based Training Course", McGraw Hill Company,

N.Y., New York, 2002, ISBN: 0-07-137473-6.

[5] Z. Navabi, "Digital Design and Implementation with Field Programmable Devices",

Kluwer Academic Publishers, 2004, ISBN: 1-4020-8011-5.

[6] Z. Navabi, "Verilog Digital System Design", Second Edition. McGraw Hill

Company, N.Y., New York, 2006, ISBN: 0-07-144564-1.

[7] Embedded Core Design with FPGAs"; August 1, 2006; McGraw Hill-Professional;

ISBN: 0071474811.

[8] VHDL: Modular Design and Synthesis of Cores and Systems, 3E; April 2007;

McGraw Hill-Professional; ISBN: 978-0071475464.

[9] Digital System Test and Testable Design: Using HDL Models and Architectures;

January 2011; Springer; ISBN: 978-1-4419-7547-8.

BOOK CHAPTERS:

[1] Z. Navabi, “Chapter 81, Hardware Description in Verilog: An Overview”, The VLSI

Handbook, CRC IEEE PRESS, 2000, ISBN: 0-8493-8593-8.

[2] Z. Navabi, “Section XIII, Design Languages”, Section Editor, The VLSI Handbook,

Second Edition (Electrical Engineering Handbook), CRC Press, 2006, ISBN: 978-

0849341991.

[3] Z. Navabi, “Chapter 85: Languages for Design and Implementation of Hardware”,

The VLSI Handbook, Second Edition (Electrical Engineering Handbook), CRC

Press, 2006, ISBN: 978-0849341991.

[4] Shahrzad Mirkhani and Zainalabedin Navabi, “Chapter 86, System Level Design

Languages”, The VLSI Handbook, Second Edition (Electrical Engineering

Handbook), CRC Press, 2006, ISBN: 978-0849341991.

[5] Mahsan Rofouei and Zainalabedin Navabi, “Chapter 87, RT Level Hardware

Description with VHDL”, The VLSI Handbook, Second Edition (Electrical

Engineering Handbook), CRC Press, 2006, ISBN: 978-0849341991.

[6] Zainalabedin Navabi, “Chapter 88, Register Transfer Level Hardware Description

with Verilog”, The VLSI Handbook, Second Edition (Electrical Engineering

Handbook), CRC Press, 2006, ISBN: 978-0849341991.

[7] Shahrzad Mirkhani and Zainalabedin Navabi, “Chapter 89, Register-Transfer Level

Hardware Description with SystemC”, The VLSI Handbook, Second Edition

(Electrical Engineering Handbook), CRC Press, 2006, ISBN: 978-0849341991.

[8] Naghmeh Karimi and Zainalabedin Navabi, “Chapter 91 VHDL-AMS Hardware

Description Language”, The VLSI Handbook, Second Edition (Electrical

Engineering Handbook), CRC Press, 2006, ISBN: 978-0849341991.

[9] Hamid Shojaei and Zainalabedin Navabi, “Chapter 92, Verification Languages”, The

VLSI Handbook, Second Edition (Electrical Engineering Handbook), CRC Press,

2006, ISBN: 978-0849341991.

[10] Naghmeh Karimi and Zainalabedin Navabi 93 ASIC and Custom IC Cell Information

Representation”, The VLSI Handbook, Second Edition (Electrical Engineering

Handbook), CRC Press, 2006, ISBN: 978-0849341991.

[11] Shahrzad Mirkhani and Zainalabedin Navabi, “Chapter 94, Test Languages”, The

VLSI Handbook, Second Edition (Electrical Engineering Handbook), CRC Press,

2006, ISBN: 978-0849341991.

[12] Naghmeh Karimi and Zainalabedin Navabi, “Chapter 95, Timing Description

Languages”, The VLSI Handbook, Second Edition (Electrical Engineering

Handbook), CRC Press, 2006, ISBN: 978-0849341991.

PATENTS:

[1] Z. Navabi, "Timed-State-Machines: A Representation for Analysis and Synthesis of

Behavioral Descriptions," Patent Application Filed with Digital Equipment

Corporation, July 1990.

CONFERENCE PUBLICATIONS:

[1] R. Swanson , F. J. Hill and Z. Navabi, "An AHPL Compiler/Simulator System,"

Proceedings of the Sixth Texas Conference on Computing Systems, November 14 &

15, 1977.

[2] F. J. Hill and Z. Navabi, "Efficient Simulation of AHPL," Proceedings of the Sixteenth

Design Automation Conference, June 1979, San Diego.

[3] H. A. Kamel and Z. Navabi, "Digitizing for Computer-Aided Finite Element Model

Generation," Proceedings of the ASME Fifth Design Automation Conference,

September 1979, St. Louis, Missouri.

[4] F. J. Hill and Z. Navabi, "Extending Second Generation AHPL Software to

Accommodate AHPL III," Proceedings of the Fourth International Symposium on

Computer Hardware Description Languages, pp. 47-53, with F. J. Hill, October 1979,

Palo Alto, CA.

[5] M. Masud, W. J. Knapp, J. Hill and Z. Navabi, "Impact of VLSI Technology on the

Hardware Description Language AHPL," Proceedings of the IEEE International

Conference on Circuits and Computers, pp. 912-915, October 1980.

[6] C. H. Chiang, Z. Navabi, W. J. Knapp, F. J. Hill and C. DeSouza, "VLSI Design

Automation Using A Hardware Description Language," Proceedings of the Phoenix

Conference on Computers and Communications, pp. 54-57, May 1982, Phoenix,

Arizona.

[7] F. J. Hill, Z. Navabi and C. H. Chiang, "Storage Logic Array Realization of RTL

Descriptions," Proceedings of the Sixth International Symposium on Computer

Hardware Description Languages, pp.153-163, May 1983, Pittsburgh, Pennsylvania.

[8] S. Payadar and Z. Navabi, "Gate Level Simulation and Testing of Technology

Independent RTL Hardware Descriptions," Proceedings of the Fifth IASTED

International Symposium on Applied Informatics, February 1985, Grindelwald,

Switzerland.

[9] Z. Navabi, "The Impact of Hardware Description Languages on the Education of

Hardware Design," Proceedings of the Eight Biennial University / Government /

Industry Microelectronics Symposium, June 1989, Westborough, Massachusetts.

[10] Z. Navabi, "Timing Compilation of VLSI Circuits for Fast Timing Simulation,"

Proceedings of the Twentieth Annual Pittsburgh Conference on Modeling and

Simulation, May 1989, Pittsburgh, Pennsylvania.

[11] Robert Emberley and Z. Navabi, "Timing Analysis and Simulation of VLSI

Components in VHDL," Proceedings of the 1990 International Conference on

Computers and Information (ICCI'90), May 23-26 1990.

[12] Andy Huang and Z. Navabi, "Modeling Logic Functions in VHDL for Timing

Simulation," Society of Computer Simulation (SCS); Proceedings of the 1990 Summer

Simulation Conference, July 18-22 1990.

[13] Z. Navabi, "VHDL: A Language For Modeling and Design of Digital Circuits,"

Control and Modeling; Proceedings of the 1990 IASTED International Conference on

Control and Modeling (ICCM'90), July 17-20 1990.

[14] Z. Navabi, "Modeling Layout Library Cells in VHDL," Control and Modeling;

Proceedings of the 1990 IASTED International Conference on Control and Modeling

(ICCM'90), July 17-20 1990.

[15] J. Spillane and Z. Navabi, "Templates For Synthesis From VHDL," Proceedings of

the 1990 IEEE ASIC Seminar, September 17-21 1990.

[16] J. Dube and Z. Navabi, "Modeling Strategy for Post Layout Verification,"

Proceedings of the 1990 IEEE ASIC Seminar, September 17-21 1990.

[17] Z. Navabi, "Elements of VHDL For Description of Hardware: A Tutorial View,"

Proceedings of the 1990 IEEE ASIC Seminar, September 17-21 1990.

[18] Z. Navabi, "Behavioral Level Modeling of Gate Level Loading Effects," 1991

International Conference on Computer Hardware Description Languages, April 1991,

Marselle France.

[19] C. Fernandez, M. Massoumi and Z. Navabi, "An Exercise In Repairing Behavioral

Models for Achieving Improved Testing and Verification," Society of Computer

Simulation (SCS); Proceedings of the 1991 Summer Simulation Conference, July 1991.

[20] J. Spillane and Z. Navabi, "Describing Controlling Hardware in VHDL," Proceedings

of the 1991 IEEE ASIC Conference and Exhibit, September 1991.

[21] J. Dube and Z. Navabi, "Behavioral VHDL Transistor Slope Models," Proceedings

of the 1991 IEEE ASIC Conference and Exhibit, September 1991.

[22] Susan Day and Z. Navabi, "Tutorial on Use of VHDL for Description of Digital

Systems," Proceedings of the 1991 IEEE ASIC Conference and Exhibit, September

1991.

[23] Z. Navabi with I. Dahan and Tedd Corman, "Implementing Timed Logic Simulation

in VHDL," Proceedings of VIUF Spring 1992 Conference, pp. 207-215, VHDL

International, May 1992, Scottsdale, Arizona.

[24] J. Dube and Z. Navabi, "Behavioral VHDL Transistor Models," Proceedings of VIUF

Spring 1992 Conference, pp. 125-132, VHDL International, May 1992, Scottsdale,

Arizona.

[25] P. Campbell, M. Vai and Z. Navabi, "Implementation of IEEE Std 1149.1-1990 in

VHDL," Proceedings of VIUF Spring 1992 Conference, pp. 151-159, VHDL

International, May 1992, Scottsdale, Arizona.

[26] S. Day, M. Massoumi and Z. Navabi, "Investigating Back Annotation of Controlling

Machines," VIUF Spring 1992 Conference, pp. 185-195, VHDL International, May

1992, Scottsdale, Arizona.

[27] N. Cooray, R. Liyanage and Z. Navabi, “Using VHDL in Parallel Fault Simulation”

Proceedings of SCS, International Conference on Simulation in Engineering Education,

v. 25, N. 3, pp. 198-203, Jan. 1993, San Diago, California.

[28] N. Cooray, R. Liyanage and Z. Navabi, “VHDL for Digital Design and Simulation”

Proceedings of SCS, International Conference on Simulation in Engineering Education,

v. 25, N. 3, pp. 114-119, Jan. 1993, San Diago, California.

[29] Niranjan Cooray, Ruchira Liyanage and Z. Navabi, "Modeling for Fault Insertation

and Parallel Fault Simulation," VIUF Spring 1993 Conference, VHDL International

Users Forum, April 1993, Ottawa Canada.

[30] Mohammad Reza Movahhedin and Z. Navabi, "Configurable VHDL Models for Field

Programmable Gate Arrays," VIUF Spring 1993 Conference, VHDL International

Users Forum, April 1993, Ottawa Canada.

[31] Zahra Razavi and Z. Navabi, "Self Adjusting Unidirectional Switch Models for

Dynamic Load Calculation and Fast Switch Level Simulation," VIUF Spring 1993

Conference, VHDL International Users Forum, April 1993, Ottawa Canada.

[32] Amirhooshang Hashemi, Massoud Eghtesad, MankuanVai and Z. Navabi, "Modeling

Timing Behavior of Logic Circuits Using Piecewise Linear Models," 1993 International

Conference on Computer Hardware Description Languages, April 1993, Ottawa

Canada.

[33] Peter Campbell and Z. Navabi, "Synthesis of Testable Controllers," VIUF Spring

1993 Conference, VHDL International Users Forum, April 1993, Ottawa Canada.

[34] Z. Razavi and Z. Navabi, “Creating an HDL Link for the VLSI CAD Tools”

Proceedings of SCS, International Conference on Simulation in Engineering Education,

Jan. 1994, Phoenix AZ, USA.

[35] M. Shadfar and Z. Navabi, "VHDL Modeling for Equivalence Fault Collapsing",

Proceedings of VHDL International Users' Forum. May 1-4, 1994, Oakland, CA.

[36] Massoud Shadfar and Z. Navabi, “A VHDL Test Environment Including Models for

Equivalence Fault Collapsing”, Proceeding of the VHDL International Users Forum,

May 1-4 , 1994, Oakland, California, USA.

[37] M. Shadfar, A. Peymandoust and Z. Navabi, “Using VHDL Critical Path Tracing

Models for Pseudo Random Test Generation”, Proceedings of VHDL International

Users’ Forum, May 1-4, 1994, Oakland, CA.

[38] W. Paulsen and Z. Navabi, “Modeling for Logic Level Minmax Simulation”,

Proceedings of VIUF,VHDL International Users’ Forum, Nov. 13-16, 1994,

Washington DC.

[39] M. Abbaspour, F. Karimi, M. Serjoui, M. Teimouri, M. Eghtesad, L. Aminzadeh and

Z. Navabi, “Modeling Techniques for Simulation, Test and Documentation of Digital

Components”, Proceedings of VIUF,VHDL International Users’ Forum, Nov. 13-16,

1994, Washington DC.

[40] M. Shadfar and Z. Navabi, "VHDL Modeling for Critical Path Tracing" ICEHDL

WMC 1995, January, Las Vegas, Nevada.

[41] F. Khani and Z. Navabi, "VHDL Structural Models for the Implementation of Path

Sensitization Test Generation" ICEHDL WMC 1995, January, Las Vegas, Nevada.

[42] M. Shadfar and Z. Navabi, “BIST Modeling and Its Application in Design

Verification”, Proceedings of VIUF,VHDL International Users’ Forum, Spring 1995,

San Diego, CA.

[43] A. Peymandoust, M. Shadfar and Z. Navabi, “Implementation Adaptive Random Test

Generation in VHDL”, Proceedings of VIUF,VHDL International Users’ Forum, pp.

10.29-10.35, Fall 1995, Newton, MA.

[44] A. Khalafi, M. Teimouri and Z. Navabi, “Using VHDL Simulation for Finding

Critical Timing Paths” ICEE-96 , May 13-16, 1996, Tehran-Iran.

[45] M.R. Movahedin and Z. Navabi, “An Introduction to ASIC Designer’s Faults and a

Fault Tolerant VHDL Synthesizer” ICEE-96 , May 13-16, 1996, Tehran-Iran.

[46] F. Karimi and Z. Navabi, “A Global Approach to Algebraic Factoring Which is

Extendable for Utilizing Don’t Cares” Proceedings of ICEE-96 , May 13-16, 1996,

Tehran-Iran.

[47] A. Peymandoust and Z. Navabi, “VHDL Concurrent Simulation of RT Level

Components”, Proceedings of VIUF,VHDL International Users’ Forum, Fall 1996,

Durham, North Carolina.

[48] A. Khalafi and Z. Navabi, “HDL Modeling for Finding Critical Timing Paths”,

Proceedings of VIUF,VHDL International Users’ Forum, pp. 309-312, Fall 1996,

Durham, North Carolina.

[49] A. Khalafi and Z. Navabi, “Adapting Differential Fault Simulation for VHDL

Implementation”, Proceedings of VIUF,VHDL International Users’ Forum, Fall 1996,

Durham, North Carolina.

[50] Morteza Fayazi and Z. Navabi, “Using VHDL Neural Network Model for Automatic

Test Generation,” Proceedings of Workshop on Modeling, March 1996, Spain.

[51] Seyed Abdollah Aftabjahani and Z. Navabi, “Functional Fault Simulation of VHDL

Gate Level Models,” Proceedings of VIUF, VHDL International Users’ Forum, IEEE

Computer Society, Fall 1997, Virginia, USA.

[52] Bijan Alizadeh and Z. Navabi, “Component Modeling For Reliability Analysis By

Simulation,” ,” Proceedings of VIUF, VHDL International Users’ Forum, IEEE

Computer Society, Fall 1997, Virginia, USA.

[53] Armita Peymandoust and Z. Navabi, “Implementing A Complete Test Tool Set in

VHDL,” ,” Proceedings of VIUF, VHDL International Users’ Forum, IEEE Computer

Society, Fall 1997, Virginia, USA.

[54] B. Alizadeh and Z. Navabi, “Repair Rate Consideration in Reliability Analysis by

Simulation", 1998

[55] R. Purtoosi and Z. Navabi, “Ethernet LAN Modeling with VHDL”, Proceedings of

the 8th Anuual International HDL Conference & Exhibition, April 1999, pp 55-60,

Santa Clara, CA.

[56] M.R. Movahedin, M. Nadjar-bashi and Z. Navabi, “Line Oriented Structural

Equivalence Fault Collapsing, Proceedings of Workshop on Model and Test, Germany,

2000.

[57] M. H. Tehranipour and Z. Navabi, "Zero-Overhead BIST for Internal SRAM Testing,"

in proc. International Conference On Microelectronics (ICM'00), Tehran, Iran, pp. 109-

112, 2000.

[58] Lily Ghasemzadeh and Z. Navabi, “ A Fast Cycle-Based Approach for Synthesizable

RT Level VHDL Simulation” Proceedings of the 12th International Conference on

Microelectronics, October 31- November 2, 2000, Tehran-Iran

[59] Mohammad Hossein Reshadi, Amir Masoud Gharehbaghi and Z. Navabi, “AIRE/CE:

A Revision Towards CAD Tool Integration”, Proceedings of the 12th International

Conference on Microelectronics, October 31- November 2, 2000, Tehran-Iran.

[60] Lily Ghasemzadeh and Z. Navabi, “A Fast Cycle-Based Approach for Synthesizable

RT Level VHDL Simulation”, Proceedings of IEEE Asia Pacific Conference on

Circuits and Systems, pp 477-480, December 4 to 6, 2000, Tianjin China, IEEE Catalog

Number 00EX394.

[61] Mehrdad Reshadi, Amir Gharebaghi and Z. Navabi, “Intermediate Format

Standardization: Ambiguities, Deficiencies, Portability Issues, Documentation and

Improvements”, Proceedings of The International HDL Conference & Exhibition,

March 8-10, 2000, San Jose, California.

[62] Farzin Karimi and Z. Navabi, “Serial Data Compression for 1149.1 Compatible Core

Testing”, Proceedings of The 9th IEEE North Atlantic Test Workshop, pp 52-58, May

25-26 2000, Gloucester, Massachusetts.

[63] Morteza Fayyazi and Z. Navabi, “Accelerating Test Generation by VLSI Hardware

Emulation”, Proceedings of The 9th IEEE North Atlantic Test Workshop, pp 84-89,

May 25-26 2000, Gloucester, Massachusetts.

[64] Amir Gharehbaghi and Z. Navabi, “High Level Test Generation from VHDL

Behavioral Descriptions” Proceedings of IEEE Computer Society VIUF Fall 2000

Workshop, pp 123-126, October 18-20, 2000, Orlando, Florida.

[65] Mehrdad Reshadi, Bita Gorji-Ara and Z. Navabi, “HDML: Compiled VHDL in

XML”, Proceedings of IEEE Computer Society VIUF Fall 2000 Workshop, pp 69-74,

October 18-20, 2000, Orlando, Florida.

[66] Mina Zolfy, Shahrzad Mirkhani and Zainalabedin Navabi. “Adaptation of an Event-

Driven Simulation Environment to Sequentially Propagated Concurrent Fault

Simulation”. Proc. of DATE’01 p. 823, March 2001.

[67] H. Farshbaf, S. Mirkhani, M. Zolfy and Z. Navabi, “Test Bench and BIST

Architecture Evaluation Environment in VHDL” Proceedings of The 10th IEEE North

Atlantic Test Workshop, pp 17-21, May 24-25, 2001 Gloucester, Massachusetts.

[68] Farzin Karimi , S. Irrinki and Z. Navabi, “Parallel Testing of Dual-Port Static Random

Access Memories” Proceedings of The 10th IEEE North Atlantic Test Workshop, pp

22-28, May 24-25, 2001 Gloucester, Massachusetts.

[69] M. Zolfy, S. Mirkhani and Z. Navabi, “SPC-FS: A New Method for Fault Simulation

Implemented in VHDL” Proceedings of The 10th IEEE North Atlantic Test Workshop,

pp 11-16, May 24-25, 2001 Gloucester, Massachusetts.

[70] Meisam Lavasani, Shahrzad Mirkhani and Z. Navabi, “Increasing Fault Simulation

Performance Using Pre-Synthesis Behavioral Model”, Proceedings of CSEC01, pp.

230-235, July 2001, Cerete, Greece.

[71] M. H. Tehranipour, S. M. Fakhraie and Z. Navabi, “An Efficient BIST Method for

Embedded SRAM Testing,” Proceedings of the International Symposium on Circuits

And Systems (ISCAS), 2001, Vol. 5, pp. 73-76, Sydney, Australia.

[72] M. H. Tehranipour, S. M. Fakhraie and Z. Navabi, “A Low-Cost BIST Architecture

for Processor Cores”, Proceedings of Electronic Circuits and Systems Conference

(ECS), 2001, Bratislava, Slovakia, pp. 11-14, 2001.

[73] Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani and Z. Navabi, “Fault Simulation

for VHDL Based Testbench and BIST Evaluation”, Proceedings of The Tenth Asian

Test Symposium, November 19-21 2001, Kyoto, Japan.

[74] Mina Zolfy, Shahrzad Mirkhani, and Zainalabedin Navabi, “Behavioral Coverage

Calculation for Testbench Evaluation,” Proc. of HDLCON 2002, March 2002.

[75] Meisam Lavasani, Shahrzad Mirkhani and Z. Navabi, “High Performance Fault

Simulation Using Dynamic Model Switching,” IEEE 11th North Atlantic Test

Workshop (NATW'02 ) May 23-24, 2002, Montauk, New York, USA.

[76] Mina Zolfy and Zainalabedin Navabi, “Stuck-at Fault Coverage Prediction in High

Level Simulation”, Proc. of 4th Irano-Armenian Workshop on Neural Networks, May

2002.

[77] Maryam S. Mirian, Majid Nili Ahmadabadi and Z. Navabi, "A New Task

Redistribution Method for Fault Clearing in Multi-Agent Systems", Proceeding of 2002

IEEE International Conference on Systems, MAN and CYBERNETICS, Yasmine

Hammamet – Tuniusia, October 2002

[78] P. A. Riahi, F. Karimi, F. Lombardi and Z. Navabi, "Using Verilog VPI

for Serial Fault Simulation in a Test Generation Environment," in Proc.

Digest of Papers, WRTLT, pp. 97-99, Nov. 2002, Guam, USA.

[79] Shahrzad Mirkhani, Meisam Lavasani and Z. Navabi, “Hierarchical Fault Simulation

Using Behavioral and Gate Level Hardware Models,” in Proc. Of IEEE Asian Test

Symposium, ATS’02, Nov. 2002, Guam, USA.

[80] F. Karimi and Z. Navabi, W. Meleis and F. Lombardi, "Data Compression for

System-on-Chip Testing Using ATE", IEEE International Symposium on Defect

and Fault Tolerance in VLSI Systems, Vancouver, Canada, November 6-8, 2002.

[81] Zohreh Karimi, Hamed Farshbaf, Elham Safi and Z. Navabi, “A Pluggable

Environment for Evaluation of RT Level Hardware Component Designs,” 2003

International Conference on Simulation and Multimedia in Engineering Education

(ICSEE'03), The Society for Modeling and Simulation International (SCS), January 19

- 23, 2003, Orlando, Florida USA.

[82] P. A. Riahi, N. Karimi, F. Lombardi and Z. Navabi, "A VPI-based IP Core

Serial Fault Simulation and Test Generation Methodology," Proceedings of The IEEE

12th North Atlantic Test Workshop (NATW'03 ), May 15-16, 2003, Montauk, New

York, USA.

[83] Naghmeh Karimi, Pedram Riyahi and Z. Navabi, “A Survey of Testability

Measurements at Various Abstraction Levels,” Proceedings of The IEEE 12th North

Atlantic Test Workshop (NATW'03 ), May 15-16, 2003, Montauk, New York, USA.

[84] Morteza Fayyazi, David Kaeli and Z. Navabi, "Dynamic Input Buffer Allocation For

Fault Tolerant Ethernet Packet Switching", Proceedings of The International

Conference of Parallel and Distributed Processing Techniques and Applications

(PDPTA'03), June 23-26 2003, Las Vegas, Nevada, USA

[85] Pedram A. Riahi, Fabrizio Lombardi and Z. Navabi, "Using Verilog VPI for Mixed

Level Serial Fault Simulation in a Test Generation Environment", Proceedings of The

International Conference on Embedded Systems and Applications (ESA '3), June 23-

26 2003, Las Vegas, Nevada, USA

[86] Shervin Sharifi, Mohammad Hosseinabadi, Pedram Riahi and Z. Navabi," Reducing

Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan

Architecture", Proceeding of The 18th IEEE International Symposium on DEFECT and

FAULT TOLERANCE in VLSI SYSTEMS, Boston, Massachusetts, Nov. 2003

[87] Elham Safi, Reihaneh Saberi, Saeed Shamshiri and Z. Navabi," A Genetic Testing

Framework for Self-Testing of Microprocessor Cores", Proceeding of 4th Workshop on

RTL and High Level Testing (WRTLT'03), Xi'an, China, Nov. 2003

[88] E. Atoofian, S. Hatami, M. Alisafaee, A. Afzali-Kusha and Z. Navabi ", A New Low-

Power Scan-Path Architecture", Proceeding of 4th Workshop on RTL and High Level

Testing (WRTLT'03), Xi'an, China, Nov. 2003

[89] Reihaneh Saberi, Elham Safi, Zohreh Karimi and Z. Navabi ", Controller Testing

Using Combination of GAs and Symbolic Methods", Proceeding of 4th Workshop on

RTL and High Level Testing (WRTLT'03), Xi'an, China, Nov. 2003

[90] Mohammad Hosseinabady, Shervin Sharifi and Z. Navabi, "A Novel Partition-based

Technique to Reduce Power, Time and Data Volume in Scan-based Test", Proceeding

of 4th Workshop on RTL and High Level Testing (WRTLT'03), Xi'an, China, Nov. 2003

[91] Pedram A. Riahi, Fabrizio Lombardi and Z. Navabi, "A VPI-based Combinational IP

Core Module-based Mixed Level Serial Fault Simulation and Test Generation

Methodology", Proceeding of 12th Asian Test Symposium (ATS 2003), Xi'an, China,

Nov. 2003

[92] Ehsan Atoofian and Z. Navabi, "A BIST Architecture for FPGA Look-up Table

Testing Reduces Reconfigurations", Proceeding of 12th Asian Test Symposium (ATS

2003), Xi'an, China, Nov. 2003

[93] Zohreh Karimi, Elham Safi, Maghsoud Abbaspour and Z. Navabi, "A Macro-Based

Instruction Level CPU Testing With an ADL”, Proceedings of the European Test

Workshop, ETW.

[94] Hadi Parandeh Afshar, Hamid Shojai and Z. Navabi, "A New Method for Checking

FSM Correctness (Simulation Replacement)" Int’l Symposium on Telecommunications

( IST2003 ), 16 -18 August, 2003 Isfahan-Iran

[95] Dara Rahmati, Hamidreza Ghasemi, Behnam Robatmili and Z. Navabi , "A Hybrid

Interpreted-Compiled Code VHDL Event Driven Simulator with Extensibility", Int’l

Symposium on Telecommunications ( IST2003 ), 16 -18 August, 2003 Isfahan-Iran

[96] Zohreh Karimi and Z. Navabi, "VHDL to SystemC Translation for Hardware-

Software Co-Simulation", Int’l Symposium on Telecommunications (IST2003 ), 16 -

18 August, 2003 Isfahan-Iran

[97] Mohammad R. Kakoee, Shervin Sharifi and Z. Navabi, "Generic Synthesis of Digital

Designs", Int’l Symposium on Telecommunications ( IST2003 ), 16 -18 August, 2003

Isfahan-Iran

[98] Behnam Robatmili, Hamidreza Ghasemi, Dara Rahmati and Z. Navabi, "A Scalable

Method for HDL Elaboration", Int’l Symposium on Telecommunications ( IST2003 ),

16 -18 August, 2003 Isfahan-Iran

[99] Pedram Riahi, Fabrizio Lombardi and Z. Navabi, “VPI-based IP Core Mixed Level

Serial Fault Simulation and Test Generation Methodology”, CCAD03

[100] Pejman Lotfi-kamran, Hamid Shojaei and Z. Navabi, "Property Intermediate

Representation with Extensibility", LATW 2004, Cartagena, Colombia, March 2004

[101] Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh,

Pejman Lotfi-Kamran, Mostafa Naderi and Z. Navabi, "Binary Taylor Diagrams

(BTD): An Efficient Way of Implementing Taylor Expansion Diagrams", NATW 2004,

The Inn at Essex, Essex Junction, VT, USA, May 2004

[102] Saeed Shamshiri, Hadi Esmaeilzadeh, Mohammad Ali Safaee, Pejman Lotfi-

Kamran and Z. Navabi, "Test Instruction Set (TIS): An Instruction Level CPU Core

Self-testing Method", ETS 2004, Congress Center, Ajaccio, Corsica, France, May 2004

[103] Saeed Shamshiri, Hadi Esmaeilzadeh and Z. Navabi, “Test Instruction Set (TIS)

for High Level Self-Testing of CPU Cores”, Asian Test Symposium (ATS’4), Nov. 15-

17 2004, Kenting, Taiwan.

[104] P. Lotfi-Kamran, M. Hosseinabady, H. Shojaei, M. Masoumi and Z. Navabi,

"TED+: a data structure for microprocessor verification", ASP-DAC Conference, Jan.

18-21, 2005, Shanghai, China.

[105] Sh. Sharifi, J. Jafari, M. Hosseinabady, A. Afzali-Kusha and Z. Navabi,

“Simultaneous Reduction of Dynamic and Static Power in Scan Structures”, DATE

2005, March 7-11, Munich, Germany.

[106] P. Lotfi-Kamran, H. Shojaei, H. Parandeh-Afshar, M. Naderi and Z. Navabi,

"Improving Logic-Level Representation of BMD/TED Diagrams", ICEE 2005, May

10-12, Zanjan, Iran

[107] Mostafa Naderi and Z. Navabi, "Property Based Design Testing", ICEE 2005, May

10-12, Zanjan, Iran

[108] M. Saneei, A. Afzali-Kusha and Z. Navabi, “Sign Bit Reduction Encoding for Low

Power Applications”, Design Automation Conference (DAC) 2005, , June 13-17 2005,

Anaheim, CA.

[109] Sh. Mirkhani, M. Lavasani and Z. Navabi, “Using RT Level Component

Descriptions for Single Stuck-At Fault Test Generation”, Computer Science and

Information Technologies (CSIT) 2005, pp. 491-497, 19-23 Sep. 2005, Armenia,

Yerevan,.

[110] N. Karimi, Sh. Mirkhani and Z. Navabi, “Making RT-Level Designs Reliable with

CERA”, Computer Science and Information Technologies (CSIT) 2005, pp. 498-505,

19-23 Sep. 2005, Armenia, Yerevan.

[111] M. Hosseinabady, P. Lotfi-Kamran, P. Riahi, F. Lombardi and Z. Navabi, “A Flow

Graph Technique for DFT Controller Modification”, SoC Conference, Sep. 25-28 2005.

[112] P. Riahi, F. Lombardi and Z. Navabi, “Simulating faults of combinational IP core-

based SOCs in a PLI environment”, IEEE International Symposium on Defect and Fault

Tolerance in VLSI Systems (DFT 2005), pp. 389 – 397, Oct. 3-5, 2005, Monterey,

USA.

[113] F. Fakhrieh, S. Shamshiri, A. Pedram, A. Sobhani and Z. Navabi, “Scan Chain

Bypass by Use of Skip Path”, The 17th International Conference on Microelectronics,

ICM 2005, Dec. 13-15 2005.

[114] M. Dehyadgari, M. Nickray, A Afzali-Kusha and Z. Navabi, “Evaluation of pseudo

adaptive XY routing using an object oriented model for NOC”, The 17th International

Conference on Microelectronics, ICM 2005, Dec. 13-15 2005.

[115] Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi and Z. Navabi, “ISC:

Reconfigurable Scan-Cell Architecture for Low Power Testing”, Asian Test

Symposium (ATS’5), pp. 236-241, Dec. 18-21, 2005, Calcutta, India.

[116] Shahrzad Mirkhani and Z. Navabi, “Enhancing Fault Simulation Performance by

Dynamic Fault Clustering”, Asian Test Symposium (ATS’5), pp. 278-283, Dec. 18-21,

2005, Calcutta, India.

[117] Mahnaz Sadoughi, Armin Alaghi and Z. Navabi, “An Optimized BIST

Architecture for FPGA Look-Up Table Testing”, IEEE Computer Society Annual

Symposium on ISVLSI 2006, pp. 420-421, March 2-3, 2006, Karlsruhe, Germany.

[118] Masood Dehyadgari, Mohsen Nickray, Ali Afzali-Kusha and Z. Navabi , “A New

Protocol Stack Model for Network on Chip”, IEEE Computer Society Annual

Symposium on ISVLSI 2006, pp. 440-441, March 2-3, 2006, Karlsruhe, Germany.

[119] M. Hosseinabady, A. Banaiyan, M. N. Bojnordi and Z. Navabi, “A Concurrent

Testing Method for NoC Switches”, DATE 2006 Conference, March 6-10, 2006,

Munich, Germany.

[120] H. Esmaeilzadeh, A. Moghimi, E. Ebrahimi, C. Lucas, M. Fakhraie and Z. Navabi,

“DCim++: a C++ library for object oriented hardware design and distributed

simulation”, ISCAS 2006 , May 21-24 , 2006, Greece.

[121] M. Saneei, A. Afzali-Kusha and Z. Navabi, “Low-power and low-latency cluster

topology for local traffic NoCs”, ISCAS 2006 , May 21-24 , 2006, Greece.

[122] A. Sobhani, M. Daneshtalab, M.H. Neishaburi, M.D. Mottaghi, A. Afzali-Kusha,

O. Fatemi and Z. Navabi, “Dynamic Routing Algorithm for Avoiding Hot Spots in On-

chip Networks”, Design & Test of Integrated Systems in Nanoscale Technology (DTIS

2006), Sep. 5-7, 2006, TUNIS, Tunisia.

[123] M. Daneshtalab, A. Sobhani, A. Afzali-Kusha, O. Fatemi and Z. Navabi, “NoC

Hot Spot Minimization Using AntNet Dynamic Routing Algorithm”, Application-

specific Systems, Architectures and Processors (ASAP’06),pp. 33-38, Sep. 11-13,

2006, Colorado, USA.

[124] Mohsen Saneei, Ali Afzali-Kusha and Z. Navabi, “A Mesochronous Technique for

Communication in Network on Chips”, International SoC Design Conference, COEX

Conference Center, pp. 119-122, October 26-27, 2006, Seoul, Korea.

[125] Rahebeh Niaraki, Sattar Mirzakuchaki, Michel Renovell and Z. Navabi, “The

Scalable and Reconfigurable DFT for Embedded A/MS Cores”, International SoC

Design Conference, COEX Conference Center, pp. 293-296, October 26-27, 2006,

Seoul, Korea.

[126] M. Riazati, S. Mohammadi and Z. Navabi, “Non-overlapping Set of Efficient

Assertions”, Norchip Conference, pp. 201-204, November 20-21, 2006, Linkoping,

Sweden.

[127] Naghmeh Karimi, Shahrzad Mirkhani and Z. Navabi, “ESTA: An Efficient Method

for Reliability Enhancement of RT-Level Designs”, Asian Test Symposium (ATS’6),

pp. 195-200, Nov. 20-23, 2006, Fukuoka, Japan.

[128] Armin Alaghi, Mahnaz Sadoughi and Z. Navabi, “An Optimum ORA BIST for

Multiple Fault FPGA Look-Up Table Testing”, Asian Test Symposium (ATS’6), pp.

293-298, Nov. 20-23, 2006, Fukuoka, Japan.

[129] M. Mottaghi, A. Naghilou, M. Daneshtalab, A Afzali-Kusha and Z. Navabi, “Hot

Block Ring Counter: A Low Power Synchronous Ring Counter”, The 18th International

Conference on Microelectronics, ICM 2006, Dec. 16-19 2006, Saudi Arabia.

[130] M. Mottaghi, M. Riazati and M. Daneshtalab and Z. Navabi, “Finding low activity

op-code sets using genetic computing”, The 18th International Conference on

Microelectronics, ICM 2006, Dec. 16-19 2006, Saudi Arabia.

[131] M. Saneei, A Afzali-Kusha and Z. Navabi, “Low-latency Multi-Level Mesh

Topology for NoCs”, The 18th International Conference on Microelectronics, ICM

2006, Dec. 16-19 2006, Saudi Arabia.

[132] M. Saneei, A Afzali-Kusha and Z. Navabi, “A Mesochronous Technique for

Communication in Network on Chips”, The 18th International Conference on

Microelectronics, ICM 2006, Dec. 16-19 2006, Saudi Arabia.

[133] M.H. Neishaburi, M.R. Kakoee, M. daneshtalab, S. safari and Z. Navabi, “A

HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating

System Services”, Design and Diagnostics of Electronic Circuits and Systems (DDECS

’07), April 11-13, 2007, Kraków, Poland.

[134] M. Hosseinabady, A. Dalirsani and Z. Navabi, “Using the Inter- and Intra-Switch

Regularity in NoC Switch Testing”, DATE’07 Conference, April 16-20, 2007, Nice,

France.

[135] M. Hosseinabady, M.H. Neishaburi, P. Lotfi-Kamran and Z. Navabi, “A UML

Based System Level Failure Rate Assessment Technique for SoC Designs”, VLSI Test

Symposium (VTS’07), May 6-10, 2007, Berkeley, California, USA.

[136] N. Honarmand, A. Shahabi, H. Sohofi, M. Abbaspour and Z. Navabi, “High Level

Synthesis of Degradable ASICs Using Virtual Binding”, VLSI Test Symposium

(VTS’07), May 6-10, 2007, Berkeley, California, USA.

[137] A. Shahabi, N. Honarmand and Z. Navabi, “Programmable Routing Tables for

Degradable Torus-Based Networks on Chips”, IEEE International Symposium on

Circuits and Systems (ISCAS 2007), May 27-30, Lousiana, USA.

[138] A. Shahabi, N. Honarmand and Z. Navabi, “Programmable Routing Tables for

Degradable Mesh-Based Networks on Chips”, ICEE Conference, May 15-17, 2007,

Tehran, Iran.

[139] Majid Nabi, Hamid Shojaei and Z. Navabi, “A New Coverage Metric in Formal

Verification of Digital Systems”, ICEE Conference, May 15-17, 2007, Tehran, Iran.

[140] A. Dalirsani, M. Hosseinabady and Z. Navabi, “An Analytical Model for

Reliability Evaluation of NoC Architectures”,

13th IEEE International On-Line Testing Symposium (IOLTS‘7), July 8-11, 2007,

Crete, Greece.

[141] M. Hosseinabady, M.H. Neishaburi, A. Benso, S. Carlo, P. Prinetto, G. Natale

and Z. Navabi, “Analysis of System-Failure Rate Caused by Soft-Errors using a UML-

Based Systematic Methodology in an SoC”, 13th IEEE International On-Line Testing

Symposium (IOLTS‘7), July 8-11, 2007, Crete, Greece.

[142] M.R. Kakoee, M.H. Neishaburi, M. daneshtalab, S. safari and Z. Navabi, “On-Chip

Verification of NoCs Using Assertion Processors”, 10th Euromicro Conference on

Digital System Design Architectures, Methods and Tools (DSD 2007). Aug. 29-31,

2007, Lubeck, Germany.

[143] M. Nabi, H. Shojaei, S. Mohammadi and Z. Navabi, “Assignment Coverage, A

Complementary Coverage Metric in Formal Verification”, Design & Technology of

Intgrated Systems (DTIS ’07), pp. 76-81, Sep. 2-5, 2007, Rabat, Morocco.

[144] M. R. Jamali, M. Valadbeigi, M. Dehyadgari, C. Lucas and Z. Navabi, “Toward

Embedded Emotionally Intelligent System”, East-West Design & Test Symposium

(EWDTS’07), pp. 51-56, Sep. 7-10, 2007, Armenia, Yerevan.

[145] Naghmeh Karimi and Z. Navabi, “DRA: A Dynamic Reconfiguration Method for

Error Recovery of RT Level Designs”, East-West Design & Test Symposium

(EWDTS’07), pp. 249-255, Sep. 7-10, 2007, Armenia, Yerevan.

[146] H. Alemzadeh, F. Refan, P. Prinetto and Z. Navabi, “High-Level Analysis for

Reconfiguration of a Fault Tolerant Mesh-based NoC Architecture Using Transaction

Level Modeling”, East-West Design & Test Symposium (EWDTS’07), pp. 256-261,

Sep. 7-10, 2007, Armenia, Yerevan.

[147] M. Sedghi, E. Koopahi , A. Alaghi and Z. Navabi, “An Exhaustive Test Strategy

Based on Flooding Routing for NoC Switch Testing”, East-West Design & Test

Symposium (EWDTS’07), pp. 262-267, Sep. 7-10, 2007, Armenia, Yerevan.

[148] P. Razaghi, Sh. Mirkhani and Z. Navabi, “Utilizing ESL Methodology: A Network

Processor Case Study”, East-West Design & Test Symposium (EWDTS’07), pp. 268-

274, Sep. 7-10, 2007, Armenia, Yerevan.

[149] N. Honarmand, H. Sohofi, M. Abbaspour and Z. Navabi, “Processor Description

in APDL for Design Space Exploration of Embedded Processors”, East-West Design

& Test Symposium (EWDTS’07), pp. 405-410, Sep. 7-10, 2007, Armenia, Yerevan.

[150] N. Honarmand, A. Shahabi and Z. Navabi, “A Heuristic Search Algorithm for Re-

routing of On-Chip Networks in the Presence of Faulty Links and Switches”, East-West

Design & Test Symposium (EWDTS’07), pp. 411-416, Sep. 7-10, 2007, Armenia,

Yerevan.

[151] Atefeh Dalirsani and Z. Navabi, “Testing of Routers in NoC Mesh Architecture

Using Router’s Functionality”, East-West Design & Test Symposium (EWDTS’07),

pp. 570-575, Sep. 7-10, 2007, Armenia, Yerevan.

[152] S. Malekshahi, R. Saberi and Z. Navabi, “Synthesizable and Improved

Performance System Level Design of a Sequential C++ Code Using a Rule Based

Technique”, East-West Design & Test Symposium (EWDTS’07), pp. 629-634, Sep. 7-

10, 2007, Armenia, Yerevan.

[153] N. Honarmand, H. Sohofi, M. Abbaspour and Z. Navabi, “APDL: A Processor

Description Language for Design Space Exploration of Embedded Processor”,

FORUM on Specification & Design Languages with Industrial Workshops (FDL’07),

Sep. 18-20 2007, Barcelona, Spain.

[154] P. Razaghi, Sh. Mirkhani, S. Amanollahi, F. Kordi and Z. Navabi, “A Configurable

TLM Model of Avalon Bus for an ESL Design Library”, FORUM on Specification &

Design Languages with Industrial Workshops (FDL’07), Sep. 18-20 2007, Barcelona,

Spain.

[155] A. Alaghi, N. Karimi, M. Sedghi and Z. Navabi, “Online NoC Switch Fault

Detection and Diagnosis Using a High Level Fault Model”, 22nd IEEE International

Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2007, Sep. 26-28,

2007, Rome, Italy.

[156] M. Nabi, H. Shojaei, S. Mohammadi and Z. Navabi, “Optimized Assignment

Coverage Computation in Formal Verification of Digital Systems”, Asian Test

Symposium (ATS’07), pp. 172-177, Oct. 8-11, 2007, Beijing, China.

[157] M. Sedghi, A. Alaghi, E. Koopahi and Z. Navabi, “An HDL-Based Platform for

High Level NoC Switch Testing”, Asian Test Symposium (ATS’07), pp. 453-458, Oct.

8-11, 2007, Beijing, China.

[158] M. Sedghi, E. Koopahi, A. Alaghi, M. Fathy and Z. Navabi, “An NoC Test Strategy

Based on Flooding with Power, Test Time and Coverage Considerations”, 21st

International Conference on VLSI Design 2008, pp. 409-414, Jan. 4-8 2008,

Heyderabad, India.

[159] P. Lotfi-Kamran, M. Massoumi, M. Mirzaei and Z. Navabi, “Enhanced TED: A

New Data Structure for RTL Verification”, 21st International Conference on VLSI

Design 2008, pp. 481-486, Jan. 4-8 2008, Heyderabad, India.

[160] P. Lotfi-Kamran, A. M. Rahmani, A. A. Salehpour, A. Afzali-Kusha and Z.

Navabi, “Stall Power Reduction in Pipelined Architecture Processors”, 21st

International Conference on VLSI Design 2008, pp. 541-546, Jan. 4-8 2008,

Heyderabad, India.

[161] P. Lotfi-Kamran, M. Daneshtalab. C. Lucas and Z. Navabi, “BARP- A Dynamic

Routing Protocol for Balanced Distribution of Traffic in NoCs”, DATE 2008

Conference, March 10-14, 2008, Munich, Germany.

[162] M. Zolfy, Z.D. Kozekanani and Z. Navabi, “Adaptation of High Level Behavioral

Models for Stuck-at Coverage Analysis”, DTIS 2008 Conference, March 25-27, 2008,

Tozeur, Tunisia.

[163] N. karimi, S. Aminzadeh, S. Safari and Z. Navabi, “A Novel GA-Based High-

Level Synthesis Technique to Enhance RT-Level Concurrent Testing”, On-Line

Testing Symposium, July 6-9, 2008, Rhodes, Greece.

[164] F. Refan, H. Alemzadeh, S. Safari, P. Prinetto and Z. Navabi, “Reliability in

Application Specific Mesh-based NoC Architectures”, On-Line Testing Symposium,

July 6-9, 2008, Rhodes, Greece.

[165] F. Refan, P. Kabiri, H. Alemzadeh, P. Prinetto and Z. Navabi, “Application

Specific Configuration of a Fault-Tolerant NoC Architecture”, Baltic Electronics

Conference, Oct. 6-8, 2008, Tallinn, Stonia.

[166] A. Alaghi, M. Sedghi, N. Karimi, M. Fathi and Z. Navabi, “Reliable NoC

Architecture Utilizing a Robust Rerouting Algorithm”, EWDTS Conference, Oct. 9-12,

2008, Lviv, Ukrain.

[167] H. Alemzadeh, S. Aminzadeh, R. Saberi and Z. Navabi, “Code Optimization for

Enhancing SystemC Simulation Time”, EWDTS Conference, Oct. 9-12, 2008, Lviv,

Ukrain.

[168] N. Hatami and Z. Navabi, “An advanced Method for Synthesizing TLM2-based

Interfaces”, EWDTS Conference, Oct. 9-12, 2008, Lviv, Ukrain.

[169] S. malekshahi, M. Sedghi and Z. Navabi, “Automating Hardware/Software

Partitioning Using Dependency Graph”, EWDTS Conference, Oct. 9-12, 2008, Lviv,

Ukrain.

[170] S. Abolmaali, P. razaghi and Z. Navabi, “TUFFAN: A TLM Framework for Fast

Architecture Exploration of Digital Systems”, EWDTS Conference, Oct. 9-12, 2008,

Lviv, Ukrain.

[171] H. Alemzadeh, M. Cimei, P. Prinetto and Z. Navabi, “Facilitating Testability of

TLM FIFO: SystemC Implementations”, EWDTS Conference, Oct. 9-12, 2008, Lviv,

Ukrain.

[172] F. Refan, P. Prinetto and Z. Navabi, “An IEEE 1500 Compatible Wrapper

Architecture for Testing Cores at Transaction Level”, EWDTS Conference, Oct. 9-12,

2008, Lviv, Ukrain.

[173] N. Mahani, P. Mokri and Z. Navabi, “System Level Hardware Design and

Simulation with System Ada”, EWDTS Conference, Oct. 9-12, 2008, Lviv, Ukrain.

[174] H. Alemzadeh, S. Di Carlo, F. Refan, P. Prinetto and Z. Navabi, “Plug & Test at

System Level via Testable TLM Primitives”, ITC Conference, Oct. 26-31, 2008, Santa

Clara, California, USA.

[175] A. Alaghi, M. Sedghi, N. Karimi and Z. Navabi, “NoC Reconfiguration for

Utilizing the Largest Fault-free Connected Sub-structure”, ITC Conference, Oct. 26-

31, 2008, Santa Clara, California, USA.

[176] H. Alemzadeh, S. Di Carlo, A. Scionti, P. Prinetto and Z. Navabi, “Functional

Testing Approaches for “BIFST-able” tlm_fifo”, HLDVT Conference, Nov. 19-21,

2008, Nevada, USA.

[177] N. Nemati, P. Prinetto and Z. Navabi, “Design Experience in TL Modeling”, 4th

International Conference on Design & Technology of Integrated Systems in Nanoscal

Era, 2009. DTIS '09, April 6-9, 2009, Cairo, Egypt.

[178] N. Nemati, A. Ghofrani, P. Prinetto and Z. Navabi, “TLM 2.0 Simple Sockets

Synthesis to RTL”, 4th International Conference on Design & Technology of Integrated

Systems in Nanoscal Era, 2009. DTIS '09, April 6-9, 2009, Cairo, Egypt.

[179] M. H. Haghbayan, A. Yazdanpanah, S. Keramati, R. Saeedi and Z. Navabi,

“Generating Test Patterns for Sequential Circuits Using Random Patterns by PLI

Functions”, IEEE East-West Design & Test Symposium (EWDTS’09) Sep. 18-21,

2009, Moscow, Russia.

[180] Elnaz Koopahi and Z. Navabi, “A New Online BIST Method for NoC

Interconnects”, IEEE East-West Design & Test Symposium (EWDTS’09) Sep. 18-21,

2009, Moscow, Russia.

[181] M. H. Sargolzaei, M. Semsarzadeh, M. R. Hashemi and Z. Navabi, “Low Cost

Error Tolerant Motion Estimation for H.264/AVC Standard”, IEEE East-West Design

& Test Symposium (EWDTS’09) Sep. 18-21, 2009, Moscow, Russia.

[182] M. S. Jahangiry, S. Keramati and Z. Navabi, “Parallel Fault Simulation Using

Verilog PLI”, IEEE East-West Design & Test Symposium (EWDTS’09) Sep. 18-21,

2009, Moscow, Russia.

[183] M. H. Haghbayan and Z. Navabi, “Architecture Design and Technical

Methodology for Bus Testing”, IEEE East-West Design & Test Symposium

(EWDTS’09) Sep. 18-21, 2009, Moscow, Russia.

[184] A. A. Ghofrani, Fatemeh Javaheri and Z. Navabi “Assertion Based Verification in

TLM”, IEEE East-West Design & Test Symposium (EWDTS’09) Sep. 18-21, 2009,

Moscow, Russia.

[185] M. Hashemi, M. Sedghi, M. Analoui and Z. Navabi, “Design Experience with

TLM-2.0 Standard: A Case Study of the IP Lookup LC-trie Application of Network

Processor”, IEEE East-West Design & Test Symposium (EWDTS’09) Sep. 18-21,

2009, Moscow, Russia.

[186] M. Zolfy, M. Hashemi, M. Sedghi, Z. Koozekanani and Z. Navabi, “Test Strategy

in OSCI TLM-2.0”, IEEE East-West Design & Test Symposium (EWDTS’09) Sep.

18-21, 2009, Moscow, Russia.

[187] N. Nemati, M. Namaki and Z. Navabi, “A Mixed HDL/PLI Test Package”, IEEE

East-West Design & Test Symposium (EWDTS’09) Sep. 18-21, 2009, Moscow,

Russia.

[188] N. Nemati, A. H. Simjour, A. A. Ghofrani and Z. Navabi, “Optimizing Parametric

BIST Using Bio-inspired Computing Algorithms”, 24th IEEE International Symposium

on Defect and Fault Tolerance in VLSI System 2009 (DFT ’09) , Oct. 7-9 2009,

Chicago, USA.

[189] S. B. Hosseini, A. Shahabi, H. Sohofi and Z. Navabi, “A reconfigurable online

BIST for combinational hardware using digital neural networks”, European Test

Symposium (ETS) 2010, May 24-28, 2010, Prague, Czech Republic.

[190] S. B. Hosseini, A. Shahabi, H. Sohofi and Z. Navabi, “A partitioning approach to

improve reconfigurable neuron-inspired online BIST”, International On-Line Testing

Symposium (IOLTS), July 5-7, 2010, Corfu, Greece.

[191] M. Zolfy, Z.D. Kozekanani, L. Mohammadkhani and Z. Navabi, “Investigation of

OSCI TLM-2.0 Employment in Grid Computing Simulation”, Second International

Conference on Advances is System Testing and Validation Lifestyle, Aug. 22-27, 2010,

Nice, France.

[192] F. Javaheri and Z. Navabi, “ESL Design Methodology for Architecture

Exploration”, IEEE East-West Design & Test Symposium (EWDTS’10) Sep. 17-20,

2010, St. Petersburg, Russia.

[193] A. A. Ghofrani, Sh. Abolmaali, Z. Najafi Haghi and Z. Navabi, “A TLM 2.0

Assertion Library with Centralized Monitoring Approach”, IEEE East-West Design &

Test Symposium (EWDTS’10) Sep. 17-20, 2010, St. Petersburg, Russia.

[194] A. Lotfi, P. Kabiri and Z. Navabi, “Configurable Architecture for Memory BIST”,

IEEE East-West Design & Test Symposium (EWDTS’10) Sep. 17-20, 2010, St.

Petersburg, Russia.

[195] A. Kamran, N. Nemati, S. Sadeghi Kohan and Z. Navabi, “Virtual Tester

Development Using HDL/PLI”, IEEE East-West Design & Test Symposium

(EWDTS’10) Sep. 17-20, 2010, St. Petersburg, Russia.

[196] A. Kamran, M. S. Jahangiri and Z. Navabi, “Merit Based Directed Random Test

Generation (MDRTG) Scheme for Combinational Circuits”, IEEE East-West Design

& Test Symposium (EWDTS’10) Sep. 17-20, 2010, St. Petersburg, Russia.

[197] N. Shakeri, N. Nemati, M. Nili Ahmadabadi and Z. Navabi, “Near Optimal

Machine Learning Based Random Test Generation”, IEEE East-West Design & Test

Symposium (EWDTS’10) Sep. 17-20, 2010, St. Petersburg, Russia.

[198] A. A. Ghofrani, F. javaheri, S. Safari and Z. Navabi, “Automatic Selection of

efficient Observability points in Combinational Gate Level Circuits using particle

swarm optimization”, International Symposium on System on Chip (SoC), Sep. 29-30,

2010, Tampere, Finland.

[199] Sara Keramati and Z. Navabi, “Using Context Based Methods for Test Data

Compression”, International Test Conference, ITC 2010, Oct. 31- Nov. 5, 2010, Texas-

Austin, USA.

[200] M.H. Haghbayan, S. Keramati, F. Javaheri and Z. Navabi, “Test Pattern Selection

and Compaction for Sequential Circuits in an HDL Environment”, Asian Test

Symposium 2010 (ATS 2010) Dec. 1-4, 2010, Shanghai, China.

[201] N. Nemati, E. Mahmoudi, A.H. Simjour and Z. Navabi, “A Simulation-Based

Feature Selection Approach for Test Point Selection in HDL Models”, IEEE 11th

Workshop on RTL and High Level Testing (WRTLT’10) Dec. 5-6, 2010, Shanghai,

China.

[202] A.A. Ghofrani, F. Javaheri, H. Noori and Z. Navabi, “Transaction Level Formal

Verification Using Timed Automata”, IEEE 11th Workshop on RTL and High Level

Testing (WRTLT’10) Dec. 5-6, 2010, Shanghai, China.

[203] N. Karimi, S. Sadeghi and Z. Navabi, “Network-on-Chip Concurrent Error

Recovery Using Functional Switch Faults”, IEEE 11th Workshop on RTL and High

Level Testing (WRTLT’10) Dec. 5-6, 2010, Shanghai, China.

[204] N. Nemati, A. Kamran, M.H. Sargolzaie, M.H. Haghbayan and Z. Navabi, “An

Optimal HDL-based Approach for Mixed-level Hierarchical Fault Simulation”, IEEE

11th Workshop on RTL and High Level Testing (WRTLT’10) Dec. 5-6, 2010,

Shanghai, China.

[205] S. Sadeghi, F. Javaheri, S. Mahmoodi and Z. Navabi, “Multi Level Test Package

”, IEEE 11th Workshop on RTL and High Level Testing (WRTLT’10) Dec. 5-6, 2010,

Shanghai, China.

[206] A. Lotfi, P. Kabiri and Z. Navabi, “Configurable Architecture for Memory BIST”,

IEEE East-West Design & Test Symposium (EWDTS’11) Sep. 9-12, 2011, Sevastopol,

Ukrain.

[207] Nastaran Nemati and Zainalabedin Navabi, “Adaptation of Standard RT Level

BIST Architectures for System Level Communication Testing”, Asian Test

Symposium 2011 (ATS 2011) Nov. 20-23, 2011, New Delhi, India.

[208] F. Javaheri, M. Namaki, P. kamranfar and Z. Navabi, “Mapping Transaction Level

Faults to Stuck-at Faults in Communication Hardware”, Asian Test Symposium 2011

(ATS 2011) Nov. 20-23, 2011, New Delhi, India.

[209] B. Khodabandehlou, A. Hosseini, S. Taheri, M.H. Haghbayan, M.R. Babaei and Z.

Navabi, “Online Test Macro Scheduling And Assignment In MPSoC Design”, Asian

Test Symposium 2011 (ATS 2011) Nov. 20-23, 2011, New Delhi, India.

[210] S. Sadeghi-Kohan, Gh. Vazhbakht, P. Kabiri and Z. Navabi, “Extending BS-

1149.1 for Interconnect Online BIST”, WRTLT 2011, Nov. 25-26, 2011, Jaipur, India.

[211] A. Shahabi, R. Nakhjavani, S. Safari and Z. Navabi, “Gracefully Degradable 3D

On-Chip Networks Using an Optimized Re-routing Mechanism”, WRTLT 2011, Nov.

25-26, 2011, Jaipur, India.

[212] Parisa Sha`afi Kabiri and Zainalabedin Navabi, “Hierarchical Instruction Level

Self Testing of Embedded Processor Cores”, WRTLT 2011, Nov. 25-26, 2011, Jaipur,

India.

[213] R. Nakhjavani , A. Shahabi, S. Safari and Z. Navabi, “A Novel Graceful

Degradable Routing Algorithm for 3D On-Chip Networks”, INA-OCMC 2012 , Jan.

25, 2012, Paris, France.

[214] M. H. Haghbayan, S. Safari and Z. Navabi, “Power Constraint Testing for Multi-

Clock Domain SoCs Using Concurrent Hybrid BIST”, DDECS 2012 , April 19-21,

2012, Tallinn, Estonia.

[215] Parisa Kabiri and Z. Navabi, “Effective RT-Level Software-Based Self-Testing of

Embedded Processor Cores”, DDECS 2012 , April 19-21, 2012, Tallinn, Estonia.

[216] M. R. Najafi, S. Ghandali and Z. Navabi, “Soft-Error-Immune Communication

Network using Unbalanced Protection Selection”, AISP & CADS 2012 , May 2-3,

2012, Shiraz, Iran.

[217] E. Sadroddini, M. R. Najafi, M. fathi and Z. Navabi, “BILBO-friendly Hybrid

BIST Architecture with Asymmetric Polynomial Reseeding”, AISP & CADS 2012 ,

May 2-3, 2012, Shiraz, Iran.

[218] Fatemeh Javaheri and Zainalabedin Navabi, “Taking Electronic Design from RTL

to ESL”, European Workshop on Microelectronics Education 2012 , May 9-11 2012,

Grenoble, France.

[219] Nastaran Nemati and Zainalabedin Navabi, “HDLs from Test Education

Perspective”, European Workshop on Microelectronics Education 2012 , May 9-11

2012, Grenoble, France

[220] Z. Najafi Haghi, M. Mohammadi, B. Foruzandeh and Z. Navabi, “Optimization

Considerations in QCA Designs”, IEEE East-West Design & Test Symposium

(EWDTS’12), Sep. 14-17, 2012, Karkov, Ukraine.

[221] E. Sadroddini, Gh. Rahimi, P. Forutan, M. Fathi and Z. Navabi, “An Improved

Scheme for Pre-computed Patterns in Core-based SoC Architecture”, IEEE East-West

Design & Test Symposium (EWDTS’12), Sep. 14-17, 2012, Karkov, Ukraine

[222] S. Sadeghi-Kohan, Sh. Keshavarz, F. Zokaei, F. Farahmandi and Z. Navabi, “A

New Structure for Interconnect Offline Testing”, IEEE East-West Design & Test

Symposium (EWDTS’12), Sep. 14-17, 2012, Karkov, Ukraine

[223] A. Kamran, V. Janfaza and Z. Navabi, “Extracting Complete Set of Equations to

Analyze VHDL-AMS Descriptions”, IEEE East-West Design & Test Symposium

(EWDTS’12), Sep. 14-17, 2012, Karkov, Ukraine

[224] S. Ghandali, B. Alizadeh, M. Fujita and Z. Navabi, “Polynomial Datapath

Synthesis and Optimization Based on Vanishing Polynomial over Z(2m and Algebraic

Techniques”, International Conference on Formal Methods and Models for Co-design,

Sep. 16-17, 2012, Arlington, USA

[225] S. Sadeghi-Kohan, M. Namaki, F. Javaheri and Z. Navabi, “BS 1149.1 Extensions

for an Online Interconnect Fault Detection and Recovery”, International Test

Conference (ITC 2012), Nov. 6-8, 2012, California, USA

[226] P. Behnam, B. Alizadeh, M. Fujita and Z. Navabi, “Mutation Based Debugging

Technique with Auto-Correction Mechanism for RTL Designs”, IEEE International

Workshop on Silicon Debug and Diagnosis, Nov. 8-9, 2012, California, USA

[227] H. Sabaghiyan, M. Namaki, and Z. Navabi, “A Probabilistic and Constraint Based

Approach for Low Power Test Generation”, Asian Test Symposium (ATS 2012) Nov.

19-22, 2012, Niigata, Japan.

[228] S. Sadeghi-Kohan, Sh. Keshavarz and Z. Navabi, “An Online Method for Serial

Interconnects Testing”, The Thirteenth Workshop on RTL and High Level Testing

(WRTLT’12), Nov. 22-23, 2012, Niigata, Japan.

[229] P. Behnam, H. Sabaghian, B. Alizadeh, K. Mohajerani and Z. Navabi, “A

Probabilistic Approach for Counterexample Generation to Aid Design Debugging”,

IEEE East-West Design & Test Symposium (EWDTS’13), Sep. 27-30, 2013, Rostov-

on-Don, Russia

[230] A. Kamran and Z. Navabi, “Online Periodic Test Mechanism for Homogeneous

Many-core Processors”, 21st IFIP/IEEE International Conference on Very Large Scale

Integration (VLSI-SoC), Oct. 6-9, 2013, Istanbul, Turkey

[231] P. Kamranfar, S. A. Shahabi, Gh. Vazhbakht and Z. Navabi, “Configurable

Systolic Matrix Multiplication”, 27th International Conference on VLSI Design & 13th

International Conference on Embedded Systems , Page(s): 336-341, Jan. 5-10, 2014,

Mumbai, India.

[232] S. Ghandali, B. Alizadeh, M. Fujita and Z. Navabi, “RTL Datapath Optimization

Using System-Level Transformations”, 15th International Symposium on Quality

Electronic Design (ISQED), Page(s): 309-316, March 3-5, 2014, Santa Clara, USA

[233] H. Sohofi and Z. Navabi, “Assertion-Based Verification for System-Level

Designs”, 15th International Symposium on Quality Electronic Design (ISQED),

Page(s): 582-588, March 3-5, 2014, Santa Clara, USA

[234] S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita and Z. Navabi, “Improving

polynomial datapath debugging with HEDs”, 19th IEEE European Test Symposium

(ETS), May 26-30, 2014, Paderborn, Germany

[235] P. Behnam, B. Alizadeh and Z. Navabi, “Automatic Correction of Certain Design

Errors Using Mutation Technique”, 19th IEEE European Test Symposium (ETS), May

26-30, 2014, Paderborn, Germany

[236] M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi and Z. Navabi, “An Off-line

MDSI Interconnects BIST Incorporated in BS 1149.1”, 19th IEEE European Test

Symposium (ETS), May 26-30, 2014, Paderborn, Germany

[237] A. Kamran and Z. Navabi, “Homogeneous Many-core Processor System Test

Distribution and Execution Mechanism”, 19th IEEE European Test Symposium (ETS),

May 26-30, 2014, Paderborn, Germany

[238] N. Farajipour and Z. Navabi, “Back-annotation of Gate-level Power Properties into

System Level Descriptions” , 12th IEEE International New Circuits and Systems

Conference (NEWCAS 2014), June 22-25, 2014, Trois-Rivières, Canada

[239] F. Farahmandi, B. Alizadeh and Z. Navabi, “Effective Combination of Algebraic

Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits”,

IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 9-11, 2014,

Tampa, Florida, USA

[240] P. Foroutan, M. Kamal and Z. Navabi, “A Heuristic Path Selection Method for

Small Delay Defects Test”, IEEE International Symposium on Defect and Fault

Tolerance in VLSI System 2014 (DFT 2014) , Oct. 1-3 2014, Amesterdam, Netherland.

[241] S. Keshavarz, A. Nekooei and Z. Navabi, “Preemptive multi-bit IJTAG testing

with reconfigurable infrastructure”, IEEE International Symposium on Defect and

Fault Tolerance in VLSI System 2014 (DFT 2014) , Oct. 1-3 2014, Amesterdam,

Netherland.

[242] S. Ghandali and Z. Navabi, “Low Power Scheduling in High-level Synthesis using

Dual-Vth Library”, 16th International Symposium on Quality Electronic Design

(ISQED), March 2-4, 2015, Santa Clara, USA

[243] M. H. Haghbayan, A.M. Rahmani, M. Fattah, P. Liljeberg, J. Plosila, H. Tenhunen

and Z. Navabi, “Power-Aware Online Testing of Manycore Systems in the Dark Silicon

Era”, Design Automation & Test in Europe (DATE), March 9-13 2015, Gernoble,

France

[244] R. Jafari, E. Zahraei-Salehi and Z. Navabi, “Utilizing NOPs for Online

Deterministic Testing of Simple Processing Cores”, Design and Technology of

Integrated Systems Conference (DTIS2015), April 21-23, 2015, Naples, Italy,

[245] A. R. Nekooei and Z. Navabi, “Multi-Valued Logic Test Access Mechanism for

Test Time and Power Reduction”, Design and Technology of Integrated Systems

Conference (DTIS2015), April 21-23, 2015, Naples, Italy

[246] S. Sadeghi, M. Kamal, J. McNeil, P. Prinetto and Z. Navabi, “Online Self

Adjusting Progressive Age Monitoring of Timing Variations”, Design and Technology

of Integrated Systems Conference (DTIS2015), April 21-23, 2015, Naples, Italy

[247] S. Sadeghi, A. Kamran, F. Forooghifar and Z. Navabi, “Aging in Digital Circuits

and Age Monitoring: Object-Oriented Modeling and Evaluation”, Design and

Technology of Integrated Systems Conference (DTIS2015), April 21-23, 2015, Naples,

Italy

[248] M. Goli, A. Ghasemazar and Z. Navabi, “Application-Specific Power-Aware

Mapping for Reconfigurable NoC Architectures”, Design and Technology of Integrated

Systems Conference (DTIS2015), April 21-23, 2015, Naples, Italy

[249] F. Refan, B. Alizadeh and Z. Navabi, “Signature Oriented Model Pruning to

Facilitate Multi-Threaded Processors Debugging”, IEEE VLSI Test Symposium (VTS

2015), April 27-29, 2015, California, USA

[250] M. Ebrahimi, Z. Ghaderi, E. Bozorgzadeh Z. Navabi, “Path Selection and Sensor

Insertion Flow for Age Monitoring in FPGAs”, Design Automation & Test in Europe

(DATE), March 14-18 2016, Dresden, Germany

[251] M. Soltani, M. Ebrahimi and Z. Navabi, “Prolonging Lifetime of Non-volatile Last

Level Caches with Cluster Mapping”, GLSIVLSI 2016, May 18-20 2016, Boston, USA

FULL TERM Hardware Design and Test HDL COURSES:

• University of Illinois at Chicago; ECE 597; “Methodologies for Design and Electonic

System Level”, Online offering, Spring 2012 to present.

• Worcester Polytechnic Institute; ECE 579T; "Digital Design Test and Design for

Testability", Online offering, Summer 2010 to present.

• Worcester Polytechnic Institute; ECE 574; "Digital Design and Synthesis with

Verilog", Online offering, Spring 2008 to present.

• Worcester Polytechnic Institute; ECE 574; "Digital Design and Synthesis with

Verilog", Online offering, Spring 2008 to present.

• Northeastern University; Electrical and Computer Engineering Department; ECE

532; "Design of Embedded Systems", 2007.

• Northeastern University; Electrical and Computer Engineering Department; ECE

3401 equivalent to National Technological University DS 765-F; "Digital System

Design with Hardware Description Languages", 1990 to 2007.

• Northeastern University; Electrical and Computer Engineering Department; ECE

3407 equivalent to National Technological University DS 766-F; " Digital System

Design and Interfacing with Verilog", 1998 to 2006.

BROADCAST AND REGULAR SHORT COURSES:

• VHDL: The Language, Top-Down Design and Synthesis (Series)

Elements of VHDL for Description of Digital Systems

Advanced VHDL: Top-Down Design Methodologies

Synthesis of Digital Systems with VHDL

• Verilog: The Language, System Design and Synthesis (Series)

Verilog for Design and Simulation of Digital Systems

Synthesis of Digital Systems with Verilog

• Practical VHDL for Simulation and Synthesis (Series)

VHDL Design and Simulation

VHDL Advanced Topics and Synthesis

• Practical Verilog for Simulation and Synthesis (Series)

Verilog Design and Simulation

Verilog Advanced Topics and Synthesis

ON-SITE HDL COURSES:

• RTL Design and Test; PhD course, TTU, Tallinn Estonia; 2014.

• ESL Methodologies; PhD course, TTU, Tallinn Estonia; 2012.

• Verilog Design and Synthesis; P&E Micro, 2007

• Verilog Elements of System Design; Intel, 2006

• VHDL Simulation and Synthesis; OpenCell, 2006

• VHDL for Design and Simulation; Teradyne, 1999-2003

• VHDL and Verilog Trainings, Aldec, 1997-2003

• VHDL Simulation, Synthesis and Testbench; Unisys, 2002

• Verilog Simulation, Synthesis and Testbench; Unisys, 2001

• VHDL for Synthesis; Teradyne, 2000

• Hardware Description in VHDL; Innoveda, 1994-1996

• VHDL for Design, Simulation and Synthesis; GTE, 1995

• VHDL for CPU Design; Hughes Networks, 1994

• VITAL Standard for Timing; Teradyne, 1994

• The complete VHDL Language; Okura (Japan), 1994

PRESENTATIONS:

[1] "Impact of VHDL on Teaching of Digital Systems," VHDL Methods Workshop, June

1989, Charlottesville, Virginia.

[2] "Introduction to VHDL," A Three Day Short Course at the Massachusetts

Microelectronics Center, September 1989.

[3] "Design of Digital Electronics Systems With VHDL," A One Day Short Course at

Johns Hopkins University, Sponsored by IEEE and IEEE Computer Society, October

1989.

[4] "Synthesis Subsets of VHDL," Fall 1989 VHDL Users' Group Meeting, Rodondo

Beach, California, October 1989.

[5] "Hardware Generation From a Synthesis Subset of VHDL," Spring 1990 VHDL

Users' Group Meeting, Boston, Massachusetts, April 1990.

[6] "Design of Digital Electronics Systems With VHDL,"A Four Day Short Course at

the Massachusetts Microelectronics Center, September 1990.

[7] "VHDL Description Style for CPU-Like Architectures," VHDL Methods Workshop,

June 1990, Charlottesville, Virginia.

[8] "Behavioral State Machine Description For Synthesis," Fall 1990 VHDL Users'

Group Meeting, Oakland, California, October 1990.

[9] "Micro Introduction to VHDL," Invited Speaker for the IEEE Sponsored Lecture

Series on VHDL, Boston, MA, March 1990.

[10] "Modeling Microprocessors with VHDL," Invited Speaker for the IEEE Sponsored

Lecture Series on VHDL, Boston, MA, March 1990.

[11] "Analysis and Modeling of Hardware with VHDL," Presented a 3-Day short course

for the Hughes Network Systems, Maryland USA, September 1992.

[12] "Analysis and Modeling of Hardware with VHDL," Presented a 3-Day short course

for the Hughes Network Systems, San Diago, CA, USA, January 1993.

[13] "Advanced VHDL for Hardware Design and Modeling," Presented A 3-Day short

course for the Okura Company, Tokyo, Japan October 1993.

[14] “Introduction to VHDL,” Presented a tutorial in conjunction with ICEHDL

Conference, Phoenix, Az USA, 1993.

[15] “Analysis and Design of Digital Systems with VHDL,” Presented a two-month

course at Teradyne, Boston, MA USA, June-July 1994.

[16] “Using VHDL in Digital System Test,” Presented a tutorial in conjunction with VIUF

Conference, 1994.

[17] “VITAL: Standard for Model Development and Timing Backannotation,” Presented

a 3-day short course at Teradyne, Boston, MA USA, November 1994.

[18] “Digital System Synthesis With VHDL,” Presented a one-month course at Teradyne,

Boston, MA USA, June-July 1995.

[19] “VHDL Modeling,” Presented a 3-day short course at Viewlogic System Inc.,

Marlboro, MA USA, 1996.

[20] “Innovative Applications of VHDL Modeling Capabilities,” Presented a tutorial in

conjunction with fall 1996 VIUF Conference, South Carolina, USA, 1996.

[21] “Influence of VHDL and Other HDLs on Digital System Design Methodologies,”

Invited KeyNote Speaker, CSICC Conference, Tehran, Iran, 1996.

[22] “VHDL Modeling for Test Applications,” Invited by Technical University of

Munich, Germany, July 1996.

[23] “Advanced VHDL Modeling,” Invited by Technical University of Munich, Germany,

July 1996.

PROFESSIONAL ACTIVITIES (Updated 1997):

Session Chairman for: Eight Biennial University/Government/Industry

Microelectronics Symposium, June 1989, Westborough, Massachusetts, USA.

Conference Co-Chairman for: Spring 1990 VHDL Users' Group Meeting, April

1990, Boston, Massachusetts.

Session Chairman for: The International Conference on Computing and

Information (ICCI'90), May 23-26 1990, Niagara Falls, Canada.

Session Chairman for: The 1990 IASTED International Conference on Control and

Modeling (ICCM'90), July 17-20 1990, Tehran, Iran.

Program Committee Member for: 1992 International Conference on Simulation in

Engineering Education, January 20-22 1992, Newport Beach, California.

Reviewer for several conferences and journals, including the CHDL conference,

UGIM conference, ACM/IEEE Applied Computing Symposium, and the

EUROMICRO journal, VIUF.

Member of Design Automation Standards Subcommittee (DASS) of IEEE.

Involved in Setting Standards for the 1998 revision of VHDL. Also working on

switch level and timing standards.

Program Committee Member for: 1994 International Conference on Simulation in

Engineering Education, January 20-22 1994, Phoenix, Arizona.

Program Committee Member for: The Spring 1994, VIUF Conference, May 1994,

San Jose California.

Editorial Board for: Journal of Hardware Languages and Modeling.

Chairman of the Test Committee of DASS of IEEE. Involved in setting standards

for hardware testing from VHDL; two year term, started May 1994.

Board Member of VHDL International (VI), responsible for setting policies

regarding the VHDL Language, two year term, started February 1997.

EDUCATIONAL ACTIVITIES (Updated 1991):

Massachusetts Microelectronics Center Liaison, in charge of CAD operations at

Northeastern University, 1989-1990.

Member of IEEE/TTTC Education Sub-Committee, working on integration of test

engineering in Electrical and Computer Engineering Curricula.

Secretary of the Faculty Committee, Massachusetts Microelectronics Center, two

year term started May 1990.

Assigned by the Development Program of the United Nations (UNDP) to present

courses and seminars in the CAD area to Universities in Iran. This assignment was

under the TOKTEN project and was supported by the UNDP. The consulting took

place in the Summer of 1991.

Conduct several credit and non-credit National Technological University courses.

COMMITTEE ACTIVITIES (Updated 1997):

Member of the Electrical and Computer Engineering, Graduate Affairs Committee,

representing Computer Engineering; since 1987.

Member of the College of Engineering, Computer Advisory Committee,

representing Electrical and Computer Engineering Department; since 1988.

Member of the University Computer Resources Center, Advisory Committee on

Academic Computing (ACAC), representing college of Engineering; 1988-1990.

Member of Iranian National Board of Computer Education for curriculum

development, since 1996.

Program Committee Member for : The Spring 1996 VIUF Conference, April 1996,

Boston MA.

Program Committee Member for : IEEE 96 Electrical Engineering Conference,

Tehran, Iran, May 1996.

Program Committee Member for : 6th IEEE North Atlantic Test Workshop, West

Greenwich, RI, May 1997.