03 fpga architecture v12

Designing with FPGA Resources

Designing with FPGA Resources - * Copyright 2010 Xilinx

ObjectivesAfter completing this module, you will be able to:Describe the I/O features of the Virtex-6 and Spartan-6 FPGAsDescribe block RAM and FIFO resourcesDescribe the available DSP48 resourcesList other resources available in Virtex-6 and Spartan-6 FPGAs


I/OBlock RAMs and FIFODSP48 ResourcesOther FeaturesSummary

Lessons


I/O Block DiagramInterconnect to FPGA fabricElectrical ResourcesNPLVDS TerminationLogical Resources


HSTL (1.8 V, 1.5 V, Classes I, II, III, IV)HSTL_I_12 (unidirectional only)DIFF_HSTL_I_18, DIFF_HSTL_I_18_DCIDIFF_HSTL_I, DIFF_HSTL_I_DCIHSTL_II_T_DCIDIFF_HSTL_II_T_DCIRSDS_25 (point-to-point)LVCMOS (2.5 V, 1.8 V, 1.5 V, and 1.2 V)LVDS, bus LVDS, extended LVDSLVPECLHyper Transport (LDT)SSTL (2.5 V, 1.8 V, 1.5 V Classes I, II)DIFF_SSTL_IDIFF_SSTL2_I_DCIDIFF_SSTL18_I, DIFF_SSTL18_I_DCISSTL15SSTL15_T_DCIDIFF_SSTL15_T_DCISelectIO Interface VersatilityEach pin can be input and (3-stateable) outputEach pin can be individually configured forInternal termination, drive strength, input threshold, and weak pull-up or pull-downEach I/O can have the same performanceUp to 1 Gbps single-ended and 1.4 Gbps differentialEach I/O supports 40 plus voltage and protocol standards, including


Virtex-6 FPGA Internal Termination Using DCIConfigures output driver impedance (series termination)Provides input impedance match toVcco (single termination) or Vcco (split termination, Thevenin equivalent)Two reference pins per bank: VRP and VRNMake DCI independent of voltage, temperature, and process variationsConnected to reference resistors (50 to 100 ohm)DCI cascading featureOne banks VRP and VRN can also be shared by adjacent banksDynamically 3-stateable input termination (*_T_DCI)Input termination is only enabled when the output driver is 3-statedVTT(50% of Vcco)50Vcco100100EquivalentVirtex-6 HSTL_I_DCITerminationExternal HSTL_ITerminationTraditional FPGA


Virtex-6 Input and Output DDRIDDR supports OPPOSITE_EDGE (legacy mode), SAME_EDGE, and SAME_EDGE_PIPELINEDODDR is similar, but only supports OPPOSITE_EDGE and SAME_EDGEOLOGIC contains ODDR for both data and 3-state enable


Spartan-6 FPGA Input and Output DDRSame-edge and opposite edge capability Attribute: DDR_ALIGNMENT = NONE (default), C0, or C1

DDR_ALIGNMENT = NONEDDR_ALIGNMENT = C0 or C1


SLAVEMASTERIOBMaster/Slave IOB PairIOBI/O SERDES CapabilityParallel/Serial to Serial/Parallel ConversionIncludes input and output SERDESOSERDES parallel-to-serial converter for both OQ and TQISERDES and OSERDES have independent CLK and CLKDIV inputsArranged as master and slave IOB pairIOB pairs share the same name with P and N suffixes for master and slaveIOB pairs allow for differential I/OMaster ISERDES & OSERDES can use slave resources to widen the interfaceIOB side can be SDR or DDR


Programmable Data DelayChange the clock/data phase relationship for data captureAdjust timing on a per-pin basis to accommodate board/package skewDynamically controllable

IODELAYDATAOUTIDATAININC/DECDelay ChainIDELAYCTRLREFCLKDelay generated in incrementsVirtex-6: Delay steps are calibrated based on REFCLK frequencyDelay can be dynamically controlledTo Pad, ILOGIC, ISERDES or FPGA fabricFrom PadUser InterfaceCFrom FPGA fabricODATAINFrom OLOGIC or OSERDESVirtex-6 only


SDR resources utilizing ILOGIC and OLOGIC resources can be inferred IDDR can be inferredSee Xilinx Answer Record 15776ODDR, ISERDES, OSERDES, IDELAY, IODELAY, and IDELAYCTRL resources must be instantiatedInstantiate primitivesMemory Interface Generator (MIG)Use Examples


Memory Interface GeneratorGenerates a complete memory controller and interface designOutput: RTL, UCF, documentation, and timing analysisVHDL or VerilogChoose from a predefined catalog of available devices and interfacesChecks SSO and all pin selection rules Included with the CORE Generator software


Apply Your KnowledgeDescribe the I/O features of the Virtex-6 and Spartan-6 FPGAs



Lessons


Virtex-6 FPGA Block RAM and FIFO36-kb sizeOne 36-kb block RAM or FIFOTwo independent 18-kb RAMsOne 18-kb RAM and one 18-kb FIFOPerformance up to 600 MHzMultiple configurationsTrue dual port, simple dual port, single port64kb x 1 integrated cascade logicMaximum data width = 72Byte-write enable Integrated 64-bit error correction


Spartan-6 FPGA Block RAM18-kb sizeOne 18-kb block RAMTwo independent 9-kb RAMsPerformance up to 300 MHzMultiple configurationsTrue dual port, simple dual port, single portMaximum data width = 72Byte-write enable

or18 Kbblock RAM 9 Kb block RAM9 Kb block RAM


Block RAM ModesSingle-port block RAM: One read/write port36-kb configurations16k x 2, 8k x 4, 4k x 9, 2k x 18, 1k x 36, 512 x 7218-kb configurations16k x 1, 8k x 2, 4k x 4, 2k x 9, 1k x 18, 512 x 36Spartan-6: 256 x 729-kb configurations8k x 1, 4k x 2, 2k x 4, 1k x 9, 512 x 18, 256 x 36Simple dual-port block RAM: one read port, one write portSeparate clock and address per portVirtex-6 FPGA 36-kb and Spartan-6 FPGA 18-kb: configurations up to 72 bits wideVirtex-6 FPGA 18-kb and Spartan-6 FPGA 9-kb: configurations up to 36 bits wide


Block RAM ModesContinuedTrue dual-port block RAMSeparate clock and address per portCan perform read and write operations simultaneously and independently on Port A and Port BWrite operation also performs read operation at same addressMode can be read-before-write, write-before-read, or no-changeVirtex-6 FPGA 36-kb and Spartan-6 FPGA 18-kb: configurations up to 36 bits wideVirtex-6 FPGA 18-kb and Spartan-6 FPGA 9-kb: configurations up to 18 bits widePorts can be different widths


Block RAM FeaturesVirtex-6 FPGA: Built-in cascade logic for 64kb x 1Cascade two adjacent 32-kb block RAMs without using external CLB logic or compromising performanceCascade option for larger arrays using external CLB logicByte enables for configurations > 9 bitsOptional pipeline register for readsVirtex-6 FPGA: Error Correcting Code (ECC)Available on 512x72 simple dual-port RAM or FIFONo byte enables64 bits of data + 8 bits of parity


Virtex-6 FPGA FIFO18/36 Features600-MHz maximum frequency Synchronous or asynchronous read and write clocksNo phase relationship required in asynchronous modeFour flagsFull, empty, programmable almost full, and programmable almost emptyOptional First Word Fall Through (FWFT)Immediate availability of the first word after emptyFIFO configurations36-kb: 8k x 4, 4k x 9, 2k x 18, 1k x 36, 512 x 72512 x 72 can implement Error Correcting Codes (ECC)18-kb: 4k x 4, 2k x 9, 1k x 18, 512 x 36No byte write enablesBoth ports must be same widthFIFO read port is block RAM Port AFIFO write port is block RAM Port BDIN Bus

WRENWRCLK

RDENRDCLK

RESETDOUT Bus

FULLAFULLEMPTYAEMPTYRDERRWRERR

RDCONTWRDCONT>>


Virtex-6 FPGA FIFO ModesAsynchronous clocksCan be used in Standard or FWFT modeEN_SYN = FALSE (default)DO_REG = 1Assertion of flags are zero latencySynchronous clocksCan be used in Standard mode onlyFIRST_WORD_FALL_THROUGH = FALSE (default)EN_SYN = TRUEDO_REG = 0, 1If DO_REG = 1, adds a pipeline stage to flags and outputimproving TckoAll flags are zero latency


Virtex-6 FPGA FIFOs are CascadableFlexible FIFO configuration No dedicated cascade logicExpand width, depth, or both using fabric logic


Inference of block RAM is possibleSpecific coding techniques are requiredMost block RAM capabilities are available Dual port, individual clocks, separate read/write ports, output register, set/resetSee the XST Users Guide > RAMs and ROMs

Inference of FIFOs is not possible

Xilinx suggests that you use IP (CORE Generator & Architecture Wizard)Block RAM and FIFO Use


IP (CORE Generator & Architecture Wizard)



Lessons


Virtex-6 FPGA DSP48E1 SlicePCINA:BX25 X 18=YZ>>17>>170001CCC48OpMode7CarryInALUMode4CarryInSel3PCOUTINMODEPPATTERN_ DETECTACINBCINAB484818DCARRY CASCOUTCARRY OUTACOUTBCOUTCARRY CASCIN30183018MULT SIGNOUT6MULT SIGNIN25PATTERNDual B RegisterCarry 5Dual A, D RegisterWithPre-adder3018484434325862301825x18 signed multiplier48-bit add/subtract/accumulate48-bit logic operationsPipeline registers for high speedPattern detectorSIMD operations (12/24 bit)Cascade paths for wide functionsPre-adder


Spartan-6 FPGA DSP48A1 SlicePCIND:A:BX18 X 18Z+/-00C48OPMODE[3:0]OPMODE[5]OPMODE[7]PCOUTOPMODE[6,4]PBCINDA4818BCCOUTCFOUTBCOUTCIN12181818Dual B, D RegisterWithPre-adder181848183618 MFOUT483618x18 signed multiplier48-bit add/subtract/accumulatePipeline registers for high speedCascade paths for wide functionsPre-adder


Virtex-6 FPGA Pre-Adder A30 ACINA MULT ACOUTX MUXD253030INMODE[0]INMODE[1]INMODE[2]INMODE[3]252525The A input to multiplier is controlled by INMODE[3:0]Dynamically selects A1/A2 pipeline levelDynamically selects add/subtractDynamically selects Zero for A or DACOUT and X MUX input are statically controlled Bitstream Controlled Dynamically Controlled


Normal or 17-bit right shifted with MSB fill for multi-precision arithmetic

Basic operations areZ (X + Y + CARRYIN) ALU_MODE = 0000 or 0011-Z (X + Y + CARRYIN) 1 ALU_MODE = 0001 or 0010X, Y, and Z multiplexers allow for dynamic OPMODEsMultiplier output requires both X and Y multiplexersX, Y, and Z Multiplexers


Apply Your KnowledgeGiven this OPMODE table, what is the OPMODE for the following functions?C + A:BA*B + CP + C + PCIN

OPMODE Controls the behavior of X, Y, and Z multiplexers


XYZP0PA:B10PPCIN0CALUMODE[3:0]OPMODE[3:0]Virtex-6 FPGA: Two-Input Logic Functions48 bit logic operationsXOR, XNOR, AND, NAND, OR, NOR, NOTALUMODEs

Logic Unit ModeOPMODE[3:2]ALUMODE[3:0]X XOR Z000100X XNOR Z000101X XNOR Z000110X XOR Z000111X AND Z 001100X AND (NOT Z)001101X NAND Z001110(NOT X) OR Z001111X XNOR Z 100100X XOR Z100101X XOR Z100110X XNOR Z100111X OR Z101100X OR (NOT Z) 101101X NOR Z 101110(NOT X) AND Z101111


Virtex-6 FPGA: Pattern Detect and SIMDPattern detectionPattern and mask operation on output of adderPattern can be constant (set by attribute) or C inputEnablesSymmetric rounding for multi-precision operationsConvergent roundingSaturationAccumulator terminal countSIMD operations48 bit adder broken into 2x24 bits or 4x12 bitsAllows two or four independent additions to be doneCarry bits brought out independently and disabled between sectionsCarry bits can be cascaded between DSP48E1 slices=C or MC


Cascade PathsCascade paths exist from each DSP48 slice to the slice above itA input, B input, P output and shifted P output, carry outEnables common functions with little or no additional resourcesWider accumulators and multipliers, complex multipliers, and FIR filters, for exampleExample: 35bitx25bit Multiplier with two Virtex-6 FPGA DSP48E1s

0,B[16:0]A[24:0]B[34:17]BP2518BPA2518SHIFT 17P[16:0] = OUT[16:0]P[42:0] = OUT[59:17]


Implement or Accelerate DSP Functions


IP is currently supported in the IP (CORE Generator and Architecture Wizard) tool for the ISE software A sampling of cores supported

Adder/SubtracterAccumulatorMultiply and Accumulate (MAC)Dynamic Control MAC FIRMADCORDICSerial DividerFilters (CIC and FFT)Transforms (DFT and FFT)SIN COS LUTDDSComplex Multipliers

IP SupportIP (CORE Generator & Architecture Wizard)


Creative Uses of DSP48E1If not needed for MACC functions, can be used to implement48-bit 2-1 multiplexer3-bit 6-1 multiplexerAnd other N bit M-1 multiplexers where NxM 1848 bit counter or multiple smaller countersMany more...Requires creative use of OPMODE and ALUMODE



Lessons


Gigabit TransceiversDedicated parallel-to-serial transmitter and serial-to-parallel receiverUnidirectional, differential bit-serial data I/OIntegrated PLL-based Clock and Data Recovery (CDR)Parallel interface to the FPGA internal fabric8 to 40 bit wide to accommodate internal speed limits and optional fabric encodingSerial interface to the printed circuit board (differential signaling)Differential Current Mode Logic (CML) Two traces for the transmitter and two traces for the receiver; removes common-mode noiseProgrammable signal swing and TX and RX equalizationFPGAFabricInterfacePMAPCSPMAPCSTXRX22


Virtex-6 FPGA GTX Transceiver ProtocolsDatacom1GbE2.5GX (Broadcom 2.5GE)XAUIDDR XAUI (RXAUI)10G-Base CX440GE (5.15Gbps interface to external MUX)100GE (5.15Gbps interface to external MUX)TelecomSONET OC-48SONET OC-12SONET OC-3 (with fabric oversampling)OTU1OTU4 (5.59Gbps interface to external MUX)SFI-5.1SFI4.2GPON 2.488Gbps TX / 1.244Gbps RX with BCDRWirelessCPRI 6G, 2.5G, 1.2G, 614MOBSAI 6G, 3G, 1.5G, 768MComputingPCI Express technology Gen1 and Gen2 (to x8)SRIO Gen1 and Gen2InfiniBandIntel QPIVideoSDIHD-SDI3G-SDIDisplay PortDVB-ASIStorageSATASASFiber ChannelChip-to-ChipInterlakenSPAUIAuroraOIF CEI-6SR


Spartan-6 FPGA GTP Transceiver ProtocolsDatacom1GbEXAUI (pending IP characterization)10G-Base CX4 (pending IP characterization)TelecomSONET OC-3 (with fabric oversampling see DRU XAPP875)SONET OC-12SONET OC-48 (pending char until then, requires ext. PHY)OTU1 (pending char until then, requires ext. PHY)Chip-to-ChipSerial RapidIOAuroraWirelessCPRI 3G, 2.5G, 1.2G, 614MOBSAI 3G, 1.5G, 768MComputingPCI Express Gen1 (Hard IP supports x1)InfiniBandVideoDisplay PortSDI (pending char - with fabric oversampling, XAPP875)HD-SDI (pending characterization)3G-SDI (pending characterization)StorageSATA


PCI Express Endpoint Block Key FeaturesHighly configurable hard PCI Express blockSupports endpoint and root portScalable bandwidth1, 2, 4, or 8 lanes for bothGen 1 and Gen 2 data ratesMeets all key PCI Express technology v2.0 requirementsElectrical signalingProtocol (CRC, automatic retry)Quality of Service (QoS)Hot pluggableUses GTX transceiver blocksTo FabricVirtex-6 FPGATransaction LayerData LinkLayerPhysicalLayerConfiguration and Capabilities Module PCI Express Block GTXGTXGTXGTXGTXGTXGTXGTX


Virtex-6 FPGA Tri-Mode EMACTri-mode 10 / 100 / 1000 Mb/s: full or half duplexIEEE 802.3 compliantAvailable in every LXT and SXT deviceFour integrated EMACs per chipProgrammable PHY interfaces Flexible support of both copper and optical networksNew 2.5 Gbps over-clocking option

EMACEMACEMACEMAC


Virtex-6 FPGA Tri-Mode EMACSupports legacy Virtex-5 FX FPGA feature setStandard PHY interface supportMII, GMII, RGMII, SGMII PCS/PMA for 1000BASE-XSelectable host interfaceGeneric or Dynamic Configuration host (DCR)Receive EMAC address filterJumbo-frame supportIncreased bandwidth with larger packetsReduced host processingNetwork traffic monitoring and filteringReal time statistics for TX and RXUp to four blocks per device


Usage ModelsUse the CORE Generator software to access all of these featuresFPGA Features and Design > IO InterfacesStandard Bus Interfaces > PCI ExpressCommunications & Networking > Ethernet



Lessons


What is the easiest method for building resources such as I/O, memory, and DSP functions?

Apply Your Knowledge


SummaryThe IOB tile contains the IOB, ILOGIC/ISERDES, OLOGIC/OSERDES, and IODELAY blocksThe ILOGIC and OLOGIC blocks provide SDR and DDR registersThe ISERDES and OSERDES blocks provide source-synchronous capabilities utilizing dedicated resourcesBlock RAMs support various memory sizes in single-port, simple dual-port, and true-dual port configurationsThe Virtex-6 FPGA FIFO18 and FIFO36 blocks resources support synchronous and asynchronous FIFOsThe DSP48 block provides maximum performance and low power for DSP applications

Trainer Note: This module describes some of the features of the Virtex-6 and Spartan-6 FPGAs. 60 minutes Editor note: In LGP, put this instructor note in the Purpose block. No need to create a separate Trainer Note block.

This block diagram shows a differential pair of I/O pins. They can also be configured as two independent, single-ended I/O pins.Spartan-6 FPGA: Differential transmitters are only available in the top and bottom I/O banks. Differential receivers are available in all banks.DCI = Digitally Controlled Impedance.This is a partial list of the I/O standards supported by Virtex-6 FPGAs. For a complete list, and for a list of Spartan-6 FPGA-supported I/O standards, refer to the user guides.Spartan-6 FPGAs also support some 3.3V I/O standards.Spartan-6 FPGAs also support internal termination, but with a less precise resistor value.The timing diagram shows the Virtex-6 FPGA IDDR primitive used in SAME_EDGE_PIPELINED mode. Data is presented to the IDDR on opposite edges. The IDDR utilizes an optional third and fourth input register to output Q1 and Q2 data on the same clock edge, and with one extra level of latency for Q1. The ODDR primitive is similar, but in reverse; if the CE is asserted, 2 bits from the fabric (D1 and D2) drive the output (Q) on opposite edges of CLK.For example, on the input side, if DDR_ALIGNMENT = NONE, data is presented to the FPGA fabric on opposite edges. Whereas, if DDR_ALIGNMENT = C0 or C1, then the data is presented to the fabric aligned with the rising edge of C0 (or C1 depending on which one is selected). C0 and C1 can be from different sources, but should be 180 degrees out of phase of each other.Virtex-6 FPGA: A single SERDES interface can be up to 6 bits wide. Using a master/slave pair increases the interface to 10 bits.Spartan-6 FPGA: A single SERDES interface can be up to 4 bits wide. Using a master/slave pair increases the interface to 8 bits.One IODELAY element is available in every I/O block, and can either be used as to delay the input data, output data or both.The delay value can be set via attributes, and/or varied with a user interface to an up/down counter associated with each IODELAY element.Virtex-6 FPGA: The IDELAYCTRL primitive calibrates the delay elements in all of the IODELAY blocks in a single I/O bank.Spartan-6 FPGA: The delay chain elements are not calibrated by default, but there are delay modes that include calibration to the I/O clock signal.1) Describe the I/O features of the Virtex-6 and Spartan-6 FPGAs.IOB drives various voltage and I/O standards and includes impedance control and termination.ILOGIC includes SDR and DDR input register resources.The IDDR primitive in the Virtex-6 FPGA supports OPPOSITE_EDGE, SAME_EDGE and SAME_EDGE_PIPELINED mode.The IDDR primitive in the Spartan-6 FPGA supports alignment to either of the input clocks.OLOGIC includes SDR and DDR output register resources.The ODDR primitive in the Virtex-6 FPGA supports OPPOSITE_EDGE and SAME_EDGE modes.The ODDR primitive in the Spartan-6 FPGA supports alignment to either of the input clocks.OLOGIC contains one ODDR for data path and one ODDR for 3-state path.SERDES serial-to-parallel converter.Virtex-6 FPGA: Up to 6 bits wide, or up to 10 bits wide utilizing a master/slave pair.Spartan-6 FPGA: Up to 4 bits wide, or up to 8 bits wide utilizing a master/slave pair.IODELAY allows programmable controlled input and output delay.Reading data from the FIFO is synchronous to the rising edge of RDCLK.Writing data to the FIFO is synchronous to the rising edge of WRCLK.The Full and Almost Full flags are synchronous to the write clock (WRCLK).The Empty and Almost Empty flags are synchronous to the read clock (RDCLK).Xilinx suggests instantiation of memory cores for the following reasons: Portability: If you change to the latest device, you can swap out new cores to utilize new features. In addition, each family and/or vendor will have different memory capabilities. The cores that were created by the IP (CORE Generator & Architecture Wizard) tool will:Create nearly any size memory and automatically include any extra logic that is required for connecting or cascading.Specify the required attributes based on the GUI selections.Only bring out the necessary portsgreatly simplifying HDL instantiation.The memories that are created from the CORE Generator software automatically include the necessary constraints and attributesmaking it easy to instantiate the resulting core into your code with minimal effort.C denotes the output of the optional C pipeline register. This bus is one input of the pattern detect multiplexer; the other input is the 48 bit PATTERN attribute.Some primary differences between the DSP resources in the Spartan-6 FPGA and the DSP resources in the Virtex-6 FPGA are:A, B and D inputs are only 18 bits wide.Smaller multiplier (18x18 vs. 25x18).Less complex add/subtract function (no ALU mode).No pattern detect on the output.No cascade on A input.Pre-adder is only 18 bits.The pre-adder doubles the efficiency of symmetrical filters and convolutions over previous technologies. The lower 25 bits of A are fed into the pre-adder.Fine-grain access to the data input pipelines optimizes the implementation of certain algorithms, like short FFTs and sequential complex multiplications.The Spartan-6 FPGA has a similar 18-bit pre-adder that can combine the B and D inputs.The OPMODE of each DSP component is individually controllable.The OPMODE can change dynamically on each cycle.

Editor Note: Pull out table in LGP

2) Given this OPMODE table, what is the OPMODE for the following functions? C + A:BOPMODE = 011 00 11 or 000 11 11A*B + COPMODE = 011 01 01P + C + PCINOPMODE = 001 11 10

EDITOR: Do not pull out table in LGP Spartan-6 FPGA: There is no cascade path on the A input.RocketIO transceiver performance will vary by family and subfamily:Full clock and data recovery8/16-bit or 10/20-bit datapath supportOptional 8B/10B or FPGA-based encode/decodeIntegrated FIFO/elastic bufferChannel bonding and clock correction supportEmbedded 32-bit CRC generation/checkingIntegrated comma-detect or A1/A2 detectionProgrammable pre-emphasis (AKA transmitter equalization)Programmable transmitter output swingProgrammable receiver equalizationProgrammable receiver termination-Embedded support for: Out of Band (OOB) signaling: serial ATABeaconing, electrical idle, and PCI Express technology receiver detection-Built-in PRBS generator/checkerThe Virtex-6 HXT family also contains new GTH transceivers that support line rates over 11 Gbps.3) What is the easiest method for building resources such as I/O, memory, and DSP functions?InferenceBasic I/O (single-ended)Single block RAMsMultipliersUse of the CORE Generator toolLarger block RAM memoriesFIFOsDSP functions, arithmetic functions, MACCs, and FIR filters, for exampleEditor Note: Put the Where Can I Learn More content in LGP after the Summary slide.Where Can I Learn More?Virtex-6 and Spartan-6 FPGA data sheets

Virtex-6 and Spartan-6 FPGA user guides

Virtex-6 and Spartan-6 FPGA home pageswww.xilinx.com/virtex6www.xilinx.com/spartan6Links to everything related to the Virtex-6 and Spartan-6 FPGAs: white papers, boards, training, data sheets, and user guides

www.xilinx.com/educationDesigning with the Spartan-6 and Virtex-6 Families course

03 fpga architecture v12

Documents

fpga input

fpga resourcesdesigning

fpga internal termination

resources available

slave resources

stateable input termination

input threshold

output ddrsameedge