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CPLD CPLD 簡介簡介

2011/01/16 v1.02011/01/16 v1.0

By Johnson ChangBy Johnson Chang

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What is CPLDWhat is CPLD

CComplex omplex PProgrammable rogrammable LLogic ogic DDeviceevice Your own ASIC Your own ASIC

( ( AApplication pplication SSpecified Integrated Circuit)pecified Integrated Circuit) Logic Design Logic Design Implementation with Implementation with

1.1. Standard TTL / COMSStandard TTL / COMS

2.2. CPLD / FPGACPLD / FPGA

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Why CPLD?Why CPLD?

LargeLarge Digital Logic Design is possible Digital Logic Design is possible Minimize PCB sizeMinimize PCB size High Speed ( 3/4/5 nS vs 18nS )High Speed ( 3/4/5 nS vs 18nS ) SecuritySecurity

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CPLDCPLD

TTLTTL

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How to design CPLDHow to design CPLD

Xilinx / AlteraXilinx / Altera Altera Quartus / Maxplux II (phase out)Altera Quartus / Maxplux II (phase out) Block Diagram Schematic ( bdf ) / VHDL / Block Diagram Schematic ( bdf ) / VHDL /

VerilogVerilog

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Study SequenceStudy Sequence Quartus InstallationQuartus Installation Example DemonstrationExample Demonstration Introduction of Terasic CPLD KitIntroduction of Terasic CPLD Kit Programming ExampleProgramming Example Implement 74LS138 with 3 SW inputImplement 74LS138 with 3 SW input Implement 74LS138 with 2Hz inputImplement 74LS138 with 2Hz input Design a 7-Segment decoderDesign a 7-Segment decoder Design a 4*7 7-Segment decoderDesign a 4*7 7-Segment decoder Design a 4-byte RAMDesign a 4-byte RAM Design a counter 1,3,5,7,1,3,5,7Design a counter 1,3,5,7,1,3,5,7 、、、、、、

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Learning MaterialLearning Material

陳慶逸的教學網站 陳慶逸的教學網站 CPLD/FPGACPLD/FPGA數位電路教學與設計資源數位電路教學與設計資源 張正賢教學網站張正賢教學網站