CS 296-33:Intro to Programmable Logic and FPGAsADEL EJJEH

UNIVERSITY OF ILLINOIS URBANA-CHAMPAIGN

Digital Logic• In CS 233:

• Logic Gates

• Build Logic Circuits• Sum of Products

F = (A’.B)+(B.C)+(A.C’)

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BlackBox

A

B

C

F

??

Programmable Logic Devices (PLDs)

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PLD

PLA(Programmable

Logic Array)

PAL(Programmable

Array Logic)

CPLD(Complex PLD)

FPGA(Field Prog.Gate Array)

•2-level structure of AND-OR gates with programmable connections

•Enhanced PLAs with reduced costs

•For large designs•Collection of multiple PLDs with an interconnection structure

•Has a much larger # of logic blocks•Larger interconnection network•Largest manufacturers: Xilinx - Altera Slide taken from

Prof. Chehab, American University of Beirut

Combinational Programmable Logic DevicesPLAs, CPLDs

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Programmable Logic Arrays (PLAs)• 2-level AND-OR device

• Programmable connections

• Used to generate SOP• Ex: 4x3 PLA

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Slide adapted fromProf. Chehab, American University of Beirut

PLAs contd• O1 = I1.I2’ + I4.I3’

• O2 = I2.I3.I4’ + I4.I3’

• O3 = I1.I2’ + I2.I1’

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Slide adapted fromProf. Chehab, American University of Beirut

Programmable Array Logic (PALs)• More Versatile than PLAs

• User Programmable AND array followed by fixed OR gates

• Flip-flops/Buffers with feedback transforming output ports into I/O ports

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Complex PLDs (CPLD)• Programmable PLD blocks (PALs)

• Programmable Interconnects

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PLDBlock

PLDBlock

Interconnection Matrix

I/O B

lock

I/O B

lock

PLDBlock

PLDBlock

I/O B

lock

I/O B

lock•••

Interconnection Matrix

•••

•••

•••

What About Sequential Circuits?Application SpecificIntegrated Circuits

(ASICS)General Purpose Computers

Pros:• Very High Performance(Fast, Efficient, …)

Pros:• Highly programmable/flexible• Cheap (relatively)

Cons:• No Programmability/flexibility• Very Expensive

Cons:• Not as fast as ASICS(Software not as fast as hardware!)

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• Very High Performance(Fast, Efficient, …)

• No Programmability/flexibility• Very Expensive

• Highly programmable/flexible• Cheap (relatively)

• Not as fast as ASICS(Software not as fast as hardware!)

Bridges the gap between ASICS and General Purpose Computes

Combines flexibility of Computers with

Performance of ASICs

Field Programmable Gate Arrays

(FPGAs)

Sequential Programmable Logic DevicesFPGAs

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Field Programmable Gate Arrays• Sequential Programmable Logic Circuits

• Configurable Logic Blocks (CLBs)

• Programmable Interconnect

• Specialized Resources• Multipliers/DSP Blocks

• Fast Memories (Block RAM)

• Clock Buffers

• I/O

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16-bit SR

flip-flop

clock

muxy

qe

abcd

16x1 RAM4-input

LUT

clock enable

set/reset

What are Look Up Tables (LUTs)?• LUT is a RAM!

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a

b

c

y

y a b c= • +

a b c y0 0 0 10 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 1

Required Function

Truth Table

Programmed LUT

10111011

MUX y

a,b,c

LUT

Slide adapted fromSerge Karabchevsky: Programmable Logic andFPGA

Xilinx FPGAs• Historically, two families:

• Virtex: High performance, very expensive

• Spartan: Lower end, not as expensive as Virtex

• Today, offer three families:• Virtex

• Kintex: Mid-range FPGA, new family

• Artix: Replaced Spartan as the lower end FPGA Family

• Series: 7

• Most upcoming slides taken from Xilinx Workshops

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Xilinx 7-series Architecture Overview

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Artix-7 Architecture Overview

Configurable Logic Blocks (CLB)

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• Primary resource for design in Xilinx FPGAs

• Combinatorial functions

• Flip-flops

• CLB contains two slices• Each slice can be (SLICEM, SLICEL)

• Connected to switch matrix for routing to other FPGA resources

• Carry chain runs vertically in a column from one slice to the one above

Slice Resources

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• Four six-input Look-Up Tables (LUT)

• Multiplexers• Used to implement 7 and 8 input

functions

• Carry chains• Used to implement fast arithmetic

addition/subtraction

• Flip-flops/latches• 4 FF/L, 4 FF

Look Up Tables (LUTs)• Used as conventional LUTs in SLICEL

• Implement 1 6-input function or 2 5-input functions

• How it works:• Basically a bunch of SRAM cells

• Saves the outputs of truth table in each cell

• Combination of inputs select the correct cell and thus output is read

• Can be used as either Memory or Shift Register in SLICEM• Not used in our case

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Other Resources• Block RAM used for close/fast storage or as FIFO

• DSP48E1 Slice: High Performance Arithmetic Block

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So What?• How do we program them?

• Each manufacturer has their own set of tools

• Write HDL (Verilog/VHDL) and synthesize onto FPGA

• Provides extra efficiency by manual Place and Route

• Tool-chain will generate ”bit stream” which is used to program FPGA

• After programming, FPGA will be like a “Hardware Entity” performing specific functions defined in HDL.

• Recently, tools providing support for High Level Synthesis• Write High Level Language (C/C++, OpenCL, myHDL)

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What we will do?• Use Vivado HLS (Xilinx tool-chain) to synthesize Verilog

• Program synthesized Verilog onto Basys 3 Xilinx FPGA

• Experiment with different labs ranging from simple combinational circuits to FSMs

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Rough Timeline• March 4: Intro to FPGAs (Today)

• March 11: MIPS++ (Purajit)

• March 18: Intro to Vivado and Tutorial

• Apr 8: Lab 1

• Apr 15: Lab 2

• Apr 22: Lab 3

• I will send out a whenisgood email to set a time for labs:• 2 hour meetings• No Lecture same week

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