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Part II

Low Voltage Technologiesand Circuits


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Low-Voltage Technologiesand Circuits (Invited)

TADAHIRO KURODA, MEMBER, IEEE, AND TAKAYASUSAKURAI,* MEMBER, IEEESYSTEM ULSI ENGINEERING LABORATORY, TOSHIBA CORPORATION(*) INSTITUTE OF INDUSTRIAL SCIENCE, UNIVERSITY OF TOKYO

Abstract-This paper reviews low-voltage device technologiesandcircuit designtechniques for low-power,high- speed CMOSVLSls.Some of the recent developments, such as employing multiplethreshold voltage and controlling threshold voltage through sub-strate bias in bulk CMOS and Silicon on Insulator (SOl) basedtechnologies, are discussed. Future directions of low-powerVLSlsare also described.

1. INTRODUCTIONLowering both of the supply voltage VDD and threshold voltageVth enables high-speed, low-power operation [1-3]. Figure 1 de-picts equi-speed (broken lines) and equi-power (solid lines)curves on a VDD-Vth plane [4] calculated from their theoreticalmodels [5]. The contour lines are normalized at a typical designwindow (box in the figure) where VDD = 3.3V 10% andVth = 0.55V O.IV.CircuitspeedbecomessloweratlowerVDDand higher Vth while power dissipation becomes larger at higherVDD and lower Vth Tradeoffs between speed and power can beexploredby sliding the design windowon the VDD-Vthplane. Theupper-left comer shows the worst case speed condition, whereasthe lower-right comer shows the worst case power scenario. Re-sults are summarized in Fig. 2 [4]. It suggests that optimum VDDand Vth can save the waste (shadows in the figure) caused by theconstant VDD of 3.3V and constant Vth of 0.55V.This approach, however, raises three problems, and thereforehas not been achieved: 1)degradation of worst-case speed due toVth fluctuation in low VDD[6,7], 2) increase in standby powerdis-sipation in low Vth [8-10], and 3) inability to sort out defectivechips by monitoring the quiescent power supply current (IDDQ)[11]. Delay variation due to Vth fluctuation is increased in low-voltage operation [6,7]. It can be understood in Fig. 1 that the de-sign window should be reduced in size to keep the delay variationpercentage constant in low VDD ' Its theoretical mode is derived inKuroda and coworkers [12]. For example, under 50% speed re-quirement VDD can be reduced to 1V and Vth fluctuation should bereduced from 0.1V to 0.02V. The second and the third prob-lems come from the increased subthreshold leakage current inlow Vth A dotted line in Fig. 1 depicts a equi-power-ratio curve

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where power dissipation due to the subthreshold leakage currentmakes up 10%of the total power dissipation. The design windowshould be set at high Vth regions in a standby mode and testing.To solve these problems, several circuit schemes are pro-posed: a multi threshold-voltage CMOS (MTCMOS) scheme[8], a variable threshold-voltage CMOS (VTCMOS) scheme[12], and an elastic-Vt CMOS (EVTCMOS) scheme [13]. Thethree circuit schemes are discussed and several circuit imple-mentations are presented in Section 2. Device technologies in-cluding bulk CMOS and SOl are then reviewed in Section 3.Section 4 is dedicated to discussions on possible future direc-tions and conclusions.

2. LOW-VOLTAGE CIRCUITS

A. Low-Voltage Circuit SchemesThe three circuit schemes which have been proposed to solvethe 10w-VDJlow-Vth problems are sketched and compared inFig. 3. Currently in a system such as a PC, the power supply isturned off by a power management controller when a chip is in-active, but this idea can even be applied at the chip level. TheMTCMOS [8] employs two types of Vth: low Vth for fast circuitoperation in logic circuits and high Vth for cutting off the sub-threshold leakage current in the standby mode. Since parasiticcapacitance is much smaller on a chip than on a board, the on-off control of the power supply can be performed much fasteron a chip. This takes less than 0.5,us, which in tum enables fre-quent power management [14]. This scheme is straightforwardand easy to be employed in a current design method. However,it requires very large transistors for the power supply control,and hence imposes area and yield penalties; otherwise circuitspeed degrades. These penalties become extreme below 0.9VVDD because (VGS-Vth) of the high-Vth transistors becomes toosmall in the active mode. One potential problem is that theMTCMOS cannot store data in the standby mode. Speciallatches have been developed to solve this problem [14].

While the MTCMOS can solve only the standby leakageproblem, the VTCMOS [12] can solve all three problems. It


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0.80.70.6

0.5.-->- 0.4~ 0.30.20.1

00.5 1.5 2 2.5 3 3.5 4Voo (V)

Figure 1 Exploring Voo-Vth design space.

dynamically varies Vth through substrate bias, VBBTypically, VBBis controlled to compensate for Vrh fluctuations in the activemode, while in the s tandby mode and in the IDDQ testing, deepVBB is applied to increase Vth and cut off the subthreshold leak-age current.

The EVTCMOS [13] controls both VDD and VBB such thatwhen VDD is lowered, VBB becomes that much deeperto raise Vthand further reduce powerdissipation. Note that internal VDD andVss are provided by source-follower n- and p-transistors, re-

spectively, whose gate voltages are controlled. In order to con-trol the internal power supply voltage independent from thepower current, the source-follower transistors should operatenear the threshold. This requires very large transistors.

The essential difference among the three schemes is that theVTCMOS controls the substrate-bias while the others controlthe powerlines. Sincemuch smallercurrent (almostnone) flowsin the substrate than in the power lines, a much smaller circuitcan control the substrate-bias. This leads to negligible penaltiesin area and speed in the VTCMOS. Global routing of substrate-contacts, however, may impose an area penalty, which may intum make the application of the VTCMOS to existing macro de-signs impractical. It has been experimentally evaluated that thenumber of substrate (well) contacts can be greatly reduced inlow-voltage environments [10-12]. Using a phase-locked loopand an SRAM in aVTCMOS gate-array [11], the substrate noiseinf luence has been shown to be negligible even with 11400of the contact frequency compared with the conventional gate-array.A DCT (DiscreteCosineTransform) macro made with theVTCMOS [12] has also been manufactured with substrate- andwell-contacts only at the peripheryof the macro; it worked with-out problems realizing power dissipations more than one orderof magnitude smaller than a DCT macro in the conventionalCMOS design.B. vrCMOS Circuits

Several variants have been reported [7,9-12] for theVTCMOS scheme, whose salient features are summarized inFig. 4.

1.5.0 0.0

'0Ql.ii iEo 1.0c::o0..'00rJl(5 0.5Q5:i:oa..

0.5 1.0Speed (Normalized)

Figure 2 Speed and power saving by optimum Voo and Vth

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Scheme

MTCMOSS t ' b y ~

Ref.[a]VDD on-off

St'by

VTCMOSn-well

p-wellRef.[ 12 ]

Vaacontrol

EVTCMOS

St'by

Ref.[ 13 ]VDD&Vaacontrol

Effect

Penalty

+,st'by reduction

- large serial MOSFET(*)slower,larger,lower yield- special latch

+ IJ\lfh compensation+ 'stlby reduction+'OOQ test- triplewell (desirable)

+ IJ. \lfh compensation+ 'stlby reduction+,ODQtest- largeserialMOSFET(*)

Figure 3 MTCMOS, VTCMOS, and EVTCMOS.

A self-adjusting threshold-voltage scheme (SATS) [7] re-duces the Vth fluctuation. When Vth is lower than a target value,larger leakage current flows through a leakage current monitor(LCM) and turns on a self-substrate bias (SSB) circuit. As a re-sult, VBB goes deeper and causes Vth to increase. Thus the sub-strate bias is controlled such that the transistor leakage currentis adjusted tobe a constantvalue. This means that the Vth processfluctuation can be canceled by the SATS. The measured overallVth controllability including static and dynamic effects is0.05V while using a bare process Vth fluctuation of 0.15V.The same idea is also presented in Kaenel and coworkers [15].

Two standby power reduction (SPR) circuits [9,10] have beenreported to lengthen battery life in mobile applications. Onecircuit in Seta [9] switches VBB between the power supply andan additional supply for substrate bias. It requires three exter-nal power supplies but takes less than O.I,us for the substratebias switching. Triplewell technology is amust. The other circuitin Kuroda [10] employs the SSB for the substrate bias. No addi-tional external power supply or additional step in processis required. An active-to-standby mode transition is performedby the SSB, and hence takes about l00,us. On the other hand,a standby-to-active mode transition is carried out by an MOS

SATS SPR SATS + SPALCM- - - - - - - -1

Circuit

l .J

Ref.[?]

"ss1. 4 ... , L . . . l ~ , L . f ~ VBB.p

~ " " , - ~ ' V p B BRef.[9]VBB

Ref.[10]VBBRef.[ 12]

ActiveSt'byTransitiontimeEffect

SSBno consideration

+ IJ.Vth compensation

0 . 1 ~ . s (St'by Active)0.1us (Active St'by)

+ 'st'by reduction+1000 test

SSB0.1us (St'by Active)100us (Active St'by)

+ 'st'by reduction+ '000 test

SSBSSB

0.1us (St'by-+ Active)100us (Active St'by)

+ IJ.Vth compensation+ Ist'by reduction+/oootest

Penalty - triplewell (desirable) -3 suppliesrequired - triplewell (desirable)- triplewell requiredLCM: Leakage CurrentMonitor, SSB:Self SubstrateBias, SCI:Substrate ChargeInjector

Figure 4 VTCMOS variants.

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References

Valuable discussions and constant encouragement by T. Fujita,K. Suzuki, T. Furuyama, and Y.Unno are appreciated.

Smallswingsignal

analogsignal


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[15] V. Kaenel et aI., "Automatic adjustment of threshold & supply voltagesfor minimum power consumption in CMOS digital circuits," Proc. Symp.onLowPowerElectr., 1994, pp. 78-79.

[16] R. M. Swanson and 1.D. Meindl, "Ion-implanted complementary MOStransistors in low-voltage circuits," IEEEJ. Solid-StateCircuits, vol. sc-7,no. 2, pp. 146-152,April 1972.

[17] J. B.BurrandT. Shott,"A200mVself-testingencoder/decoder using Stanfordultra-low-powerCMOS," in ISSCCDig.Tech. Papers, Feb. 1994,pp. 84-85.

[18] Z. Chen, J. Burr, 1. Shott, and J. Plummer, "Optimization of quarter mi-cron MOSFETs for low voltage/low power application," Proc. IEDM'95,Dec. 1995,pp.63-66.

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[19] F.Assaderaghi et aI., "A dynamic threshold voltage MOSFET (DTMOS)for very low voltage operation," IEEE ElectronDevice Letter, vol. 15,no. 12, Dec. 1994,pp.51Q-512.

[20] I. Yang, C. Vieri, A. P. Chandrakasan, and D. Antoniadis, "Back gatedCMOS on SOIAS for dynamic thresho ld cont ro l," Proc. IEDM'95,Dec. 1995,pp.877-880.

[21] T. Douseki et aI., "A 0.5V SIMOX-MTCMOS circuit with 200ps logicgate," ISSCCDig.Tech. Papers, Feb. 1996, pp. 84-85.

[22] V. Gutnik and A. Chandrakasan, "An efficient controller for variablesupply-voltage low power processing," Proc. Symposium on VLSI Cir-cuits,June 1996, pp. 158-159.

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