140 June 2008

1-W High Linear Broadband RF Power Amplifier with Cartesian Feedback for TETRA Modulation■ Kumar Narendra, Lokesh Anand, Pragash Sangaran, M.F. Ain, and S.I.S. Hassan

Designing a high-linearity, high-efficiency RF poweramplifier with wide bandwidth design is a realchallenge. This article explores a technique to

achieve 30 dBm output power with an adjacent channelpower ratio (ACPR) of more than −65 dBc for frequencyrange of 800–900 MHz. A three-stage gallium arsenide het-erojunction bipolar transistor (GaAs HBT) RF power ampli-fier with Cartesian feedback in closed-loop form is the mainarchitecture of the design. An adaptive bias technique wasused in the RF power amplifier design to achieve highlinearity while preserving good efficiency. From the mea-sured results, the RF power amplifier without Cartesianfeedback was found to have a 1-dB power compressionpoint of 34 dBm, ACPR of −37 to −38 dBc, and power-aidedefficiency (PAE) of 35–37% for the frequency range of800–900 MHz. The designed RF power with Cartesian feed-back (Javelin IC) on prototype board was found to performwell with an ACPR of −65 to −67 dBc for frequency spacingof 25 kHz. This article also presents the simulation modelingof the ACPR performance of the closed-loop power amplifi-er based on the Cartesian feedback model across wide fre-quency spacing.

A new European standard for private mobile radio (PMR)

called TETRA (Trans-European Trunked Radio) has beenintroduced. The TETRA [1] standard requires a very highdegree of linearity compared with the cellular- and satellite-based systems. TETRA uses a time division multiple access(TDMA) and digital modulation scheme known as π/4 dif-ferential quarternary phase shift keying (DQPSK) which is aspecial form of phase shift keying (PSK). To facilitate theimplementation of linear transmitters, the standard providesdedicated time slots corresponding to roughly 2% of thetransmission time to accommodate training and adjustmentof the linearization circuitry. The specified ACPR of theTETRA standard is more than −60 dBc for a frequency spac-ing of 25 kHz [1]. In order to meet the ACPR specifications forTETRA, a good design of the open-loop power amplifiertogether with feedback architecture must be employed.

Some works have been reported to achieve good linearityand high efficiency for a power amplifier [2]–[4], [7], [10].These techniques use envelope tracking of supply voltageand adaptive bias methods. Hanington et al. [2] achieved anACPR of greater than 26 dB with dynamic power supply volt-age. Anderson et al. [3] demonstrated increasing efficiencyfrom 20% to 32% for CDMA using the envelope trackingmethod. With the adaptive bias technique, Noh et al. [4]showed an ACPR improvement of 4 dB with a deep pinch-offbiasing. Mann et al. has demonstrated closed-loop ACPR per-formance of −67 dBc with predistortion technique for TETRAmodulation standard [7].

Principle Operations and Considerations

Adaptive Bias TechniqueThe adaptive bias technique enables the change of quiescentcurrent of a device with respect to input power levels. Inother words, low quiescent current with low output powerlevel and increasing quiescent current with high outputpower can be achieved. Therefore, the power amplifier con-sistently maintains adequate quiescent current for the ampli-fier to operate in the near-saturation region. This techniquesimultaneously provides both high linearity and efficiencycharacteristics over a broad range of power levels [3]. Theprinciple operation of the adaptive bias technique is shown inFigure 1.

For multistage amplifiers, similar techniques can beemployed for each stage of the amplifier. In this work, athree-stage power amplifier is chosen to simultaneouslyachieve high gain, high output power, and high efficiency. Asmart dc bias regulator is built to provide necessary bias volt-age to each power amplifier with respect to input powerDigital Object Identifier 10.1109/MMM.2008.920434

Kumar Narendra (cnk020@motorola.com) and Pragash Sangaran are withthe Research and Development Dept. of Motorola Technology, Penang,

Malaysia. Lokesh Anand, M.F. Ain, and S.I.S. Hassan are with the Dept. ofElectronics Engineering of the Univ. of Science Malaysia, Penang, Malaysia.

Figure 1. Block diagram of the adaptive bias technique.

PowerDetector

Vreg VCC

RFin

BiasControl

RFout

PA(Class AB)

+

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levels. Each stage of the amplifier operates in deep class AB atpretty low quiescent current. As soon as input power isapplied to the amplifier, the bias point is shifted to produceoptimum power performance.

Bandwidth AnalysisBandwidth analysis is carried out to provide an optimummatching condition for a wide frequency range (800–900MHz). The inherent bandwidth (BW)i is the bandwidthobtained under conjugate matching conditions where thematching loads terminate the two-port device. A conjugatematch means �S = �∗

IN or admittances YS = Y∗IN = G − jB.

Here G and B represent the conductance and susceptanceunder conjugate match conditions. Figure 2 shows equiva-lent networks under conjugate matched conditions. �S

and �IN are the reflection coefficients of the matching net-work and the device, respectively, and YS and YIN are the

corresponding admittances. The inherent bandwidth isgiven by

(BW)i = foQ

Hz, (1)

where ωo (ωo = 2πfo) is the angular frequency where conju-gate match values were obtained and Q is the quality factor ofthe parallel network defined by

Q = ωoRC = RωoL

. (2)

By substituting (2) into (1), we can express the inherent band-width as

(BW)i = 2 foG|B| , (3)

where R = 1/2 G and |B| = ωoC = 1/ωoL.

Figure 2. Equivalent network of the input port under conjugatematched conditions.

YS YIN

ΓS Γ IN

VIN

Figure 3. Typical Cartesian feedback system [6].

ωCartesian Feedback

Σ−

−Σ

sin t

ω φsin( t + )ωcos t

H(s)

H(s)

I

I ′

Q ′

Q

ω φcos( t + )

PA

Id(s)

Qd(s) eQ(s)

eI(s)

Figure 4. Simulation modeling of Cartesian feedback (Javelin IC).

Comparator

I and Q Modulator

Complete PADesign

Attenuator

Phase Shifterπ/4 DQPSKSource

SingleFrequency

VoltageSource

Coupler

I and Q Demodulator

∅

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From (1), it is shown that in order to achieve a wide band-width, Q of the network has to be sufficiently low. Similarly,from (3), it should be noted that conductance G must be highenough while keeping susceptance B at a low level in order tomaximize the bandwidth.

Cartesian FeedbackFigure 3 illustrates the block diagram of a typical Cartesianfeedback system. Cartesian feedback generates high-outputpower signals with good ACPR. This is accomplished by cou-pling off a partial of the demodulated signal to predistort theinput baseband I and Q signals via the comparator circuit [4].The demodulated signals I and Q at the output of the poweramplifier are fed back to the summing input of the compara-tor or filter circuit after 180◦ of phase shift.

The comparator or filter circuit will predistort its output tomain virtual ground at the comparator’s summing node. Thiswill occur when both inputs of the comparator circuit are inthe same phase when the loop is open. When the loop isclosed, the input of the comparator or filter will be equal butin a different phase.

The modulated signals are considered as the sum of I andQ signals as follows:

A(t) sin(ωot + φ(t)) = I(t) sin ωot + Q(t) cos ωot . (4)

I(t) = A(t) cos φ(t) . (5)

Q(t) = A(t) sin φ(t) . (6)

The demodulated signals of Cartesian feedback can beexpressed as follows:

I′ = (I sin ωt + Q cos ωt) sin(ωt + φ) , (7)

Q′ = (I sin ωt + Q cos ωt) cos(ωt + φ) , (8)

where ω is the carrier frequency.To gain loop stability, the comparator circuit uses a low-

pass filter circuit to limit loop bandwidth. The cutoff frequen-cy must be sufficiently wider than the bandwidth spread dueto the power amplifier nonlinearity. This limits the uppermodulation bandwidth, but is sufficient for mobile radio

Figure 5. Prototype board of RF power amplifier.

RF2173 Device RF Switch / Harmonic Filter

TantalumCapacitor

Figure 6. Measured gain versus output power across bandwidth(800–900 MHz).

28

32

36

40

44

10 20 30 40

Pout [dBm]

Gai

n [d

B]

800 MHz850 MHz900 MHz

Figure 8. Measured PAE versus output power across bandwidth(800–900 MHz).

0

15

30

45

20 25 30 35P out [dBm]

PA

E [%

]

800 MHz850 MHz900 MHz

Figure 7. Measured ACPR versus output power across bandwidth (800–900 MHz).

−55

−45

−35

−25

20 25 30 35

P out [dBm]

AC

PR

[dB

c]

800 MHz850 MHz900 MHz

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applications. Linearity is limited by two factors: loop gainand the accuracy of the feedback system.

The loop gain should be as large as possible, but it is lim-ited by the loop stability, which in turn is closely dependenton phase response. Adjustment of the phase shifter is critical.With the loop opened, the phase should be adjusted so thatthere is no rotation of the demodulated I and Q signals withrespect to the I and Q signals at the input of the comparatoror filter circuit.

RF Power Amplifier DesignThe design goal for the RF power amplifier is to achieve ACPRof −35 dBc at operating power of 30 dBm for the frequencyrange of 800–900 MHz. The three-stage RF2173 device poweramplifier from RF micro devices (RFMD) has been foundbeing a suitable component for this task. It offers an operatinggain of 32 dB and is manufactured using an advanced GaAsHBT process technology. To keep the margin of junction tem-perature below the specifications, an operating power of 30dBm and obligatory efficiency (PAE) of higher than 30% werecalculated. The device utilizes an adaptive bias scheme. Lowbase voltage applied to the device provides deep class AB bias.

A broadband matching network with loaded Q of five waschosen to transform optimum load impedance ZOL to 50 �

load termination. The load impedance is obtained from aload-pull simulation template and correlated with measure-ment data. From the calculation, loaded Q of 5 is sufficient toachieve wideband matching characteristics in the 800–900 MHz frequency range. A three-stage low-pass match-ing network is used to transform ZOL to 50 �. The first match-ing component is a tapered microstrip line which significant-ly increases the efficiency for a wide frequency band. A sec-ond harmonic trap is introduced at the final stage feedingline. The bonding wires together with the external capacitorform a series resonator that should be tuned at the secondharmonic frequency to increase efficiency and reduce spuri-ous output.

Simulation Modeling of Cartesian Feedback (Javelin IC)Figure 4 shows the basic block diagram design of closed-loopCartesian feedback (Javelin IC). The block diagram consists of

Figure 9. Measured case temperature at 100% duty cycle versustime across bandwidth (800–900 MHz).

20

40

60

80

100

0 10 20 30

Time [min]

Tem

pera

ture

[%]

800 MHz900 MHz

Figure 10. Simulation results of closed-loop ACPR performanceat 800 MHz.

0 120−120−100

−50

0RF InputSource RF Output

Source

Frequency [kHz]

Pow

er L

evel

[dB

m]

π/4 DQPSKSource

Figure 11. Test board of the RF power amplifier with Cartesian IC.

Javelin IC

RF PA

Isolator

RF Switch /Harmonic

Filter 40 mm

55 mm

Figure 12. Measured results of closed-loop ACPR versus fre-quency spacing across bandwidth (800–900 MHz).

The specified ACPR of the TETRAstandard is more than –60 dBc for afrequency spacing of 25 kHz.

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a DQPSK source, a modulator, a demodulator, a comparator,and some basic components. To make the design appear sim-pler and easier to analyze, the complete schematic designincluding dc network and impedance matching of poweramplifier are pushed into a symbol.

A single frequency voltage source is used as the inputsource for Cartesian feedback. RF power would be the power

available from the input source if no modulation is present.However, the modulation signal amplitude also affects thepower available from the source. The π/4 DQPSK (TETRA)source is used to generate the baseband I and Q signals. Atuned modulator selects the input harmonic defined by thespecified frequency and modulates it according to I (in-phase)and Q (quadrature) modulation inputs.

The tuned demodulator selects the input harmonic closestto the specified frequency and generates two baseband out-put signals equal to the instantaneous in-phase and quadra-ture-phase components of the selected carrier frequency. Thetuned modulator selects the input harmonic defined by thespecified frequency and modulates it according to the I (in-phase) and Q (quadrature) modulation inputs. The tuneddemodulator selects the input harmonic closest to the speci-fied frequency and generates two baseband output signalsequal to the instantaneous in-phase and quadrature-phasecomponents of the selected carrier frequency.

To generate a spectrum waveform in the Advanced DesignSystem (ADS), the envelope simulator is used along with theaid of Kaiser’s fundamental equation. Channel spacing fre-quency is defined as per the TETRA standard to computeACPR performance.

Prototype Measurements

RF Power Amplifier Measurement ResultsThe simulations were carried out with ADS from Agilent.The RF power amplifier and passive components modelhave been developed. To validate the principle, the RF2173RF power amplifier from RFMD was used. In our experi-ment, a test board using FR-4 material was fabricated. Theprinted circuit board (PCB) has a permittivity εr of 4.5 andthickness h of 14 mils. The test board size is 40 × 30 mm, asshown in Figure 5.

Experimental studies show that a 200-μF tantalum capaci-tor polymerized organic semiconductor capacitor (POSCAPSmodel from Sanyo) is required at the supply line, whichimproves transient ACPR and wideband frequency noise.Input and output impedance are externally matched withbroadband matching networks. Loaded Q of the input andoutput matching networks are sufficiently low to achievewide matching characteristics conditions. High-Q capacitors(from AVX manufacturer) are used for matching networks.An RF switch and harmonic filter are placed after the RFpower amplifier. The insertion loss is about 1 dB, and thusrated output power must compensate the loss. Power ampli-fier measurements under TETRA modulation were estab-lished. For precise measurements, we have developed auto-mated Labview software. For a 1-dB compression point andefficiency characterization, a duty cycle of 25% and pulsewidth of 600 μs for base bias are applied.

The ACPR parameter is measured with the TETRAanalyzer ifR 2310. A current probe with Tektronix scope(DPO7000) was used to measure dc current. Measured per-formance of saturation power, 1-dB compression point, gainat rated power, ACPR, and PAE are shown in Figures 6–8.

TABLE 2: Comparison between simulation andmeasurement results of ACPR of the power amplifier withCartesian feedback.

Simulation (MHz) Measurement (MHz)

Frequency Spacing (kHz) 800 900 800 900

25 −65.6 −65.4 −66.1 −67.6

50 −77.8 −77.5 −76.4 −76.3

75 −79.5 −81.8 −81.6 −81.6

112 −87.3 −88.4 −86.7 −86.3

262 −89.4 −90.2 −91.8 −91.8

512 −89.5 −89.8 −92.8 −94

TABLE 3: Summarized measurement results of transmitmodulation accuracy of RF power amplifier with Cartesianfeedback.

Frequency [MHz] 800 840 870 900 Specs

RMS Vector Error [%] 5.55 6.08 5.66 6.32 10

Peak Vector Error [%] 19.05 20.82 20.79 20.18 30

Res. Carr Power [%] 2.36 2.3 1.75 1.97 5

Freq. Error [Hz] 0.08 0.04 0.4 0.43 0

TABLE 1: Comparison between simulation and measuredresults of the RF power amplifier alone.

Simulation (MHz) Measurement (MHz)

Parameters 800 850 900 800 850 900

1 dB 34.4 34.3 34.3 34.7 34.6 34.5compression point [dBm]

PAE [%] 35.4 36.8 37.1 37.4 37.3 35.1

ACPR [dBc] 33.2 34.7 35.8 36.9 37.5 38.9

Maximum 36.4 36.3 35.9 36.5 36.4 36power [dBm]

The design goal for the RF poweramplifier is to achieve ACPR of –35dBc at operating power of 30 dBmfor the frequency range of 800–900MHz.

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The ACPR result refers to channel spacing of 25 kHz.Comparisons between measurement and simulation resultsof saturation power, 1-dB compression point, gain, ACPR,and PAE are summaraized in Table 1.

Case temperature TC and power dissipation Pd must beknown prior to the determination of the junction tempera-ture Tj. A thermal scanner machine is used to measure theheat generated by the power amplifier and around the board.To determine the robustness of the device, the case tempera-ture was measured at 100% duty cycle operation and isshown in Figure 9.

For this operation, we determined output power and cur-rent consumption as well. The junction temperature is withinthe limits of the device manufacturer. The equation whichdetermines the junction temperature is as follows:

Tj = TC + ηPd , (9)

where η is a thermal coefficient of the device (22◦C/W) andPd, also known as heat dissipation at any power level, isdefined as

Pd =VCC ∗ IDC + PRF − POUT , (10)

where VCC and IDC are supply voltage and total dc currentconsumed by the power amplifier, respectively. PRF is inputRF power and POUT is operating output power.

RF Power Amplifier with Cartesian Feedback Measurement ResultsThe simulation of the closed-loop ACPR characteristics ofan RF power amplifier with Cartesian feedback model isdeveloped based on Figure 4. The π/4 DQPSK (TETRA)source is used to generate baseband I and Q signals. Thesesignals together with the RF signal are fed to the system. Anenvelope simulator combines features of time and frequen-cy domain representation, offering a fast and completeanalysis of complex signals such as digitally modulated RFsignals. Kaiser fundamental equations are used to evaluatethe closed-loop ACPR performances. Figure 10 shows anexample of the closed-loop ACPR simulation results at 800MHz. The prototype board of the RF amplifier withCartesian feedback (Javelin IC) is fabricated using FR-4material which has a permittivity εr of 4.5 and a thickness hof 14 mils.

The test board of size 55 × 40 mm is shown in Figure 11.In addition to RF switch and harmonic filter, an isolator isused in the test board to minimize the reflected phase. Thisincreased the insertion loss up to 2 dB across the operatingbandwidth, which must be compensated by the outputpower. Measurement results of the closed-loop ACPR acrossbandwidth (800–900 MHz) is shown in Figure 12. The ACPRresults are plotted for a frequency spacing of ±25 kHz to±512 kHz. The output power operation is 30 dBm. Theresults meet TETRA specifications for wide frequency spac-ing up to ±512 kHz. Comparison between simulation andmeasurement results (ACPR) of the power amplifier with

Cartesian feedback model are presented in Table 2. Goodagreement between simulated and measured results isachieved. Take note that other performance such as efficien-cy and temperature performance are not affected in closed-loop form measurement.

A transmit modulation accuracy measurement was carriedout with ifr 2310 (TETRA Analyzer). The π/4 DQPSK(TETRA) source baseband I and Q signals were generatedusing an Agilent digital signal generator (E4432B ESG-D).Transmit modulation accuracy measurement of closed-loopform RF power amplifier with Cartesian feedback acrossbandwidth (800–900 MHz) is summarized in Table 3. RMSvector error, peak vector error, carrier power, and frequencyerror are within TETRA specifications.

ConclusionsA power amplifier linearization concept based on Cartesianfeedback exhibited improvements in performance. Theconcept has been applied for the TETRA standard in the800–900 MHz frequency range. The power amplifier perfor-mance has been validated on the board level. Both open- andclosed-loop performance have been determined on simula-tion and measurement levels, and good results have beendemonstrated. The power amplifier with Cartesian feedbackfulfills the TETRA specifications. Modeling work has beenperformed for the simulation of the closed-loop ACPR per-formances of the power amplifier with Cartesian feedback.Model-based simulation and measurement results show agood agreement.

References[1] J.F. Wilson, “The TETRA system and its requirements for linear amplifi-cations,” in IEEE Colloquium on Linear RF Amplifiers and Transmitters Dig.,Apr. 1994, pp. 4/1–7.[2] G. Hanington, P.F. Chen, P.M. Asbeck, and L.E. Larson, “High efficiencypower amplifier using dynamic power supply voltage for CDMA applications,”IEEE Trans. Microwave Theory Tech., vol. 47, no. 8, pp. 1471–1476, Aug. 1999.[3] D.R. Anderson and W.H. Cantrell, “High efficiency high level modulatorfor use in dynamic envelope tracking CDMA RF power amplifiers,” in IEEEMTT-S Int. Microwave Symp. Dig., 2001, pp. 1509–1512.[4] Y.S. Noh and C.S. Park, “An intelligent power amplifier MMIC using anew adaptive bias control circuit for W-CDMA applications,” IEEE J. SolidState Circuits, vol. 39, no. 6, pp. 967–970, June 2004.[5] B. Razavi, RF Microelectronic. Upper Saddle River, NJ: Prentice-Hall, 1979.[7] S. Mann, M. Beach, P. Warr, and J. McGeehan, “Increasing the talk-time ofmobile radios with efficient linear transmitter architectures,” Elect. Commun.Eng. J., pp. 65-76, Apr. 2001. [8] S.C. Cripps, Advanced Techniques in RF Power Amplifier Design. Norwood,MA: Artech, 2002.[9] F.H. Raab, P. Asbeck, S. Cripps, P.B. Kenington, Z.B. Popovic, N.Pothecary, J.F. Sevic, and N.O. Sokal, “Power amplifiers and transmitters forRF and microwave,” IEEE Trans. Microwave Theory Tech., vol. 50, pp. 814–826,Mar. 2002.

A smart dc bias regulator is built toprovide necessary bias voltage toeach power amplifier with respect to input power levels.