10 - high power circuits - multimedia universitypesona.mmu.edu.my/~wlkung/ads/rf/lesson10.pdf · 10...

1

September 2008 2006 by Fabian Kung Wai Lee 1

10 - High Power Circuits

The information in this work has been obtained from sources believed to be reliable.

The author does not guarantee the accuracy or completeness of any information

presented herein, and shall not be responsible for any errors, omissions or damages

as a result of the use of this information.


References

• [1]* G. Gonzalez, “Microwave transistor amplifiers - analysis and design”, 2nd Edition 1997, Prentice-Hall.

• [2] C. W. Sayre, “Complete wireless design”, 2001, McGraw-Hill.

• [3]* S. C. Cripps, “RF power amplifier for wireless communications”, 1999, Artech House (2nd edition 2005 is available).

• [4] G. D. Vendelin, A. M. Pavio, U. L. Rohde, “Microwave circuit design - using linear and nonlinear techniques”, 1990, John-Wiley & Sons (2nd

edition 2005 is available).

• [5] S. A. Maas, “Nonlinear microwave circuits”, 1988, Artech House.

• [6] G. Massobrio, P. Antognetti, “Semiconductor device modeling with SPICE”, 2nd edition, 1993, McGraw-Hill.

• [7]* B. Razavi, “RF microelectronics”, 1998 Prentice Hall.

• [8] Gilmore R., Besser L., “Practical RF circuit design for modern wireless systems”, Vol. 1 & 2, 2003, Artech House.

• [9] Gray P. R., Meyer R. G., “Analysis and design of analog integrated circuits”, 3rd Edition, 1993, John-Wiley & Sons.

2


1.0 Introduction

May 2009 2006 by Fabian Kung Wai Lee 4

Introduction

• Thus far we have considered various aspects of small-signal amplifier

design based on small-signal S-parameters.

• The small-signal S-parameters are not useful for large-signal or high

power circuit design such as power amplifier, mixers, frequency

converters because the active devices (i.e. transistor/FET/diode) in

these circuits usually operate in the nonlinear regions (recall that S-

parameters are obtained by assuming the BJT or FET to be linear).

• In large-signal circuits the voltage and current variation will be large, for

BJT this means the variation of the transistor terminal voltages will be

greater than VT.

• Here we will concentrate on aspects of large-signal circuit design

concerning power amplifiers and mixers.

• This short note will focus on discrete design, using BJT or FET,

although the concepts can be extended to integrated circuit design.

3

Small-Signal Versus Large-Signal

Operation

• Consider a 2-port system:


ZL

Vs

Zs

Large-signal

Small-signal

( ) ( ) ( ) ( ) ...

3

3

2

21TOHtvatvatvatv

iiio+++=

f

Usually non-sinusoidal waveform

vi(t)

vo(t)

f

Sinusoidal waveform

T

1/T


Large-Signal Model of Active

Components (1)

• Amplitude of the voltage and current in the transistor/FET of high power

circuit is large so that small-signal linear model (such as hybrid pi

model) cannot be employed.

• We must use large-signal model of the transistor, such as Eber-Molls

model, the Gummel-Poon model, the VBIC model. For MOSFET, the

BSIM model is popular.

• Design of high power circuits is more of an art. A lot of experience is

needed.

• Usually nonlinear circuit simulator is used (such as SPICE based circuit

simulator). Simulation algorithms such as nonlinear transient simulation

for time-domain and harmonic-balance (HB) method for frequency-

domain are usually employed, see [5] for a primer into the HB method.

• The active device model is very important, as it affects the accuracy of

the simulation result.

4


Large-Signal Model of Active

Components (2)

• Most bipolar junction transistor and field effect transistor manufacturers

provide SPICE based model of their device online, these are usually

Gummel-Poon model or VBIC model for BJT and BSIM model for FET.

• These models usually come in the form of a netlist of a sub-circuits,

which we can easily incorporate into our schematic using commercial

circuit simulators.

• Here a design example of Class A power amplifier will be shown. This

can also be applied to Class AB and Class B. Class C, E, F and others

will not be discussed in depth due to lack of time.

• Please refer to Cripps [3] for more details.


Large-Signal Model for Bipolar

Junction Transistor (BJT)

CC

CE

rB

rC

rE

VBC

VBE

B

E

C

R

ECI

β

F

CCI

βLEI

LCI

ECCC II −

As an example see http://www.designers-guide.org/Modeling/

and

eesof.tm.agilent.com/docs/iccap2002/ MDLGBOOK/

7DEVICE_MODELING/3TRANSISTORS/2VBIC

for more information on VBIC models.

• The most popular large-signal model for BJT is the SPICE Gummel-Poon(SGP) model (See Ref [6] for further details). A more recent alternative to the SGP model is the Vertical Bipolar Intercompany Model (VBIC) model which offers more accuracies as compared to SGP model.

• The SPICE Gummel-Poon model is based on the device physics of bipolar junction transistor. A simplified version is shown below.

C

B

E

5


Relationship Between Large and

Small-Signal Models

IC

VCE

0

IB1

IB2

IB3

IB4

IB5

D.C. load line

Small-signal model

Large-signal model

CC

CE

rB

rC

rE

VBC

VBE

B

E

C

R

ECI

β

F

CCI

βLEI

LCI

ECCC II −


Large-Signal Model for MOS Field

Effect Transistor (1)

• For MOSFET, the current industry standard is the BSIM (Berkeley Short-channel IGFET Model, IG stands for insulated-gate) model.

• BSIM is a physics-based threshold model of field-effect transistor. It is accurate, scalable, robust and predictive MOSFET SPICE model for circuit simulation and CMOS technology development. It is developed by the BSIM Research Group in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley.

• Optimized for modeling MOSFET in VLSI circuits, deep submicron technology (<0.25µm channel length).

• Various flavors (in the order of increased complexities and accurracy) e.g. BSIM1, BSIM2, BSIM3, BSIM4 and BSIMSOI.

• Official homepage: http://www-device.eecs.berkeley.edu/~bsim3/

• See Massobrio & Antognetti [6] for more information on large signal field effect transistor modeling.

6




• SPICE model for NMOS field-effect transistor.

CGD

ECCC II −

G

D

S

B

CGS

CGB

CDB

CSB

RD

RS

iD

DDB

DSB

G

D

S

B

PN+

S GD

N+P+

B

SiO2

Silicon substrate

(semi-insulating)




• In recent year there is an alternative to BSIM, based on physics-based

surface potential or inversion charge based model.

• This model is called PSP MOSFET model and is jointly developed by

Pennsylvania State University and Philips Semiconductor. PSP

probably stands for (Pennsylvania or Philips Surface Potential).

• The PSP model includes an accurate description of all physical effects

important for modern and future CMOS technologies.

• See

http://www.semiconductors.philips.com/Philips_Models/mos_models/ps

p/ and http://pspmodel.ee.psu.edu/introductiontopsp.asp for more

information.

7


2.0 Basic Power Amplifier

Design


Amplifier Classification (1)

• According to signal level:

– Small-Signal Amplifier.

– Power Amplifier (Large-Signal Amplifier).

• According to dc biasing scheme:

– Class A.

– Class B.

– Class AB.

– Class C.

Almost all small-signal amplifiers are Class A

8


Amplifier Classification (2)

VCE

Rc

Vcc

VCE

IC

Rc

Vcc

VCE

IC

Re

IC

IB=0

D.C. load line

Class A

Class AB

Class B

Class C

cCCEcc RIVV +=

( )ecCCEcc RRIVV ++=

D.C. Load

Line

equation

or


Important Parameters for Power

Amplifier

• Maximum output power.

• Efficiency (%).

• Harmonic Distortion or Linearity.

• Large-signal power gain (dB) / maximum power rating (W).

• Operating voltage (V).

• Bandwidth (Hz).

• Isolation.

9


Class-A Power Amplifier Schematic

Template

Vcc

Rb1

Rb2

Re

Cc1

Cc2

Ce

L1

L2

L3

Cd

Output

Matching

Network

Input

Matching

Network RL

t

vb

t

vc

• Low efficiency (<50%).

• High linearity.

• Suitable for wideband system.

• Suitable for low voltage system.

Note that most power

amplifiers are of CE or

CC configurations.


Class-B Power Amplifier Schematic

Template (Push-Pull Configuration)

Vcc

Rb

10


Class-C Power Amplifier Schematic

Template

11

Amplifier Large-Signal Response – 1

Tone Excitation (1)

• Consider an amplifier which can be characterized by a power series

expansion of it’s input.

• If the input voltage is a sinusoidal signal (1 Tone), and considering up to

3rd order:


( )tvo

( )tvi

( ) ( ) ( ) ( ) ...

3

3

2

21 TOHtvtvtvtv iiio +++= ααα

( ) ( )tAtvi

ωcos=

( ) ( ) ( ) ( )tAtAtAtvo

ωαωαωα33

3

22

21coscoscos ++≅

( ) ( )[ ] ( ) ( )[ ]

[ ] ( ) ( ) ( )tAtAtAAA

ttAtAtA

ωαωαωααα

ωωαωαωα

3cos2coscos

3coscos32cos1cos

3

34

12

22

12

34

3

1

2

22

1

3

34

12

22

1

1

++++=

++++=

DC term Fundamental frequency

term (Po)

1st harmonic

term (P1)2nd harmonic

term (P2)

|Vi(f)|

f

|Vi(f)|

f

(2.2)

(2.1)( )( )12coscos

2

12+= θθ

( )( )θθθ 3coscos3cos4

13+=

Typically α3

is negative

Amplifier Large-Signal Response - 1

Tone Excitation (2)

• Now converting all powers into dB scale, assuming the system

impedance is Zo

(real) and we are referencing with respect to 1mW.

• Input power:

• Fundamental:

• Similarly we can show that:

• 1st harmonic:

• 2nd harmonic:


2

2

1AP

oZin

= ( )001.0/log102_

2

oZ

A

dBminP =

( )[ ][ ] ( )

1_

2

34

31_

2

22

34

31_

log20log20

001.0/log102

ααα

αα

+≅++=

+=

dBmindBmin

Z

A

dBmo

PAP

APo

Pin/1mW

( ) 30log102 2

22__1−+= α

oz

dBmindBmPP

( ) 60log203 32__2 −+= αoz

dBmindBmPP

Pin/dBm

0

Slope=1

Slope=2

Slope=3

(2.3a)

(2.3b)

(2.3c)

(2.3d)

Active component

goes into

saturation

12



Tones Excitation (1)

( ) ( ) ( ) ( ) ...

3

3

2


( ) ( ) ( )tAtAtvi 2211

coscos ωω +=

( ) ( )

( ) ( )

( ) ( )

( ) ( )

( ) ( )tt

tt

tAAtAA

tAAAA

tAAAA

AAAA

AAAA

124

3

124

3

12

214

3

214

3

21

212122121221

2

2

1232

33

234

3

212

1

2

2132

33

134

3

111

2cos2cos:2

2cos2cos:2

coscos:

cos:

cos:

1

2

231

2

23

2

2

132

2

13

ωωωωωω

ωωωωωω

ωωαωωαωω

ωαααω

ωαααω

αα

αα

−++±

−++±

−++±

++

++

Component of interest

in implementing mixer

circuit

Component of interest

in implementing amplifier

Undesirable components,

cause Intermodulation

Distortion (IMD).

ff1-f2

2f1-f2 2f

2-f1

f2

f1

2f1

f1+f2 2f

2

3f1

3f2

2f1+f

2 2f2+f

1

|Vo|

IMD

ff1

f2

|Vi|

2 sinusoidal signal

At f1

and f2

(2.4)

( )tvo

( )tvi

(2.5a)

(2.5b)

(2.5c)

(2.5d)

(2.5e)

Note that we interchage

f and ω freely




• Let A1 = A2 = A, and α3 << α1.

• Now converting all powers into dB scale, assuming the system

impedance is Zo (real) and we are referencing with respect to 1mW.

• As in 1 Tone excitation case, we again notice that:

– Fundamental Component: The output power at f1 and f2 (Po_f1, Po_f2)

increases with slope = 1 with respect to Pin in dBm (for Pin sufficiently

small).

– Mixing Component: The output power at f1-f2 and f1+ f2 increases

with slope = 2 with respect to Pin in dBm.

– Intermodulation Component: The output power at 2f1±f2 and 2f2±f1increases with slope = 3 with respect to Pin in dBm.

( ) ( )tAA1

2

34

9

11cos: ωααω + ( ) 22

121222

349

121

1_ AAAPoo

ZZoααα

ω≅+=

( ) ( )ttAA

214

3

214

3

212cos2cos:2

3

3

3

3

ωωωωωωαα

−++±

( )tA21

2

221cos: ωωαωω −−

13




• For amplifier design, Po_f1 , Po_ 2f1-f2 and Po_ 2f2-f1 (or related components)

versus Pin are off interest. These can be plotted in dB scale are shown in

the next slide.

• Po_ 2f1-f2 and Po_ 2f2-f1 are typically very close to the fundamental terms,

thus are difficult to remove via band-pass filtering, and result in distorted

output signals.

• For mixer design, Po_ f1±f2 versus Pin are off interest.


Dynamic Range, 1dB Gain Compression and

Third Order Intercept Point

• Plotting P2ω2-ω1, Pω1 versus Pin in log scale, a few parameters can be

defined:out

Noise Floor

in

Dynamic range (DR)

1dB compression

point (Pin_1dB)

Saturation

Burn

out

Power gain Gp =

Pout(dB) - Pin(dB)

1dB Gain compression

Point

Spurious free

dynamic range

(DRf)

Third-order Intercept

Point (TOI)

1

1

1

3

Note: Spurious free

dynamic range is

important, for within

this range the 3rd

order component

power is less than

the noise power,

thus

distortion due to

this component is

negligible.

1ωP

2 ωω −

P

PIP

Po,mds

P1dB

14


Some Useful Relations for Large-

Signal Parameters

• Please refer to Chapter 2 of [7] and Chapter 4 of [1] for derivation.

• All parameters are in dB scale.

dBPPdBIP

101

+≅

IPPPP 231212 −=

− ωωω

( )mdsoIPf PPDR,3

2−=

( )21211

23

2

2 ωωωωω −−

−=− PPPPIP

Po/dBm

Pin/dBm

DRf

PIP

1ωP

212 ωω −

P

Po,mds

P1dB

≅10dB( )2111

222

ωωωω −

−+= PPPPIP

IMDPPIP 2

1

1

+=⇒ω

2112 ωωω −

−= PPIMDwhere

(2.2a)

(2.2b)

(2.2c)

IMD


Relationship between TOI, DR, DRf and

Linearity (1)

• Levels of input and output TOI, DR and DRf indicate the linearity of the

power amplifier.

• Highly linear power amplifier has small α2 and α3 compare to α1.

• Large DR implies small α2/ α1 ratio.

• Large DRf and TOI levels imply small α2/ α1 and α3/ α1 ratios.*

• In essence, a linear power amplifier

- Has larger DR and DRf.

- Has larger TOI levels.

*Here we ignore the effect of

higher order terms (H.O.T.) and

time delay effect.

Undesirable, suppress these

( ) ( ) ( ) ( ) ...

3

3

2


15

Relationship between TOI, DR, DRf and

Linearity (2)

• The 1dB Gain Compression point (P1dB) and the TOI point (PIP) are

important as both determine the dynamic range DR and the spurious-

free dynamic range DRf.

• The DRf is usually taken as the output power range where the large-

signal amplifier is considered linear.


Po/dBm

Pin/dBm

1ωP

212 ωω −

P

Po,mds

Smaller DRf (larger |α3|)

Larger DRf (smaller |α3|)

Suppose we have 2

amplifiers, with different

α3 values. Typically |α3|

<<1, so it’s logarithm is

negative. One with larger

|α3| (blue) and the

other with smaller |α3|

(red).

( ) ( ) ( ) 60log203 343

10_001.0

log102

4

3

21

2

103

3

12

−+ →=±

αα

ωω

ZPP

o

Measuring TOI Level

• Equation (2.2b) provides a convenient way to measure the third-order

intercept point (IP) output power PIP.

• A typical setup is shown below:


CW

Generator 1

at f1

CW

Generator 2

at f2

Power

Combiner

Spectrum

Analyzer

CW = Continuous sine Wave

Output power level for both

generators must be similar

Amplifier

under test

Note that cable and connector

loss has to be accounted for.

f1

f2

2f2-f1

2f1-f2

f

Power/dBm

IMD

IMDPPIP 2

1

1

+=ω

Note that the IMD

level will decrease

as CW generator

output is increased.

Po

Pin

PIP

1ωP

212 ωω −

P

16


For Class A, AB and B Power

Amplifier- Constant P1dB Contour

Typical Power

contour for FET at a

fixed frequency.

The power contour

is obtained

by varying the load

impedance while

ensuring conjugate

match at the input, then

the input power is slowly

increased until

1dB gain compression

is observed. ZL with

similar P1B are then

joint together. ΓL Plane

At fixed frequency !

P1dB Contour


For Class A, AB and B Power Amplifier

- Large-Signal Reflection Coefficients

Typical Γs and ΓL as a function of frequency for an FET amplifier

Large-signal Γs

Large-signal ΓL

17

Large-Signal Parameters Measurement

Setup

• A typical setup as shown below is used to obtain the large-signal data on

the previous slides.


Power

Meter

A

Power

Meter

B

Power

Meter

C

A A

B B

Transistor Amplifier

Under Test

D.C.

Supply

Load

Signal

Generator

Input

tuning

Stub

Output

tuning

Stub

For measuring the

amount of mismatch

at input

For measuring

Input power

For measuring

Output power

Variable

Attenuator

RF choke

Directional

coupler


Example 2.1 – Class-A Power Amplifier

Design

• In this example we would like to design a single transistor Class-A

power amplifier for a battery operated device at operating frequency fo =

868.0 MHz.

• The amplifier is driven by a source with 50Ω source impedance and

with available power level of PA= -5.0 dBm or 0.32 mW. The output

power into a 50Ω load is required to be 10.0 mW or 10 dBm.

• The transistor chosen for the job is BFG520 from Philips

Semiconductors. This is an NPN wideband transistor, with fT = 9 GHz,

IC(max) = 70 mA and maximum power dissipation of 300 mW. Using a

transistor with fT > 5×fo allows us to reduce the dc collector current (IC),

thereby reducing idle power dissipation.

• Here we rely on Agilent Technologies ADS 2003C software for the

analysis.

18


Example 2.1 - Class A Power Amplifier

Design Cont…

• The basic amplifier core circuit.

• DC analysis is performed to find the transistor quiescent point.

DC analysis results:

Vcc = 3.3 V

Ic = 10.8 mA

VCE = 2.14 V

Ideal voltage swing = 2.14 V

3.30 V

811 mV

811 mV811 mV

811 mV

811 mV

811 mV

2.14 V

2.14 V 2.14 V

2.14 V

2.14 V

2.14 V2.14 V

2.14 V2.14 V

2.14 V

DC

DC1

DC-11.6 mA

V_DC

VCC

Vdc=3.3 V

811 uA

R

RB2

R=1 kOhm

Port

P1

Num=1

Port

P2

Num=2

10.7 mA

L

L1

R=

L=100.0 nH

0 AC

CD1

C=100.0 pF

0 AC

CD2

C=22.0 pF

10.7 mA

10.8 mA

-10.8 mA

pb_phl_BFG520_19921215

Q1 L

LB

R=

L=100.0 nH

885 uA

R

RB1

R=1.5 kOhm

11.6 mA

R

RC

R=100 Ohm

Input

Terminal

Output

TerminalmW0.38V3.3mA5.11 =⋅== ccccdc VIP

%3.26100 )( Efficiency lTheoretica38

10=×=η

%5.25100 (PAE)

Efficiency AddedPower lTheoretica

38

32.010=×=

−

This is within the limit

of ideal efficiency of

50% for Class-A PA

A compromise has

to be made in terms

of voltage swing

and IC, owing to the

dc biasing circuit

chosen.



Design Cont…

• Performing a load pull test to find the optimum load impedance ZL.

VSupply

Vin

NOTE: Depending on the v alue of the internal v ariable 'f req', the v ariable TLArray Index will assume the integerv alue 0 if f req = dc, 1 if f req = f undamental,2 if f req = 1st harmonic etc. This prov idesthe index to the one dimensional arrayTLArray [ ]. Thus ef f ectiv ely the HarmonicBalance solv er will 'see' dif f erent load impedance/ref lection coef f icient at dif f erentf requencies. Similar action is perf ormed f or Source_Impedance Variable Equation.

This def ines the load andsource impedance at thef undamental and harnomics.Here we assume the circuitparasitics will short out thehigher harmonics

User can change theparameters in the Variable Equation"Stimulus_User_Setting"

VL

VAR

Load_Ref lection_Coef f ient

TLoad=TLArray [TLArray Index]

TLArray =list(r(ZL_dc),TL,r(ZL_2),r(ZL_3),r(ZL_4),r(ZL_5),r(ZL_6),r(ZL_7))

TLArray Index=int(min(abs(f req)/RFf req + 1.5, length(TLArray )))

EqnVar

V_DC

Vcc

Vdc=3.3 V

ParamSweep

Sweep1

Step=5

Stop=360

Start=0

SimInstanceName[6]=

SimInstanceName[5]=

SimInstanceName[4]=

SimInstanceName[3]=

SimInstanceName[2]=

SimInstanceName[1]="HB1"

SweepVar="TLphase"

PARAMETER SWEEPVAR

Stimulus_User_Settings

Ps_dBm=-5

Max_Rho=0.9

Max_Harmonic=5

RFf req=868 MHz

Zo=50

EqnVar

HarmonicBalance

HB1

Step=0.1

Stop=Max_Rho

Start=0

SweepVar="TLmag"

Order[1]=Max_Harmonic

Freq[1]=RFf req

HARMONIC BALANCE

VAR

Source_Impedance

Zs=ZsArray [ZsArray Index]

ZsArray =list(Zs_dc,Zs_1,Zs_2,Zs_3,Zs_4,Zs_5,Zs_6,Zs_7)

ZsArray Index=int(min(abs(f req)/RFf req + 1.5, length(TLArray )))

EqnVar

VAR

Load_Ref lection_Coef f icient_Sweep

TL=TLcenter+TLmag*exp(j*(TLphase/180)*pi)

TLcenter=0

r(x)=(x-Zo)/(x+Zo)

TLphase=0

TLmag=0

EqnVar

VAR

Load_Source_Impedance_at_Harmonics

Zs_7=1+j*0

Zs_6=1+j*0

Zs_5=1+j*0

Zs_4=1+j*0

Zs_3=1+j*0

Zs_2=1+j*0

Zs_1=Zo

Zs_dc=Zo

ZL_7=1+j*0

ZL_6=1+j*0

ZL_5=1+j*0

ZL_4=1+j*0

ZL_3=1+j*0

ZL_2=1+j*0

ZL_dc=1000000

EqnVar

P_1Tone

PORT1

Freq=RFf req

P=polar(dbmtow(Ps_dBm),0)

Z=Zs Ohm

Num=1

PA_core

X1

I_Probe

ISupply

I_Probe

ISource

I_Probe

ILoadS1P_Eqn

S1P1

Z[1]=Zo

S[1,1]=TLoad

C

Cc1

C=100.0 pF

C

Cc2

C=100.0 pF

Nonlinear

HB analysis

is applied. This

is a single-tone

analysis since there

is only one source.

Up to 5th harmonic

is considered.

(Max_Harmonic = 5)

one tone

source

(at 868 MHz)

PA

= Ps_dBm

or -5 dBm in

this instance.

Amplifier core

circuit (see previous

slide)

Expressions to set the

load and source

impedance at the

harmonics.

Expression to

sweep ΓL

across

the Smith Chart

in polar form.

Expressions to generate the correct

ΓL

and Zs

at each frequency

component during HB analysis

Source available

power = -5dBm

into 50Ω load.

19



Design Cont…

• Method of sweeping ΓL to cover the Smith Chart.

• Sweeping the

angle of ΓL from

0 to 360o,

at 5o interval and

the magnitude |ΓL|

from 0 to 0.9 at 0.1

step.

• Of course we

could refine this

by using smaller

steps at the expense

of greater computational

resources needed.

θ

|Γ|

Re Γ

Im Γ



Design Cont…

• The expressions on the ADS’s Data Display required to generate a

contour plot of load power PL at fundamental frequency on the Smith

Chart.

Eqn PL1_watt = re(0.5*VL[::,::,1]*conj(ILoad.i[::,::,1]))

Eqn PL1_dBm = 10*log10(PL1_watt) + 30

Eqn PL1_dBm_max = max(max(PL1_dBm))

Eqn PL_step = 0.2

Eqn NumLine = 6

Eqn contour_PL1_dBm = contour(PL1_dBm, PL1_dBm_max-0.01-[0::NumLine-1]*PL_step)

Eqn contour_PL1_dBm_polar = indep(contour_PL1_dBm)*exp(i*(contour_PL1_dBm/180)*pi)

PL1_dBm_max

9.151

Create a contour plot for load power. This actually produces a 3D array. The indexes to thearray corresponds to 1) the Power 2) TLmag and 3) TLphase. This can be plotted on X-Y plotwhere TLmag forms the x-axis, and TLphase forms the y-axis.

Change the contour plot into polar form. The function indep( ) returns the independent variableassociated with the datatype contour_PL1_dBm. There are two independent variables associatedwith contour_PL_dBm, since we varies the magnitude and phase of TL. The innermost independentvariable is TLmag, since it is embedded in the Harmonic Balance simulation control. So this isreturned by the indep( ) function. Datatype contour_PL1_dBm itself is simply the phase in degrees. So this can be easily converted in polar form.

Compute Load power and Creating Load Power ContourVL[::,::,1] extracts the fundamental component of the load voltage, for all (as indicated by the symbol '::') TLmag and TLphase. Same can be said for ILoad.i[::,::,1]

Eqn Distortion_step = 0.05

Eqn N_step = 3

Maximum load

power (9.151 dBm)

at fundamental

frequency, with input

power -5 dBm into

50Ω load, input

not match condition.

freq

TLphase=0.000, TLmag=0.0000.0000 Hz868.0MHz1.736GHz2.604GHz3.472GHz4.340GHz



Mix

012345

012345

012345

Note: Plotting out the

variable ‘Mix’ in the Data

Display shows the index to

the frequency components

22



Design Cont…

• Finally, upon adding the input and output transformation networks.

• Note that we are performing conjugate matching at the input.

This defines the load andsource impedance at the

fundamental and harnomics.Here we assume the circuitparasitics will short out the

higher harmonics

User can change theparameters in the

Variable Equation"Stimulus_User_Sett ing"

Vin

VL

VSupply

VAR

Load_Reflection_Coeffient

TLoad=TLArray[TLArrayIndex]

TLArray=list(r(ZL_dc),TL,r(ZL_2),r(ZL_3),r(ZL_4),r(ZL_5),r(ZL_6),r(ZL_7))

TLArrayIndex=int(min(abs(freq)/RFfreq + 1.5, length(TLArray)))

EqnVar

VAR

Load_Reflection_Coefficient_Sweep


TLcenter=0

r(x)=(x-Zo)/(x+Zo)

TLphase=0

TLmag=0

EqnVar

VAR


Zs_7=1+j*0

Zs_6=1+j*0

Zs_5=1+j*0

Zs_4=1+j*0

Zs_3=1+j*0

Zs_2=1+j*0

Zs_1=Zo

Zs_dc=Zo

ZL_7=1+j*0

ZL_6=1+j*0

ZL_5=1+j*0

ZL_4=1+j*0

ZL_3=1+j*0

ZL_2=1+j*0

ZL_dc=1000000

EqnVar

VAR

Source_Impedance

Zs=ZsArray[ZsArrayIndex]

ZsArray=list(Zs_dc,Zs_1,Zs_2,Zs_3,Zs_4,Zs_5,Zs_6,Zs_7)

ZsArrayIndex=int(min(abs(freq)/RFfreq + 1.5, length(TLArray)))

EqnVar

VAR

Stimulus_User_Settings

Ps_dBm=-5

Max_Rho=0.9

Max_Harmonic=5

RFfreq=868 MHz

Zo=50

EqnVar

HarmonicBalance

HB1

Step=

Stop=

Start=

SweepVar=


Freq[1]=RFfreq

HARMONIC BALANCE

C

C3

C=5.6 pF

C

C4B

C=0.68 pF

C

C4A

C=10.0 pF

L

L2

R=

L=4.7 nHP_1Tone

PORT1

Freq=RFfreq


Z=Zs Ohm

Num=1

I_Probe

ISource

C

C1B

C=0.47 pF

C

C1A

C=4.7 pF

L

L1

R=

L=8.2 nH

C

C2

C=8.2 pF

R

RL

R=50 Ohm

V_DC

Vcc

Vdc=3.3 V

PA_core

X1

I_Probe

ISupply

C

Cc1

C=100.0 pF

C

Cc2

C=100.0 pF

Input

transformation

network

Output

transformation

network

Zin*

Zin

ZLopt



Design Cont…

• The results at PA = -5 dBm:

Eqn Zin = Vin/ISource.i

freq

0.0000 Hz868.0MHz1.736GHz2.604GHz3.472GHz4.340GHz

Zin

<invalid>36.417 + j17.783

-1.000 + j0.000-1.000 - j7.016E-17

-1.000 + j0.000-1.000 + j0.000

Eqn PL = (mag(VL)*mag(VL))/(2*50)

freq

0.0000 Hz868.0MHz1.736GHz2.604GHz3.472GHz4.340GHz

PL

0.0000.013

3.031E-65.878E-91.475E-9

2.244E-100.5 1.0 1.5 2.00.0 2.5

-1.0

-0.5

0.0

0.5

1.0

-1.5

1.5

time, nsec

Vin

t, V

VLt,

V

Eqn VLt = ts(VL) Eqn Vint = ts(Vin)

Time-domain waveform at input

and load resistor

23



Design Cont…

• Now we sweep the source PA to perform a gain compression test:

This defines the load andsource impedance at the

fundamental and harnomics.Here we assume the circuitparasitics will short out the

higher harmonics

User can change theparameters in the

Variable Equation"Stimulus_User_Setting"

Vin

VL

VSupply

HarmonicBalance

HB1

Step=1

Stop=5

Start=-20

SweepVar="Ps_dBm"


Freq[1]=RFfreq

HARMONIC BALANCEVAR

Stimulus_User_Sett ings

Ps_dBm=-5

Max_Rho=0.9

Max_Harmonic=5

RFfreq=868 MHz

Zo=50

EqnVar

VAR

Load_Reflection_Coeffient

TLoad=TLArray[TLArrayIndex]

TLArray=list(r(ZL_dc),TL,r(ZL_2),r(ZL_3),r(ZL_4),r(ZL_5),r(ZL_6),r(ZL_7))

TLArrayIndex=int(min(abs(freq)/RFfreq + 1.5, length(TLArray)))

EqnVar

VAR

Load_Reflection_Coefficient_Sweep


TLcenter=0

r(x)=(x-Zo)/(x+Zo)

TLphase=0

TLmag=0

EqnVar

VAR


Zs_7=1+j*0

Zs_6=1+j*0

Zs_5=1+j*0

Zs_4=1+j*0

Zs_3=1+j*0

Zs_2=1+j*0

Zs_1=Zo

Zs_dc=Zo

ZL_7=1+j*0

ZL_6=1+j*0

ZL_5=1+j*0

ZL_4=1+j*0

ZL_3=1+j*0

ZL_2=1+j*0

ZL_dc=1000000

EqnVar

VAR

Source_Impedance

Zs=ZsArray[ZsArrayIndex]

ZsArray=list(Zs_dc,Zs_1,Zs_2,Zs_3,Zs_4,Zs_5,Zs_6,Zs_7)

ZsArrayIndex=int(min(abs(freq)/RFfreq + 1.5, length(TLArray)))

EqnVar

C

C3

C=5.6 pF

C

C4B

C=0.68 pF

C

C4A

C=10.0 pF

L

L2

R=

L=4.7 nHP_1Tone

PORT1

Freq=RFfreq


Z=Zs Ohm

Num=1

I_Probe

ISource

C

C1B

C=0.47 pF

C

C1A

C=4.7 pF

L

L1

R=

L=8.2 nH

C

C2

C=8.2 pF

R

RL

R=50 Ohm

V_DC

Vcc

Vdc=3.3 V

PA_core

X1

I_Probe

ISupply

C

Cc1

C=100.0 pF

C

Cc2

C=100.0 pF

We sweep the

variable ‘Ps_dBm’



Design Cont…

• 1dB Gain Compression test result.

m1Ps_dBm=m1=10.738

-6.000

-15 -10 -5 0-20 5

0

5

10

-5

15

Ps_dBm

PL_dBm

m1

Slope of 1

Thus, P1dB ≅ 10.74 dBm

meeting our specs.

24



Design Cont…

• Snapshot of the completed hardware.



Design Cont…

• Measurement at 868 MHz.

Freq. = 868 MHz

+10.5 dBm1st harmonic

-11.0 dBm

Output of the amplifier when driven with a frequency synthesizer with

Pin

= -3.0 dBm into 50Ω load, fin

= 868.0 MHz. Averaging = 10

25



Design Cont…

• P1dB gain compression measurement.

+16 dB

+15 dB

1 dB Gain

Compression

point


Typical Parameters for Medium Power

Amplifiers

• Operating frequency range: 0.1-10GHz.

• Output power at 1dB gain compression: +15Bm (31.6mW) to +30dBm

(1000mW).

• Power gain at 1dB gain compression: 12 - 20 dB.

• Furthermore VCE and IC will be specified for BJT and VDS and ID will be

specified for FET. For MMIC, the supply voltage and current will be

specified.

• Noise Figure: 3.0dB or greater.

• TOI input level: +10 to +15 dBm.

• TOI output level: +20 to +40 dBm.

• For MMIC, most of the time the source and load impedance is internally

matched to 50Ω.

26


3.0 Basic Mixer Design


Mixers

• A mixer uses the nonlinearity of a diode, transistor or FET under large-

signal operation to generate an output spectrum consisting of the sum

and difference frequencies of two input signals.

• A mixer used for RF receiver usually consists of three ports, the RF, LO

(Local Oscillator) and IF (Intermediate Frequency) ports.

• There are several types of mixers, the simplest being the Single-Ended

Mixer. The single ended mixers are often used as components for

more sophisticated mixers.

• The Balanced Mixer combines two or more identical single-ended mixer

to give better input SWR or matching and higher isolation between the

RF/LO ports.RF

LO IF

Symbol and

terminals of

a mixer

28

Simplified Analysis of the Diode Mixer

• Under DC condition the diode

voltage and current are VD and ID.

• Imagine the RF chokes (RFC)

present a high impedance to the

AC voltage and current.

• The input AC voltage vd will

modulate the diode junction

voltage, which results in variation

of the diode current id.

• The current flowing across the

RFC is assumed constant, thus the

change in current id is forced

through the output of the mixer.

• Due to the nonlinear nature of the

PN junction, id contains the sum

and difference components.December 2010 2006 by Fabian Kung Wai Lee 55

L2

L1

Cd

RFC

RFC

VCC

VD

+ vd I

D High

impedanceHigh

impedance idI

D+ i

d

−≅+

+

1TnV

dvDV

eIiIsdD

−= 1TnV

DV

eIIsD

21vvv

d+=

( ) ( )[ ]L++≅

−=

2

2

11

T

d

T

dTnV

DV

TnV

dv

TnV

DV

nV

v

nV

v

ssdeIeeIi

( ) ( )[ ]L++≅++

2

2

1 2121

TT

TnV

DV

nV

vv

nV

vv

sdeIi

Causes mixing effectAffects

conversion

gain

DC:

DC with RF

and LO:( )tAv

111cos ω= ( )tAv

222cos ω=

Mixer Types (1)

• Following the definition by [4], mixer can be classified depending on the

signaling type on the RF terminals.

• By signaling type we imply whether the RF input signal is single-ended or

differential (double-ended).

• Sometimes two or more mixers can be combined to form a Balanced

architecture.


Single-Ended Mixer

RF

LO IF

Double-Ended Mixer

RF

LO IF

+ -

Differential RF input

Note:

The LO input can be

single-ended or

differential.

29

Mixer Types (2)

• Example of balanced type mixers.

Chapter 9 (May 2014) 2014 by Fabian Kung Wai Lee 57

RF

IF

Single-Balanced Mixer

(Can be viewed as

two single-ended

mixers combined

together)

LO

Power

Splitter

With

balun

Power

Splitter

Power

Combiner

Double-Balanced Mixer (Can

be viewed as four single-ended

mixers or two single-balanced

mixers)

+

-RF

IF

LO

Power

Splitter

with

balun

Power

Splitter

Power

Combiner

with balun

Each mixer

in turn can be

split into 2

complementary

mixers.


Conversion Gain and Leakage (1)

• If a diode is used for the nonlinear element, there is no gain, i.e. the

conversion gain GC (dB) is negative. Sometimes this negative value is

called conversion loss instead.

• If BJT or FET is used as the nonlinear element, there is usually a

positive conversion gain GC (dB).

• A major issue with single-ended mixer is the leakage between the two

RF inputs. This is due to the fact that the power combiner used is

usually narrowband, and the frequency difference between RF and LO

input is usually substantial.

RF

LO IF

Power Leakage

Power LeakageRF

LO IF

Power Leakage Power Leakage

Electrical energy

into LO terminal

leaks out at RF and

IF terminals.

Electrical energy

into RF terminal

leaks out at LO and

IF terminals.

30

Conversion Gain and Leakage (2)

• The simplicity and performance of single-ended mixer make it very

attractive in terms of cost, productivity and conversion loss. However

this type of mixer usually exhibits higher leakage (e.g. lower isolation

between ports), spurious products and low operating bandwidth.

• Leakage due to LO can be reduced by using differential RF input and

differential IF output.

• Balanced mixers have better isolation between ports (lower leakage),

lower spurious products. But this comes in terms of higher complexity,

and usually larger conversion loss.

• A single-ended signal can be converted into differential signal and vice

versa by using a Balun (balanced-unbalanced converter).

• Examples of balun are center-tapped transformer, and various type of

directional couplers (see notes on RF Passive Circuits Design).



Example 3.1 – 430 MHz Single-Ended

Discrete BJT Mixer Design

NOTE:By convention for a successful analysis of mixer:1. Set the RF input to PORT 1, IF output to PORT 2 and LO input to PORT 3 (by editing the NUM property).2. Set the signal with largest amplitude to Freq[1] to ensure convergence of the HB method.

Input matching network

Output matching network

VARVAR1

RF_pow=-20

freq_RF=430 Mhzfreq_LO=410 Mhz

EqnVar

CCc2

C=15.0 pF

CCdecC=1000.0 pF

Options

Options1

MaxWarnings=10

GiveAllWarnings=yesI_RelT ol=1e-6

V_RelTol=1e-6TopologyCheck=yesTemp=23.85

OPTIONS

HarmonicBalance

HB1

Other=OutVar="RF_pow"NoiseOutputPort=2

NoiseInputPort=1FreqForNoise=freq_RF-freq_LONLNoiseMode=yesOrder[2]=5

Order[1]=7

Freq[2]=freq_RFFreq[1]=freq_LOMaxOrder=7

HARMONIC BALANCE

DCDC1

DC

R

RbR=47 kOhm

RR2R=1000 Ohm

P_1TonePrf

Freq=freq_RF

P=polar(dbmtow(RF_pow),0)Z=50 Ohm

Num=1

TermTerm3

Z=50 Ohm

Num=2

P_1TonePLO

Freq=freq_LOP=polar(dbmtow(0),0)

Z=50 OhmNum=3

LLm1

R=

L=68.0 nH

I_ProbeISource

CCm3C=270.5 pF

LLm3

R=

L=800.0 nHCCm2

C=97.0 pF

I_ProbeILoadC

Cc3C=330.0 pF

CCm1C=0.33 pF

C

Cc1C=330.0 pF

LLb

R=

L=220.0 nH

CCbyp1C=1000.0 pF

V_DC

SRC1Vdc=3.0 V

RReR=330 Ohm

pb_phl_BFR92A_19921214Q1

For more information, please refer to the document entitled:

“Designing A Single-Ended UHF BJT Mixer Using the ADS

Software” Sep 2001 by F.Kung.

http://pesona.mmu.edu.my/~wlkung/ADS/ads.htm

Adding a series LC network (from E to Gnd)

tuned to IF frequency will boost

the conversion gain, at the expense of

larger LO leakage through RF input.

RF = 430 MHz

LO = 410 MHz

IF = 20 MHz

IF

LO

RF

31


Example 3.1 Cont...

RF source: frequency = 430.0MHz, Power = -20dBm into 50Ω load.

LO source: frequency ≈ 410 MHz , Power = -5.48dBm into 50Ω load.

Power supply for mixer: 3.0V.Local Oscillator

Input

RF InputIF Output

To 2.7-3.3V D.C.

Source

1.57mm thick FR4 printed

circuit board

BNC to PCB

adapter

SMA to PCB

adapter

Measurement at IF output,

around 17MHz

≅60ns

Simplified Analysis of the BJT Mixer

• A similar analysis as in the

diode mixer can be applied to

the single-ended BJT mixer.

• Since there is current

amplication (β), there is the

possibility of conversion gain

greater than unity.

• The variation in the BE

voltage can be injected by the

approach shown on the

diagram or using a power

combiner.

December 2010 2006 by Fabian Kung Wai Lee 62

−= 1TnV

BEV

eIIEOC

β

VBE+vRF-vLO vLO

vRF

High

impedance

High

impedanceICQ

ICQ+ic

ic

At DC:

DC with RF

and LO:

−≅+

++

1TnV

RFvLOvBEV

eIiIEOcC

β

( ) ( )[ ]L++≅⇒++

2

2

1

nV

vv

nV

vv

EOceIi β

Transistor’s β

and VBE

affects the

conversion

gainCauses mixing effect

Let VBE be the DC bias, vRF and vLO are the

AC RF and LO voltages:

( ) ( )( )

−+++≅+⇒ ++

112

2

1L

T

LORF

T

LORFTnV

BEV

nV

vv

nV

vv

EOcCeIiI β

Considering only the AC term (ic):

32


Example 3.2 – 868 MHz Single-Ended

Discrete BJT Mixer Design

C

Cc2

C=470.0 pF

C

CB1

C=470.0 pF

C

CB2

C=100.0 pF

C

CD1

C=100.0 pFC

CD0

C=2.2 uF

R

RD1

R=100 Ohm

Port

VCC

Num=4

R

RD2

R=4.7 kOhm

Diode

DD2

Model=LSR976

Diode

DD1

Model=BZX284-C3V3

Port

IF_out

Num=2

Port

LO_in

Num=3

Port

RF_in

Num=1

C

C1B

C=1.5 pF

C

C1A

C=1.5 pF

L

L1

R=

L=33.0 nH

C

C2

C=22.0 pF

C

Cc1

C=3.3 pFC

C3

C=4.7 pF

C

C4

C=1.5 pF

L

L2

R=

L=10.0 nH

R

RC

R=470 Ohm

pb_phl_BFR92A_19921214

Q1

C

C5

C=100.0 pF

L

LC

R=

L=100.0 nH

R

RB1

R=470 Ohm

L

LB

R=

L=100.0 nH

R

RB2

R=1.8 kOhm

R

RB3

R=100 Ohm

RF = 868 MHz

LO = 818 MHz

IF = 50 MHz

Power Supply

LO Input

RF Input

IF Output

Power combiner


Example 3.2 Cont…

• Snapshot of the Mixer prototype.

33


Example 3.2 Cont…

• Measurement setup.

50.0 MHz, -22 dBm

A RF signal generator, IFR2023B supplies the RF signal to the mixer RF input, at 868.0 MHz and -20.0 dBm

power level (into 50Ω load). The frequency synthesizer built for this project drives the LO input,

at 818.0 MHz and -2.4 dBm power level (into 50Ω load).


Example 3.2 Cont…

• LO leakage at the RF terminal output.

818.0 MHz, -12 dBm

34


Block Diagram of Single-Balanced

Mixer (1)

RF and LO power is

divided equally to the

two identical single-ended mixer.

Hence the term ‘balanced’

RF

Rbias

Cc2

L1

Vcc

Cd

RL

Cc1

L2

Input

matching

network

LO

Cc3

L3

Cc4

Input

matching

network

Low-pass

filter

Low-pass

filter

Power

Combi

-ner

3dB Hybrid

(90o or 180o)

The RF and LO inputs are

split into 2 equal halves and

imposed on the 2 diodes.

This type of configuration is

better known as Single-Balanced

Mixer.


Block Diagram of Single-Balanced

Mixer (2)

• 3dB hybrid directional coupler or junction (either 90o or 180o) are used to combine two identical single-ended mixers.

• 90o hybrid junction gives better wideband input SWR at the RF and LO inputs (this principle is also used in balanced amplifier).

• 180o hybrid junction gives better RF/LO isolation. This balanced mixer can also suppress even harmonics of LO input.

• Both types can also give cancellation of AM noise from the local oscillator.

• For details of mathematical analysis see chapter 10 of Pozar [8].

35


More on Mixer Types

• Double-Balanced Mixer - suppresses even harmonics of both LO and

RF inputs. Give good conversion gain. Also has good RF/LO isolation.

Can be implemented using diode ring or using differential amplifier on

integrated circuit.

• Image Rejection Mixer.

• In integrated circuit, a double-balanced mixer can be implemented

using the ‘Gilbert Cell’, which is a modification of the two-quadrant

analog multiplier. The two-quadrant analog multiplier is essentially an

emitter (or source coupled) differential amplifier. See Gray & Meyer [7].

Most commercial integrated circuit mixer uses this method.

Example 3.3 - Double-Ended Balanced

Mixer in Integrated Circuit

• This type of mixer is called the

Gilbert Cell/Mixer.


Vcc

+

-

v2

-

+

v1

Vout = R(Ic1 - Ic2)

+

-

R RIc1 I

c2

IEE

Differential input:

Hence the term

double-ended.

Popular

General purpose

Gilbert cell

mixer ICs:

MC1496 – 100 MHz

SA602AD – 200 MHz

SA612AD – 500 MHz

AD8342 – 500 MHz

36


Example 3.4 - Discrete Double-Ended

Balanced Mixer Using Diode Ring

Bottom Side

Another

varactor-tuned

BPFImplemented on the PCBitself

Implemented on the PCBitself

Port

TP5003

Num=5

JUNCAP

D5005

Model=JUNCAPM1

JUNCAP

D5004

Model=JUNCAPM1

Diode_Model

DIODEM1Port

PIF

Num=3

L

L5008

R=

L=470.0 nH

C

C5052

C=82.0 pF

L

L5051

R=

L=150.0 nH

R

R5051

R=51 Ohm

L

L5004b

C

C5055

L

L5004a

Port

PRFE2

Num=1

C

C5019-23

C=77.0 pF

C

C5024

C=1.0 nF

R

R5012

R=100 kOhm

R

R5060

R=330 kOhm

Port

FECTRL

Num=2

Juncap_Model

JUNCAPM1MSUB

MSub1

T=1.38 mil

Cond=5.8E+7

Er=4.5

MSub

R

R5052

R=0 Ohm

Diode

DIODE2

Model=DIODEM1

Diode

DIODE1

Model=DIODEM1

Diode

DIODE3

Model=DIODEM1

Diode

DIODE4

Model=DIODEM1

XFERTAP

T5052

XFERP

T5051a

XFERP

T505b1

C

C5030C

C5032

C=8.2 pF

C

CL5005

L

L5005b

L

L5005a

C

C5053

C=6.8 pF

L

L5053

R=

L=15.0 nH C

C5054

C=16.0 pF

L

L5054

R=

L=15.0 nH

Port

RXINJ

Num=4

L

L5009

R=

L=1.0 nH

C

C5031

C=1.0 pF

MLIN

TL1

L=100.0 mi l

W=25.0 mil

Subst="MSub1"

C

C5017-18

C

C5029

RF power flow

IF power flow

Diode ring

Balun

IF trap, tuned to 44.85MHz

, shunts IF leakage to ground


Typical Performance Parameters for

Commercial Mixers

• Parameters for an integrated circuit mixer in the 1-3GHz range (for RF

power = -20dBm, LO power = -5dBm, Zo=50Ohm, VCC = 5.0V).

• Power supply: single polarity, 4.0-8.0V.

• Typical LO power requirement: -5dBm.

• Conversion gain GC: 6.5 - 10dB.

• Single Sideband (SSB) noise figure: 17dB.

• LO leakage at IF port: -25dBm.

• LO leakage at RF port: -30dBm.

• VSWR: RF - 1.5, LO - 2.0, IF - 1.5.

10 - high power circuits - multimedia universitypesona.mmu.edu.my/~wlkung/ads/rf/lesson10.pdf · 10...

Documents