16-bit microcontroller programming manual€¦ · 16-bit microcontroller programming manual...

FUJITSU MICROELECTRONICSCONTROLLER MANUAL

F2MC-16FX16-BIT MICROCONTROLLER

PROGRAMMING MANUAL

CM44-00203-1E

FUJITSU MICROELECTRONICS LIMITED

F2MC-16FX16-BIT MICROCONTROLLER

PROGRAMMING MANUAL

i

CONTENTS

■ Objectives and Intended ReadershipThe F2MC-16FX series products are original 16-bit one-chip microcontrollers that support

application specific ICs (ASICs). They are suitable for use in various types of industrial

equipment, office-automation equipment, on-vehicle equipment, and other equipment that is

required to operate at high speed in real-time mode.

■ Trademark

Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.

The company names and brand names herein are the trademarks or registered trademarks of

their respective owners.

■ Intended ReadershipThis manual is written for engineers involved in the development of products using the F2MC-

16FX series microcontrollers. It is designed specially for programmers working in assembly

language for use with F2MC-16FX series assemblers, and describes the various instructions

used with the F2MC-16FX series products. Be sure to read the entire manual carefully.

■ Configuration of this ManualThis manual contains the following 9 chapters and appendix.

CHAPTER 1 CPU

This chapter describes an overview of the F2MC-16FX CPU core and its sample

configuration.

CHAPTER 2 MEMORY SPACE

This chapter describes memory spaces in the F2MC-16FX CPU.

CHAPTER 3 DEDICATED REGISTER

This chapter describes the dedicated registers of the F2MC-16FX CPU.

CHAPTER 4 GENERAL-PURPOSE REGISTERS

This chapter describes the general-purpose registers of the F2MC-16FX CPU.

CHAPTER 5 PREFIX CODES

This chapter describes the prefix codes.

CHAPTER 6 INTERRUPTS

This chapter describes the interrupt functions and operations of the F2MC-16FX .

CHAPTER 7 ADDRESSING

This chapter describes the addressing mode for each instruction of the F2MC-16FX.

CHAPTER 8 INSTRUCTION OVERVIEW

This chapter describes the meanings of items and symbols used in explanations in

"CHAPTER 9 DETAILED INSTRUCTIONS".

ii

CHAPTER 9 DETAILED INSTRUCTIONS

This chapter describes each execution instruction used in the assembler in a reference

format.

APPENDIX

The appendix section includes lists and maps of instructions for the F2MC-16FX.

■ ReferencesThe following manuals should be referred along with this manual:

• F2MC-16FX/16L/16/16H/16F Assembler Manual

• F2MC-16FX Model-Specific Hardware Manual

iii

Copyright ©2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.

• The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering.

• The information, such as descriptions of function and application circuit examples, in this document are presentedsolely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICSdevice; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to usebased on such information. When you develop equipment incorporating the device based on such information, youmust assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICSassumes no liability for any damages whatsoever arising out of the use of the information.

• Any information in this document, including descriptions of function and schematic diagrams, shall not beconstrued as license of the use or exercise of any intellectual property right, such as patent right or copyright, orany other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICSwarrant non-infringement of any third-party's intellectual property right or other right by using such information.FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights orother rights of third parties which would result from the use of information contained herein.

• The products described in this document are designed, developed and manufactured as contemplated for generaluse, including without limitation, ordinary industrial use, general office use, personal use, and household use, butare not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangersthat, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly todeath, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch controlin weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificialsatellite).Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for anyclaims or damages arising in connection with above-mentioned uses of the products.

• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or lossfrom such failures by incorporating safety design measures into your facility and equipment such as redundancy,fire protection, and prevention of over-current levels and other abnormal operating conditions.

• Exportation/release of any products described in this document may require necessary procedures in accordancewith the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export controllaws.

• The company names and brand names herein are the trademarks or registered trademarks of their respectiveowners.

v

CONTENTS

CHAPTER 1 CPU .................................................................................................. 11.1 Overview of CPU ................................................................................................................. 21.2 Sample Configuration .......................................................................................................... 3

CHAPTER 2 MEMORY SPACE ............................................................................ 72.1 CPU Memory Space ............................................................................................................ 82.2 Linear Addressing Mode ...................................................................................................... 92.3 Bank Addressing Mode ..................................................................................................... 112.4 Memory Space Divided into Banks and Value in Each Bank Register .............................. 132.5 Data Configuration of and Access to Multi-byte Data in Memory ...................................... 14

CHAPTER 3 DEDICATED REGISTER ............................................................... 173.1 Dedicated Registers .......................................................................................................... 183.2 Accumulator (A) ................................................................................................................. 193.3 User Stack Pointer (USP) and System Stack Pointer (SSP) ............................................. 213.4 Processor Status (PS) ....................................................................................................... 233.5 Program Counter (PC) ....................................................................................................... 273.6 Direct Page Register (DPR) .............................................................................................. 283.7 Bank register (PCB, DTB, ADB, USB, SSB) ..................................................................... 29

CHAPTER 4 GENERAL-PURPOSE REGISTERS .............................................. 314.1 Register Banks in RAM ..................................................................................................... 324.2 Calling General-purpose Registers in RAM ....................................................................... 33

CHAPTER 5 PREFIX CODES ............................................................................. 355.1 Bank Select Prefix ............................................................................................................. 365.2 Common Register Bank Prefix (CMR) ............................................................................... 385.3 Flag Change Inhibit Prefix Code (NCC) ............................................................................ 395.4 Constraints Related to the Prefix Codes ........................................................................... 40

CHAPTER 6 INTERRUPTS ................................................................................. 436.1 Overview of Interrupts ....................................................................................................... 446.2 Interrupt Vector .................................................................................................................. 466.3 Interrupt Control Registers (ICR) ....................................................................................... 496.4 Non Maskable Interrupt (NMI) ........................................................................................... 516.5 Interrupt Flow (ICR) ........................................................................................................... 536.6 Hardware Interrupts ........................................................................................................... 556.7 Software Interrupts ............................................................................................................ 586.8 Multiple interrupts .............................................................................................................. 606.9 Exceptions ......................................................................................................................... 63

CHAPTER 7 ADDRESSING ................................................................................ 677.1 Effective Address Field ...................................................................................................... 687.2 Direct Addressing .............................................................................................................. 69

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7.3 Indirect Addressing ............................................................................................................ 71

CHAPTER 8 INSTRUCTION OVERVIEW ........................................................... 758.1 Instruction Overview .......................................................................................................... 768.2 Symbols (Abbreviations) Used in Detailed Instructions ..................................................... 778.3 Effective Address Field ...................................................................................................... 798.4 Execution Cycles ............................................................................................................... 80

CHAPTER 9 DETAILED INSTRUCTIONS .......................................................... 839.1 ADD (Add Byte Data of Destination and Source to Destination) ....................................... 849.2 ADDC (Add Byte Data of AL and AH with Carry to AL) ..................................................... 869.3 ADDC (Add Byte Data of Accumulator and Effective Address with Carry to Accumulator)

............................................................................................................................................ 879.4 ADDCW (Add Word Data of Accumulator and Effective Address with Carry to Accumulator)

............................................................................................................................................ 899.5 ADDDC (Add Decimal Data of AL and AH with Carry to AL) ............................................ 919.6 ADDL (Add Long Word Data of Destination and Source to Destination) ........................... 929.7 ADDSP (Add Word Data of Stack Pointer and Immediate Data to Stack Pointer) ............ 949.8 ADDW (Add Word Data of AL and AH to AL) .................................................................... 959.9 ADDW (Add Word Data of Destination and Source to Destination) .................................. 969.10 AND (And Byte Data of Destination and Source to Destination) ....................................... 989.11 AND (And Byte Data of Immediate Data and Condition Code Register) ......................... 1009.12 ANDL (And Long Word Data of Destination and Source to Destination) ......................... 1029.13 ANDW (And Word Data of AH and AL to AL) .................................................................. 1049.14 ANDW (And Word Data of Destination and Source to Destination) ................................ 1059.15 ASR (Arithmetic Shift Byte Data of Accumulator to Right) .............................................. 1079.16 ASRL (Arithmetic Shift Long Word Data of Accumulator to Right) .................................. 1099.17 ASRW (Arithmetic Shift Word Data of Accumulator to Right) .......................................... 1119.18 ASRW (Arithmetic Shift Word Data of Accumulator to Right) .......................................... 1139.19 BBcc (Branch if Bit Condition satisfied) ........................................................................... 1159.20 Bcc (Branch relative if Condition satisfied) ...................................................................... 1179.21 CALL (Call Subroutine) .................................................................................................... 1199.22 CALLP (Call Physical Address) ....................................................................................... 1219.23 CALLV (Call Vectored Subroutine) .................................................................................. 1239.24 CBNE (Compare Byte Data and Branch if not equal) ...................................................... 1259.25 CLRB (Clear Bit) .............................................................................................................. 1279.26 CMP (Compare Byte Data of Destination and Source) ................................................... 1289.27 CMPL (Compare Long Word Data of Destination and Source) ....................................... 1309.28 CMPW (Compare Word Data of Destination and Source) .............................................. 1329.29 CWBNE (Compare Word Data and Branch if not Equal) ................................................ 1349.30 DBNZ (Decrement Byte Data and Branch if not "0") ....................................................... 1369.31 DEC (Decrement Byte Data) ........................................................................................... 1389.32 DECL (Decrement Long Word Data) ............................................................................... 1399.33 DECW (Decrement Word Data) ...................................................................................... 1409.34 DIV (Divide Word Data by Byte Data) ............................................................................. 1429.35 DIVW (Divide Long Word Data by Word Data) ................................................................ 1449.36 DIVU (Divide unsigned Word Data by unsigned Byte Data) ............................................ 1469.37 DIVUW (Divide unsigned Long Word Data by unsigned Word Data) .............................. 1489.38 DWBNZ (Decrement Word Data and Branch if not Zero) ................................................ 150

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9.39 EXT (Sign Extend from Byte Data to Word Data) ............................................................ 1529.40 EXTW (Sign Extend from Word Data to Long Word Data) .............................................. 1539.41 FILS, FILSI (Fill String Byte) ............................................................................................ 1549.42 FILSW, FILSWI (Fill String Word) .................................................................................... 1569.43 INC (Increment Byte Data (Address Specification)) ........................................................ 1589.44 INCL (Increment Long Word Data) .................................................................................. 1599.45 INCW (Increment Word Data) ......................................................................................... 1609.46 INT (Software Interrupt) ................................................................................................... 1629.47 INT (Software Interrupt (Vector Specification)) ................................................................ 1649.48 INT9 (Software Interrupt) ................................................................................................. 1669.49 INTP (Software Interrupt) ................................................................................................ 1689.50 JCTX (Jump Context) ...................................................................................................... 1709.51 JMP (Jump Destination Address) .................................................................................... 1729.52 JMPP (Jump Destination Physical Address) ................................................................... 1739.53 LINK (Link and create new stack frame) ......................................................................... 1749.54 LSL (Logical Shift Byte Data of Accumulator to Left) ...................................................... 1759.55 LSLL (Logical Shift Long Word Data of Accumulator to Left) .......................................... 1769.56 LSLW (Logical Shift Word Data of Accumulator to Left) .................................................. 1779.57 LSLW (Logical Shift Word Data of Accumulator to Left) .................................................. 1789.58 LSR (Logical Shift Byte Data of Accumulator to Right) ................................................... 1799.59 LSRL (Logical Shift Long Word Data of Accumulator to Right) ....................................... 1819.60 LSRW (Logical Shift Word Data of Accumulator to Right) ............................................... 1839.61 LSRW (Logical Shift Word Data of Accumulator to Right) ............................................... 1849.62 MOV (Move Byte Data from Source to Accumulator) ...................................................... 1869.63 MOV (Move Byte Data from Accumulator to Destination) ............................................... 1889.64 MOV (Move Byte Immediate Data to Destination) ........................................................... 1899.65 MOV (Move Byte Data from Source to Destination) ........................................................ 1919.66 MOV (Move Byte Data from AH to Memory) ................................................................... 1939.67 MOVB (Move Bit Data from Bit Address to Accumulator) ............................................... 1949.68 MOVB (Move Bit Data from Accumulator to Bit Address) ............................................... 1969.69 MOVEA (Move Effective Address to Destination) ........................................................... 1989.70 MOVL (Move Long Word Data from Source to Accumulator) ......................................... 1999.71 MOVL (Move Long Word Data from Accumulator to Destination) ................................... 2009.72 MOVN (Move Immediate Nibble Data to Accumulator) ................................................... 2019.73 MOVS, MOVSI (Move String Byte with Increment) ......................................................... 2029.74 MOVSD (Move String Byte with Decrement) ................................................................... 2049.75 MOVSW, MOVSWI (Move String Word with Increment) ................................................. 2059.76 MOVSWI (Move String Word with Decrement) ............................................................... 2079.77 MOVW (Move Word Data from Source to Accumulator) ................................................. 2089.78 MOVW (Move Word Data from Accumulator to Destination) ........................................... 2109.79 MOVW (Move Immediate Word Data to Destination) ...................................................... 2129.80 MOVW (Move Word Data from Source to Destination) ................................................... 2149.81 MOVW (Move Immediate Word Data to io) ..................................................................... 2169.82 MOVW (Move Word Data from AH to Memory) .............................................................. 2179.83 MOVX (Move Byte Data with Sign Extension from Source to Accumulator) ................... 2189.84 MUL (Multiply Byte Data of Accumulator) ........................................................................ 2209.85 MUL (Multiply Byte Data of Accumulator and Effective Address) .................................... 2219.86 MULW (Multiply Word Data of Accumulator) ................................................................... 2229.87 MULW (Multiply Word Data of Accumulator and Effective Address) ............................... 223

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9.88 MULU (Multiply Unsigned Byte Data of Accumulator) ..................................................... 2249.89 MULU (Multiply Unsigned Byte Data of Accumulator and Effective Address) ................. 2259.90 MULUW (Multiply Unsigned Word Data of Accumulator) ................................................ 2269.91 MULUW (Multiply Unsigned Word Data of Accumulator and Effective Address) ............ 2279.92 NEG (Negate Byte Data of Destination) .......................................................................... 2289.93 NEGW (Negate Word Data of Destination) ..................................................................... 2299.94 NOP (No Operation) ........................................................................................................ 2309.95 NOT (Not Byte Data of Destination) ................................................................................ 2319.96 NOTW (Not Word Data of Destination) ........................................................................... 2339.97 NRML (NORMALIZE Long Word) ................................................................................... 2349.98 OR (Or Byte Data of Destination and Source to Destination) .......................................... 2359.99 OR (Or Byte Data of Immediate Data and Condition Code Register to Condition Code

Register) .......................................................................................................................... 2379.100 ORL (Or Long Word Data of Destination and Source to Destination) ............................. 2399.101 ORW (Or Word Data of AH and AL to AL) ...................................................................... 2419.102 ORW (Or Word Data of Destination and Source to Destination) ..................................... 2429.103 POPW (Pop Word Data of Accumulator from Stack Memory) ......................................... 2449.104 POPW (Pop Word Data of AH from Stack Memory) ....................................................... 2469.105 POPW (Pop Word Data of Program Status from Stack Memory) .................................... 2479.106 POPW (Pop Registers from Stack Memory) ................................................................... 2489.107 PUSHW (Push Word Data of Inherent Register to Stack Memory) ................................. 2509.108 PUSHW (Push Registers to Stack Memory) ................................................................... 2529.109 RET (Return from Subroutine) ......................................................................................... 2549.110 RETI (Return from Interrupt) ............................................................................................ 2559.111 RETP (Return from Physical Address) ............................................................................ 2579.112 ROLC (Rotate Byte Data of Accumulator with Carry to Left) ........................................... 2589.113 RORC (Rotate Byte Data of Accumulator with Carry to Right) ........................................ 2609.114 SBBS (Set Bit and Branch if Bit Set) ............................................................................... 2629.115 SCEQ, SCEQI (Scan String Byte until equal with Increment) ......................................... 2639.116 SCEQD (Scan String Byte until equal with Decrement) .................................................. 2659.117 SCWEQ, SCWEQI (Scan String Word until equal with Increment) ................................. 2679.118 SCWEQD (Scan String Word until equal with Decrement) ............................................. 2699.119 SETB (Set Bit) ................................................................................................................. 2719.120 SUB (Subtract Byte Data of Source from Destination to Destination) ............................. 2729.121 SUBC (Subtract Byte Data of AL from AH with Carry to AL) ........................................... 2749.122 SUBC (Subtract Byte Data of Effective Address from Accumulator with Carry to Accumulator)

.......................................................................................................................................... 2759.123 SUBCW (Subtract Word Data of Effective Address from Accumulator with Carry to

Accumulator) ................................................................................................................... 2779.124 SUBDC (Subtract Decimal Data of AL from AH with Carry to AL) ................................... 2799.125 SUBL (Subtract Long Word Data of Source from Destination to Destination) ................. 2809.126 SUBW (Subtract Word Data of Source from Destination to Destination) ........................ 2829.127 SUBW (Subtract Word Data of AL from AH to AL) .......................................................... 2849.128 SWAP (Swap Byte Data of Accumulator) ........................................................................ 2859.129 SWAPW (Swap Word Data of Accumulator) ................................................................... 2869.130 UNLINK (Unlink and Create New Stack Frame) .............................................................. 2879.131 WBTc (Wait until Bit Condition Satisfied) ........................................................................ 2889.132 XCH (Exchange Byte Data of Source to Destination) ..................................................... 2909.133 XCHW (Exchange Word Data of Source to Destination) ................................................. 2929.134 XOR (Exclusive Or Byte Data of Destination and Source to Destination) ....................... 294

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9.135 XORL (Exclusive Or Long Word Data of Destination and Source to Destination) ........... 2969.136 XORW (Exclusive Or Word Data of AH and AL to AL) .................................................... 2989.137 XORW (Exclusive Or Word Data of Destination and Source to Destination) .................. 2999.138 ZEXT (Zero Extend from Byte Data to Word Data) ......................................................... 3019.139 ZEXTW (Zero Extend from Word Data to Long Word Data) ........................................... 302

APPENDIX ............................................................................................................. 303APPENDIX A Explanation of Instruction Lists ............................................................................. 304

A.1 Items Used in Instruction Lists ........................................................................................ 305A.2 Symbols Used in Instruction Lists ................................................................................... 307A.3 Effective Address Field ................................................................................................... 309A.4 Calculating the Execution Cycle Count ........................................................................... 310

APPENDIX B Instruction Lists (351 Instructions) ........................................................................ 311APPENDIX C Instruction Maps .................................................................................................... 327

C.1 Structure of the Instruction Map ...................................................................................... 328C.2 Basic Page Map .............................................................................................................. 330C.3 Bit Operation Instruction Map .......................................................................................... 332C.4 Character String Operation Instruction Map .................................................................... 334C.5 2-byte Instruction Map ..................................................................................................... 336C.6 ea-type Instruction Map ................................................................................................... 338C.7 MOVEA RWi, ea Instruction Map .................................................................................... 348C.8 MOV Ri, ea Instruction Map ............................................................................................ 350C.9 MOVW RWi, ea Instruction Map ..................................................................................... 352C.10 MOV ea, Ri Instruction Map ............................................................................................ 354C.11 MOVW ea, RWi Instruction Map ..................................................................................... 356C.12 XCH Ri, ea Instruction Map ............................................................................................. 358C.13 XCHW RWi, ea Instruction Map ...................................................................................... 360

APPENDIX D Failure of String Instructions and WBTC/WBTS Instructions ................................ 362D.1 Problem Description ........................................................................................................ 362D.2 List of affected Devices ................................................................................................... 363D.3 Details of the Failure ....................................................................................................... 364D.4 Possible workaround ....................................................................................................... 366

APPENDIX E Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt ............... 367E.1 Overview ......................................................................................................................... 367E.2 List of affected Devices ................................................................................................... 368E.3 Detailed explanation ........................................................................................................ 369E.4 Possible workaround ....................................................................................................... 370

CM44-00203-1E FUJITSU MICROELECTRONICS LIMITED 1

CHAPTER 1CPU

This chapter describes an overview of the

F2MC-16FX CPU core and its sample configuration.

1.1 Overview of CPU

1.2 Sample Configuration

2 FUJITSU MICROELECTRONICS LIMITED CM44-00203-1E

CHAPTER 1 CPU1.1 Overview of CPU

1.1 Overview of CPU

The F2MC-16FX CPU core is a 16-bit CPU designed for applications that require high-speed real-time processing, such as home-use or vehicle-mounted

electronic appliances. The F2MC-16FX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing.

■ Overview of CPU

In addition to 16-bit data, the F2MC-16FX CPU core can process 32-bit data by using an

internal 32-bit accumulator. 32-bit data can be processed with some instructions. Up to 16

MBytes of memory space can be used, which can be accessed by either the linear pointer or

bank method. The instruction set is compatible to F2MC-16FX. The instruction set is

compatible with high-level languages, has a rich set of addressing modes, multiplication and

division instructions, and bit processing. The features of the F2MC-16FX CPU are explained

below.

● Fast execution speed

• Minimum instruction execution time: 16 ns (when operating at an internal frequency of 64MHz)

• Basic instructions are executed in one cycle

• High speed processing using a 5 stage pipeline

• 8 byte instruction queue

● General purpose registers: 32 banks x 8 words x 16 bits

● Memory space: 16 MBytes, accessed in linear or bank method

● Instruction set optimized for controller applications

• High code efficiency

• Rich data types: Bit, byte, word, long word

• Extended addressing modes: 23 types

• High-precision operation (32-bit length) based on 32-bit accumulator

• Signed and unsigned multiplication and division instructions

● Powerful interrupt functions

• Fast response speed (about 10 clock cycles CLKB)

• Eight priority levels (programmable)

• Non maskable interrupt (NMI)

• DMA transfer can serve interrupt requests (16 channels max.) without involving CPU

● Instruction set compatible with high-level language (C)/multitasking

• System stack pointer

• Instruction set symmetry

• Barrel shift instructions


CHAPTER 1 CPU1.2 Sample Configuration

1.2 Sample Configuration

A sample configuration of the F2MC-16FX CPU and that of the MCU device are shown.

■ Hardware configuration of the F2MC-16FX CPU

● Figure 1.2-1 shows the block diagram of the F2MC-16FX CPU.

Figure 1.2-1 Block diagram of F2MC-16FX CPU

● CPU Pipeline Operation

To execute most instructions in one clock cycle, the CPU uses a five-stage instruction pipeline.

The pipeline consists of the following stages:

• Instruction fetch (IF): Fetches the instruction from instruction queue.

• Instruction decode 1 (D1): Decodes the instruction and controls address operation.

• Instruction decode 2 (D2): Decodes the instruction and selects operands and data operation.

• Execution (EX): Executes the operation.

• Write back (WB): Writes the operation result to a register or memory location.

Direct Page Register

DPR

Bank Register

USB, SSB, DTB, ADB

Stack Pointer

USP, SSP

GeneralPurpose

Register

Ri, RWi, RLi

Program Counter

PCB, PC

Processor Status

PS

Accumulator

AH, AL

Instruction

Queue

ALU

Decode Address

Operation

Operation

Decode Data

Fetch stage

Decode stage 1

Decode Stage 2

F2MC-16FX CPU

Execution stage

Write Back stage



Figure 1.2-2 Instruction Pipeline

Instructions are not executed out of order. Therefore, if instruction A enters the pipeline ahead

of instruction B, instruction A always reaches write back stage before instruction B.

The standard instruction execution speed is one instruction per cycle. However, transfer

instructions that involve memory wait, branch instructions and multi-cycle instructions require

more than one cycle to execute. The instruction execution speed also drops if the delivery of

instructions during code fetch is slow.

● Instruction Queue

The CPU has an instruction queue of 8 byte.

The instruction queue is filled by the fetch unit. Prefetch is used on consecutive addresses for

code fetch. The prefetch mechanism removes drawbacks due to the latency of the pipelined

implementation of the CPU and the system bus of the 16FX core.

● Program counter

The program counter bank (PCB, upper 8 bits of the program address) and the program counter

(PC, lower 16 bits of the program address) are controlled by the decode stage 1.

The instruction that is executed next is specified by a 24-bit address {PCB, PC} where the

program counter bank and the program counter are concatenated.

● ALU

The ALU is controlled by decode stage 2. The operation mode of the ALU is selected and the

operands are loaded. The execution of the operation is performed in the next cycle.

The ALU is used for logical and arithmetical operations. Multiplication and division are

included.

● CPU registers and memory access

In the write back stage the result of the operation is written to CPU registers and/or to a

memory location. All CPU registers except the program counter are assigned to the last

pipeline stage.

EX

D2

D1

IF

EX

D2

D1

IF

EX

D2

D1

WB

EX

D2

WB

EX WB

WB

WB

WB

Instruction 6

Instruction 5

Instruction 4

Instruction 3

Instruction 2

Instruction 1

CLK



■ Sample Hardware configuration of F2MC-16FX Family MCU

Figure 1.2-3 shows a sample hardware configuration of the MCU device based on the F2MC-

16FX CPU.

Figure 1.2-3 MCU Device based on the F2MC-16FX Core

● Interrupt Controller

The interrupt controller evaluates the priority of incoming interrupt requests (IRQ) and selects

the interrupt number with the highest priority. If accepted, the selected interrupt service is

processed by the CPU. Each hardware IRQ has its own interrupt level register to control its

priority.

● DMA Controller

The DMA controller can also serve IRQs, but without interrupting the actual program

execution of the CPU. This can be used to automate data transfer between peripherals and

memory.

Depending on the device, up to 16 DMA channels are usable. Each DMA channel can select an

IRQ number to be served.

RAM

(data area)

ROM

(program area)

Boot ROMF2MC-16FX

CPU

Interrupt

Controller

DMA

Controller

Clock and

Mode Control

External Bus

Interface

Peripheral

Bus Bridge

Peripheral

Bus Bridge

CAN

Timer Serial ADC

16

FX

Co

re B

us

F2MC-16FX Core

User Ports

Peripheral Bus 2

Peripheral Bus 1

MCU Device



● Clock and Mode Control

This unit has control over the operation mode and monitors correct operation of the device. It

supplies all units with their appropriate clock, depending on the operation mode.

● External Bus Interface

The external bus interface is an optional component. Its availability depends on the

configuration of the specific device.

● Boot ROM

After device initialization by reset, the program counter points to the boot ROM. The CPU

starts the execution of the boot ROM program. After further device initialization the reset

vector is fetched and the boot ROM code branches to user program execution starting at the

reset vector.

● Peripheral Bus Bridge

The peripheral bus bridge acts as an interface between the system bus of the F2MC-16FX core

and the peripheral bus connecting to all other MCU internal peripheral resources.

The peripheral bus bridge synchronizes between core clock and peripheral clock domains.


CHAPTER 2MEMORY SPACE

This chapter describes memory spaces in the

F2MC-16FX CPU.

2.1 CPU Memory Space

2.2 Linear Addressing Mode

2.3 Bank Addressing Mode

2.4 Memory Space Divided into Banks and Value in Each Bank Register

2.5 Data Configuration of and Access to Multi-byte Data in Memory


CHAPTER 2 MEMORY SPACE2.1 CPU Memory Space

2.1 CPU Memory Space

All data, programs, and I/O areas managed in the CPU are allocated in its 16-Mbyte memory space. The CPU can access these resources using an address on the 24-bit address bus (see Figure 2.1-1 ).

The F2MC-16FX addressing mode can be classified either as a linear or bank mode. The linear mode specifies an entire 24-bit address using a instruction. The bank mode specifies the upper 8 bits of each address using a bank register, and the remaining 16-bit address using an instruction.

■ CPU Memory Space

Figure 2.1-1 Example of Relationship between the F2MC-16FX System and Memory Map

F2MC-16FX

FFFFFFH

FF8000H

810000H

800000H

0000C0H

0000B0H

000020H

000000H

Program area

Data area

Interrupt controller

Peripheral circuit

CPU

Interrupt

Data

Program

[Device]General-purpose port

⎨⎧

⎩

⎨⎧

⎩

⎨⎧

⎩

⎨⎧

⎩

⎨⎪⎧

⎩⎪⎪

⎪

General-purpose

Peripheralcircuit

port


CHAPTER 2 MEMORY SPACE2.2 Linear Addressing Mode

2.2 Linear Addressing Mode

The linear addressing mode of the F2MC-16FX specifies an entire 24-bit address using an instruction.The linear addressing mode can operate in two different ways. In the first way, an operand of an instruction directly specifies an entire 24-bit address. In the second way, the lower 24-bit of a 32-bit general-purpose register is referred as an address.

■ Linear Addressing Mode

The linear addressing mode of the F2MC-16FX specifies an entire 24-bit address using an

instruction. The address mode of the F2MC-16FX is determined according to the specification

of the effective address or instruction code (implied) of an instruction.

The linear addressing mode can operate in two different ways. In the first way, an operand of

an instruction directly specifies an entire 24-bit address. In the second way, the lower 24-bit of

a 32-bit general-purpose register is referred as an address (see Figure 2.2-1 ).


CHAPTER 2 MEMORY SPACE2.2 Linear Addressing Mode

Figure 2.2-1 Examples of Generating an Address in the Linear Addressing Mode

Previous content of452D

17452DHJMPP 123456H

123456H

17program counter plus

Next instructionLatest content of

345612program counter plus

program bank

program bank

Example 2: Indirect Addressing Based on 32-bit Register in the Linear Addressing Mode

MOV A @RL1+7

090700H

+7

RL1(Upper 8 bits are ignored.)

XXXX

003A

3A

240906F9

Previous content of the AL

Latest contentof the AL

Example 1: 24-bit Operand Specification in the Linear Addressing Mode

JMPP 123456H


CHAPTER 2 MEMORY SPACE2.3 Bank Addressing Mode

2.3 Bank Addressing Mode

The bank addressing mode of the F2MC-16FX specifies the upper 8 bits of an address using a bank register for use, and the remaining 16 bits using an instruction.

■ Bank Addressing ModeIn the bank addressing mode, the 16-Mbyte memory space is divided into 256 banks of 64-

Kbyte, and the corresponding bank to each space is specified by the following 4 bank registers.

● Program bank register (PCB)

A 64-Kbyte bank specified using the PCB register is called a program (PC) space. It is used to

hold mainly instruction codes, vector tables, and immediate data.

● Data bank register (DTB)

A 64-Kbyte bank specified using the DTB register is called a data (DT) space. It is used to

hold mainly readable/writable data and control/data registers for internal and external

resources.

● User stack bank register (USB) and system stack bank register (SSB)

A 64-Kbyte bank specified using the USB or SSB register is called a stack (SP) space. It is

accessed when the execution of a push or pop instruction or interrupt handling is performed

and which to be used, the USB or SSB register, is determined according to the S flag in the

condition code register to save register contents and a stack access occurs.

● Additional data bank register (ADB)

A 64-Kbyte bank specified using the ADB register is called an additional (AD) space. It is

used to hold mainly data overflowing from the DT space.

Each instruction is assigned with one of the default spaces by each addressing listed in Table

2.3-1 to improve instruction code efficiency.

Table 2.3-1 Default Spaces

Default space Addressing

Program space PC-indirect, program access, branch type

Data space @A, addr16, dir, or addressing using @RW0, @RW1, @RW4, or @RW5

Stack space Addressing using PUSHW, POPW, @RW3, @RW7, or @SP

Additional space Addressing using @RW2 or @RW6


CHAPTER 2 MEMORY SPACE2.3 Bank Addressing Mode

If a space other than a default space is used, an arbitrary bank space corresponding to a prefix

code can be accessed by specifying the prefix code before the instruction.

Table 2.3-2 lists bank select prefixes and the memory space selected using each prefix.

The DTB, USB, SSB, and ADB registers are initialized to "00H" at a reset. The PCB register is

initialized to "FFH" at a reset. After a reset, the data, stack, and additional spaces are allocated

in bank 00H (000000H to 00FFFFH), and the program space is allocated in bank FFH (FF0000H

to FFFFFFH).

Table 2.3-2 Bank Selection Prefix

Bank select prefix Selected space

PCB Program space

DTB Data space

ADB Additional space

SPBSystem or user stack space depending on the contents of the selected stack flag


CHAPTER 2 MEMORY SPACE2.4 Memory Space Divided into Banks and Value in Each Bank

Register

2.4 Memory Space Divided into Banks and Value in Each Bank Register

Figure 2.4-1 shows an example of a memory space divided into banks and a value in each register bank.

■ Memory Space Divided into Banks and Values in Each Register Bank

Figure 2.4-1 Example of the Physical Addresses of Each Space

Phy

sica

l Add

ress

FFFFFFH

FF0000H

B3FFFFH

B30000H

92FFFFH

920000H

68FFFFH

680000H

4BFFFFH

4B0000H

000000H

Program space

Additional space

User stack space

Data space

System stack space

FFH : PCB (program bank register)

B3H : ADB (additional data bank register)

92H : USB (user stack bank register)

68H : DTB (data bank register)

4BH : SSB (system stack bank register)


CHAPTER 2 MEMORY SPACE2.5 Data Configuration of and Access to Multi-byte Data in Memory

2.5 Data Configuration of and Access to Multi-byte Data in Memory

Multi-byte data is written to memory starting at the lowest address. If the multi-byte data is 32-bit long, the lower 16 bits are written to memory first and then upper 16 bits.

■ Multi-byte Data Layout in a Memory SpaceMulti-byte data is written to memory starting at the lowest address. If the multi-byte data is

32-bit length, the lower 16 bits are written to memory first and then upper 16 bits.

If a reset signal is input immediately after the low-order data is written to memory, the high-

order data may not be written. To keep the data in integrity, it is necessary to input a reset

signal after the high-order data is written.

Figure 2.5-1 shows the layout of multi-byte data in memory. The lower 8 bits are placed at

address n, the next lower 8 bits are placed at address n + 1, and the next lower 8 bits are placed

at address n + 2, and so on.

Figure 2.5-1 Multi-byte Data Layout in Memory

H

Address n

L

01010101

MSB LSB

11001100 11111111 00010100

01010101

11001100

11111111

00010100


CHAPTER 2 MEMORY SPACE2.5 Data Configuration of and Access to Multi-byte Data in

Memory■ Access to Multi-byte Data

When multi-byte data is accessed, it is assumed that all parts of the multi-byte data are within a

single bank. To put it another way, an instruction accessing multi-byte data assumes that an

address that follows address FFFFH is 0000H in the same bank as for FFFFH.

Figure 2.5-2 shows an execution example of an instruction accessing multi-byte data.

Figure 2.5-2 Execution Example of an Instruction (MOVPW A, 080FFFFH) Accessing Multi-byte Data

Higher address

80FFFFH

800000H

AL before execution

Lower address

?? ??

AL after execution 23H 01H

···

23H

01H


CHAPTER 2 MEMORY SPACE2.5 Data Configuration of and Access to Multi-byte Data in Memory


CHAPTER 3DEDICATED REGISTER

The F2MC-16FX CPU registers are classified into two types: dedicated registers and general-purpose registers. This chapter describes the

dedicated registers of the F2MC-16FX CPU. The dedicated registers are dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture. These registers can be accessed without using an address. The register operations are defined by specific instructions.This chapter explains the CPU.

3.1 Dedicated Registers

3.2 Accumulator (A)

3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)

3.4 Processor Status (PS)

3.5 Program Counter (PC)

3.6 Direct Page Register (DPR)

3.7 Bank register (PCB, DTB, ADB, USB, SSB)


CHAPTER 3 DEDICATED REGISTER3.1 Dedicated Registers

3.1 Dedicated RegistersThe F2MC-16FX CPU has the following dedicated registers:

• Accumulator (A=AH:AL): Two 16-bit accumulators (can be used as a single 32-bitaccumulator)

• User stack pointer (USP): 16-bit user stack pointer

• System stack pointer (SSP): 16-bit system stack pointer

• Processor status (PS): 16-bit register indicating the system status

• Program counter (PC): 16-bit register holding the address of the next instruction to beexecuted

• Program bank register (PCB): 8-bit register indicating the program bank

• Data bank register (DTB): 8-bit register indicating the data bank

• User stack bank register (USB): 8-bit register indicating the user stack bank

• System stack bank register (SSB): 8-bit register indicating the system stack bank

• Additional bank register (ADB): 8-bit register indicating the additional data bank

• Direct page register (DPR): 8-bit register indicating the page for direct access

Figure 3.1-1 "Dedicated registers" is a diagram of the dedicated registers.

Figure 3.1-1 Dedicated registers

Accumulator

User stack pointer

System stack pointer

Processor status

Program counter

Direct page register

Program bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

USP

SSP

PS

PC

DPR

PCB

DTB

USB

SSB

ADB

8 bit16 bit

32 bit

AH AL


CHAPTER 3 DEDICATED REGISTER3.2 Accumulator (A)

3.2 Accumulator (A)

The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH and AL), and is used as a temporary storage for operation results and transfer data.

■ Accumulator (A)The A register consists of two 16-bit arithmetic operation registers (AH and AL). The A

register is used as a temporary storage for operation results and transfer data. During 32-bit

data processing, AH and AL are used together. Only AL is used for word processing in 16-bit

data processing mode or for byte processing in 8-bit data processing mode (see Figure 3.2-1

“32-bit data transfer” and Figure 3.2-2 “AL-AH transfer”). The data stored in the A register

can be operated upon with the data in memory or registers (Ri, Rwi, or RLi). In the same

manner as with the F2MC-16FX, when a word or shorter data item is transferred to AL, the

previous data item in AL is automatically sent to AH (data preservation function). The data

preservation function and operation between AL and AH help to improve processing

efficiency.

When a byte or shorter data item is transferred to AL, the data is sign-extended or zero-

extended and stored as a 16-bit data item in AL. The data in AL can be handled either as word

or byte.

When a byte-processing arithmetic operation instruction is executed on AL, the high-order

eight bits of AL before the operation are ignored. After the operation the heigh-order eight bits

become zero.

The A register is not initialized by a reset. The A register holds an undefined value

immediately after a reset.

Figure 3.2-1 Example of a 32-bit data transfer

+6

MSB

A61540H

A6153EH

RW1

8FH 74H

2BH 52H

15H 38H

LSB

A6HDTB

AH AL

Previous contentof the A register

Latest contentof the A register 8F74H 2B52H

XXXXH XXXXH

MOVL A, @RW1+6


CHAPTER 3 DEDICATED REGISTER3.2 Accumulator (A)

Figure 3.2-2 Example of AL-AH transfer by means of data preservation

+6

MSB

A61540H

A6153EH

RW1

XXXXH 1234H 8FH 74H

2BH 52H

15H 38H

LSB

A6HDTB

1234H 2B52H

AH AL

Previous contentof the A register

Latest contentof the A register

MOVW A, @RW1+6


CHAPTER 3 DEDICATED REGISTER3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)

3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)

USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data when a push/pop instruction or subroutine is executed.

■ User stack pointer (USP) and system stack pointer (SSP)USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring

data in the event of a push/pop instruction or subroutine execution. The USP and SSP registers

are used by stack instructions.

The USP register is enabled when the S flag in the processor status register is “0”, and the SSP

register is enabled when the S flag is “1” (see Figure 3.3-1“Stack manipulation instruction and

stack pointer”). Since the S flag is set when an interrupt is accepted, register values are always

saved in the memory area indicated by SSP during interrupt processing. SSP is used for stack

processing in an interrupt routine, while USP is used for stack processing outside an interrupt

routine. If the stack space is not divided, use only the SSP.

During stack processing, the high-order eight bits of an address are indicated by SSB (for SSP)

or USB (for USP).

USP and SSP are not initialized by a reset. Instead, the values are undefined.

Figure 3.3-1 Stack manipulation instruction and stack pointer

AL A624 H USB USP

SSPSSB0

C6 H

56H

F328 H

1234 H

C6F326 H XXXX

AL A624 H USB USP

SSPSSB0

C6 H

56H

F326 H

1234 H C6F326 H 24HA6 H

AL A624 H USB USP

SSPSSB

C6 H

56H

F328 H

1234 H

561232 H XXXX

1

AL A624 H USB USP

SSPSSB1

C6 H

56H

F328 H

1232 H

561232 H 24HA6 H

Example 1 PUSHW A when the S flag is "0"

Before execution

S flag

After executionUser stack is used because

Example 2 PUSHW A when the S flag is "1"

System stack is used becausethe S flag is "1".

the S flag is "0".

MSB LSB


CHAPTER 3 DEDICATED REGISTER3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)

Note:

Specify an even-numbered address in the stack pointer whenever possible. An odd valuewill cause drawback in stack performance.


CHAPTER 3 DEDICATED REGISTER3.4 Processor Status (PS)

3.4 Processor Status (PS)

The PS register consists of the bits controlling the CPU Operation and indicating the CPU status.

■ Processor status (PS)As shown in Figure 3.4-1“Processor status (PS) structure”, the high-order byte of the PS

register consists of a register bank pointer (RP) and an interrupt level mask register (ILM). The

RP indicates the start address of a register bank. The low-order byte of the PS register is a

condition code register (CCR), containing the flags to be set or reset depending on the results

of instruction execution or interrupt occurrences.

Figure 3.4-1 Processor status (PS) structure

■ Condition code register (CCR)Figure 3.4-2“Condition code register (CCR) configuration” is the diagram of the condition

code register configuration.

Figure 3.4-2 Condition code register (CCR) configuration

● P: Priviledged mode flag:

P = 1 indicates user mode, P = 0 indicates privileged mode.

The P flag is cleared by a reset. However, the P flag will be set during execution of the Boot

ROM code.

Only NMI, HW-INT9 (EDSU) and DSU interrupts will clear the P flag and disable all other

hardware interrupts. If the P flag is cleared, ILM defines system interrupt levels of the

privileged mode (P0 to P7). These interrupt levels have higher priority than any ILM setting in

user mode (U0 to U7).

The P flag can be set by dedicated instructions (OR CCR #imm, POPW PS) or by restoring the

processor status (RETI, JCTX @A). Restoring P=0 is not accepted, if P has been "1" before.

● I: Interrupt enable flag:

Interrupts other than software interrupts are enabled when the I flag is "1" and are masked

when the I flag is "0". The I flag is cleared by a reset.

ILM RPPS

15 1312 87 0bit

CCR

0 0 1 0 00 0 0 initial value after reset

0 11 X X X X X value after Boot ROM execution

07 6 5 4 3 2 1

P I S T N Z V C PS: CCR

bit



● S: Stack flag:

When the S flag is "0", USP is enabled as the stack pointer.

When the S flag is "1", SSP is enabled as the stack pointer.

The S flag is set by an interrupt reception or a reset.

● T: Sticky bit flag:

A value of "1" is set in the T flag when there is at least one "1" in the data shifted out from the

carry after execution of a logical right/arithmetic right shift instruction, otherwise, "0" is set in

the T flag.

In addition, "0" is set in the T flag when the shift amount is zero.

● N: Negative flag:

The N flag is set when the MSB of the operation result is "1", and is otherwise cleared.

● Z: Zero flag:

The Z flag is set when the operation result is all zeroes, and is otherwise cleared.

● V: Overflow flag:

The V flag is set when an overflow of a signed value occurs as a result of operation execution

and is otherwise cleared.

● C: Carry flag:

The C flag is set when a carry-up or carry-down from the MSB or LSB occurs as a result of

operation execution, and is otherwise cleared.

■ Register bank pointer (RP)

The RP register indicates the relationship between the general-purpose registers of the F2MC-

16FX and the internal RAM addresses. Specifically, the RP register indicates the first memory

address of the currently used register bank in the following conversion expression: [00180H +

(RP) × 10H]. The RP register consists of five bits, and can take a value between 00H and 1FH.

Register banks can be allocated at addresses from 000180H to 00037FH in memory.

Figure 3.4-3 Register bank pointer (RP)

The RP register is initialized to all zeroes by a reset. An instruction may transfer an eight-bit

immediate value to the RP register; however, only the low-order five bits of that data are used.

0 00 0 0

RP

initial value

B4 B3 B2 B1 B0

15 14 13 12 11 10 9 8bit



■ Interrupt level mask register (ILM)

The ILM register consists of three bits, indicating the CPU interrupt masking level. An

interrupt request is accepted only when the priority of the interrupt is higher than that indicated

by the ILM register and the P flag. Highest priority interrupt is level P0 and lowest priority is

level U7. Therefore, for an interrupt to be accepted, its level value must be smaller than the

current ILM value (see Figure 3.4-4 Interrupt level register (ILM)). In addition, the P flag has

to be considered. When an interrupt is accepted, the level value of that interrupt is set in the P

flag and ILM register. Thus, an interrupt of the same or lower priority cannot be accepted

subsequently.

Figure 3.4-4 Interrupt level register (ILM)

ILM is initialized to 100B by a reset. However, during execution of the Boot ROM program

ILM is set to 000B.

An instruction may transfer an eight-bit immediate value to the ILM register, but only the low-

order three bits of that data are used (MOV ILM #imm, POPW PS, RETI, JCTX @A). If P=1

(in user level), any ILM change is possible. If P=0 (priviledged level), an ILM change is only

accepted, if the new value defines a user level U0 to U7 (with P=1) or if the privileged level

(P0 to P7) is increased. The lower levels of the privileged mode P0 to P7 can not be reached by

execution of an instruction from a higher level. Writing "0" to the P flag and reducing the level

with P=0 is only possible by NMI, HW-INT9 or a DSU interrupt.

Note:

The P flag can be understood as bit extension of ILM. Then it defines the most significantbit of the the interrupt level mask {P, ILM}.

After initialization with reset the CPU is in level P4. This disables all interrupts, including

NMI, except for the DSU. After execution of the Boot ROM program the CPU is in level U0.

Peripheral interrupts are disabled.

All privileged mode levels P0 to P7 are locked against entering or decreasing the level by an

instruction. The levels P0 to P7 can only be increased. This protects the operation of HW-

INT9, NMI and DSU operation. Only DSU can interrupt the NMI or mask its acceptance

during a debug session.

The user levels U0 to U7 are backward compatible to F2MC-16FX interrupt levels 0 to 7. The

P flag is not writeable in a user level.

15 14 13 12 11 10 9 8

ILM2 ILM1 ILM0 PS: ILM

0 initial value after reset1 0

0 0 value after Boot ROM execution0

bit



Table 3.4-1 Levels indicated by the P flag and interrupt level mask (ILM) register

Level P flag ILM value Acceptable interrupt level

P0 0 0 none Interrupts disabled

P1 0 1 Level < P1 Interrupts disabled

P2 0 2 Level < P2 Interrupts disabled

P3 0 3 Level < P3 DSU

P4 0 4 Level < P4 DSU

P5 0 5 Level < P5 NMI, DSU

P6 0 6 Level < P6 NMI, DSU

P7 0 7 Level < P7 HW-INT9, NMI, DSU

U0 1 0 Level < U0 User Interrupts disabled HW-INT9, NMI, DSU

U1 1 1 Level < U1 User level 0

U2 1 2 Level < U2 User level 0, 1

U3 1 3 Level < U3 User level 0 to 2






CHAPTER 3 DEDICATED REGISTER3.5 Program Counter (PC)

3.5 Program Counter (PC)

The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU.

■ Program counter (PC)The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address

of an instruction code to be executed by the CPU. The high-order eight bits of the address are

indicated by the program bank register (PCB).

The PC register is updated by a branch instruction, subroutine call instruction, interrupt or

reset. Within a linear program segment, the PC is incremented by the number of bytes of the

last instruction.

The PC register can also be used as a base pointer for operand access.

Figure 3.5-1"Program counter" shows the program counter.

Figure 3.5-1 Program counter

The reset address is fixed to the Boot ROM program start address of 0F:FC00H. At reset, the

PC is initialized to FC00H and the PCB is initialized to 0FH.

In external vector mode a value specified by the reset vector on address FF:FFDCH is loaded

when leaving the Boot ROM code execution. In internal vector mode the PCB and the PC are

loaded with fixed values defined by the product.

PCB PCFE H ABCD H

FEABCD H

Next instruction to be executed


CHAPTER 3 DEDICATED REGISTER3.6 Direct Page Register (DPR)

3.6 Direct Page Register (DPR)

The direct page register (DPR) specifies bits 8 to 15 (addr 8 to addr 15) of the operand address for direct addressing instructions.

■ Direct page register (DPR)DPR specifies bits 8 to 15 of the instruction operands in direct addressing mode as shown in

Figure 3.6-1"Generating a physical address in direct addressing mode".

Figure 3.6-1 Generating a physical address in direct addressing mode

DPR is eight bits long, and is initialized to 01H by a reset. DPR can be read or written to by an

instruction.

α α α α α α α α β β β β β β β β γ γ γ γ γ γ γ γ

α α α α α α α α β β β β β β β β γ γ γ γ γ γ γ γ

MSB

DTB register

24-bit physicaladdress

LSB

DPR register Direct address during instruction


CHAPTER 3 DEDICATED REGISTER3.7 Bank register (PCB, DTB, ADB, USB, SSB)

3.7 Bank register (PCB, DTB, ADB, USB, SSB)

Each bank register indicates a memory bank where a program space, data space, user stack space or additional data space is allocated.

■ Bank RegisterAll bank registers are one byte long. Each bank register (PCB, DTB, USP, SSP, ADB)

indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is

allocated.

Bank registers other than PCB can be read and written to. PCB can be read but cannot be

written to. The PCB register is updated upon the JMPP or CALLP instruction, branching to the

entire 16 MByte space, upon the RETP or RETI instruction or upon an interrupt.

For details of the operation of bank registers, see section "2.3 Bank Addressing Mode".

● Program counter bank register (PCB)

Initial value: 0FH after reset, and later a value from reset vector at user program start.

● Data bank register (DTB)

Initial value: 00H.

● User stack bank register (USB)

Initial value: 00H.

● System stack bank register (SSB)

Initial value: 00H.

● Additional data bank register (ADB)

Initial value: 00H.


CHAPTER 3 DEDICATED REGISTER3.7 Bank register (PCB, DTB, ADB, USB, SSB)


CHAPTER 4GENERAL-PURPOSE

REGISTERS

The registers of the F2MC-16FX can be grouped into two major categories: dedicated registers in the CPU and general-purpose registers allocated in memory.

This chapter describes the F2MC-16FX general-purpose registers. These registers are allocated in a RAM in address space of the CPU. Similarly to the dedicated registers, the general-purpose registers can be accessed without specifying their address. However, the user can specify the purpose for which they are used in the same manner as for ordinary memory.

4.1 Register Banks in RAM

4.2 Calling General-purpose Registers in RAM


CHAPTER 4 GENERAL-PURPOSE REGISTERS4.1 Register Banks in RAM

4.1 Register Banks in RAM

Each register bank consists of 8 words (16 bytes). They can be used as general-purpose registers (byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3) for performing various types of operations and specifying pointers. RL0 to RL3 can be used also as a linear pointer to gain direct access to all spaces in memory.

■ Register Banks in RAMTable 4.1-1 lists the function of each register, and Figure 4.1-1 shows relationships between the

registers.

Figure 4.1-1 Relationship between Registers

Table 4.1-1 Functions of Each Register

Register name Function

R0 to R7Used to hold an operand in various types of instructions.Note: R0 is also used as a barrel shift counter and a counter of normarize instruction.

RW0 to RW7Used to hold a pointer.Used to hold an operand in various types of instructions.Note: RW0 is used also as a string instruction counter.

RL0 to RL3Used to hold a long pointer.Used to hold an operand in various types of instructions.

RW0RL0

RW1

RW2RL1

RW3

R0RW4

R1RL2

R2RW5

R3

R4RW6

R5RL3

R6RW7

R7


CHAPTER 4 GENERAL-PURPOSE REGISTERS4.2 Calling General-purpose Registers in RAM

4.2 Calling General-purpose Registers in RAM

For general-purpose registers of the F2MC-16FX, the register bank pointer (RP) is used to specify where in internal RAM between 000180H and 00037FH the

register bank currently in use is allocated.

■ Calling General-purpose Registers in RAM

The general-purpose registers of the F2MC-16FX are allocated in internal RAM between

000180H and 00037FH (in maximum configuration). The register bank pointer (RP) is used to

indicate where in internal RAM between 000180H and 00037FH the register bank currently in

use is allocated. Each bank contains the following 3 different registers. These registers are not

independent of one another. Instead, they have the relationships shown in Figure 4.2-1 .

• R0 to R7: 8-bit general-purpose registers

• RW0 to RW7:16-bit general-purpose registers

• RL0 to RL3: 32-bit general-purpose registers

Figure 4.2-1 General-purpose Registers

The relationships among the high- and low-order bytes in word registers (RW4 to RW7) and

byte registers (R0 to R7) are represented using the following expression:

RW (i + 4) = R (i × 2 + 1) × 256 + R (i × 2) [where i = 0 to 3]

The relationships among the high- and low-order bytes in long registers (RL0 to RL3) and

word registers (RW0 to RW7) are represented using the following expression:

RL (i) = RW (i × 2 + 1) × 65536 + RW (i × 2) [where i = 0 to 3]

For example, if the data in R1 and the data in R0 are arranged as high- and low-order bytes,

respectively, the resulting data equals the data (2 bytes) in RW4.

Start address of a Lower order

MSB LSB

RW4

RL0RW0RW1RW2

R1 R0R3 R2R5 R4R7 R6

16 bits

Higher order

RW5RW6RW7

⎨⎧

⎩

⎨⎧

⎩

⎨⎧

⎩

⎨⎧

⎩

RL1

RL2

RL3

general-purpose register

000180H + RP × 10H

RW3


CHAPTER 4 GENERAL-PURPOSE REGISTERS4.2 Calling General-purpose Registers in RAM


CHAPTER 5PREFIX CODES

The operation of an instruction can be modified by prefixing it with prefix code. The following 3 types of prefix codes are available.• Bank select prefix• Common register bank prefix• Flag change inhibit prefix codeThis chapter describes these prefixes.

5.1 Bank Select Prefix

5.2 Common Register Bank Prefix (CMR)

5.3 Flag Change Inhibit Prefix Code (NCC)

5.4 Constraints Related to the Prefix Codes


CHAPTER 5 PREFIX CODES5.1 Bank Select Prefix

5.1 Bank Select Prefix

Placing a bank select prefix before an instruction enables selecting the memory space accessed by the instruction regardless of what the current addressing mode is.

■ Bank Select PrefixThe memory space of data to be accessed is determined according to the addressing mode.

Placing a bank select prefix before an instruction enables to select the memory space accessed

by the instruction regardless of what the current addressing mode is. Table 5.1-1 lists the bank

select prefixes and the memory space selected according to each bank select prefix.

The effect of the prefix codes is different for the following instructions.

● Transfer instructions (I/O access)

MOV A,io MOV io, A MOVX A,io MOVW A,io

MOVW io,A MOV io,#imm8 MOVW io,#imm16

These instructions access the I/O space regardless of whether there is a prefix before them.

● Branch instruction

RETI

The system stack bank (SSB) is used regardless of whether there is a prefix before the branch

instruction.

● Bit manipulation instructions (I/O access)

MOVB A,io:bp MOVB io:bp,A SETB io:bp

CLRB io:bp BBC io:bp,rel BBS io:bp,rel

WBTC WBTS

The I/O space is accessed regardless of whether there is a prefix before those instructions.

● String manipulation instructions

MOVS MOVSW SCEQ SCWEQ FILS FILSW

A bank register specified in the operand is used regardless of whether there is a prefix before

these instructions.

Table 5.1-1 Bank Select Prefixes

Bank select prefix Memory space to be selected

PCB Program counter space

DTB Data space

ADB Additional space

SPB System or user stack space depending on the state of the stack flag


CHAPTER 5 PREFIX CODES5.1 Bank Select Prefix

● Other types of control instructions (stack manipulation)

PUSHW POPW

The system stack bank (SSB) or user stack bank (USB) is used depending on the state of the S

flag, regardless of whether there is a prefix before these instructions.

POPW PS

In the following cases, the prefix of an instruction affects not only that instruction but also an

instruction that follows it.

● Other types of control instructions (flag change)

AND CCR,#imm8 OR CCR,#imm8

The operations of these instructions are performed normally. The prefix of each of these

instructions affects not only the instructions but also an instruction that follows them.

● Another type of control instruction (interrupt control)

MOV ILM,#imm8

The operation of the instruction is performed normally. The prefix of the instruction affects

not only that instruction but also an instruction that follows it.


CHAPTER 5 PREFIX CODES5.2 Common Register Bank Prefix (CMR)

5.2 Common Register Bank Prefix (CMR)

Placing a common register bank prefix (CMR) before an instruction accessing a register bank enables to change that the instruction is to access only the registers in a common bank (register bank selected when RP = 0) allocated between 000180H and 00018FH, regardless of what the current value of the

register bank pointer (RP) is.

■ Common Register Bank Prefix (CMR)To make data exchange among tasks easier, it is necessary to use a method that can access a

certain specified register bank relatively easily no matter what value the RP register holds. To

meet this requirement, the F2MC-16FX has a register bank that can be used by all tasks in

common. It is called a common bank. The common bank is allocated in memory between

address 000180H and 00018FH. It is selected when the RP register contains a value of "0".

Placing the common register bank prefix (CMR) before an instruction accessing a register bank

enables to change that the instruction is to access only the registers in a common bank (register

bank selected when RP = 0) allocated between 000180H and 00018FH, regardless of what the

current value of the register bank pointer (RP) is.


● String instructions

MOVS NOVSW SCEQ FILS FILSW

If an interrupt is requested during execution of a string manipulation instruction attached with a

prefix code, the prefix becomes ineffective for the string manipulation instruction after a return

is made from the interrupt handling routine, possibly resulting in a malfunction. Do not place

the CMR prefix before these string manipulation instructions.


AND CCR,#imm8 OR CCR,#imm8 POPW PS

The operations of these instructions are performed normally. The prefix of each of these

instructions affects not only the instructions but also an instruction that follows them.

● MOV ILM,#imm8




CHAPTER 5 PREFIX CODES5.3 Flag Change Inhibit Prefix Code (NCC)

5.3 Flag Change Inhibit Prefix Code (NCC)

Placing the flag change inhibit prefix code (NCC) before an instruction inhibits flags from changing during execution of the instruction.

■ Flag Change Inhibit Prefix Code (NCC)The flag change inhibit prefix code (NCC) is used to suppress undesired changes to flags.

Placing the NCC prefix before an instruction inhibits flags from changing during execution of

the instruction.


● Branch instructions

INT #vct8 INT9 INT addr16

INTP addr24 RETI

These instructions change the flags in the condition code register (CCR) regardless of whether

there is a prefix before them.

● String instructions

MOVE MOVSW SCEQ SCWEQ FILS FISW

If an interrupt is requested during execution of a string manipulation instruction attached with a

prefix code, the prefix becomes ineffective for the string manipulation instruction after a return

is made from the interrupt handling routine, possibly resulting in a malfunction. Do not place

the NCC prefix before these string manipulation instructions.

● Another type of control instruction (task switching)

JCTX @A

This instruction changes the flags in the CCR register regardless of whether there is a prefix

before it.


AND CCR,#imm8 OR CCR,#imm8 POPW PS

These instructions change the flags in the CCR register regardless of whether there is a prefix

before them. The prefix of each of these instructions affects not only the instructions but also

an instruction that follows them.

● Another type of control instruction (interrupt control)

MOV ILM,#imm8




CHAPTER 5 PREFIX CODES5.4 Constraints Related to the Prefix Codes

5.4 Constraints Related to the Prefix Codes

If a prefix code is placed before an instruction where interrupt and hold requests are inhibited, the effect of the prefix code lasts until an instruction where neither an interrupt nor hold request is inhibited appears for the first time, as shown in Figure 5.4-2 .If a prefix is followed by conflicting prefix codes, the last one is valid.

■ Relationships between Instructions Rejecting Interrupt Requests and Prefix Codes

The following 10 instructions/prefix codes reject interrupt and hold requests.

• MOV ILM,#imm8 • AND CCR,#imm8

• OR CCR,#imm8 • POPW PS

• PCB • ADB

• NCC • DTB

• SPB • CMR

If an interrupt or hold request is issued during execution of any of the above instructions, the

request is accepted only after any instruction not listed above appears for the first time after

that instruction and is executed, as shown in Figure 5.4-1 .

Figure 5.4-1 Instructions Rejecting Interrupt and Hold Requests

If a prefix code is placed before an instruction rejecting interrupt and hold requests, its effect

lasts until an instruction other than instructions rejecting interrupt and hold requests appears for

the first time after the prefix code and is executed, as shown in Figure 5.4-2 .

Figure 5.4-2 Instructions Rejecting Interrupt and Hold Requests and Prefix Code

Instructions rejecting interrupt and hold requests

(a)

Interrupt request issued Interrupt accepted (a):Ordinary instruction

• • • • • • • • • • •

Instructions rejecting interrupt and hold requests

ADD A,01H• • • •MOV A,FFHCCR: XXX10XX

The NCC protects the

NCC MOV ILM,#imm8CCR: XXX10XX

CCR from changing.



■ If Two or More Prefix Codes Appear in Succession

If a prefix is followed by conflicting prefix codes, the last one is valid (see Figure 5.4-3 ).

Figure 5.4-3 Consecutive Prefix Codes

The term "conflicting prefix codes" indicates PCB, ADB, DTB, and SPB in the above figure.

Prefix codes

ADB• • • • • • • • • DTB PCB ADD A,01H

The PCB prefix code is valid for this instruction.


CHAPTER 6INTERRUPTS

This chapter describes the interrupt functions and operations.

6.1 Overview of Interrupts

6.2 Interrupt Vector

6.3 Interrupt Control Registers (ICR)

6.4 Non Maskable Interrupt (NMI)

6.5 Interrupt Flow (ICR)

6.6 Hardware Interrupts

6.7 Software Interrupts

6.8 Multiple interrupts

6.9 Exceptions


CHAPTER 6 INTERRUPTS6.1 Overview of Interrupts

6.1 Overview of Interrupts

The F2MC-16FX has interrupt functions that terminate the currently executed program and transfer control to another specified program when a specific event occurs. There are four types of interrupt functions:• Hardware interrupt: Interrupt processing due to an internal resource event• Software interrupt: Interrupt processing due to a software event (instruction)• Exception: Handling of an operation exception• DMA: Data transfer without CPU interaction due to an internal resource event.

■ Hardware interruptsA hardware interrupt is activated by an interrupt request from an internal resource. A hardware

interrupt request occurs when both the interrupt request flag and the interrupt enable flag in an

internal resource are set.

● Specifying an interrupt level

An interrupt level can be specified for the hardware interrupt. To specify an interrupt level, use

the level setting bits (IL0, IL1, and IL2) in the interrupt control register ICR.

For each hardware interrupt its own interrupt level (IL) can be specified. Access to a dedicated

IL can be done by setting the index IX. Both IX and IL are accessible through the interrupt

control register ICR.

● Masking a hardware interrupt request

A hardware interrupt request can be masked by using the I flag and the ILM bits (ILM0, ILM1,

and ILM2). The interrupt is executed only, when the I flag is set and the value of the interrupt

level IL is smaller than the interrupt level mask ILM. In addition the P flag has to be set for

hardware interrupt acceptance. P, I and ILM are parts of the processor status word PS of the

CPU.

When an unmasked interrupt request occurs, the CPU saves 12 bytes of data that consists of

registers PS, PC, PCB, DTB, ADB, DPR, and A in the memory area indicated by the system

stack bank and pointer registers (SSB and SSP).

■ Software interruptsInterrupts requested by executing the INT instruction are software interrupts. An interrupt

request by the INT instruction does not have an interrupt request or enable flag. An interrupt

request is issued always by executing the INT instruction.

No interrupt level is assigned to the INT instruction. Therefore, ILM is not updated when the

INT instruction is used. Instead, the I flag is cleared and the continuing interrupt requests are

suspended.


CHAPTER 6 INTERRUPTS6.1 Overview of Interrupts

■ Exceptions

Following software exceptions can be processed:

• Undefined instruction

• INT9

• INTE (only available on the EVA device)

Following hardware exceptions can be processed:

• NMI

• HW-INT9 (embedded debug support)

• DSU break factors (only available on the EVA device)

Exception processing is basically the same as interrupt processing. When an exception is

detected during instruction execution, exception processing is performed. In general, exception

processing occurs as a result of an unexpected operation. Therefore, use exception processing

only for debugging programs or for activating recovery software in an emergency case.

■ Direct memory access (DMA)

● DMA Function

F2MC-16FX offers a DMA function to automatically transfer data between peripheral

resources and memory upon an interrupt.

The number of DMA channels is device dependent.

When a DMA data transfer of a specified count is completed, an interrupt processing program

is automatically executed on the original IRQ channel. The handling of such an interrupt by

DMA completion is same as for standard type of hardware interrupts.

For a detailed decription of DMA, refer to the hardware manual for each device.


CHAPTER 6 INTERRUPTS6.2 Interrupt Vector

6.2 Interrupt Vector

Hardware and software interrupts use the same vector table. The execution of interrupt service routines can be triggered by asserting the specific IRQ line or by executing the INT instruction and specifying the number of the interrupt vector. Interrupt vectors are allocated between addresses as shown in Table 6.2-2 Interrupt vector table. The location of the Interrupt vector table can be selected by the Table base register.

■ Interrupt vector

● Interrupt Vector Table Base Register (TBR)

Figure 6.2-1 Interrupt vector Table base register (TBR)

The Table Base Register allows to relocate the interrupt vector table to any memory location in

steps of 1 kbytes.

The value of the TBR defines the most significant 14 bits TB[23:10] of the 24 bit start address

of the interrupt vector table. The least significant bits of TB[9:0] are fixed to "0".

The table base register TBR is initialized with FFFCH at reset, which results in an initial table

base TB = FFFC00H.

The interrupt vector table has a size of 1 kbyte (256 vector entries).

R:R/W:

readablereadable and writable

Address:

Initial Value:

Read/Write: (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)(R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

(R/W) (R/W) (R/W) (R/W) (R/W)

0 0

(R/W)

TBRH, TBRL

(R) (R)

1 1 1 1 1 1 1 1 1 1 1 1 1 1

TB23 TB22 TB21 TB20 TB19 TB18 TB17 TB16 TB15 TB14 TB13 TB12 TB11 TB103A3H, 3A2H

bit

Table 6.2-1 Examples for TBR

TBR valuestart address of

Interrupt vector table (table base)

end of Interrupt vector table

Comment

FFFCH FF.FC00H FF.FFFFH as F2MC-16FX (default)

FB00H FB.0000H FB.03FFH start of ROM bank FB

00FCH 00.FC00H 00.FFFFH end of bank 00 (can be external memory)

0010H 00.1000H 00.13FFH inside of RAM-area

0000H 00.0000H 00.03FFH do not use, because of IO-area



● Interrupt Vector Table

The interrupt vector table referenced during interrupt processing is assigned to addresses 256 ×TBR to 256 × TBR + 3FFH in memory. The reset defaults are from FFFC00H to FFFFFFH for

the location of the vector table. If the vector table should not be located at top of ROM

memory, another TBR value has to be configured.

Hardware interrupts, exceptions and software interrupts share the same vector table. Hence the

interrupt service routine can either be called by a hardware interrupt or by the corresponding

software interrupt.

The three bytes of each start address of the interrupt service routines have to be written to the

appropriate interrupt vectors (VecAddr = 4 × (255-INT#) + 256 × TBR).

Table 6.2-2 Interrupt vector table (1 / 2)

Interrupt / Vector number Vector address Index of level

register in ICRHardware IRQ / Interrupt cause

INT 0CALLV 0/1 *

TB+3FCH -- --

INT 1CALLV 2/3 *

TB+3F8H -- --

INT 2CALLV 4/5 *

TB+3F4H -- --

INT 3CALLV 6/7 *

TB+3F0H -- --

INT 4CALLV 8/9 *

TB+3ECH -- --

INT 5CALLV 10/11 *

TB+3E8H -- --

INT 6CALLV 12/13 *

TB+3E4H -- --

INT 7CALLV 14 *

TB+3E0H -- --

INT 8MODE Byte

TB+3DCH -- Reset

INT 9 TB+3D8H -- INT9 instruction

INT 10 TB+3D4H -- Undefined Instruction Exception

INT 11 TB+3D0H -- NMI

INT 12 TB+3CCH IL12 Delayed Interrupt

INT 13 TB+3C8H IL13 RC Timer

INT 14 TB+3C4H IL14 MC Timer

INT 15 TB+3C0H IL15 SC Timer

INT 16 TB+3BCH IL16 <reserved for PLL Unlock>



*: When the program bank register (PCB) is same as TBRH, the CALLV instruction vector area overlaps the

vector table of the INT#0 to INT#7 instruction. Ensure that the CALLV instruction does not use the same

address as that of the INT#0 to INT#7 instruction, or do not use INT#0 to INT#7.

INT 17 TB+3B8H IL17 Device specific peripheral.

INT 18 TB+3B4H IL18

Device specific peripheral.INT 19 TB+3B0H IL19

... ... ...

INT 254 TB+004H -- --

INT 255 TB+000H -- --

Table 6.2-2 Interrupt vector table (2 / 2)

Interrupt / Vector number Vector address Index of level

register in ICRHardware IRQ / Interrupt cause


CHAPTER 6 INTERRUPTS6.3 Interrupt Control Registers (ICR)

6.3 Interrupt Control Registers (ICR)

For each peripheral resource that has an interrupt function, there is an interrupt control register (ICR). The interrupt control register sets the interrupt level (IL) for the peripheral resource it is assigned to.

■ Interrupt control register (ICR)Figure 6.3-1 Interrupt control register (ICR) is a diagram of the bit configuration of the

interrupt control register.

Figure 6.3-1 Interrupt control register (ICR)

ICR [bits 15 to 8]: IX[7:0] Index of the interrupt level (IL) to be accessed

These bits are readable and writable, and specify the index of the interrupt level of the

corresponding internal resource. It selects the number of the interrupt level to be accessed.

IL[n] belongs to the peripheral interrupt request number IRQ[n], which both are related to

the interrupt INT[n].

The system interrupts INT0 to INT11 have a fixed priority and thus have no interrupt levels.

Writing to interrupt levels below the index of 12 has no effect, reading returns an undefined

value. The same restriction applies for not available hardware interrupts above a device

dependent maximum interrupt number.

At reset IX is initialized to "0", thus no valid interrupt level register is selected.

Figure 6.3-2 Relationship between index (IX), level (IL) and IRQ number, example for IX =

20 illustrates the access to level registers by the IX pointer. The dashed line around IX and

the selected IL shows the actual contents of the ICR.

Level configuration is written to or read from IL, where IX points to. To write the level

configuration to a dedicated IL, specify the according index by writing IX before or

simultaneously by word access. To read from a dedicated IL, IX must be written before

reading IL.

15 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

IL2 IL1 IL0

IX0IX1IX2IX3IX4IX5IX6IX7

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

0 0 0 0 0

(R/W)

0

(R/W) (R/W) (R/W)

X X X X X 1 1 1

ICR: IL

ICR: IX

( ) ( ) ( ) ( ) ( )

R/W: readable and writable: no access

1 1

Address:

Initial Value:

Read/Write:

Address:

Initial Value:

Read/Write:

3A1H

3A0H

bit

bit


CHAPTER 6 INTERRUPTS6.3 Interrupt Control Registers (ICR)

Caution for the use of concurrent tasks:

In the case of concurrent tasks accessing the interrupt level information, be careful at the

handling of the indexed access:

- Use word access to write information to ICR:IX and ICR:IL simultaneously.

- At read access, set the index ICR:IX and read the whole ICR register using word access.

Check the ICR:IX value to match the intended index to be read for validation of the

correct ICR:IL entry.

ICR [bit7 to bit3]: unused bits

Read access returns an undefined value.

Write always 0 to these bits.

ICR [bit2 to bit0]: IL[2:0] Interrupt level setting bits

These bits are readable and writable, and specify the interrupt level of the corresponding

internal resources. Upon a reset, these bits are initialized to level 7 (no interrupt). Table 6.3-1

describes the relationship between the interrupt level setting bits and interrupt levels.

Figure 6.3-2 Relationship between index (IX), level (IL) and IRQ number, example for IX = 20

Table 6.3-1 Interrupt level setting bits and interrupt levels

IL2 IL1 IL0 Level

0 0 0 0 (Strongest)

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6 (Weakest)

1 1 1 7 (No interrupt)

ICR IRQ16

IRQ21

IRQ20

IRQ18

IRQ17

IRQ19

IL16

IL17

IL18

IL19

IL20

IL21

IX=20


CHAPTER 6 INTERRUPTS6.4 Non Maskable Interrupt (NMI)

6.4 Non Maskable Interrupt (NMI)

The F2MC-16FX CPU has a non maskable interrupt. The feature of the external NMI pin can be enabled, it’s level can be defined and a flag to quit the NMI request is provided.

■ NMI control status register (NMI)Figure 6.4-1 NMI control status register (NMI) is a diagram of the bit configuration of the

interrupt control register.

Figure 6.4-1 NMI control status register (NMI)

NMI [bit15 to bit10]: unused bits

Read access returns an undefined value.

Write always 0 to these bits.

NMI [bit11]: FIX9 - Fix the location of the INT9 vector.

The FIX9 bit changes to an alternative location of the interrupt vector of INT9.

If it is set to "1", the interrupt vector is obtained from address 0F:FFD8H. If it is set to "0" the

INT9 vector location is defined by the TBR+3D8H.

At reset the FIX9 bit is initialized to "0".

The function is used by the firmware executed at device startup. Making the interrupt vector

of INT9 independent from the TBR improves the reliability of the embedded debug support

unit (EDSU).

NMI [bit10]: LEV - Signal activity level of the NMI pin.

The LEV bit defines the signal activity level of the NMI pin. A value of "1" defines logic

high active input, a value of "0" define logic low active input of the NMI pin.

If the EN bit is not set, the LEV bit is readable and writable. If the EN bit is set, the state of

LEV is locked. In that case LEV can only be read, writing to LEV with EN=1 has no effect.

At reset the LEV bit is initialized to "1", thus the NMI pin is active high by default.

15 14 13 12 11 10 9 8

(R/W)

0

Address:

Initial Value:

Read/Write:

LEV EN FLAG NMI

( ) ( ) ( ) ( ) (R/W1) (R/W0)

1 X

R/W: readable and writable: no access

R/W!:R/W0:

readable, bit can be set onlyreadable, bit can be cleared only

3A5HFIX9

(R/W)

0

bit


CHAPTER 6 INTERRUPTS6.4 Non Maskable Interrupt (NMI)

NMI [bit9]: EN - Non Maskable Interrupt feature enable bit

The EN bit enables the feature to have a dedicated NMI pin. If EN is set to "0" the device has

no NMI. The CPU will not react on signal level change at the NMI input. The pin can be

used for an other function or general purpose. If EN is set to "1", the NMI pin is enabled. The

CPU branches to the NMI exception processing, if an active signal level is detected at the

NMI pin (defined by the LEV bit).

If EN is set to "1", both the LEV and EN bits are locked for writing. Neither the signal level

can be changed nor the NMI can be disabled after the NMI feature was enabled once. Only a

device reset can change the EN bit back to "0".

At reset the EN bit is initialized to "0", thus the NMI feature is not enabled by default.

The LEV and EN bits must not be activated at same time (changed using the same access).

EN must be enabled individually at last. Otherwise, an NMI can be caused due to relaxation

time of the spike filter.

NMI [bit 8]: FLAG - Non Maskable Interrupt Flag

The NMI FLAG stores an asynchronous event of the NMI occurrence at the NMI pin.

A spike filter is used to filter out short pulses for spike suppression. The polarity of the

pulses depends on the definition in the LEV bit.

The NMI flag is set by the hardware event (NMI occurrence) and can be cleared by software

to quit the interrupt. An interrupt is only caused, if both the EN bit and FLAG are set.

The NMI FLAG can be read and cleared. Writing "1" to FLAG is ignored.

The NMI FLAG is undefined after reset. Before enabling the NMI, this flag should be

cleared.

For bit manipulation, an RMW-read operation returns always "1" for this flag.

Figure 6.4-2 Operation of the NMI control/status register

level selectionand spike filter

16FX Bus EN

SynchronizationCLKB

Wakeup

SLEEP || STOP || TIMER

1

0

NMI to CPU

lock function

NMI pin

EN

[9]

[10]

[8]

NMI LEV

NMI EN

NMI FLAGASET

SCLR

ASET: asynchronous setSCLR: synchronous clear


CHAPTER 6 INTERRUPTS6.5 Interrupt Flow (ICR)

6.5 Interrupt Flow (ICR)

Figure 6.5-2 Interrupt flow shows the interrupt flow.

■ Interrupt flowThe interrupt processing flow is entered at occurrence of hardware interrupts, software

interrupts or exceptions. For a detailed interrupt flow chart see Figure 6.5-2 Interrupt flow.

The CPU special registers are saved on the stack before the interrupt is processed (see Figure

6.5-1 Register saving during interrupt processing).

Figure 6.5-1 Register saving during interrupt processing

At the end of the interrupt processing, the context of the CPU registers is restored while

executing the RETI instruction. The CPU returns to normal program execution.

PC

PS

DPR

DTB

ADB

PCB

AL

AH

H

SSP

SSP (value before interrupt)

SSP (value after interrupt)

Word (16 bits)MSB LSB

L


CHAPTER 6 INTERRUPTS6.5 Interrupt Flow (ICR)

Figure 6.5-2 Interrupt flow

Fetching and decodingthe next instruction

INT instruction

Executing an ordinaryinstruction

Completion ofstring instruction

repetition

Updating PC

Saving PS, PC, PCB, DTB,ADB, DPR and A into thesystem stack (SSP) and

setting I = 0

S = 1Fetching the interrupt vector

I/O service byDMA processing

Saving PS, PC, PCB, DTB,ADB, DPR and A into thesystem stack (SSP) and

setting ILM = IL

IF & IE = 1and DER = 1 and

DISEL = IRQ#

STARTI, ILM: Interrupt flag and interrupt level mask in CCR/PS of CPU

Internal resource interrupt request flag and enableIF, IE:DER: DMA enable register of the related DMA channel

Level configuration of the IRQ channel by ICR/ILRIL:S: System stack flag in the CCR/PSDISEL: DMA intserrupt select register

YES

YES

NO

YES

NO

NO

YES

NO

IF & IE = 1

I=1 & IL<ILMand


CHAPTER 6 INTERRUPTS6.6 Hardware Interrupts

6.6 Hardware Interrupts

In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user.

■ Hardware interruptsA hardware interrupt occurs when the relevant conditions are satisfied as a result of two

operations:

• Comparison between the interrupt request level (IL) and the value in the interrupt levelmask register (ILM) of PS in the CPU, and

• Hardware reference to the I flag value of PS.

The CPU performs the following processing when a hardware interrupt occurs:

• Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPUto the system stack.

• The S flag is set.

• Sets ILM in the PS register. The currently requested interrupt level (IL) is automatically set.

• Fetches the corresponding interrupt vector and branches to the processing indicated by thatvalue.

If the device is in standby mode, a hardware interrupt with IL<7 generates a wake-up event to

the clock and mode control unit.

■ Structure of the hardware interrupt systemThe interrupt status is indicated by internal resources, the ICR for the interrupt controller, and

the PS value of the CPU. To use a hardware interrupt, make the following set-up:

• Interrupt vector (in memory)

- Consider the TBR value for a non-default location of the vector table.

- The start address of the interrupt service routine has to be written to the appropriate

interrupt vector (VecAddr = 4 × (255-INT#) + 256 × TBR).

• Peripheral resource

- Use the Interrupt enable and request bits to control interrupt requests from peripheral

resources.

• Interrupt controller

- Assign interrupt levels (ICR:IL) for each interrupt, which can occur.

- If interrupts occur simultaneously, a higher priority is defined by lower interrupt levels.

IL=7 disables the interrupt.

- If multiple requests are at the same level, the interrupt controller selects the request with

the lowest interrupt number. In the case of same levels configured, the delayed interrupt

has the lowest priority, independent from its interrupt number.

- There is a fixed relationship between the interrupt requests and the ILs. A level can be

defined by IL[n] for each hardware interrupt request IRQ[n] (for n >= 12).



• CPU

- ILM and I in the PS register are used to compare the requested interrupt level (IL) with

the current interrupt level mask (ILM) and to identify the interrupt enable status (I). For

acceptance of hardware interrupts, the I flag has to be set and ILM has to be larger than

IL.

- During interrupt processing, the CPU saves 12 bytes to the memory area indicated by

SSB and SSP. Thus the system stack pointer has to be initialized before using interrupts.

- The CPU fetches three bytes of the interrupt vector and loads them onto PC and PCB.

The interrupt handler routine has to start at this location. As a result, the interrupt

processing program defined by the user is executed next. Normal operation is resumed at

execution of the RETI instruction.

■ Hardware interrupt operationInterrupt requests (IRQs) from peripheral resources are fed through the DMA controller before

connecting to the interrupt controller. The DMA controller decides depending on it’s channel

configuration (DMA interrupt request select register DISEL and DMA enable DER:ENx bit), if

the IRQ is handled by DMA transfer or passed to the interrupt controller. DMA transfers are

accepted regardless of the status of the I flag and the interrupt level. The DMA controller has a

fixed priority scheme, channel 0 has highest priority and channel 15 has lowest priority.

Figure 6.6-1 Occurrence and release of hardware interrupt shows the processing flow from the

occurrence of a hardware interrupt to the release of the interrupt request in an interrupt

processing program.

Figure 6.6-1 Occurrence and release of hardware interrupt

1. An interrupt cause occurs in a peripheral.

2. The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, theperipheral issues an interrupt request (IRQ).

3. The DMA controller checks, if the IRQ should be handled by DMA. It evaluates for eachchannel, if the interrupt number of the asserted IRQ is selected and if DMA is enabled.

- If the evaluation is true, the transfer is handled by DMA (3a). If the evaluation is false,

interrupt processing is done by the interrupt controller, proceeding with step 4.

Enable FF (IE)

Source FF (I)

Peripheral

(1)

Execution Pipeline

Register File

F2 M

C-1

6FX

Bus

rator

InterruptLevelsIL

InterruptController

INT LevelINT Number

PS I

IRQ

(2)

Peripherals with IRQ

control of data transfer (3a) and IRQ clear (3b)

(4)Compa?Level

ControllerDMA(3) (5)

(6)

Comparator(7)

Check(8)

F2MC-16FX CPU

S ILM

(9a)

(9b)(9c)

(10)

(12)

Int (9)

StackOp.



- At the end of the DMA transfer, the interrupt bit is cleared in the peripheral (3b).

- If the final transfer count is reached, the DMA completion interrupt is processed by the

interrupt controller.

4. The interrupt controller receives the interrupt request.

5. The interrupt controller determines the priority levels of simultaneously requestedinterrupts.

6. The interrupt controller transfers the highest priority interrupt level and the correspondinginterrupt number to the CPU.

7. The interrupt level requested by the interrupt controller is compared with the ILM value ofthe processor status register.

8. If the comparison shows that the requested level is higher than the current interruptprocessing level (IL<ILM), the I flag value of the same processor status register is checked.

9. If the check in step 5 shows, that the I flag indicates interrupt enable status, interruptprocessing is performed as soon as the currently executing instruction is completed.

- To save the CPU status, special CPU registers are transferred to the system stack (9a).

- The S bit is set to "1" (9b).

- The requested level is written to the ILM bits (9c).

- The interrupt vector is fetched.

- Then control is transferred to the interrupt processing routine (branch to the address read

as interrupt vector).

10.When the interrupt cause of step 1 is cleared by software in the user interrupt processingroutine, the interrupt request is completed.

11.The RETI instruction is used to return from the interrupt processing routine as its lastinstruction.

12.The CPU status is restored from system stack and normal program execution is resumed.

■ Hardware interrupt processing timeThe time required for the CPU to execute the interrupt processing (stack operation, interrupt

vector fetch, branch to the interrupt vector) is shown below. The value is valid if stack

operation and interrupt vector fetch are executed without any wait cycles.

• Interrupt start: 10 cycles + c

• Interrupt return: 9 cycles + c (RETI instruction)

In addition wait cycles for bus transfers have to be added, if any (e.g. access to vector table in

slower ROM memory or external area).

Table 6.6-1 Compensation values (c) for interrupt processing cycle count

Address indicated by the stack pointer Compensation value

Internal area, even-numbered address 0

Internal area, odd-numbered address +2


CHAPTER 6 INTERRUPTS6.7 Software Interrupts

6.7 Software Interrupts

In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. This is called the software interrupt function. A software interrupt occurs always when the software interrupt instruction is executed.

■ Software interruptsA software interrupt request issued by the INT instruction has no interrupt request or enable

flag. A software interrupt request is always issued and accepted by executing the INT

instruction.

The INT instruction does not have an interrupt level. Therefore, the INT instruction does not

update ILM. The INT instruction clears the I flag to suspend subsequent hardware interrupt

requests.

The CPU performs the following processing when a software interrupt occurs:

• Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPUto the system stack.

• The S flag is set.

• Clears I in the PS register. Hardware interrupts are automatically disabled.

• Fetches the corresponding interrupt vector and branches to the processing indicated by thatvalue.

■ Structure of the software interrupt systemSoftware interrupts are fully handled within the CPU. To use a software interrupt, make the

following set-up:

• Interrupt vector (in memory)

- Consider the TBR value for a non-default location of the vector table.

- The start address of the interrupt service routine has to be written to the appropriate

interrupt vector (VecAddr = 4 × (255-INT#) + 256 × TBR).

• CPU

- During interrupt processing, the CPU saves 12 bytes to the memory area indicated by

SSB and SSP. Thus the system stack pointer has to be initialized before using interrupts.

- The CPU fetches three bytes of the interrupt vector and loads them onto PC and PCB.

The interrupt handler routine has to start at this location. As a result, the interrupt

processing program defined by the user is executed next. Normal operation is resumed at



CHAPTER 6 INTERRUPTS6.7 Software Interrupts

■ Software interrupt operation

When the CPU fetches and executes the software interrupt instruction, the software interrupt

processing sequence is activated. The software interrupt processing sequence saves 12 bytes

(PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The

sequence then fetches three bytes of interrupt vector and loads them into PC and PCB, resets

the I flag, and sets the S flag. Then, the sequence performs branch processing. As a result, the

interrupt processing program defined by the user application program is executed next.

Figure 6.7-1 Occurrence and release of software interrupt illustrates the flow from the

occurrence of a software interrupt until the return from the interrupt processing program.

Figure 6.7-1 Occurrence and release of software interrupt

1. The software interrupt instruction is executed.

2. Interrupt processing is performed by the CPU according to the software interruptinstruction.

- To save the CPU status, special CPU registers are transferred to the system stack (2a).

- The S bit is set to "1" (2b).

- The I flag is cleared to disable hardware interrupts (2c).

- The interrupt vector is fetched.

- Then control is transferred to the interrupt processing routine (branch to the address read

as interrupt vector).

3. The Interrupt service routine is processed by the CPU.

4. The interrupt processing is completed with the RETI instruction in the user interruptprocessing routine.

5. The CPU restores its context of special registers from system stack.

6. The CPU proceeds program execution with the next instruction after the INT instruction.

StackOp.

PS ILMI

Execution Pipeline

Register File

F2MC-16FX CPUQueue

F2 M

C-1

6FX

Bus

(5)Instruction

Instruction (1)INT

Instruction (4)RETI

Routine (3)Interrupt ServiceProcessing of the

S

INT (1)(2a)

clear (2c)

(2b)


CHAPTER 6 INTERRUPTS6.8 Multiple interrupts

6.8 Multiple interrupts

The F2MC-16FX CPU supports multiple interrupts (simultaneous occurring interrupts and nested interrupt processing).

■ Multiple hardware interruptsIf an hardware interrupt of a higher priority (lower level value) occurs while another interrupt

is being processed, control is transferred to the higher priority interrupt after the currently

executing instruction is completed. After processing of the higher priority interrupt is

completed, the original interrupt processing is resumed.

An interrupt of the same or lower priority may be generated while another interrupt is being

processed. If this happens, the new interrupt request is suspended until the current interrupt

processing is completed, unless the ILM value or I flag is changed by an instruction.

A DMA transfer cannot be interrupted and activated from multiple sources. While a DMA

transfer is being processed, all other DMA requests are suspended. At simultaneous occurrence

of requests for the DMA controller, the lowest channel number is processed first.

For a detailed description of DMA, refer to the hardware manual for each device.

■ Multiple software interruptsSoftware interrupts can not occur simultaneously. They are entered by executing the INT

instruction and are always accepted. However, if an INT instruction is placed within an

interrupt service routine, nested execution of software interrupts is possible.



■ Interrupt acceptance priority

Following table lists all interrupts with conditions for their acceptance.

IL and ILM: Interrupt level and mask

I: Interrupt enable flag (Peripheral type interrupts)

S: System stack flag

P: Privileged mode flag (bit 7 of CCR, PS)

Table 6.8-1 Control of interrupt acceptance priority

Event INT# Type Level Acceptance condition Action, if accepted

-Instruction Break (VEIB)system reserved

P2Current instruction execution is finished,ILM>2 || P == 1

Save CPU status to system stack

S = 1

Branch to interrupt vector

P = 0ILM = 2

-Tool Break (VENMI)system reserved

P2

Current instruction execution is finished, string instruction is interrupted,ILM>2 || P == 1

P = 0ILM = 2

11 NMI P4


P = 0ILM = 4

9Address match detection (HW-INT9)

P6


P = 0ILM = 6

from 13 on

Peripheral IRQIL

U0...U7

Current instruction execution is finished, string instruction is interrupted,ILM > ILP == 1I == 1For multiple requests with same IL, smallest IRQ number is accepted.

ILM = IL

12 Delayed INTIL

U0...U7

Current instruction execution is finished, string instruction is interrupted,ILM > ILP == 1I == 1No peripheral IRQs pending with same IL.

ILM = IL

-Software Instruction Break (INTE)system reserved

P2

always accepted

P = 0ILM = 2I = 0

9 INT9 - I = 0

10Undefined instruction exception

- I = 0

all INT instruction - I = 0

- RETI instruction -restore CPU status (including P, I, S, ILM)

Har

dwar

e ev

ent

Soft

war

e ev

ent (

Inst

ruct

ion)



Following table defines the naming of the interrupt levels, its corresponding P flag and ILM

values. It also lists the interrupt cause, which can request the interrupt level.

Table 6.8-2 Interrupt levels

Name Category P flag ILM value Priority Remarks

P0 Priviledged mode 0 0 Highest -

P1 0 1 -

P2 0 2 DSU

P3 0 3 -

P4 0 4 NMI

P5 0 5 -

P6 0 6 HW-INT9

P7 0 7 -

U0 User mode 1 0 Peripherals

U1 1 1

U2 1 2

U3 1 3

U4 1 4

U5 1 5

U6 1 6

U7 1 7 Lowest no request


CHAPTER 6 INTERRUPTS6.9 Exceptions

6.9 Exceptions

The F2MC-16FX performs exception processing at occurrence of various software and hardware events.

■ Software exceptions (op-code)Software exceptions are always accepted. Same as software interrupts, software exceptions

disable any hardware interrupt acceptance. The software exceptions occur at code execution of

following specific op-codes:

● Execution of an undefined instruction

All codes that are not defined in the instruction map are handled as undefined instructions.

When an undefined instruction is executed, processing similar to the INT #10 software

interrupt instruction is performed. Specifically, the PC value saved in the stack is the address at

which the undefined instruction is stored. Processing can be restored by the RETI instruction,

however it is of no use, because the same exception occurs again.

Operation:

(SSP)<-(SSP)-2, ((SSP))<-(AH)

(SSP)<-(SSP)-2, ((SSP))<-(AL)

(SSP)<-(SSP)-2, ((SSP))<-(DPR):(ADB)

(SSP)<-(SSP)-2, ((SSP))<-(DTB):(PCB)

(SSP)<-(SSP)-2, ((SSP))<-(PC)

(SSP)<-(SSP)-2, ((SSP))<-(PS)

(S)<-1, (I)<-0

(PCB)<-Vector #10 address (upper byte)

(PC)<-Vector #10 address (lower word)

● INT9

This instruction branches to the interrupt processing routine indicated by vector #9. Executing

the RETI instruction in the interrupt routine restores the processing subsequent to the INT9

instruction.

Operation:

(SSP)<-(SSP)-2, ((SSP))<-(AH)

(SSP)<-(SSP)-2, ((SSP))<-(AL)



(SSP)<-(SSP)-2, ((SSP))<-(PC)+1

(SSP)<-(SSP)-2, ((SSP))<-(PS)

(S)<-1, (I)<-0





● INTE (System reserved, only available with DSU)

INTE is used to insert a software break point for the debug system, using the in circuit

emulator (ICE). At insertion of a software instruction break, the first byte of the original

instruction is replaced by INTE.

This instruction branches to the interrupt processing routine indicated by a fixed vector defined

by the DSU. The PC value saved in the stack is the address at which INTE is stored. Executing

the RETI instruction in the interrupt routine restores the processing at this location (INTE can

be replaced by the original instruction at removal of the software break point).

The privileged mode flag (P flag) is cleared and the ILM register is set to 2 (enters level P2).

This disables all hardware interrupts and exceptions. The P flag and ILM are restored at


Operation:

(SSP)<-(SSP)-2, ((SSP))<-(AH)

(SSP)<-(SSP)-2, ((SSP))<-(AL)



(SSP)<-(SSP)-2, ((SSP))<-(PC)

(SSP)<-(SSP)-2, ((SSP))<-(PS)

(S)<-1, (I)<-0, (P)<-0, (ILM)<-2

(PCB)<-Fixed vector from DSU (upper byte, 00H, address is ignored by DSU)

(PC)<-Fixed vector from DSU (lower word, 0400H, address is ignored by DSU)

Without the DSU, INTE is handled same as the undefined instruction exception. Interrupt

vector #10 is referenced. The P flag is not cleared and ILM is not updated.

■ Hardware exceptions (non maskable interrupts)Hardware exceptions are external events, which are not maskable by any software instruction.

Hardware exceptions with a higher level number, than the actual processed one, are suspended

until execution of the RETI instruction restores the previous level. In addition, hardware

exceptions disable any hardware interrupt acceptance.

At occurrence of multiple hardware exceptions at the same time, they will be accepted with

following priority: VEIB > VENMI > NMI > HW-INT9. If the current interrupt level mask and

P flag setting allows it, hardware exceptions are accepted at the end of each instruction

execution and during execution of string instructions.

● HW-INT9

HW-INT9 is used by the address match detection function. With that function embedded debug

support (operand address break or data value break) or a simple memory protection can be

provided.

The privileged mode flag (P flag) is cleared and ILM is set to 6 (enters level P6). This disables

all hardware interrupts from peripherals. The P flag and ILM are restored at the execution of

the RETI instruction.

Operation:

(SSP)<-(SSP)-2, ((SSP))<-(AH)

(SSP)<-(SSP)-2, ((SSP)<-(AL)





(SSP)<-(SSP)-2, ((SSP))<-(PC)

(SSP)<-(SSP)-2, ((SSP))<-(PS)

(S)<-1, (P)<-0, (ILM)<-6



● NMI

NMI provides external hardware exception handling.


all hardware interrupts from peripherals and the HW-INT9. The P flag and ILM are restored at


Operation:

(SSP)<-(SSP)-2, ((SSP))<-(AH)

(SSP)<-(SSP)-2, ((SSP))<-(AL)



(SSP)<-(SSP)-2, ((SSP))<-(PC)

(SSP)<-(SSP)-2, ((SSP))<-(PS)

(S)<-1, (P)<-0, (ILM)<-4



● Tool break (VENMI, system reserved, only available with DSU)

VENMI is provided for debugging with DSU. It implements various break factors.


all hardware interrupts and exceptions. The P flag and ILM are restored at execution of the

RETI instruction.

Operation:

(SSP)<-(SSP)-2, ((SSP))<-(AH)

(SSP)<-(SSP)-2, ((SSP))<-(AL)



(SSP)<-(SSP)-2, ((SSP))<-(PC)

(SSP)<-(SSP)-2, ((SSP))<-(PS)

(S)<-1, (P)<-0, (ILM)<-2

(PCB)<-Fixed vector from DSU (upper byte, 00H, address is ignored by DSU)

(PC)<-Fixed vector from DSU (lower word, 0400H, address is ignored by DSU)

● Instruction break (VEIB, system reserved, only available with DSU)

VEIB is provided for debugging with DSU. It implements the instruction break before

execution. Opposed to other hardware exceptions, VEIB is not accepted during execution of a

string instruction.


CHAPTER 7ADDRESSING

This chapter describes addressing for the

F2MC-16FX instructions.Addressing specifies the data to be used and an address.

In F2MC-16FX, effective addressing or an used instruction code determines the address format (absolute address or relative address). When the address format is determined by the instruction code itself, an address must be specified in compliance with the used instruction code.Some instructions enable several types of addressing to be specified.

7.1 Effective Address Field

7.2 Direct Addressing

7.3 Indirect Addressing


CHAPTER 7 ADDRESSING7.1 Effective Address Field


Table 7.1-1 lists the address formats that may be specified in the effective address field.

■ Effective Address FieldTable 7.1-1 Effective Address Field

Code Coding Address format Default bank

0001020304050607

R0R1R2R3R4R5R6R7

RW0RW1RW2RW3RW4RW5RW6RW7

RL0(RL0)RL1

(RL1)RL2

(RL2)RL3

(RL3)

Register direct

Each column corresponds to the address coding in the byte, word, and long word types in the order left to right.

None

08090A0B

@RW0@RW1@RW2@RW3

Register indirect

DTBDTBADBSPB

0C0D0E0F

@RW0 +@RW1 +@RW2 +@RW3 +

Register indirect with post-increment

DTBDTBADBSPB

10111213

@RW0 + disp8@RW1 + disp8@RW2 + disp8@RW3 + disp8

Register indirect with 8-bit displacement

DTBDTBADBSPB

14151617


DTBDTBADBSPB

18191A1B



DTBDTBADBSPB

1C1D1E1F

@RW0 + RW7@RW1 + RW7@PC + disp16addr16

Register indirect with indexRegister indirect with indexPC indirect with 16-bit displacementDirect address

DTBDTBPCBDTB


CHAPTER 7 ADDRESSING7.2 Direct Addressing

7.2 Direct Addressing

In direct addressing, a value, register, and address must be directly specified for the operands.

■ Direct Addressing

● Immediate data (#imm)

Directly specify an operand value. There are four types of immediate data according to data

length as below:

• #imm4

• #imm8

• #imm16

• #imm32

● Register direct

Directly specify a register for the operand. Registers that can be specified are as below:

• General-purpose registers (Byte): R0, R1, R2, R3, R4, R5, R6, R7

(Word): RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

(Long word):RL0, RL1, RL2, RL3

• Dedicated registers (Accumulator): A, AL

(Pointer): SP *

(Bank): PCB, DTB, USB, SSB, ADB

(Page): DPR

(Control): PS, CCR, RP, ILM

*: For SP, either user stack pointer (USP) or system stack pointer (SSP) is selected for use,

according to the value of the S flag in the condition code register (CCR). For branch

instructions, program counter (PC) is not described in the operand of the instruction, but

it is automatically specified.

● Direct branch address (addr16)

Directly specify an address to which the execution will branch by means of displacement. The

address length with displacement is 16 bits and the address indicates the destination of the

branch in the logical space. This addressing is applied to an unconditional branch instruction

and a subroutine call instruction. bits 16 to 23 of the address are given by the program bank

register (PCB).

● Physical direct branch address (addr24)

Directly specify a physical address to which the execution will branch by means of

displacement. The data length with displacement is 24 bits. This addressing is applied to an

unconditional branch instruction, a subroutine call instruction, and a software interrupt

instruction.


CHAPTER 7 ADDRESSING7.2 Direct Addressing

● I/O direct (io)

Directly specify a memory address in the operand by means of 8-bit displacement.

Independently of the respective values for data bank register (DTB) and direct page register

(DPR), the I/O space with physical addresses 000000H to 0000FFH is accessible. It is invalid

to describe the bank select prefix to specify a bank before an instruction using this addressing.

● Abbreviated direct address (dir)

Specify lower eight bits of a memory address in the operand. Bits 8 to 15 of the address are

given by the direct page register (DPR). Bits 16 to 23 of the address are given by the data bank

register (DTB).

● Direct address (addr16)

Specify lower 16 bits of a memory address in the operand. Bits 16 to 23 of the address are

given by the data bank register (DTB).

● I/O direct bit address (io:bp)

Directly specify a bit within the range of physical addresses 000000H to 0000FFH. Bit position

is represented by :bp. The higher number is the most significant bit and the lower number is

the least significant bit.

● Abbreviated direct bit address (dir:bp)

Directly specify lower eight bits of a memory address in the operand. Bits 8 to 15 of the

address are given by the direct page register (DPR). Bits 16 to 23 of the address are given by

the data bank register (DTB). Bit position is represented by :bp. The higher number is the

most significant bit and the lower number is the least significant bit.

● Direct bit address (addr16:bp)

Directly specify an arbitrary bit within 64 Kbytes. Bits 16 to 23 of the address are given by the

data bank register (DTB). Bit position is represented by :bp. The higher number is the most

significant bit and the lower number is the least significant bit.

● Vector address (#vct)

The address to which the execution will branch is determined by the content of the vector that

is specified herein. The vector number data length may be either four bits or eight bits. This

addressing is applied to a subroutine call instruction and a software interrupt instruction.


CHAPTER 7 ADDRESSING7.3 Indirect Addressing

7.3 Indirect Addressing

In indirect addressing, the data indicated by the operand you coded indirectly gives an address.

■ Indirect Addressing

● Register indirect (@RWj j = 0 to 3)

The register indirect addressing is used to access a memory location whose address is specified

by the content of general-purpose register RWj. Bits 16 to 23 of the address are given by the

data bank register (DTB) if RW0 and RW1 are used, by the SPB if RW3 is used, and by the

additional data bank register (ADB) if RW2 is used.

● Register indirect with post-increment (@RWj+ j = 0 to 3)

This addressing is also used to access a memory location whose address is specified by the

content of general-purpose register RWj. After the execution of the operand operation, RWj is

incremented by the operand data length (1 for byte, 2 for word, and 4 for long word). Bits 16

to 23 of the address are given by the data bank register (DTB) if RW0 and RW1 are used, by

the SPB if RW3 is used, and by the additional data bank register (ADB) if RW2 is used.

If the value resulting from post-increment indicates the address of the increment-specified

register itself, the value of this register is incremented when referred subsequently. Then, if a

data write instruction is issued to the register, the priority is given to the data write instruction,

so that the register value, which would otherwise be incremented, becomes the written data.

● Register indirect with displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j = 0 to 3)

This addressing is used to access a memory location whose address is specified by the

displacement added to the content of general-purpose register RWj. Displacement may be

either byte or word and is added as a signed value. Bits 16 to 23 of the address are given by

the data bank register (DTB) if RW0, RW1, RW4, and RW5 are used. Bits 16 to 23 are given

by the SPB if RW3 and RW7 and by the additional data bank register (ADB) if RW2 and RW6

are used.

● Long register indirect with displacement (@RLi+disp8 i = 0 to 3)

This addressing is used to access a memory location whose address is specified by the lower 24

bits that result from the displacement added to the content of general-purpose register RLi.

Displacement is eight bits and added as a signed value.



● Program counter indirect with displacement (@PC+disp16)

This addressing is used to access a memory location whose address is specified by (address of

instruction + 4 + disp16). Displacement is a word length. Bits 16 to 23 of the address are

given by the program bank register (PCB).

Note that respective operand addresses of the instructions listed next are not regarded as being

(next instruction address + disp16):

• DBNZ eam, rel

• DWBNQ eam, rel

• CBNE eam, #imm8, rel

• CWBNE eam, #imml16, rel

• MOV eam, #imm8

• MOVM eam, #imm16

● Register indirect with base index (@RW0+RW7, @RW1+RW7)

This addressing is used to access a memory location whose address is specified by a value

obtained by adding the content of RW0 or RW1 to the content of general-purpose register

RW7. Bits 16 to 23 of the address are given by the data bank register (DTB).

● Program counter relative branch address (rel)

The address to which the execution will branch is determined by a value obtained by adding

the 8-bit displacement to the value of the program counter (PC). If the result of the addition

exceeds 16 bits, the bank register is not incremented or decremented and the part of excess is

ignored. Consequently, the address falls within the closed bank of 64 Kbytes. This addressing

is applied to an unconditional or conditional branch instruction. Bits 16 to 23 of the address

are given by the program bank register (PCB).

● Register List (rlst)

This addressing specifies a register subjected to push/pop for the stack (see Figure 7.3-1 ).

Figure 7.3-1 Configuration of Register List

● Accumulator indirect (@A)

This addressing is used to access a memory location whose address is specified by the 16-bit

content of the lower bytes of the accumulator (AL). Bits 16 to 23 of the address are given by

the data bank register (DTB).

MSB LSB

When the bit is "1", the associated register is selected. When the bit is "0", the associated register is not selected.

RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0



● Accumulator indirect branch address (@A)

The address to which the execution will branch is determined by the 16-bit content for the

lower bytes of the accumulator (AL). This address indicates the destination of the branch

within the bank space. Bits 16 to 23 of the address are given by the program bank register

(PCB). In the case of the jump context (JCTX) instruction, however, bits 16 to 23 of the

address are given by the data bank register (DTB). This addressing is applied to an

unconditional branch instruction.

● Indirectly specified branch address (@ear)

The word data with the address specified by ear corresponds to the address to which the

execution will branch.

● Indirectly specified branch address (@eam)

The word data with the address specified by eam corresponds to the address to which the

execution will branch.


CHAPTER 8INSTRUCTION OVERVIEW

This chapter describes the meanings of items and symbols used in explanations in "CHAPTER 9 DETAILED INSTRUCTIONS".

8.1 Instruction Overview

8.2 Symbols (Abbreviations) Used in Detailed Instructions


8.4 Execution Cycles


CHAPTER 8 INSTRUCTION OVERVIEW8.1 Instruction Overview

8.1 Instruction Overview

In "CHAPTER 9 DETAILED INSTRUCTIONS", the following items are described for each instruction.• Assembler format • Example• Operation• CCR• Byte count, cycle count

In "CHAPTER 9 DETAILED INSTRUCTIONS", the following items are described for each

instruction.

● Assembler format

The format for coding each instruction into an assembler source program is presented.

• Upper case letters and symbols: Write them as they are into a source program.

• Lower case letters: Rewrite them into a source program.

• Number after a lower case letter: Indicates a bit width in the instruction.

● Operation

The operation for registers and data by instruction execution is presented.

● CCR

The status of each flag (I, S, T, N, Z, V and C) of the condition code register (CCR) is

presented.

• *: Denotes that the flag changes with the instruction execution.

• –: Denotes that the flag does not change.

• S: Denotes that the flag is set with the instruction execution.

• R: Denotes that the flag is reset with the instruction execution.

● Byte count, cycle count

The byte count of an instruction, the cycle count at instruction execution time, and the cycle

count for correcting odd addresses are shown.

● Example

An example of each instruction is presented.

All numeric values of the data given in any example are hexadecimal numbers. Any numeric

value of the data given in the operand represents a hexadecimal number with suffix (H).


CHAPTER 8 INSTRUCTION OVERVIEW8.2 Symbols (Abbreviations) Used in Detailed Instructions

8.2 Symbols (Abbreviations) Used in Detailed Instructions

Table 8.2-1 lists the symbols used in the detailed instructions.

Table 8.2-1 Symbols (abbreviations) Used in Detailed Instructions (1 / 2)

Coding Meaning

A

32-bit accumulatorThe length of used bits varies depending on the instruction. Byte: Lower 8 bits of AL Word: 16 bits of AL Long word: 32 bits of AL and AH

AHAL

Upper 16 bits of ALower 16 bits of A

SP Stack pointer (USP or SSP)

PC Program counter

PCB Program bank register

DTB Data bank register

ADB Additional data bank register

SSB System stack bank register

USB User stack bank register

DPR Direct page register

brg1 DTB, ADB, SSB, USB, DPR, PCB

brg2 DTB, ADB, SSB, USB, DPR

Ri R0, R1, R2, R3, R4, R5, R6, R7

Rj R0, R1, R2, R3

RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RWj RW0, RW1, RW2, RW3

RLi RL0, RL1, RL2, RL3

dir Abbreviated direct addressing

addr16addr24

ad24 0-15ad24 16-23

Direct addressingPhysical direct addressingBits 0 to 15 of addr24Bits 16 to 23 of addr24

io I/O area (000000H to 0000FFH)

imm4imm8

imm16imm32

ext (imm8)

4-bit immediate data8-bit immediate data16-bit immediate data32-bit immediate data16-bit data resulting from the signed extension of 8-bit immediate data

disp8disp16

8-bit displacement16-bit displacement

bp Bit offset value


CHAPTER 8 INSTRUCTION OVERVIEW8.2 Symbols (Abbreviations) Used in Detailed Instructions

vct4vct8

Vector number (0 to 15)Vector number (0 to 255)

( )b Bit address

re1 Specifies a PC relative branch.

eaream

Effective addressing (codes 00 to 07)Effective addressing (codes 08 to 1F)

r1st Register list

Table 8.2-1 Symbols (abbreviations) Used in Detailed Instructions (2 / 2)

Coding Meaning


CHAPTER 8 INSTRUCTION OVERVIEW8.3 Effective Address Field


Table 8.3-1 lists the address formats that may be specified in the effective address field.

*: The byte count of the address expansion part is shown in the "#" (byte count) column. "numeric value+", such as "2+", written in the detailed instructions indicates the byte count of the address expansion part added to the value.

Table 8.3-1 Effective Address Field

Code Coding Address formatByte count of

address extension *

0001020304050607

R0R1R2R3R4R5R6R7

RW0RW1RW2RW3RW4RW5RW6RW7

RL0(RL0)RL1

(RL1)RL2

(RL2)RL3

(RL3)

Register direct

ea corresponds to the address coding in the byte, word, and long word types in the order left to right.

-

08090A0B

@RW0@RW1@RW2@RW3

Register indirect 0

0C0D0E0F

@RW0 +@RW1 +@RW2 +@RW3 +

Register indirect with post-increment 0

1011121314151617

@RW0 + disp8@RW1 + disp8@RW2 + disp8@RW3 + disp8@RW4 + disp8@RW5 + disp8@RW6 + disp8@RW7 + disp8

Register indirect with 8-bit displacement 1

18191A1B



1C1D1E1F

@RW0 + RW7@RW1 + RW7@PC + disp16addr16

Register indirect with indexRegister indirect with indexPC indirect with 16-bit displacementDirect address

0022


CHAPTER 8 INSTRUCTION OVERVIEW8.4 Execution Cycles

8.4 Execution Cycles

The cycle count required for the execution of an instruction (execution cycles) is obtained by adding a value of "odd addresses correction", which is determined according to the condition, to the "cycle count" specific to each instruction.

■ Execution CyclesThe cycle count required for the execution of an instruction is obtained by adding up the "cycle

count" specific to each instruction, a value of "odd addresses correction", which is determined

according to the condition.

At the actual instruction execution time, the execution cycles may become larger than the

calculated value due to the instruction fetch delay, the data access conflict, etc. Especially,

when performing instruction fetch and data access from an external bus by using the external

bus interface, the execution cycles becomes larger than the calculated value.

■ Calculating Execution CyclesTable 8.4-1 provides the referenced information which may help you to calculate instruction

execution cycles.

Table 8.4-1 Execution Cycles Specific to Each Addressing Method of an Effective Address

Code Operand(a) *

Execution cycles specific to each addressing method

00to07

RiRWiRLi

Presented in the instruction list.

08to0B

@RWj 2

0Cto0F

@RWj + 4

10to17

@RWi + disp8 2

18to1B

@RWj + disp16 2

1C1D1E1F

@RW0 + RW7@RW1 + RW7@PC + disp16

addr16

4421

*: (a) is used in "~" (cycles) in "APPENDIX B Instruction Lists (351 Instructions)" as well as "CHAPTER 9 DETAILED INSTRUCTIONS".



■ Odd address correctionFor some instructions, the execution cycles increases when performing data access to odd

addresses. The execution cycles that increases at data access time to odd addresses is shown

under the title of "odd address correction" in item B in the instruction list.


CHAPTER 9DETAILED

INSTRUCTIONS

This chapter describes each execution instruction used in the assembler in a reference format. The execution instructions are presented in alphabetical order. For an explanation of each of the items and symbols (abbreviations) used in the explanation of each execution instruction, see "CHAPTER 8 INSTRUCTION OVERVIEW".


CHAPTER 9 DETAILED INSTRUCTIONS9.1 ADD (Add Byte Data of Destination and Source to Destination)

9.1 ADD (Add Byte Data of Destination and Source to Destination)

Add the byte data specified by the second operand to the byte data specified by the first operand and store the result in the first operand.

If the first operand is the accumulator (A), "0" are transferred to bits 8 to 15 of A.

● Assembler format:

ADD A,#imm8 ADD A,dir

ADD A,ear ADD A,eam

ADD ear,A ADD eam,A

● Operation:

(First operand) ← (First operand)+(Second operand) (Byte addition)

● CCR:

I, S, and T: Unchanged

N: Set when the MSB of the operation result is "1", cleared otherwise.

Z: Set when the operation result is "0", cleared otherwise.

V: Set when an overflow has occurred as a result of the operation, cleared otherwise.

C: Set when a carry has occurred as a result of the operation, cleared otherwise.

● Byte count and cycle count:

I S T N Z V C

– – – * * * *

First operand A A A A ear eam

Second operand #imm8 dir ear eam A A

Byte count 2 2 2 2+ 2 2+

Cycle count 1 2 1 2 1 3


CHAPTER 9 DETAILED INSTRUCTIONS9.1 ADD (Add Byte Data of Destination and Source to

Destination)● Example:

ADD A,0E021H

In this example, the data (ABH) at address E021H is added to the least significant byte data

(46H) of A.

× × × × A 0 4 6 A

Before execution

× × × × 0 0 F 1 A

After execution

Memory

A B E021

Memory

A B E021

CCR × × × × ×T N Z V C

CCR × 1 0 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.2 ADDC (Add Byte Data of AL and AH with Carry to AL)

9.2 ADDC (Add Byte Data of AL and AH with Carry to AL)

Add the low-order byte data of AL, low-order byte data of AH, and carry bit (C) together and restore the result in AL. "0" are transferred to the high-order byte of AL.


ADDC A

● Operation:

(AL) ← (AH)+(AL)+(C) (Byte addition with a carry)

● CCR:







Byte count: 1

Cycle count: 1

● Example:

ADDC A

In this example, the low-order byte data (05H) of AH, low-order byte data (D4H) of AL, and

carry bit (0) are added together.

I S T N Z V C

– – – * * * *

0 5 0 5 0 0 D 4 A

Before execution

0 5 0 5 0 0 D 9 A

After execution

CCR × × × × 0

T N Z V C

CCR × 1 0 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.3 ADDC (Add Byte Data of Accumulator and Effective Address

with Carry to Accumulator)

9.3 ADDC (Add Byte Data of Accumulator and Effective Address with Carry to Accumulator)

Add the least significant byte data of the accumulator (A), byte data at the effective address, and carry bit (C) together and restore the result in the least significant byte of A. "0" are transferred to bits 8 to 15 of A.


ADDC A, ear

ADDC A, eam

● Operation:

(A) ← (A)+(ea)+(C) (Byte addition with a carry)

● CCR:







I S T N Z V C

– – – * * * *

First operand A A

Second operand ear eam

Byte count 2 2+

Cycle count 1 2


CHAPTER 9 DETAILED INSTRUCTIONS9.3 ADDC (Add Byte Data of Accumulator and Effective Address with Carry to Accumulator)

● Example:

ADDC A, 0E035H

In this example, the least significant byte data (46H) of A, data (D5H) at address E035H, and

carry bit (1) are added together.

× × × × A 0 4 6 A

Before execution

× × × × 0 0 2 C A

After execution

Memory

D 5 E035

Memory

D 5 E035

CCR × × × × 1

T N Z V C

CCR × 0 0 0 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.4 ADDCW (Add Word Data of Accumulator and Effective

Address with Carry to Accumulator)

9.4 ADDCW (Add Word Data of Accumulator and Effective Address with Carry to Accumulator)

Add the low-order word data (AL) of the accumulator (A), word data specified by the second operand, and carry bit (C) together and restore the result in the low-order word of A.


ADDCW A, ear

ADDCW A, eam

● Operation:

(A) ← (A)+(ea)+(C) (Word addition with a carry)

● CCR:







I S T N Z V C

– – – * * * *

First operand A A


Byte count 2 2+

Cycle count 1 2

Odd address correction 0 1


CHAPTER 9 DETAILED INSTRUCTIONS9.4 ADDCW (Add Word Data of Accumulator and Effective Address with Carry to Accumulator)

● Example:

ADDCW A,@RW0+

In this example, the low-order word data (2068H) of A, address data (8952H) specified by

RW0, and carry bit (1) are added together.

× × × × 2 0 6 8 A

Before execution

× × × × A 9 B B A

After execution

Memory

8 9 E025

Memory

8 9 E025

E 0 2 4RW0 E 0 2 6RW0

5 2 E024 5 2 E024

CCR × × × × 1

T N Z V C

CCR × 1 0 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.5 ADDDC (Add Decimal Data of AL and AH with Carry to AL)

9.5 ADDDC (Add Decimal Data of AL and AH with Carry to AL)

Add the low-order byte data of AL, low-order byte data of AH, and carry bit (C) together in decimal and restore the result in the low-order byte of AL. "0" are transferred to the high-order byte of AL.


ADDDC A

● Operation:

(AL) ← (AH)+(AL)+(C) (Decimal addition with a carry)

● CCR:




V: Undefined

C: Set when a carry has occurred as a result of the decimal operation, cleared otherwise.


Byte count: 1

Cycle count: 2

● Example:

ADDDC A

In this example, the low-order byte data (62H) of AL, low-order byte data (58H) of AH, and

carry bit (C) are added together in decimal operation.

I S T N Z V C

– – – * * * *

× × 6 2 × × 5 8 A

Before execution

× × 6 2 0 0 2 0 A

After execution

CCR × × × × 0

T N Z V C

CCR × 0 0 × 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.6 ADDL (Add Long Word Data of Destination and Source to Destination)

9.6 ADDL (Add Long Word Data of Destination and Source to Destination)

Add the long word data specified by the second operand to the long word data specified by the first operand and restore the result in the first operand.


ADDL A,#imm32

ADDL A,ear ADDL A,eam

● Operation:

(First operand) ← (First operand)+(Second operand) (Long word addition)

● CCR:







I S T N Z V C

– – – * * * *

First operand A A A

Second operand #imm32 ear eam

Byte count 5 2 2+

Cycle count 2 2 3

Odd address correction 0 0 1


CHAPTER 9 DETAILED INSTRUCTIONS9.6 ADDL (Add Long Word Data of Destination and Source to


ADDL A,0E077H

In this example, the data (357F41ABH) at addresses E077H to E07AH is added to the data

(85B7A073H) of A.

Before execution After execution

Memory

3 5 E07A7 F E0794 1 E078A B E077

Memory

3 5 E07A7 F E0794 1 E078A B E077

8 5 B 7 A 0 7 3 A B B 3 6 E 2 1 E A

CCR × × × × ×T N Z V C

CCR × 1 0 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.7 ADDSP (Add Word Data of Stack Pointer and Immediate Data to Stack Pointer)

9.7 ADDSP (Add Word Data of Stack Pointer and Immediate Data to Stack Pointer)

Add 16-bit immediate data or the value resulting from sign-extending 8-bit immediate data to the word data pointed to by SP (stack pointer) and restore the result in SP. If the addition result exceeds 16 bits, an underflow occurs.

CCR does not indicate whether an underflow has occurred.


(1) ADDSP #imm8

(2) ADDSP #imm16

● Operation:

(1) (SP) ← (SP)+Sign-extended #imm8 (Word addition)

(2) (SP) ← (SP)+#imm16 (Word addition)

● CCR:

None of the flags is changed.


● Example:

ADDSP #89BAH

In this example, 89BAH is added. The addition result exceeds 16 bits, causing an underflow.

I S T N Z V C

– – – – – – –

Operand #imm8 #imm16

Byte count 2 3

Cycle count 1 1

E 2 A 4

× 0 0 0 0CCR

SP

T N Z V C

Before execution

6 C 5 E

× 0 0 0 0CCR

SP

T N Z V CAfter execution


CHAPTER 9 DETAILED INSTRUCTIONS9.8 ADDW (Add Word Data of AL and AH to AL)

9.8 ADDW (Add Word Data of AL and AH to AL)

Add the word data of AH and that of AL together and restore the result to AL.


ADDW A

● Operation:

(AL) ← (AH)+(AL) (Word addition)

● CCR:







Byte count: 1

Cycle count: 1

● Example:

ADDW A

In this example, a carry occurs, causing the carry flag to be set.

I S T N Z V C

– – – * * * *

8 3 A 2 7 F 2 3 A

Before execution

8 3 A 2 0 2 C 5 A

After execution

CCR × × × × ×T N Z V C

CCR × 0 0 0 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.9 ADDW (Add Word Data of Destination and Source to Destination)

9.9 ADDW (Add Word Data of Destination and Source to Destination)

Add the word data specified by the second operand to the word data specified by the first operand and restore the result in the first operand.


ADDW A,#imm16

ADDW A,ear ADDW A,eam

ADDW ear,A ADDW eam,A

● Operation:

(First operand) ← (First operand)+(Second operand) (Word addition)

● CCR:







I S T N Z V C

– – – * * * *

First operand A A A ear eam

Second operand #imm16 ear eam A A

Byte count 3 2 2+ 2 2+

Cycle count 1 1 2 1 3

Odd address correction 0 0 1 0 2


CHAPTER 9 DETAILED INSTRUCTIONS9.9 ADDW (Add Word Data of Destination and Source to


ADDW @RW0+1,A

In this example, the low-order word data (CD04H) of the accumulator is added to the address

value (315DH) specified by @RW0+1.


Memory

3 1 E2A6

Memory

F E E2A6

E 2 A 4RW0 E 2 A 4RW0

5 D E2A5 6 1 E2A5X X E2A4 × × E2A4

× × × × C D 0 4 A × × × × C D 0 4 A

CCR × × × × ×T N Z V C

CCR × 1 0 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.10 AND (And Byte Data of Destination and Source to Destination)

9.10 AND (And Byte Data of Destination and Source to Destination)

Take the logical AND operation of the byte data specified by the first operand and the byte data specified by the second operand and restore the result in the first operand.


AND A,#imm8

AND A,ear AND A,eam

AND ear,A AND eam,A

● Operation:

(First operand) ← (First operand) and (Second operand) (Byte logical AND)

The logical AND operation of the byte data specified by the first operand and the byte data

specified by the second operand is taken on a bit-by-bit basis and the result is restored in the

first operand.

● CCR:




V: Cleared

C: Unchanged


I S T N Z V C

– – – * * R –






CHAPTER 9 DETAILED INSTRUCTIONS9.10 AND (And Byte Data of Destination and Source to


AND 0052H,A

In this example, the logical AND operation is taken of the address data (FAH) at 0052H and the

least significant byte data (55H) of the accumulator.

× × × × 0 0 5 5 A

Before execution

× × × × 0 0 5 5 A

After execution

Memory

F A 0052

Memory

5 0 0052

CCR × × × × ×T N Z V C

CCR × 0 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.11 AND (And Byte Data of Immediate Data and Condition Code Register)

9.11 AND (And Byte Data of Immediate Data and Condition Code Register)

Take the logical AND operation of the byte data of the condition code register (CCR) and 8-bit immediate data and restore the result in CCR.

In the logical AND operation, the most significant bit of the byte data is not taken into

consideration.


AND CCR,#imm8

● Operation:

(CCR) ← (CCR) and #imm8 (Byte logical AND)

● CCR:

I: Stores bit 6 of the operation result.

S: Stores bit 5 of the operation result.

T: Stores bit 4 of the operation result.

N: Stores bit 3 of the operation result.

Z: Stores bit 2 of the operation result.

V: Stores bit 1 of the operation result.

C: Stores bit 0 of the operation result.

●Byte count and cycle count:

Byte count: 2

Cycle count: 1

I S T N Z V C

* * * * * * *


CHAPTER 9 DETAILED INSTRUCTIONS9.11 AND (And Byte Data of Immediate Data and Condition

Code Register)● Example:

AND CCR,#57H

In this example, the logical AND operation is taken of the value (0110101B) of the condition

code register (CCR) and 57H.

× × × × × × × ×

CCR

A

ILM

Before execution

0I

1S

1T

0N

1Z

0V

1C

×ILM2

×ILM1

×ILM0

×MSB

× × × ×LSB

RP

× × × × × × × ×

CCR

A

ILM

After execution

0I

0S

1T

0N

1Z

0V

1C

×ILM2

×ILM1

×ILM0

×MSB

× × × ×LSB

RP


CHAPTER 9 DETAILED INSTRUCTIONS9.12 ANDL (And Long Word Data of Destination and Source to Destination)

9.12 ANDL (And Long Word Data of Destination and Source to Destination)

Take the logical AND operation for the long word data of the accumulator (A) and that specified by the second operand in a bit-by-bit basis and restore the result in A.


ANDL A,ear ANDL A,eam

● Operation:

(A) ← (A) and (Second operand) (Long word logical AND)

● CCR:




V: Cleared

C: Unchanged


I S T N Z V C

– – – * * R –

First operand A A


Byte count 2 2+

Cycle count 2 3



CHAPTER 9 DETAILED INSTRUCTIONS9.12 ANDL (And Long Word Data of Destination and Source to


ANDL A,0FFF0H

In this example, the logical AND operation is taken of the long word data (8252FEACH) of A

and the data (FF55AA00H) at 0FFF0H to 0FFF3H, in a bit-by-bit basis.


Memory

F F FFF35 5 FFF2A A FFF10 0 FFF0

Memory


8 2 5 2 F E A C A 8 2 5 0 A A 0 0 A

CCR × × × × ×T N Z V C

CCR × 1 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.13 ANDW (And Word Data of AH and AL to AL)

9.13 ANDW (And Word Data of AH and AL to AL)

Take the logical AND operation of the word data of AH and that of AL and restore the result in AL.


ANDW A

● Operation:

(AL) ← (AH) and (AL) (Word logical AND)

● CCR:




V: Cleared

C: Unchanged


Byte count: 1

Cycle count: 1

● Example:

ANDW A

In this example, the logical AND operation is taken of the word data (0426H) of AH and word

data (AB98H) of AL.

I S T N Z V C

– – – * * R –

0 4 2 6 A B 9 8 A

Before execution

0 4 2 6 0 0 0 0 A

After execution

CCR × × × × ×T N Z V C

CCR × 0 1 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.14 ANDW (And Word Data of Destination and Source to

Destination)

9.14 ANDW (And Word Data of Destination and Source to Destination)

Take the logical AND operation of the word data specified by the first operand and the word data specified by the second operand and restore the reresult in the first operand.


ANDW A,#imm16

ANDW A,ear ANDW A,eam

ANDW ear,A ANDW eam,A

● Operation:

(First operand) ← (First operand) and (Second operand) (Word logical AND)

● CCR:




V: Cleared

C: Unchanged


I S T N Z V C

– – – * * R –







CHAPTER 9 DETAILED INSTRUCTIONS9.14 ANDW (And Word Data of Destination and Source to Destination)

● Example:

ANDW 0E001H,A

In this example, the logical AND operation is taken of the word data (8342H) at addresses

0E001H and 0E002H and the low-order word data (5963H) of the accumulator.

× × × × 5 9 6 3 A

Before execution

× × × × 5 9 6 3 A

After execution

Memory

8 3 E002

Memory

0 1 E0024 2 E001 4 2 E001

CCR × × × × ×T N Z V C

CCR × 0 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.15 ASR (Arithmetic Shift Byte Data of Accumulator to Right)

9.15 ASR (Arithmetic Shift Byte Data of Accumulator to Right)

Shift the least significant byte data of the accumulator (A) arithmetically to the right by the number of bits specified by the second operand. The most significant bit of the least significant byte data for A is not changed.

The bit last shifted out from the least significant bit is stored in the carry bit (C) of the

condition code register (CCR).


ASR A,R0

● Operation:

● CCR:

I and S: Unchanged

T: Set when the shifted-out data from the carry contains one or more "1" bits, cleared

otherwise. Also cleared when the shift amount is "0".

N: Set when the MSB of the shifting result is "1", cleared otherwise.

Z: Set when the shifting result is "0", cleared otherwise.

V: Unchanged

C: Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is "0".


Byte count: 2

Cycle count: 1

I S T N Z V C

– – * * * – *

A

MSB LSB

1

C T


CHAPTER 9 DETAILED INSTRUCTIONS9.15 ASR (Arithmetic Shift Byte Data of Accumulator to Right)

● Example:

ASR A,R0

In this example, the least significant byte data (96H) of A is shifted arithmetically to the right

by three bits.

× × × × × × 9 6A

Before execution

0 3R0

× × × × × × F 2A

After execution

0 3R0CCR × × × × ×T N Z V C

CCR 1 1 0 × 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.16 ASRL (Arithmetic Shift Long Word Data of Accumulator to

Right)

9.16 ASRL (Arithmetic Shift Long Word Data of Accumulator to Right)

Shift the long word data of the accumulator (A) arithmetically to the right by the number of bits specified by the second operand.

The most significant bit of A is not changed. The bit last shifted out from the least significant

bit is stored in the carry bit (C) of the condition code register (CCR).


ASRL A,R0

● Operation:

● CCR:

I and S: Unchanged





V: Unchanged



Byte count: 2

Cycle count: 1

I S T N Z V C

– – * * * – *

A

MSB LSB

1

C T


CHAPTER 9 DETAILED INSTRUCTIONS9.16 ASRL (Arithmetic Shift Long Word Data of Accumulator to Right)

● Example:

ASRL A,R0

In this example, the long word data (12345678H) of A is shifted arithmetically to the right by

two bits.

1 2 3 4 5 6 7 8A

Before execution

0 2R0

0 4 8 D 1 5 9 EA

After execution

0 2R0

CCR × × × × 0T N Z V C

CCR 1 0 0 × 0T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.17 ASRW (Arithmetic Shift Word Data of Accumulator to Right)

9.17 ASRW (Arithmetic Shift Word Data of Accumulator to Right)

Shift the low-order word data of the accumulator (A) arithmetically to the right by one bit.

The most significant bit of the low-order word data for A is not changed. The bit shifted out

from the least significant bit is stored in the carry bit (C).


ASRW A

● Operation:

● CCR:

I and S: Unchanged

T: Set when the old carry value is equal to "1" or the old T value is equal to "1", cleared

otherwise.



V: Unchanged

C: Stores the bit shifted out from the LSB of A.


Byte count: 1

Cycle count: 1

I S T N Z V C

– – * * * – *

A

MSB LSB

1

C T



● Example:

ASRW A

In this example, the low-order word data (A096H) of A is shifted arithmetically to the right by

one bit.

× × × × A 0 9 6 A

Before execution

× × × × D 0 4 B A

After execution

CCR 0 × × × 1

T N Z V C

CCR 1 1 0 × 0

T N Z V C



9.18 ASRW (Arithmetic Shift Word Data of Accumulator to Right)

Shift the low-order word data of the accumulator (A) arithmetically to the right by the number of bits specified by the second operand.

The most significant bit of the low-order word data for A is not changed. The bit last shifted

out from the least significant bit is stored in the carry bit (C) of the condition code register

(CCR).


ASRW A,R0

● Operation:

● CCR:

I and S: Unchanged





V: Unchanged



Byte count: 2

Number of states: 1

I S T N Z V C

– – * * * – *

A

MSB LSB

1

C T



● Example:

ASRW A,R0

In this example, the low-order word data (A096H) of A is shifted arithmetically to the right by

two bits.

× × × × A 0 9 6A

Before execution

0 2R0

× × × × E 8 2 5 A

After execution

0 2R0CCR × × × × 0

T N Z V C

CCR 0 1 0 × 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.19 BBcc (Branch if Bit Condition satisfied)

9.19 BBcc (Branch if Bit Condition satisfied)

Cause a branch if the bit data specified by the first operand satisfies the condition.

Control is transferred to the address resulting from word-adding the sign-extended data,

specified by the second operand, to the address of the instruction following the BBcc

instruction.


BBC <First operand>,rel BBS <First operand>,rel

● Operation:

If the condition is satisfied: (PC) ← (PC) + <Byte count> + rel (Word addition)

If the condition is not satisfied: (PC) ← (PC)+<Byte count> (Word addition)

● CCR:

I, S, T, and N: Unchanged

Z: Set when the bit data is "0"; cleared when "1".

V and C: Unchanged


I S T N Z V C

– – – – * – –

BBcc BBC BBS

Condition Bit data = 0 Bit data = 1

First operand addr16:bp dir:bp io:bp addr16:bp dir:bp io:bp

Byte count 5 4 4 5 4 4



CHAPTER 9 DETAILED INSTRUCTIONS9.19 BBcc (Branch if Bit Condition satisfied)

● Example:

BBC 1234H:7,12H

In this example, a branch is taken if bit 7 of the data at memory address 1234H is equal to "0"

(condition satisfied).

E 1 0 0 PC

Before execution

Memory

× ×7 F 1234 : bit7 = 0× ×

E 1 1 7 PC

After execution

Memory

× ×7 F 1234× ×

+ (12 + number of bytes 5)


CHAPTER 9 DETAILED INSTRUCTIONS9.20 Bcc (Branch relative if Condition satisfied)

9.20 Bcc (Branch relative if Condition satisfied)

Each instruction causes a branch if the condition determined for that instruction is satisfied.

Control is transferred to the address resulting from word-adding the sign-extended data,

specified by the operand, to the address of the instruction following the BBcc instruction.


BZ/BEQ rel BNZ/BNE rel

BC/BLO rel BNC/BHS rel

BN rel BP rel

BV rel BNV rel

BT rel BNT rel

BLT rel BGE rel

BLE rel BGT rel

BLS rel BHI rel

BRA rel

● Operation:

If the condition is satisfied: (PC) ← (PC)+2+rel (Word addition)

If the condition is not satisfied: (PC) ← (PC)+2 (Word addition)

● CCR:



Byte count: 2

Cycle count: 2

I S T N Z V C

– – – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.20 Bcc (Branch relative if Condition satisfied)

● Branch instruction and condition:

● Example:

BHI 50H

In this example, a branch is taken if either C or Z or both of the condition code register (CCR)

are equal to "0" (condition satisfied).

Bcc BZ/BEQ

BNZ/BNE

BC/BLO

BNC/BHS

BN BP BV BNV BT BNT BRA

Condition Z=1 Z=0 C=1 C=0 N=1 N=0 V=1 V=0 T=1 T=0Always satisfied

Bcc BLT BGE BLE BGT BLS BHI

Condition V xor N = 1 V xor N = 0(V xor N) or

Z = 1(V xor N) or

Z = 0C or Z = 1 C or Z = 0

PC PC+(2+50)

CCR CCRC or Z = 0, then


E 2 0 0

0 1 0 1 0

T N Z V C

E 2 5 2

0 1 0 1 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.21 CALL (Call Subroutine)

9.21 CALL (Call Subroutine)

Cause a branch to the address specified by the operand. By executing the RET instruction in the subroutine to which control has been transferred, control returns to the instruction following the CALL instruction.


CALL @ear CALL @eam

CALL addr16

● Operation:

(SP) ← (SP)–2 (Word subtraction), ((SP)) ← (PC)+<Byte count>

(PC) ← <Operand>

● CCR:



I S T N Z V C

– – – – – – –

Operand @ear @eam addr16

Byte count 2 2+ 3

Cycle count 3 5 3

Odd address correction 1 1+1 1


CHAPTER 9 DETAILED INSTRUCTIONS9.21 CALL (Call Subroutine)

● Example:

CALL @RW0

E 5 5 8PC

Before execution

Memory

D C F3410 8 F340

× × 0124

F 3 4 0RW0 0 1 2 4SP

× × 0123× × 0122

SP

D C 0 8PC

After execution

Memory

D C F3410 8 F340

× × 0124

F 3 4 0RW0 0 1 2 2SP

E 5 01235 A 0122SP


CHAPTER 9 DETAILED INSTRUCTIONS9.22 CALLP (Call Physical Address)

9.22 CALLP (Call Physical Address)

Cause a branch to the physical address specified by the operand. By executing the RETP instruction in the subroutine to which control has been transferred, control returns to the instruction following the CALLP instruction.

The program bank register (PCB) stores the most significant byte of the data specified by the

operand.


CALLP @ear CALLP @eam

CALLP addr24

● Operation:

(SP) ← (SP)–2 (Word subtraction), ((SP)) ← (PCB) (Zero extension)

(SP) ← (SP)–2 (Word subtraction), ((SP)) ← (PC)+<Byte count>

(PCB) ← Physical address to branch to (High-order byte)

(PC) ← Physical address to branch to (Low-order word)

● CCR:



I S T N Z V C

– – – – – – –

Operand @ear @eam addr24

Byte count 2 2+ 4

Cycle count 5 7 4

Odd address correction 5 2+1 2


CHAPTER 9 DETAILED INSTRUCTIONS9.22 CALLP (Call Physical Address)

● Example:

CALLP 080711H

In this example, the most significant byte (08H) of the operand is set in the program bank

register (PCB).

4 3 4 5PC

Before execution

Memory

× × 15F900× × 15F8FF× × 15F8FE

A DPCB

F 9 0 0SP

× × 15F8FD× × 15F8FC

SP

1 5USB

0 7 1 1PC

After execution

Memory

× × 15F9000 0 15F8FFA D 15F8FE

0 8PCB

F 8 F CSP

4 3 15F8FD4 9 15F8FCSP

1 5USB

CCR × 0 × × × × ×I S T N Z V C

CCR × 0 × × × × ×I S T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.23 CALLV (Call Vectored Subroutine)

9.23 CALLV (Call Vectored Subroutine)

Cause a branch to the address pointed to by the interrupt vector specified by the operand. By executing the RET instruction in the subroutine to which control has been transferred, control returns to the instruction following the CALLV instruction.

The RET instruction is the same as that used with the CALL instruction.


CALLV #vct4

● Operation:

(SP) ← (SP)–2 (Word subtraction)((SP)) ← (PC) + 1

(PC) ← Vector address

Note:

When the value of the program bank register (PCB) is equal to "FFH", the vector area isalso used as the vector area for INT #vct8 (#0 to #7). Caution must, therefore, beexercised when the area is used. (See Table 9.23-1 .)

● CCR:



Byte count: 1

Cycle count: 5

Odd address correction: 1

I S T N Z V C

– – – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.23 CALLV (Call Vectored Subroutine)

● Example:

CALLV #15

* Note: XX is replaced by the value of the PCB register.

F 4 A 7PC

Before execution

Memory

E 1 FFE15 4 FFE0

× × 0102

0 1 0 2SP

× × 0101× × 0100

SP

E 1 5 4PC

After execution

Memory

E 1 FFE15 4 FFE0

× × 0102

0 1 0 0SP

F 4 0101A 8 0100SP

Table 9.23-1 CALLV Vector List

Instruction Vector address L Vector address H

CALLV #0 XXFFFEH XXFFFFH

CALLV #1 XXFFFCH XXFFFDH

CALLV #2 XXFFFAH XXFFFBH

CALLV #3 XXFFF8H XXFFF9H





CALLV #8 XXFFEEH XXFFEFH

CALLV #9 XXFFECH XXFFEDH

CALLV #10 XXFFEAH XXFFEBH

CALLV #11 XXFFE8H XXFFE9H






CHAPTER 9 DETAILED INSTRUCTIONS9.24 CBNE (Compare Byte Data and Branch if not equal)

9.24 CBNE (Compare Byte Data and Branch if not equal)

Perform byte comparison on the first and second operands (8-bit immediate data) and cause a branch if the first and second operands are not equal. A branch is not taken if the first and second operands are equal.

Control is transferred to the address equal to the address of the instruction following the CBNE

instruction plus the word value resulting from sign-extending the third operand.

Note that, when the first operand is @PC + disp16, the operand address is equal to the "address

of the location containing the machine instruction for the CBNE instruction + 4 + disp16", not

the "address of the location containing the machine instruction for the instruction following the

CBNE instruction 4 + disp16".


CBNE A,#imm8,rel

CBNE ear,#imm8,rel

CBNE eam,#imm8,rel

● Operation:

(First operand)≠imm8 (Byte comparison) : (PC) ← (PC)+<Byte count>+rel

(First operand)=imm8 (Byte comparison) : (PC) ← (PC)+<Byte count>

● CCR:


N: Set when the MSB of the compare operation result is "1", cleared otherwise.

Z: Set when (First operand) = imm8, cleared otherwise.

V: Set when an overflow has occurred as a result of the compare operation, cleared

otherwise.

C: Set when a borrow has occurred as a result of the compare operation, cleared

otherwise.


* : @Rwj+ addressing cannot be used in eam. If such code is executed, +4 is added to the contents of Rwj.

I S T N Z V C

– – – * * * *

First operand A ear eam *

Byte count 3 4 4+

Cycle count 5 4 5


CHAPTER 9 DETAILED INSTRUCTIONS9.24 CBNE (Compare Byte Data and Branch if not equal)

● Example:

CBNE A, #0F4H,55H

In this example, (First operand) ≠ Second operand (8-bit immediate data) is indicated.

× × × × 0 0 F 3A

Before execution

E 3 1 0PC

× × × × 0 0 F 3 A

After execution

E 3 6 8 PC

F3H≠F4H

+(55H+Byte count: 3)

CCR × × × × ×T N Z V C

CCR × 1 0 0 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.25 CLRB (Clear Bit)

9.25 CLRB (Clear Bit)

Clear the bit specified by bp to "0", in the memory location specified by the operand.


CLRB dir:bp

CLRB io:bp

CLRB addr16:bp

● Operation:

(Operand) b ← 0 (Bit transfer)

● CCR:



● Example:

CLRB 0AA55H:3

In this example, bit 3 of the data (FFH) at address AA55H is cleared to "0".

I S T N Z V C

– – – – – – –

Operand dir:bp io:bp addr16:bp

Byte count 3 3 4

Cycle count 3 3 3

Before execution

Memory

× ×F F AA55× ×

After execution

Memory

× ×F 7 AA55× ×


CHAPTER 9 DETAILED INSTRUCTIONS9.26 CMP (Compare Byte Data of Destination and Source)

9.26 CMP (Compare Byte Data of Destination and Source)

Compare the byte data specified by the first operand with that specified by the second operand and set the flag changes in the condition code register (CCR).

The data specified by the first operand and that by the second operand are not changed.

If only the accumulator (A) is specified as an operand, AH and AL are compared.


(1) CMP A,#imm8

CMP A,ear CMP A,eam

(2) CMP A

● Operation:

(1) (First operand)–(Second operand) (Byte comparison)

(2) (AH)–(AL) (Byte comparison)

● CCR:





C: Set when a borrow has occurred as a result of the operation, cleared otherwise.


I S T N Z V C

– – – * * * *

First operand A A A AH

Second operand #imm8 ear eam AL

Byte count 2 2 2+ 1

Cycle count 1 1 2 1


CHAPTER 9 DETAILED INSTRUCTIONS9.26 CMP (Compare Byte Data of Destination and Source)

● Example:

CMP A,#7FH

In this example, the least significant byte data (22H) of A is compared with 7FH.

× × × × A 0 2 2 A

Before execution

× × × × A 0 2 2A

After execution

CCR × × × × ×T N Z V C

CCR × 1 0 0 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.27 CMPL (Compare Long Word Data of Destination and Source)

9.27 CMPL (Compare Long Word Data of Destination and Source)

Compare the long word data specified by the first operand with that specified by the second operand and set the result in the condition code register (CCR).

The data specified by the first operand and that specified by the second are not changed.


CMPL A,#imm32

CMPL A,ear CMPL A,eam

● Operation:

(First operand)–(Second operand) (Long word comparison)

● CCR:







I S T N Z V C

– – – * * * *

First operand A A A


Byte count 5 2 2+

Cycle count 2 2 3



CHAPTER 9 DETAILED INSTRUCTIONS9.27 CMPL (Compare Long Word Data of Destination and

Source)● Example:

CMPL A,#12345678H

1 2 3 4 5 6 7 8 A

Before execution

1 2 3 4 5 6 7 8 A

After execution

CCR × × × × ×T N Z V C

CCR × 0 1 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.28 CMPW (Compare Word Data of Destination and Source)

9.28 CMPW (Compare Word Data of Destination and Source)

Compare the word data specified by the first operand with that specified by the second operand and set the result in the condition code register (CCR).

The data specified by the first operand and that specified by the second operand are not

changed.

If only A is specified as an operand, AH and AL are compared.


(1) CMPW A,#imm16

CMPW A,ear CMPW A,eam

(2) CMPW A

● Operation:

(1) (First operand)–(Second operand) (Word comparison)

(2) (AH)–(AL) (Word comparison)

● CCR:







I S T N Z V C

– – – * * * *

First operand A A A AH

Second operand #imm16 ear eam AL

Byte count 3 2 2+ 1

Cycle count 1 1 2 1

Odd address correction 0 0 1 0


CHAPTER 9 DETAILED INSTRUCTIONS9.28 CMPW (Compare Word Data of Destination and Source)

● Example:

CMPW A,RW0

In this example, the low-order word data (ABCDH) of A is compared with the data (ABCCH)

specified by RW0.

× × × × A B C DA

Before execution

A B C CRW0

× × × × A B C DA

After execution

A B C CRW0

CCR × × × × ×T N Z V C

CCR × 0 0 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.29 CWBNE (Compare Word Data and Branch if not Equal)

9.29 CWBNE (Compare Word Data and Branch if not Equal)

Perform word comparison on the first and second operands (16-bit immediate data) and cause a branch if the first and second operands are not equal. A branch is not taken if the first and second operands are equal.

Control is transferred to the address equal to the address of the instruction following the

CWBNE instruction plus the word data resulting from sign-extending the third operand.

When the first operand is @PC + disp16, the operand address is equal to the "address of the

location containing the machine instruction for the CWBNE instruction + 4 + disp16", not the

"address of the location containing the machine instruction for the instruction following the

CWBNE instruction + disp16".


CWBNE A,#imm16,rel

CWBNE ear,#imm16,rel

CWBNE eam,#imm16,rel

● Operation:

(First operand)≠imm16 (Word comparison) : (PC) ← (PC)+<Byte count>+rel

(First operand)=imm16 (Word comparison) : (PC) ← (PC)+<Byte count>

● CCR:


N: Set when the MSB of the comparison result is "1", cleared otherwise.

Z: Set when (First operand) = #imm16, cleared otherwise.

V: Set when an overflow has occurred as a result of the compare operation, cleared

otherwise.

C: Set when a borrow has occurred as a result of the compare operation, cleared

otherwise.


I S T N Z V C

– – – * * * *

First operand A ear eam *

Byte count 4 5 5+

Cycle count 5 5 6



CHAPTER 9 DETAILED INSTRUCTIONS9.29 CWBNE (Compare Word Data and Branch if not Equal)

● Example:

CWBNE A,#0E5E5H,30H

In this example, (First operand) ≠ imm16.

× × × × 5 E E 5A

Before execution

D 8 5 6PC

× × × × 5 E E 5 A

After execution

D 8 8 A PC

CCR × × × × ×T N Z V C

CCR × 0 0 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.30 DBNZ (Decrement Byte Data and Branch if not "0")

9.30 DBNZ (Decrement Byte Data and Branch if not "0")

Decrement the data specified by the first operand by one byte, and if the result is not equal to "0", a branch is generated. If the decrement result is equal to "0", control is transferred to the next instruction.

Control is transferred to the address equal to the address of the instruction following the DBNZ

instruction plus the word data resulting from sign-extending the data specified by the second

operand. When the first operand is @PC + disp16, the operand address is equal to the "address

of the location containing the machine instruction for the DBNZ instruction + 4 + disp16", not

the "address of the location containing the machine instruction for the instruction following the

DBNZ instruction + disp16".


DBNZ ear,rel DBNZ eam,rel

● Operation:

(ea) ← (ea)–1 (Byte subtraction)

if (ea) ≠ 0 : (PC) ← (PC)+<Byte count>+rel

if (ea) = 0 : (PC) ← (PC)+<Byte count>

● CCR:





C: Unchanged


I S T N Z V C

– – – * * * –

First operand ear eam

Byte count 3 3+

Cycle count 5 6


CHAPTER 9 DETAILED INSTRUCTIONS9.30 DBNZ (Decrement Byte Data and Branch if not "0")

● Example:

DBNZ @RW0+2,40H

In this example, (First operand) - 1 ≠ 0 is shown.

E 3 5 8 PC

Before execution

Memory

0 3 0122× × 0121× × 0120

0 1 2 0 RW0

RW0+2

E 3 9 C PC

After execution

Memory

0 2 0122× × 0121× × 0120

0 1 2 0 RW0

RW0+2

CCR 0 0 0 0 1T N Z V C

CCR 0 0 1 0 1T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.31 DEC (Decrement Byte Data)

9.31 DEC (Decrement Byte Data)

Decrement the byte data specified by the operand by one and store the result in the operand.


DEC ear DEC eam

● Operation:

(ea) ← (ea)–1 (Byte subtraction)

● CCR:





C: Unchanged


● Example:

DEC R1

I S T N Z V C

– – – * * * –

Operand ear eam

Byte count 2 2+

Cycle count 1 3

Before execution

8 0R1

After execution

7 FR1

CCR × 0 0 1 ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.32 DECL (Decrement Long Word Data)

9.32 DECL (Decrement Long Word Data)

Decrement the long word data specified by the operand by one and restore the result in the operand.


DECL ear DECL eam

● Operation:

(ea) ← (ea)–1 (Long word subtraction)

● CCR:





C: Unchanged


● Example:

DECL RL0

I S T N Z V C

– – – * * * –

Operand ear eam

Byte count 2 2+

Cycle count 2 4


0 0 0 0 1 0 0 0 RL0

Before execution

0 0 0 0 0 F F F RL0

After execution

CCR × × × × ×T N Z V C

CCR × 0 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.33 DECW (Decrement Word Data)

9.33 DECW (Decrement Word Data)

Decrement the word data specified by the operand by one and restore the result in the operand.


DECW ear DECW eam

● Operation:

(ea) ← (ea)–1 (Word subtraction)

● CCR:





C: Unchanged


I S T N Z V C

– – – * * * –

Operand ear eam

Byte count 2 2+

Cycle count 1 3



CHAPTER 9 DETAILED INSTRUCTIONS9.33 DECW (Decrement Word Data)

● Example:

DECW @RW0+1000H

Before execution

Memory

0 0 77810 1 7780× × 777F

6 7 8 0 RW0

RW0+1000H

After execution

Memory

0 0 77810 0 7780× × 777F

6 7 8 0 RW0

RW0+1000H

CCR × × × × ×T N Z V C

CCR × 0 0 1 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.34 DIV (Divide Word Data by Byte Data)

9.34 DIV (Divide Word Data by Byte Data)

Divide the word data specified by the first operand by the byte data specified by the second operand and store the quotient (byte data) in the first operand and the remainder (byte data) in the second operand. The operation assumes that the values are signed ones.

If only A is specified by an operand, the word data of AH is divided by the byte data of AL and

the quotient (byte data) is stored in AL and the remainder (byte data) in AH. The operation

assumes that the values are signed ones.

If division by "0" occurs, the second operand or AL retains the value it had immediately before

the instruction was executed. If an overflow occurs, the contents of AL are destroyed.


(1) DIV A,ear DIV A,eam

(2) DIV A

● Operation:

(1) Word (A)/Byte (ea), Quotient → Byte (A), Remainder → Byte (ea)

(2) Word (AH)/Byte (AL), Quotient → Byte (AL), Remainder → Byte (AH)

● CCR:

I, S, T, N, and Z: Unchanged

V: Set when an overflow has occurred as a result of the operation or the divisor

is "0", cleared otherwise.

C: Set when the divisor is "0", cleared otherwise.


I S T N Z V C

– – – – – * *

Second operand DIV A DIV A, ear DIV A, eam

Byte count 2 2 2+

Cycle countOverflow: 5

Normal termination: 11Overflow: 5


Normal termination: 13


CHAPTER 9 DETAILED INSTRUCTIONS9.34 DIV (Divide Word Data by Byte Data)

● Example:

DIVA

1 3 5 7 0 0 A AA

Before execution

0 0 3 1 E C D 8A

After execution

AH AHAL AL

CCR × × × × ×T N Z V C

CCR × × × 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.35 DIVW (Divide Long Word Data by Word Data)

9.35 DIVW (Divide Long Word Data by Word Data)

Divide the long word data specified by the first operand (A) by the word data specified by the second operand and store the quotient (word data) in A and the remainder (word data) in the second operand. The operation assumes that the values are signed ones.

If division by "0" occurs, the second operand or AL retains the value it had immediately before

the instruction was executed. If an overflow occurs, the contents of AL are destroyed.


DIVW A,ear DIVW A,eam

● Operation:

Long word (A)/Word (ea), Quotient → Word (A), Remainder → Word (ea)

● CCR:






I S T N Z V C

– – – – – * *


Byte count 2 2+






CHAPTER 9 DETAILED INSTRUCTIONS9.35 DIVW (Divide Long Word Data by Word Data)

● Example:

DIVW A,7254H

0 0 0 0 1 3 5 7 A

Before execution

0 0 0 0 0 0 1 D A

After execution

Memory

0 0 7255

Memory

0 0 7255A A 7254 1 5 7254

AH AL AH AL

CCR × × × × ×T N Z V C

CCR × × × 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.36 DIVU (Divide unsigned Word Data by unsigned Byte Data)

9.36 DIVU (Divide unsigned Word Data by unsigned Byte Data)

Divide the word data specified by the first operand by the byte data specified by the second operand and store the quotient (byte data) in the first operand and the remainder (byte data) in the second operand. The operation assumes that the values are unsigned ones.

If only A is specified by an operand, the word data of AH is divided by the byte data of AL and

the quotient (byte data) is stored in AL and the remainder (byte data) in AH. The operation

assumes that the values are unsigned ones.

If an overflow or division by "0" occurs, the second operand or AL retains the value it had

immediately before the instruction was executed.


(1) DIVU A,ear DIVU A,eam

(2) DIVU A

● Operation:

(1) Word (A)/Byte (ea), Quotient → Byte (A), Remainder → Byte (ea)

(2) Word (AH)/Byte (AL), Quotient → Byte (AL), Remainder → Byte (AH)

● CCR:






I S T N Z V C

– – – – – * *

Second operand – ear eam

Byte count 1 2 2+






CHAPTER 9 DETAILED INSTRUCTIONS9.36 DIVU (Divide unsigned Word Data by unsigned Byte Data)

● Example:

DIVU A

1 3 5 7 0 0 A A A

Before execution

0 0 1 5 0 0 1 DA

After execution

CCR × × × × ×T N Z V C

CCR × × × 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.37 DIVUW (Divide unsigned Long Word Data by unsigned Word Data)

9.37 DIVUW (Divide unsigned Long Word Data by unsigned Word Data)

Divide the long word data specified by the first operand (A) by the word data specified by the second operand and store the quotient (word data) in A and the remainder (word data) in the second operand. The operation assumes that the values are unsigned ones.

If an overflow or division by "0" occurs, the second operand or AL retains the value it had

immediately before the instruction was executed.


DIVUW A,ear DIVUW A,eam

● Operation:

Long Word (A)/Word (ea), Quotient → Word (A), Remainder → Word (ea)

● CCR:






I S T N Z V C

– – – – – * *


Byte count 2 2+






CHAPTER 9 DETAILED INSTRUCTIONS9.37 DIVUW (Divide unsigned Long Word Data by unsigned

Word Data)● Example:

DIVUW A,7254H

0 0 0 0 1 3 5 7 A

Before execution

0 0 0 0 0 0 1 DA

After execution

Memory

0 0 7255

Memory

0 0 7255A A 7254 1 5 7254

CCR × × × × ×T N Z V C

CCR × × × 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.38 DWBNZ (Decrement Word Data and Branch if not Zero)

9.38 DWBNZ (Decrement Word Data and Branch if not Zero)

Decrement the data specified by the first operand by one word, and if the result is not equal to "0", cause a branch. If the decrement result is equal to "0", control is transferred to the instruction following the DWBNZ instruction.

Control is transferred to the address equal to the address of the instruction following the

DWBNZ instruction plus the word data resulting from sign-extending the data specified by the

second operand.

When the first operand is @PC + disp16, the operand address is equal to the "address of the

location containing the machine instruction for the DWBNZ instruction + 4 + disp16", not the

"address of the location containing the machine instruction for the instruction following the

DWBNZ instruction + disp16".


DWBNZ ear,rel DWBNZ eam,rel

● Operation:

(First operand) ← (First operand)–1 (Word subtraction)

When (First operand)≠0, (PC) ← (PC)+<Byte count>+second operand

(PC) ← (PC)+<Byte count>

● CCR:





C: Unchanged


I S T N Z V C

– – – * * * –


Byte count 3 3+

Cycle count 5 6



CHAPTER 9 DETAILED INSTRUCTIONS9.38 DWBNZ (Decrement Word Data and Branch if not Zero)

● Example:

DWBNZ RW0,30H

In this example, (First operand) – 1 = 0.

F 8 2 0PC

Before execution

0 0 0 1RW0

F 8 2 3PC

After execution

0 0 0 0RW0

CCR × × × × ×T N Z V C

CCR × 0 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.39 EXT (Sign Extend from Byte Data to Word Data)

9.39 EXT (Sign Extend from Byte Data to Word Data)

Extend the least significant byte data of A to word data as a signed binary number.


EXT

● Operation:

When bit 7 of A=0, bits 8 to 15 of A ← 00H

When bit 7 of A≠0, bits 8 to 15 of A ← FFH

● CCR:


N: Set when the MSB of the sign-extended data is "1", cleared otherwise.

Z: Set when the sign-extended data is "0", cleared otherwise.

V and C: Unchanged


Byte count: 1

Cycle count: 1

● Example:

EXT

In this example, the most significant bit of the least significant byte data ("80H") for A is equal

to "1", and "FFH" is set in bits 8 to 15 of A to extend the byte data.

I S T N Z V C

– – – * * – –

× × × × × × 8 0 A

Before execution

× × × × F F 8 0 A

After execution

CCR × × × × ×T N Z V C

CCR × 1 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.40 EXTW (Sign Extend from Word Data to Long Word Data)

9.40 EXTW (Sign Extend from Word Data to Long Word Data)

Extend the low-order word data of A to long word data as a signed binary number.


EXTW

● Operation:

When bit15 of A=0, bits 16 to 31 of A ← 0000H

When bit15 of A≠0, bits 16 to 31 of A ← FFFFH

● CCR:


N: Set when the MSB of the sign-extended data is "1", cleared otherwise.

Z: Set when the sign-extended data is "0", cleared otherwise.

V and C: Unchanged


Byte count: 1

Cycle count: 1

● Example:

EXTW

In this example, the most significant bit of the low-order word data ("FF80H") for A is equal to

"1", and "FFFFH" is set in bits 16 to 31 of A to extend the low-order word data.

I S T N Z V C

– – – * * – –

× × × × F F 8 0 A

Before execution

F F F F F F 8 0 A

After execution

CCR × × × × ×T N Z V C

CCR × 1 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.41 FILS, FILSI (Fill String Byte)

9.41 FILS, FILSI (Fill String Byte)

Transfer the contents of AL to the RW0-byte area that starts from the address whose high-order eight bits are specified by the bank register specified by <bank> and whose low-order 16 bits are specified by the contents of AH.

If RW0 is equal to "0", transfer is not performed. If an interrupt occurs during the execution of

the instruction, the execution of the instruction is suspended. After the interrupt has been

handled, the execution of the instruction is resumed.

Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. If <bank> is

omitted, DTB is assumed.


FILS [<bank>]

FILSI [<bank>]

● Operation:

While RW0 ≠ 0, the following operation is repeated:

((AH)) ← (AL) (Byte transfer), (AH) ← (AH)+1,

(RW0) ← (RW0)–1

● CCR:


N: Set when the MSB of the transferred data is "1", cleared otherwise.

Z: Set when the transferred data is "0", cleared otherwise.

V and C: Unchanged


Byte count: 2

Cycle count: ((RW0)+1)/2


I S T N Z V C

– – – * * – –


CHAPTER 9 DETAILED INSTRUCTIONS9.41 FILS, FILSI (Fill String Byte)

● Example:

FILS

0 1 0 0RW0

Before execution

Memory

× × 94BD00× × 94BCFF× × 94BCFE

9 4DTB

× × 94BC02× × 94BC01

AH

B C 0 0 0 0 E 5 AH AL

× × 94BC00

0 0 0 0RW0

Memory

× × 94BD00E 5 94BCFFE 5 94BCFE

9 4DTB

E 5 94BC02E 5 94BC01

AH

B D 0 0 0 0 E 5 AH AL

E 5 94BC00

After execution

... ... ... ...

CCR × × × × ×T N Z V C

CCR × 1 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.42 FILSW, FILSWI (Fill String Word)

9.42 FILSW, FILSWI (Fill String Word)

Transfer the contents of AL to the RW0-word area that starts from the address whose high-order eight bits are specified by the bank register specified by <bank> and whose low-order 16 bits are specified by the contents of AH.

If RW0 is equal to "0", transfer is not performed. If an interrupt occurs during the execution of

the instruction, the execution of the instruction is suspended. After the interrupt has been

handled, the execution of the instruction is resumed.

Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. If <bank> is

omitted, DTB is assumed.


FILSW [<bank>]

FILSWI [<bank>]

● Operation:

While RW0 ≠ 0, the following operation is repeated:

((AH)) ← (AL) (Word transfer), (AH) ← (AH)+2,

(RW0) ← (RW0)–1

● CCR:




V and C: Unchanged


Byte count: 2

Cycle count: 1 when (RW0) is "0"; (RW0) in all other cases


I S T N Z V C

– – – * * – –


CHAPTER 9 DETAILED INSTRUCTIONS9.42 FILSW, FILSWI (Fill String Word)

● Example:

FILSW ADB

0 0 8 0RW0

Before execution

Memory

× × 49ACFF× × 49ACFE× × 49ACFD

4 9ADB

× × 49AC00× × 49ABFF

AH

A B F E E 5 5 EAH AL

× × 49ABFE

0 0 0 0RW0

Memory

× × 49ACFF× × 49ACFEE 5 49ACFD

4 9ADB

5 E 49AC00E 5 49ABFF

AH

A C F E E 5 5 EAH AL

5 E 49ABFE

After execution

... ... ... ...

CCR × × × × ×T N Z V C

CCR × 0 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.43 INC (Increment Byte Data (Address Specification))

9.43 INC (Increment Byte Data (Address Specification))

Increment the byte data specified by the operand by one and restore the result in the operand.


INC ear INC eam

● Operation:

(Operand) ← (Operand)+1 (Byte increment)

● CCR:





C: Unchanged


● Example:

INC R0

I S T N Z V C

– – – * * * –

Operand ear eam

Byte count 2 2+

Cycle count 1 3

Before execution

F FR0

After execution

0 0R0

CCR × × × × ×T N Z V C

CCR × 0 1 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.44 INCL (Increment Long Word Data)

9.44 INCL (Increment Long Word Data)

Increment the long word data specified by the operand by one and restore the result in the operand.


INCL ear INCL eam

● Operation:

(Operand) ← (Operand)+1 (Long word increment)

● CCR:





C: Unchanged


● Example:

INCL RL0

I S T N Z V C

– – – * * * –

Operand ear eam

Byte count 2 2+

Cycle count 2 4


7 F F F F F F FRL0

Before execution

8 0 0 0 0 0 0 0A

After execution

CCR × × × × ×T N Z V C

CCR × 1 0 1 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.45 INCW (Increment Word Data)

9.45 INCW (Increment Word Data)

Increment the word data specified by the operand by one and restore the result in the operand.


INCW ear INCW eam

● Operation:

(Operand) ← (Operand)+1 (Word increment)

● CCR:





C: Unchanged


I S T N Z V C

– – – * * * –

Operand ear eam

Byte count 2 2+

Cycle count 1 3



CHAPTER 9 DETAILED INSTRUCTIONS9.45 INCW (Increment Word Data)

● Example:

INCW @RW0+

Before execution

Memory

× × 0357× × 03560 1 0355

0 3 5 4 RW0

RW0

After execution

0 3 5 6 RW0

0 1 0354

Memory

× × 0357× × 03560 1 0355

RW0

0 2 0354

CCR × × × × ×T N Z V C

CCR × 0 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.46 INT (Software Interrupt)

9.46 INT (Software Interrupt)

Cause a branch to the interrupt handling routine at the specified address in the bank 0FFH. By executing the RETI instruction in the interrupt handling routine

to which control has been transferred, control returns to the instruction following this instruction.


INT addr16

● Operation:

(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP)) ← (AL)

(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB) (DPR and ADB are saved as a set, DPR as

the high-order byte and ADB as the low-

order byte.)

(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB) (DTB and PCB are saved as a set, DTB as the

high-order byte and PCB as the low-order

byte.)

(SSP) ← (SSP)–2, ((SSP)) ← (PC+3), (SSP) ← (SSP)–2, ((SSP)) ← (PS)

(S) ← 1, (I) ← 0, (PCB) ← 0FFH, (PC) ← addr16

● CCR:

I: Cleared

S: Set

T, N, Z, V, and C: Unchanged


Byte count: 3

Cycle count: 8


I S T N Z V C

R S – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.46 INT (Software Interrupt)

● Example:

INT 020F2H

7 7 6 6PC

9 9DTB

F F E E D D C CSA

Memory038000

× × 037FFF× × 037FFE

SSP

8 8PCB

B BDPR

A AADB

0 3ILM

1 0RP

0 3SSB

8 0 0 0SSP

× × 037FFD× × 037FFC× × 037FFB× × 037FFA× × 037FF9× × 037FF8× × 037FF7× × 037FF6× × 037FF5× × 037FF4

Before execution

2 0 F 2PC

9 9DTB

F F E E D D C CSA

Memory038000

F F 037FFFE E 037FFE

SSP

F FPCB

B BDPR

A AADB

0 3ILM

1 0RP

0 3SSB

7 F F 4 SSP

D D 037FFDC C 037FFCB B 037FFBA A 037FFA9 9 037FF98 8 037FF87 7 037FF76 9 037FF67 0 037FF58 5 037FF4

After execution

CCR CCR

I S T N Z V C0 1 0 0 1 0 1

I S T N Z V C0 0 0 0 1 0 1


CHAPTER 9 DETAILED INSTRUCTIONS9.47 INT (Software Interrupt (Vector Specification))

9.47 INT (Software Interrupt (Vector Specification))

Cause a branch to the interrupt handling routine pointed to by the interrupt vector specified by the operand.


INT #vct8

● Operation:

(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP) ← (AL)



order byte.)



byte.)


(S) ← 1, (I) ← 0, (PCB) ← Vector address (High-order byte)

(PC) ← Vector address (Low-order word)

● CCR:

I: Cleared

S: Set



Byte count: 2

Cycle count: 12


I S T N Z V C

R S – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.47 INT (Software Interrupt (Vector Specification))

● Example:

INT #11

7 7 6 6PC

9 9DTB

CCR

SA

038000× × 037FFF× × 037FFE

SSP

8 8PCB

B BDPR

A AADB

0 2ILM

1 5RP

0 3SSB

8 0 0 0SSP


Before execution

E 7 9 5PC

9 9DTB

CCR

SA

F F 037FFFE E 037FFE

SSP

8 9PCB

B BDPR

A AADB

0 2ILM

1 5RP

0 3SSB

7 F F 4SSP


After execution

Memory

8 9 FFFFD2E 7 FFFFD19 5 FFFFD0

Memory

8 9 FFFFD2E 7 FFFFD19 5 FFFFD0

I S T N Z V C0 1 0 0 1 0 1

I S T N Z V C0 0 0 0 1 0 1

F F E E D D C C F F E E D D C C


CHAPTER 9 DETAILED INSTRUCTIONS9.48 INT9 (Software Interrupt)

9.48 INT9 (Software Interrupt)

Cause a branch to the interrupt handling routine pointed to by the vector. By executing the RETI instruction in the interrupt handling routine to which control has been transferred, control returns to the instruction following this instruction.


INT9

● Operation:




order byte.)



byte.)


(S) ← 1, (I) ← 0, (PCB) ← Vector address (High-order byte)

(PC) ← Vector address (Low-order word)

● CCR:

I: Cleared

S: Set



Byte count: 1

Cycle count: 12


I S T N Z V C

R S – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.48 INT9 (Software Interrupt)

● Example:

INT9

9 9 A APC

7 7DTB

SA

038000× × 037FFF× × 037FFE

SSP

8 8PCB

5 5DPR

6 6ADB

0 2ILM

1 5RP

0 3SSB

8 0 0 0 SSP


Before execution

E 7 9 5PC

7 7DTB

SA

1 1 037FFF2 2 037FFE

SSP

8 9PCB

5 5DPR

6 6ADB

0 2ILM

1 5RP

0 3SSB

7 F F 4 SSP

3 3 037FFD4 4 037FFC5 5 037FFB6 6 037FFA7 7 037FF98 8 037FF89 9 037FF7A B 037FF65 5 037FF58 5 037FF4

After execution

Memory

8 9 FFFFDAE 7 FFFFD99 5 FFFFD8

Memory

8 9 FFFFDAE 7 FFFFD99 5 FFFFD8

1 1 2 2 3 3 4 4 1 1 2 2 3 3 4 4

CCR CCR

I S T N Z V C0 1 0 0 1 0 1

I S T N Z V C0 0 0 0 1 0 1


CHAPTER 9 DETAILED INSTRUCTIONS9.49 INTP (Software Interrupt)

9.49 INTP (Software Interrupt)

Cause a branch to the interrupt handling routine at the 24-bit physical address specified by the operand. Any address in the entire 16MB space can be specified. By executing the RETI instruction in the interrupt handling routine to which control has been transferred, control returns to the instruction following this instruction.


INTP addr24

● Operation:


(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB) (DPR: High-order byte, ADB: Low-order byte)

(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB) (DTB: High-order byte, PCB: Low-order byte)


(S) ← 1, (I) ← 0, (PCB) ← Most significant byte of addr24,

(PC) ← Low-order word of addr24

● CCR:

I: Cleared

S: Set



Byte count: 4

Cycle count: 8


I S T N Z V C

R S – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.49 INTP (Software Interrupt)

● Example:

INTP 0C8F220H

9 9 A APC

7 7DTB

1 1 2 2 3 3 4 4A

Memory038000

× × 037FFF× × 037FFE

SSP

8 8PCB

5 5DPR

6 6ADB

0 3ILM

1 0RP

0 3SSB

8 0 0 0SSP


Before execution

F 2 2 0PC

7 7DTB

A

Memory038000

1 1 037FFF2 2 037FFE

SSP

C 8PCB

5 5DPR

6 6ADB

0 3ILM

1 0RP

0 3SSB

7 F F 4 SSP

3 3 037FFD4 4 037FFC5 5 037FFB6 6 037FFA7 7 037FF98 8 037FF89 9 037FF7A E 037FF67 0 037FF58 5 037FF4

After execution

1 1 2 2 3 3 4 4

CCR CCR

I S T N Z V C0 1 0 0 1 0 1

I S T N Z V C0 0 0 0 1 0 1


CHAPTER 9 DETAILED INSTRUCTIONS9.50 JCTX (Jump Context)

9.50 JCTX (Jump Context)

Restore register contents or an address saved in memory.


JCTX @A

● Operation:

(temp) ← (AL)

(PS) ← ((temp)) : (temp) ← (temp)+2

(PC) ← ((temp)) : (temp) ← (temp)+2

(DTB), (PCB) ← ((temp)) : (temp) ← (temp)+2

(DPR), (ADB) ← ((temp)) : (temp) ← (temp)+2

(AL) ← ((temp)) : (temp) ← (temp)+2

(AH) ← ((temp))

● CCR:

I: Stores bit 6 of the address indicated by AL.

S: Stores bit 5 of the address indicated by AL.

T: Stores bit 4 of the address indicated by AL.

N: Stores bit 3 of the address indicated by AL.

Z: Stores bit 2 of the address indicated by AL.

V: Stores bit 1 of the address indicated by AL.

C: Stores bit 0 of the address indicated by AL.


Byte count: 1

Cycle count: 23 when the content of RP changes; 6 in all other cases

I S T N Z V C

* * * * * * *


CHAPTER 9 DETAILED INSTRUCTIONS9.50 JCTX (Jump Context)

● Example:

JCTX @A

× × × ×PC

0 9DTB

SA

Memory09E02C

C B 09E02B7 5 09E02A

AL

× ×PCB

× ×DPR

× ×ADB

× ×ILM

× ×RP

0 2 09E0295 0 09E0280 8 09E027C E 09E0268 0 09E0255 0 09E0248 8 09E0230 1 09E022F 6 09E0218 A 09E020

Before execution

8 8 0 1PC

8 0DTB

SA

5 0PCB

0 8DPR

C EADB

0 7ILM

1 6RP

Memory09E02C

C B 09E02B7 5 09E02A0 2 09E0295 0 09E0280 8 09E027C E 09E0268 0 09E0255 0 09E0248 8 09E0230 1 09E022F 6 09E0218 A 09E020

After execution

CCR CCR

I S T N Z V C0 0 0 1 0 1 0

I S T N Z V C

× × × × × × ×

× × × × E 0 2 0 C B 7 5 0 2 5 0


CHAPTER 9 DETAILED INSTRUCTIONS9.51 JMP (Jump Destination Address)

9.51 JMP (Jump Destination Address)

Read the word data from the address specified by the operand and cause a branch to the address specified by the word data.


JMP @A JMP addr16

JMP @ear JMP @eam

● Operation:

(PC) ← (Operand)

● CCR:



● Example:

JMP @@ RW0+2

I S T N Z V C

– – – – – – –

Operand @A @ear @eam addr16

Byte count 1 2 2+ 3

Cycle count 2 2 4 2


Before execution

Memory

D B A0A38 0 A0A2× × A0A1

E 0 0 0 PC

RW0+2

× × A0A0

A 0 A 0 RW0

After execution

Memory

D B A0A38 0 A0A2× × A0A1

D B 8 0 PC

RW0+2

× × A0A0

A 0 A 0 RW0


CHAPTER 9 DETAILED INSTRUCTIONS9.52 JMPP (Jump Destination Physical Address)

9.52 JMPP (Jump Destination Physical Address)

If the operand is addr24, this instruction causes a branch to the physical address specified by addr24. If the operand is @ea, the instruction causes a branch to the physical address specified by the contents of the operand.


(1) JMPP addr24

(2) JMPP @earJMPP @eam

● Operation:

(1): (PC) ← Low-order word of addr24

(PCB) ← Most significant byte of addr24

(2): (PC) ← (ea) (Word transfer)

(PCB) ← (ea+2) (Byte transfer)

● CCR:



● Example:

JMPP 0FFC850H

I S T N Z V C

– – – – – – –

Operand addr24 @ear @eam

Byte count 4 2 2+

Cycle count 2 3 5


1 2 4 8 PC

Before execution3 4PCB

C 8 5 0 PC

After executionF FPCB


CHAPTER 9 DETAILED INSTRUCTIONS9.53 LINK (Link and create new stack frame)

9.53 LINK (Link and create new stack frame)

Store the current value of the frame pointer (RW3) in a stack and set a new frame pointer. This allows an area for a new local variable to be reserved. This instruction is used before a function is called.


LINK #imm8

● Operation:

(sp) ← (sp)–2 ; ((sp)) ← (RW3) ; (RW3) ← (sp) ; (sp) ← (sp)–imm8

● CCR:



Byte count: 2

Cycle count: 2


● Example:

LINK #20H

I S T N Z V C

– – – – – – –

Before execution

Memory

× × E022

E 0 2 2SP

SP

A 0 4 6RW3

After execution

Memory

A 04 6 E020

E 0 0 0SP

SP × × E000

E 0 2 0RW3


CHAPTER 9 DETAILED INSTRUCTIONS9.54 LSL (Logical Shift Byte Data of Accumulator to Left)

9.54 LSL (Logical Shift Byte Data of Accumulator to Left)

Shift the least significant byte data of the accumulator (A) to the left by the number of bits specified by the second operand.

The least significant bit of A is set to "0". The bit last shifted out from the most significant bit

of the least significant byte data for A is stored in the carry bit (C).


LSL A,R0

● Operation:

● CCR:




V: Unchanged

C: Stores the bit last shifted out from the MSB of A. Cleared when the shift amount is "0".


Byte count: 2

Cycle count: 1

● Example:

LSL A,R0

I S T N Z V C

– – – * * – *

MSB LSBC A

0

CCR

Before execution

CCR

After execution

0 2R0 0 2R0

× × × × × × F F A × × × × × × F C A

× × × × ×T N Z V C

× 1 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.55 LSLL (Logical Shift Long Word Data of Accumulator to Left)

9.55 LSLL (Logical Shift Long Word Data of Accumulator to Left)

Shift the long word data of the accumulator (A) to the left by the number of bits specified by the second operand.


is stored in the carry bit (C).


LSLL A,R0

● Operation:

● CCR:




V: Unchanged



Byte count: 2

Cycle count: 1

● Example:

LSLL A,R0

I S T N Z V C

– – – * * – *

MSB LSBC A

0

3 3 3 3 3 3 3 3A

Before execution

C C C C C C C C A

After execution

0 2R0 0 2R0

CCR × × × × ×T N Z V C

CCR × 1 0 × 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.56 LSLW (Logical Shift Word Data of Accumulator to Left)

9.56 LSLW (Logical Shift Word Data of Accumulator to Left)

Shift the low-order word data of the accumulator (A) to the left by one bit. The least significant bit of A is set to "0".

The bit shifted out from the most significant bit of the low-order word data for A is stored in

the carry bit (C).


LSLW A/SHLW A

● Operation:

● CCR:




V: Unchanged

C: Stores the bit shifted out from the MSB of A.


Byte count: 1

Cycle count: 1

● Example:

LSLW A

I S T N Z V C

– – – * * – *

MSB LSBAC

0


× × × × A A 5 5 A × × × × 5 5 A A A

CCR × × × × ×T N Z V C

CCR × 0 0 × 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.57 LSLW (Logical Shift Word Data of Accumulator to Left)

9.57 LSLW (Logical Shift Word Data of Accumulator to Left)

Shift the low-order word data of the accumulator (A) to the left by the number of bits specified by the second operand.


of the low-order word data for A is stored in the carry bit (C).


LSLW A,R0

● Operation:

● CCR:




V: Unchanged



Byte count: 2

Cycle count: 1

● Example:

LSLW A,R0

I S T N Z V C

– – – * * – *

MSB LSBAC

0

× × × × A A 5 5 A

Before execution

× × × × A 5 5 0 A

After execution

0 4R0 0 4R0

CCR × × × × ×T N Z V C

CCR × 1 0 × 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.58 LSR (Logical Shift Byte Data of Accumulator to Right)

9.58 LSR (Logical Shift Byte Data of Accumulator to Right)

Shift the least significant byte data of the accumulator (A) to the right by the number of bits specified by the second operand.

The most significant bit of the least significant byte for A is set to "0". The bit last shifted out



LSR A,R0

● Operation:

● CCR:

I and S: Unchanged





V: Unchanged



Byte count: 2

Cycle count: 1

I S T N Z V C

– – * * * – *

MSB LSB CA

0

T1


CHAPTER 9 DETAILED INSTRUCTIONS9.58 LSR (Logical Shift Byte Data of Accumulator to Right)

● Example:

LSR A,R0

× × × × × × F F A

Before execution

× × × × × × 0 7 A

After execution

0 5 R0 0 5 R0

CCR × × × × ×T N Z V C

CCR 1 1 0 × 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.59 LSRL (Logical Shift Long Word Data of Accumulator to

Right)

9.59 LSRL (Logical Shift Long Word Data of Accumulator to Right)

Shift the long word data of the accumulator (A) to the right by the number of bits specified by the second operand.

The most significant bit of A is set to "0". The bit last shifted out from the least significant bit

of A is stored in the carry bit (C).


LSRL A,R0

● Operation:

● CCR:

I and S: Unchanged





V: Unchanged



Byte count: 2

Cycle count: 1

I S T N Z V C

– – * * * – *

MSB LSB CA

0

T1


CHAPTER 9 DETAILED INSTRUCTIONS9.59 LSRL (Logical Shift Long Word Data of Accumulator to Right)

● Example:

LSRL A,R0

3 3 3 3 3 3 3 3 A

Before execution

0 0 0 0 3 3 3 3 A

After execution

1 0R0 1 0R0

CCR × × × × ×T N Z V C

CCR 1 0 0 × 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.60 LSRW (Logical Shift Word Data of Accumulator to Right)

9.60 LSRW (Logical Shift Word Data of Accumulator to Right)

Shift the low-order word data of the accumulator (A) to the right by one bit.

The most significant bit of the low-order word data for A is set to "0". The least significant bit

is stored in the carry bit (C).


LSRW A/SHRW A

● Operation:

● CCR:

I and S: Unchanged

T: Stores the OR of the shifted-out data from the carry and the old T flag value.

N: Cleared


V: Unchanged



Byte count: 1

Cycle count: 1

● Example:

LSRW A

I S T N Z V C

– – * R * – *

MSB LSBA C

0

T1

× × × × A A A A A

Before execution

× × × × 5 5 5 5 A

After execution

CCR 1 × × × 0

T N Z V C

CCR 1 0 0 × 0

T N Z V C



9.61 LSRW (Logical Shift Word Data of Accumulator to Right)

Shift the low-order word data of the accumulator (A) to the right by the number of bits specified by the second operand.

The most significant bit of the low-order word data for A is set to "0". The bit last shifted out



LSRW A,R0

● Operation:

● CCR:

I and S: Unchanged





V: Unchanged



Byte count: 2

Cycle count: 1

I S T N Z V C

– – * * * – *

MSB LSBA C

0

T1



● Example:

LSRW A,R0

× × × × A A A A A

Before execution

× × × × 0 0 0 A A

After execution

0 CR0 0 CR0

CCR × × × × ×T N Z V C

CCR 1 0 0 × 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.62 MOV (Move Byte Data from Source to Accumulator)

9.62 MOV (Move Byte Data from Source to Accumulator)

Transfer the values of bits 0 to 15 for the accumulator (A) to bits 16 to 31, then transfer "0" to bits 8 to 15. The byte data specified by the second operand is transferred to bits 0 to 7. If the second operand is @A, transfer to bits 16 to 31 is not performed.


MOV A,#imm8 MOV A,Ri

MOV A,@A MOV A,dir

MOV A,@RLi + disp8 MOV A,addr16

MOV A,io MOV A,brg1

MOV A,eam MOV A,ear

● Operation:

(A) ← (Second operand) (Byte transfer)

● CCR:




V and C: Unchanged


I S T N Z V C

– – – * * – –

Second operand #imm8 @A @RLi+disp8 io addr16 Ri dir ear eam brg1

Byte count 2 2 3 2 3 1 2 2 2+ 2

Cycle count 1 1 1 1 1 1 1 1 1 1


CHAPTER 9 DETAILED INSTRUCTIONS9.62 MOV (Move Byte Data from Source to Accumulator)

● Example:

MOV A,0092H

× × × × A 0 4 6 A

Before execution

A 0 4 6 0 0 7 1 A

After execution

Memory

7 1 0092

Memory

7 1 0092

CCR × × × × ×T N Z V C

CCR × 0 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.63 MOV (Move Byte Data from Accumulator to Destination)

9.63 MOV (Move Byte Data from Accumulator to Destination)

Transfer the least significant byte data of the accumulator (A) to the address specified by the first operand.


MOV dir,A MOV Ri,A

MOV @RLi+disp8,A MOV io,A

MOV addr16,A MOV brg2,A

MOV ear,A MOV eam,A

● Operation:

(First operand) ← (A) (Byte transfer)

● CCR:




V and C: Unchanged


● Example:

MOV R1,A

I S T N Z V C

– – – * * – –

First operand dir @RLi+disp8 addr16 io Ri ear eam brg2

Byte count 2 3 3 2 1 2 2+ 2

Cycle count 1 1 1 1 1 1 1 1

× × × × 4 9 3 2 A

Before execution

× × × × 4 9 3 2A

After execution

× ×R1 3 2R1CCR × × × × ×T N Z V C

CCR × 0 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.64 MOV (Move Byte Immediate Data to Destination)

9.64 MOV (Move Byte Immediate Data to Destination)

Transfer the 8-bit immediate data specified by the second operand to the address specified by the first operand.

When the first operand is @PC + disp16, the data is transferred to the "address of the location

containing the machine instruction for the MOV instruction + 4 + rel", not the "address of the

location containing the machine instruction for the instruction following the MOV instruction +

rel".


MOV RP,#imm8 MOV ILM,#imm8

MOV io,#imm8 MOV dir,#imm8

MOV ear,#imm8 MOV eam,#imm8

● Operation:

(First operand) ← #imm8

● CCR:


N: Unchanged if the data is transferred to a register other than the general-purpose

registers. If the data is transferred to the general-purpose register, N is set when

the MSB of the transferred data is "1", cleared otherwise.

Z: Unchanged if the data is transferred to a register other than the general-purpose

registers. If the data is transferred to the general-purpose register, Z is set when the

transferred data is "0", cleared otherwise.

V and C: Unchanged

If the data is transferred to a general-

purpose registers (R0 to R7) or bank

register

If the data is transferred to a register other

than the general-purpose registers (R0 to

R7) and the bank register

I S T N Z V C I S T N Z V C

– – – * * – – – – – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.64 MOV (Move Byte Immediate Data to Destination)


● Example:

MOV 009FH,#22H

First operand RP ILM dir io ear eam

Second operand #imm8 #imm8 #imm8 #imm8 #imm8 #imm8

Byte count 2 2 3 3 3 3+

Cycle count19 when the content of RP

changes; 4 in all other cases1 1 1 1 1

× × × × × × × × A

Before execution

× × × × × × × × A

After execution

Memory Memory

7 1 009F 2 2 009F

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.65 MOV (Move Byte Data from Source to Destination)

9.65 MOV (Move Byte Data from Source to Destination)

Transfer the byte data specified by the second operand to the first operand.

MOV Ri, #imm8, described below, is an instruction contained in the basic page map (see C.1

Table C.2-1 ), with code different from that contained in MOV ear, #imm8.


MOV Ri,#imm8

MOV Ri,ear MOV Ri,eam

MOV ear,Ri MOV eam,Ri

● Operation:

(First operand) ← (Second operand) (Byte transfer)

● CCR:




V and C: Unchanged


I S T N Z V C

– – – * * – –

First operand Ri Ri Ri ear eam

Second operand #imm8 ear eam Ri Ri




CHAPTER 9 DETAILED INSTRUCTIONS9.65 MOV (Move Byte Data from Source to Destination)

● Example:

MOV R3,@RW0


Memory

7 1 E001

E 0 0 1RW0

× ×R3

E 0 0 1RW0

7 1R3

Memory

7 1 E001

CCR × × × × ×T N Z V C

CCR × × 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.66 MOV (Move Byte Data from AH to Memory)

9.66 MOV (Move Byte Data from AH to Memory)

Transfer the low-order byte data of AH to the memory location specified by the contents of AL.


MOV @AL,AH

● Operation:

((AL)) ← (AH) (Byte transfer)

● CCR:




V and C: Unchanged


Byte count: 2

Cycle count: 1

● Example:

MOV @AL,AH

I S T N Z V C

– – – * * – –

0 1 2 2 E 0 8 4 A

Before execution

0 1 2 2 E 0 8 4 A

After execution

Memory Memory

7 1 E084 2 2 E084

CCR × × × × ×T N Z V C

CCR × 0 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.67 MOVB (Move Bit Data from Bit Address to Accumulator)

9.67 MOVB (Move Bit Data from Bit Address to Accumulator)

Transfer zeros to bits 8 to 15 of the accumulator (A). "00H" is transferred to bits

0 to 7 of A if the bit of the address specified by the second operand is equal to "0" and "FFH" is transferred if the bit is equal to "1".


MOVB A,addr16:bp

MOVB A,dir:bp

MOVB A,io:bp

● Operation:

If (Second operand)=0 : (A) ← 00H (Byte transfer)

If (Second operand)=1 : (A) ← FFH (Byte transfer)

● CCR:


N: Set when the transferred bit is "1", cleared when "0".

Z: Set when the transferred bit is "0", cleared when "1".

V and C: Unchanged


I S T N Z V C

– – – * * – –

Second operand addr16:bp dir:bp io:bp

Byte count 4 3 3

Cycle count 1 1 1


CHAPTER 9 DETAILED INSTRUCTIONS9.67 MOVB (Move Bit Data from Bit Address to Accumulator)

● Example:

MOVB A,32H:3

× × × × × × × × A

Before execution

× × × × 0 0 F F A

After execution

Memory

× ×

Memory

7 F 0032× ×

× ×7 F 0032× ×

CCR × × × × ×T N Z V C

CCR × 1 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.68 MOVB (Move Bit Data from Accumulator to Bit Address)

9.68 MOVB (Move Bit Data from Accumulator to Bit Address)

Transfer bit data 0 to the bit address specified by the first operand if the least significant byte data of the accumulator (A) is 00H.

Bit data 1 is transferred to the bit address specified by the first operand if the least significant byte data of A is not 00H.


MOVB addr16:bp,A

MOVB dir:bp,A

MOVB io:bp,A

● Operation:

If the byte data of (A) is 00H : (First operand) b=0 (Bit transfer)

If the byte data of (A) is not 00H : (First operand) b=1 (Bit transfer)

● CCR:


N: Set when the MSB of the byte data for A is "1", cleared otherwise.

Z: Set when the byte data of A is "0", cleared otherwise.

V and C: Unchanged


I S T N Z V C

– – – * * – –

First operand addr16:bp dir:bp io:bp

Byte count 4 3 3

Cycle count 3 3 3


CHAPTER 9 DETAILED INSTRUCTIONS9.68 MOVB (Move Bit Data from Accumulator to Bit Address)

● Example:

MOVB 765FH: 7,A

× × × × × × 0 1 A

Before execution

× × × × × × 0 1 A

After execution

Memory

× ×7 F 765F× ×

Memory

× ×F F 765F× ×

CCR × × × × ×T N Z V C

CCR × 0 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.69 MOVEA (Move Effective Address to Destination)

9.69 MOVEA (Move Effective Address to Destination)

Transfer the value specified by the second operand (effective address) to the first operand.

If a general-purpose register is specified by the second operand, the address of the general-

purpose register is transferred.

If the destination (first operand) is the accumulator (A), the pre-transfer values of bits 0 to 15

are transferred to bits 16 to 31 of A.


MOVEA <destination>,ear MOVEA <destination>,eam

● Operation:

First operand ← ea (Word transfer)

● CCR:



● Example:

MOVEA RW2,@RW0+2

I S T N Z V C

– – – – – – –

First operand A A RWi RWi

Second operand ear eam ear eam

Byte count 2 2+ 2 2+

Cycle count 1 1 1 1

Before execution

× × × ×RW2

After execution

0 0 6 BRW2

0 0 6 9RW0 0 0 6 9RW0

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.70 MOVL (Move Long Word Data from Source to Accumulator)

9.70 MOVL (Move Long Word Data from Source to Accumulator)

Transfer the long word data specified by the second operand to the accumulator (A).


MOVL A,#imm32

MOVL A,ear MOVL A,eam

● Operation:

(A) ← (Second operand) (Long word transfer)

● CCR:




V and C: Unchanged


● Example:

MOVL A,#0053FF64H

I S T N Z V C

– – – * * – –


Byte count 5 2 2+

Cycle count 2 2 2


× × × × × × × ×A

Before execution

0 0 5 3 F F 6 4A

After execution

CCR × × × × ×T N Z V C

CCR × 0 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.71 MOVL (Move Long Word Data from Accumulator to Destination)

9.71 MOVL (Move Long Word Data from Accumulator to Destination)

Transfer the long word data of the accumulator (A) to the first operand.


MOVL ear,A MOVL eam,A

● Operation:

(First operand) ← (A) (Long word transfer)

● CCR:




V and C: Unchanged


● Example:

MOVL RL1,A

I S T N Z V C

– – – * * – –


Byte count 2 2+

Cycle count 2 2



0 1 9 7 A 0 2 4A 0 1 9 7 A 0 2 4A

× × × × × × × ×RL1 0 1 9 7 A 0 2 4RL1

CCR × × × × ×T N Z V C

CCR × 0 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.72 MOVN (Move Immediate Nibble Data to Accumulator)

9.72 MOVN (Move Immediate Nibble Data to Accumulator)

Transfer the values of bits 0 to 15 for the accumulator (A) to bits 16 to 31. "0" is transferred to bits 4 to 15 and the nibble data specified by the second operand is transferred to bits 0 to 3.


MOVN A,#imm4

● Operation:

(A) ← imm4 (Byte transfer)

● CCR:


N: Cleared


V and C: Unchanged


Byte count: 1

Cycle count: 1

● Example:

MOVN A,#0FH

I S T N Z V C

– – – R * – –

× × × × 6 2 0 7 A

Before execution

6 2 0 7 0 0 0 F A

After execution

CCR × × × × ×T N Z V C

CCR × 0 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.73 MOVS, MOVSI (Move String Byte with Increment)

9.73 MOVS, MOVSI (Move String Byte with Increment)

Transfer byte data from the address specified by AL in the space specified by <source bank> to the address specified by AH in the space specified by <destination bank>. The transfer is repeated the number of times specified by RW0, with the addresses being incremented each time.

The transfer is not performed if RW0 is equal to "0". Four types of registers PCB, DTB, ADB,

and SPB can be used as <destination bank> and <source bank>. By default, DTB is assumed.

If an interrupt occurs during the transfer, the transfer is suspended to handle the interrupt. The

transfer is resumed after the interrupt has been handled.


MOVS [<destination bank>] [,<source bank>]

MOVSI [<destination bank>] [,<source bank>]

● Operation:

The following is repeated until RW0 becomes equal to "0":

((AH)) ← ((AL)) (Byte transfer)

(AH) ← (AH)+1, (AL) ← (AL)+1

(RW0) ← (RW0)–1

● CCR:



Byte count: 2

Cycle count: 1 when (RW0) is "0"; (RW0) when (RW0) is "1" or greater and

the transfer-source-address area and the transfer-destination-

address area do not overlap; and 2 × (RW0) in all other cases


I S T N Z V C

– – – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.73 MOVS, MOVSI (Move String Byte with Increment)

● Example:

MOVSI ADB,PCB

0 0 0 3RW0

Before execution

Memory

F C FF0003F D FF0002F E FF0001

F FPCB

× × 018002× × 018001

AH

8 0 0 0 0 0 0 0 AH AL

× × 018000

0 1ADB

F F FF0000AL

× × 018003

0 0 0 0RW0

After execution

Memory

F C FF0003F D FF0002F E FF0001

F FPCB

F D 018002F E 018001

AH

AH AL

F F 018000

0 1ADB

F F FF0000

AL

× × 018003

8 0 0 3 0 0 0 3

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.74 MOVSD (Move String Byte with Decrement)

9.74 MOVSD (Move String Byte with Decrement)

Transfer byte data from the address specified by AL in the space specified by <source bank> to the address specified by AH in the space specified by <destination bank>. The transfer is repeated the number of times specified by RW0, with the addresses being decremented each time.






MOVSD [<destination bank>] [,<source bank>]

● Operation:



(AH) ← (AH)-1, (AL) ← (AL)-1

(RW0) ← (RW0)–1

● CCR:



Byte count: 2

Cycle count: 1 when (RW0) is "0"; 2 × (RW0) in all other cases

I S T N Z V C

– – – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.75 MOVSW, MOVSWI (Move String Word with Increment)

9.75 MOVSW, MOVSWI (Move String Word with Increment)

Transfer word data from the address specified by AL in the space specified by <source bank> to the address specified by AH in the space specified by <destination bank>. The transfer is repeated the number of times specified by RW0, with the addresses being incremented each time.






MOVSW [<destination bank>] [,<source bank>]

MOVSWI [<destination bank>] [,<source bank>]

● Operation:



(AH) ← (AH)+2, (AL) ← (AL)+2

(RW0) ← (RW0)–1

● CCR:



Byte count: 2


I S T N Z V C

– – – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.75 MOVSW, MOVSWI (Move String Word with Increment)

● Example:

MOVSW,ADB

0 0 0 3RW0

Before execution

Memory

× × CD0005× × CD0004× × CD0003

C DDTB

3 1 38A0024 D 38A001

AL

AH AL

4 6 38A000

3 8ADB

× × CD0002

AH

3 6 38A003

0 0 0 0RW0

After execution

Memory

2 6 CD00054 2 CD00043 6 CD0003

C DDTB

3 1 38A0024 D 38A001

AL

AH AL

4 6 38A000

3 8ADB

3 1 CD0002

AH

3 6 38A0034 2 38A0042 6 38A005

4 2 38A0042 6 38A005

× × CD0001× × CD0000

4 D CD00014 6 CD0000

0 0 0 0 A 0 0 0 0 0 0 6 A 0 0 6

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.76 MOVSWI (Move String Word with Decrement)

9.76 MOVSWI (Move String Word with Decrement)

Transfer word data from the address specified by AL in the space specified by <source bank> to the address specified by AH in the space specified by <destination bank>. The transfer is repeated the number of times specified by RW0, with the addresses being decremented each time.






MOVSWI [<destination bank>] [,<source bank>]

● Operation:



(AH) ← (AH)–2, (AL) ← (AL)–2

(RW0) ← (RW0)–1

● CCR:



Byte count: 2


Odd address correction: (RW0) when the transfer destination is an odd address; (RW0)

when the transfer source is an odd address; and 2 × (RW0)

when both the transfer destination and the transfer source are

odd addresses

I S T N Z V C

– – – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.77 MOVW (Move Word Data from Source to Accumulator)

9.77 MOVW (Move Word Data from Source to Accumulator)

Transfer the values of bits 0 to 15 for the accumulator (A) to bits 16 to 31. Then, the word data specified by the second operand is transferred to bit0 to bit15 of A.

If the second operand is @A, transfer the values of bits 0 to 15 of A to bits 16 to 31 is not

performed.


MOVW A,#imm16 MOVW A,@RWi+disp8

MOVW A,@A MOVW A,addr16

MOVW A,@RLi+disp8 MOVW A,RWi

MOVW A,SP MOVW A,dir

MOVW A,io

MOVW A,ear MOVW A,eam

● Operation:

(A) ← (Second operand)(Word transfer)

● CCR:




V and C: Unchanged


I S T N Z V C

– – – * * – –

Second operand #imm16 @A @RLi+disp8 SP io @RWi+disp8 addr16 RWi dir ear eam

Byte count 3 2 3 1 2 2 3 1 2 2 2+

Cycle count 1 1 1 1 1 1 1 1 1 1 1

Odd address correction 0 1 1 0 1 1 1 0 1 0 1


CHAPTER 9 DETAILED INSTRUCTIONS9.77 MOVW (Move Word Data from Source to Accumulator)

● Example:

MOVW A,0F9A0H

× × × × 4 9 0 1 A

Before execution

4 9 0 1 A E 8 6 A

After execution

Memory Memory

A E F9A1 A E F9A18 6 F9A0 8 6 F9A0

CCR × × × × ×T N Z V C

CCR × 1 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.78 MOVW (Move Word Data from Accumulator to Destination)

9.78 MOVW (Move Word Data from Accumulator to Destination)

Transfer the low-order word data of the accumulator (A) to the first operand.


MOVW @RLi+disp8,A MOVW addr16,A

MOVW SP,A MOVW RWi,A

MOVW io,A MOVW dir,A

MOVW @RWi+disp8,A

MOVW ear,A MOVW eam,A

● Operation:

(First operand) ← (A) (Word transfer)

● CCR:




V and C: Unchanged


I S T N Z V C

– – – * * – –

First operand dir @RLi+disp8 addr16 SP io @RWi+disp8 RWi ear eam

Byte count 2 3 3 1 2 2 1 2 2+

Cycle count 1 1 1 1 1 1 1 1 1

Odd address correction 1 1 1 0 1 1 0 0 1


CHAPTER 9 DETAILED INSTRUCTIONS9.78 MOVW (Move Word Data from Accumulator to Destination)

● Example:

MOVW RW0,A

× × × × 0 0 0 0A

Before execution

× × × ×RW0

× × × × 0 0 0 0A

After execution

0 0 0 0RW0

CCR × × × × ×T N Z V C

CCR × 0 1 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.79 MOVW (Move Immediate Word Data to Destination)

9.79 MOVW (Move Immediate Word Data to Destination)

This instruction transfers the 16-bit immediate data to the first operand.

When the first operand is @PC + disp16, the transfer destination address is the address where

the machine instruction of the MOVW instruction is stored + 4 + disp16. Note that this is not

the address where the machine instruction of the instruction subsequent to the MOVW

instruction is stored+disp16.


MOVW ear,#imm16 MOVW eam,#imm16

● Operation:

(First operand) ← #imm16

● CCR:


N: Unchanged if the data is transferred to a register other than the general-purpose

registers. If the data is transferred to the general-purpose register, N is set when

the MSB of the transferred data is "1", cleared otherwise.

Z: Unchanged if the data is transferred to a register other than the general-purpose

registers. If the data is transferred to the general-purpose register, Z is set when the

transferred data is "0", cleared otherwise.

V and C: Unchanged and none of the flags is changed.


If the data is transferred to a general-

purpose register (RW0 to RW7)

If the data is transferred to a register other

than the general-purpose registers (RW0 to

RW7)


– – – * * – – – – – – – – –


Byte count 4 4+

Cycle count 2 2



CHAPTER 9 DETAILED INSTRUCTIONS9.79 MOVW (Move Immediate Word Data to Destination)

● Example:

MOVW RW0,#2343H

Before execution

× × × ×RW0

After execution

2 3 4 3RW0

CCR × × × × ×T N Z V C

CCR × 0 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.80 MOVW (Move Word Data from Source to Destination)

9.80 MOVW (Move Word Data from Source to Destination)

Transfer the word data specified by the second operand to the first operand.


MOVW RWi,#imm16

MOVW ear,RWi MOVW eam,RWi

MOVW RWi,ear MOVW RWi,eam

● Operation:

(First operand) ← (Second operand)(Word transfer)

● CCR:




V and C: Unchanged


I S T N Z V C

– – – * * – –

First operand RWi RWi RWi ear eam

Second operand #imm16 ear eam RWi RWi





CHAPTER 9 DETAILED INSTRUCTIONS9.80 MOVW (Move Word Data from Source to Destination)

● Example:

MOVW RW1,RW0

Before execution

0 0 4 ARW0

After execution

0 0 4 ARW0

× × × × RW1 0 0 4 A RW1

× × × × × × × × A × × × × × × × × A

CCR × × × × ×T N Z V C

CCR × 0 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.81 MOVW (Move Immediate Word Data to io)

9.81 MOVW (Move Immediate Word Data to io)

Transfer 16-bit immediate data to the I/O area specified by the first operand.


MOVW io,#imm16

● Operation:

(First operand) ← imm16 (Word transfer)

● CCR:



Byte count: 4

Cycle count: 1


● Example:

MOVW 24H,#2343H

I S T N Z V C

– – – – – – –


Memory

× ×

Memory

× ×× × 000025 2 3 000025× × 000024 4 3 000024× × × ×

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.82 MOVW (Move Word Data from AH to Memory)

9.82 MOVW (Move Word Data from AH to Memory)

Transfer the word data of AH to the memory location specified by the contents of AL.


MOVW @AL,AH

● Operation:

((AL)) ← (AH) (Word transfer)

● CCR:




V and C: Unchanged


Byte count: 2

Cycle count: 1


● Example:

MOVW @AL,AH

I S T N Z V C

– – – * * – –

0 0 C B F E F F A

Before execution

0 0 C B F E F F A

After execution

Memory Memory

7 1 FEFF C B FEFF

CCR × × × × ×T N Z V C

CCR × 1 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.83 MOVX (Move Byte Data with Sign Extension from Source to Accumulator)

9.83 MOVX (Move Byte Data with Sign Extension from Source to Accumulator)

Transfer the values of bits 0 to 15 for the accumulator (A) to bits 16 to 31. Then, the value resulting from sign-extending the second operand is transferred to bits 0 to 15 of A. If the second operand is @A, transfer to bits 16 to 31 is not performed.


MOVX A,#imm8 MOVX A,@RWi+disp8

MOVX A,@A MOVX A,addr16

MOVX A,@RLi+disp8 MOVX A,Ri

MOVX A,dir MOVX A,io

MOVX A,ear MOVX A,eam

● Operation:

(A) ← (Second operand) (Byte transfer with sign extension)

● CCR:




V and C: Unchanged


I S T N Z V C

– – – * * – –

Second operand #imm8 @A @RLi+disp8 dir io @RWi+disp8 addr16 Ri ear eam

Byte count 2 2 3 2 2 2 3 2 2 2+

Cycle count 1 1 1 1 1 1 1 1 1 1


CHAPTER 9 DETAILED INSTRUCTIONS9.83 MOVX (Move Byte Data with Sign Extension from Source

to Accumulator)● Example:

MOVX A,0E001H

× × × × A 0 4 6 A

Before execution

A 0 4 6 F F 8 6 A

After execution

Memory Memory

8 6 E001 8 6 E001

CCR × × × × ×T N Z V C

CCR × 1 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.84 MUL (Multiply Byte Data of Accumulator)

9.84 MUL (Multiply Byte Data of Accumulator)

This instruction multiplies the low-order byte data of AH by that of AL as signed binary numbers, then returns the result to AL of the accumulator (A).


MUL A

● Operation:

word (A) ← byte (AH)×byte (AL) (Byte multiplication)

● CCR:



Byte count: 2

Cycle count: 4

● Example:

MUL A

I S T N Z V C

– – – – – – –


AH AL AH AL

0 0 F A 0 0 1 1 A 0 0 F A F F 9 A A

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.85 MUL (Multiply Byte Data of Accumulator and Effective

Address)

9.85 MUL (Multiply Byte Data of Accumulator and Effective Address)

Multiply the byte data of the accumulator (A) by the byte data specified by the second operand as signed binary numbers and restore the result in bits 0 to 15 of A.


MUL A,ear MUL A,eam

● Operation:

word (A) ← byte (A) × byte (ea) (Byte multiplication)

● CCR:



● Example:

MUL A,R7

I S T N Z V C

– – – – – – –


Byte count 2 2+

Cycle count 4 5

× × × × 0 0 8 5A

Before execution

× × × × 2 B B 9 A

After execution

A 5R7 A 5R7

AH AL AH AL

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.86 MULW (Multiply Word Data of Accumulator)

9.86 MULW (Multiply Word Data of Accumulator)

Multiply the word data of AH by the word data specified by AL as signed binary numbers and restore the result in the accumulator as long word data.


MULW A

● Operation:

Long (A) ← word (AH)×word (AL) (Word multiplication)

● CCR:



Byte count: 2

Cycle count: 6

● Example:

MULW A

I S T N Z V C

– – – – – – –

A D 0 1 0 5 E D A


AH AL AH AL

F E 1 4 2 E E D A

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.87 MULW (Multiply Word Data of Accumulator and Effective

Address)

9.87 MULW (Multiply Word Data of Accumulator and Effective Address)

Multiply the word data of the accumulator (A) by the word data specified by the second operand as signed binary numbers and restore the result in A as long word data.


MULW A,ear MULW A,eam

● Operation:

Long (A) ← word (A)×word (Second operand) (Word multiplication)

● CCR:



● Example:

MULW A,RW5

I S T N Z V C

– – – – – – –


Byte count 2 2+

Cycle count 6 7



AH AL AH AL

4 3 1 4 RW5 4 3 1 4RW5

× × × × 8 3 4 2 A D F 5 0 8 7 2 8 A

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.88 MULU (Multiply Unsigned Byte Data of Accumulator)

9.88 MULU (Multiply Unsigned Byte Data of Accumulator)

Multiply the low-order byte data of AH by the low-order byte data of AL as unsigned binary numbers and restore the result in the AL of the accumulator (A).


MULU A

● Operation:

word (A) ← byte (AH)×byte (AL) (Byte multiplication)

● CCR:



Byte count: 1

Cycle count: 2

● Example:

MULU A

I S T N Z V C

– – – – – – –


0 0 F A 0 0 1 1 A 0 0 F A 1 0 9 A A

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.89 MULU (Multiply Unsigned Byte Data of Accumulator and

Effective Address)

9.89 MULU (Multiply Unsigned Byte Data of Accumulator and Effective Address)

Multiply the byte data of the accumulator (A) by the byte data specified by the second operand as unsigned binary numbers and restore the result in bits 0 to 15 of A.


MULU A, ear MULU A, eam

● Operation:

word (A) ← byte (A) × byte (Second operand) (Byte multiplication)

● CCR:



● Example:

MULU A, R7

I S T N Z V C

– – – – – – –


Byte count 2 2 +

Cycle count 2 3


R7 R7A 5 A 5

× × × × 0 0 8 5 A × × × × 5 5 B 9 A

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.90 MULUW (Multiply Unsigned Word Data of Accumulator)

9.90 MULUW (Multiply Unsigned Word Data of Accumulator)

Multiply the word data of AH by the word data of AL as unsigned binary numbers and restore the result in the accumulator (A) as long word data.


MULUW A

● Operation:

Long (A) ← word (AH)×word (AL) (Word multiplication)

● CCR:



Byte count: 1

Cycle count: 4

● Example:

MULUW A

I S T N Z V C

– – – – – – –


A D 0 1 0 5 E D A 0 4 0 1 2 E E D A

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.91 MULUW (Multiply Unsigned Word Data of Accumulator and

Effective Address)

9.91 MULUW (Multiply Unsigned Word Data of Accumulator and Effective Address)

Multiply the word data of the accumulator (A) by the word data specified by the second operand as unsigned binary numbers and restore the result in A as long word data.


MULUW A, ear MULUW A, eam

● Operation:

Long (A) ← word (A)×word (Second operand) (Word multiplication)

● CCR:



● Example:

MULUW A, RW5

I S T N Z V C

– – – – – – –


Byte count 2 2+

Cycle count 4 5


4 3 1 4RW5

Before execution

× × × × 8 3 4 2 A

4 3 1 4RW5

After execution

A 2 2 6 4 8 7 2 8

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.92 NEG (Negate Byte Data of Destination)

9.92 NEG (Negate Byte Data of Destination)

Take the 2's complement of the byte data specified by the operand and restore the result in the operand. If the operand is the accumulator (A), the value resulting from sign-extending the operation result is transferred to bits 8 to 15 of A.


NEG A

NEG ear NEG eam

● Operation:

(Operand) ← 0–(Operand) (Byte operation)

● CCR:







● Example:

NEG R0

I S T N Z V C

– – – * * * *

Operand A ear eam

Byte count 1 2 2+

Cycle count 1 1 3


5 9R0 A 7R0

CCR × × × × ×T N Z V C

CCR × 1 0 0 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.93 NEGW (Negate Word Data of Destination)

9.93 NEGW (Negate Word Data of Destination)

Take the 2's complement of the word data specified by the operand and restore the result in the operand.


NEGW A

NEGW ear NEGW eam

● Operation:

(Operand) ← 0–(Operand) (Word operation)

● CCR:







● Example:

NEGW A

I S T N Z V C

– – – * * * *

Operand A ear eam

Byte count 1 2 2+

Cycle count 1 1 3


× × × × A B 9 8 A

Before execution

× × × × 5 4 6 8 A

After execution

CCR × × × × ×T N Z V C

CCR × 0 0 0 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.94 NOP (No Operation)

9.94 NOP (No Operation)

Perform no operation.


NOP

● Operation:

No operation is performed.

● CCR:



Byte count: 1

Cycle count: 1

● Example:

NOP

I S T N Z V C

– – – – – – –

× × × × × × × × A

F 0 0 0 PC

× × × × × × × × A

F 0 0 1 PC


Memory Memory

× × F001 × × F0010 0 F000 0 0 F000PC

PC

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.95 NOT (Not Byte Data of Destination)

9.95 NOT (Not Byte Data of Destination)

Take the logical NOT of the byte data specified by the operand and restore the result in the operand.


NOT A

NOT ear NOT eam

● Operation:

(Operand) ← not (Operand) (Byte logical NOT)

● CCR:




V: Cleared

C: Unchanged


I S T N Z V C

– – – * * R –

Operand A ear eam

Byte count 1 2 2+

Cycle count 1 1 3


CHAPTER 9 DETAILED INSTRUCTIONS9.95 NOT (Not Byte Data of Destination)

● Example:

NOT 0071H

× × × × × × × × A

Before execution

× × × × × × × × A

After execution

Memory Memory

F F 0071 0 0 0071

CCR × × × × ×T N Z V C

CCR × 0 1 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.96 NOTW (Not Word Data of Destination)

9.96 NOTW (Not Word Data of Destination)

Take the logical NOT of the word data specified by the operand and restore the result in the operand.


NOTW A

NOTW ear NOTW eam

● Operation:

(Operand) ← not (Operand) (Word logical NOT)

● CCR:




V: Cleared

C: Unchanged


● Example:

NOTW RW3

I S T N Z V C

– – – * * R –

Operand A ear eam

Byte count 1 2 2+

Cycle count 1 1 3


Before execution

2 5 8 B RW3

After execution

D A 7 4 RW3

CCR × × × × ×T N Z V C

CCR × 1 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.97 NRML (NORMALIZE Long Word)

9.97 NRML (NORMALIZE Long Word)

Shift the long word data of the accumulator (A) to the left until the most significant bit of A becomes "1", if the long word data is not "0".

R0 is set to the number of shifts required and the zero flag (Z) is cleared.

If the long word data of the accumulator (A) is "0", R0 is set to "0" and the zero flag (Z) is set.


NRML A,R0

● Operation:

If A≠0: The long word data is shifted to the left until the most significant bit of A becomes 1.

(R0) ← Number of shifts required, Z ← 0

If A=0: (R0) ← 0, Z ← 1

● CCR:


Z: Set when A is equal to "0", cleared otherwise.

V and C: Unchanged


Byte count: 2

Cycle count: 1

● Example:

NRML A,R0

I S T N Z V C

– – – – * – –

0 0 0 0 8 3 6 1 A

Before execution

8 3 6 1 0 0 0 0A

After execution

3 4R0 1 0R0

CCR × × × × ×T N Z V C

CCR × × 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.98 OR (Or Byte Data of Destination and Source to Destination)

9.98 OR (Or Byte Data of Destination and Source to Destination)

Take the logical OR of the byte data specified by the first operand and the byte data specified by the second operand and restore the result in the first operand.


OR A,#imm8

OR A,ear OR A,eam

OR ear,A OR eam,A

● Operation:

(First operand) ← (First operand) or (Second operand) (Byte logical OR)

● CCR:




V: Cleared

C: Unchanged


I S T N Z V C

– – – * * R –






CHAPTER 9 DETAILED INSTRUCTIONS9.98 OR (Or Byte Data of Destination and Source to Destination)

● Example:

OR 0052H,A

× × × × 0 0 3 7 A

Before execution

× × × × 0 0 3 7 A

After execution

Memory Memory

F A 0052 F F 0052

CCR × × × × ×T N Z V C

CCR × 1 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.99 OR (Or Byte Data of Immediate Data and Condition Code

Register to Condition Code Register)

9.99 OR (Or Byte Data of Immediate Data and Condition Code Register to Condition Code Register)

Take the logical OR of the byte data in the condition code register (CCR) and specified 8-bit immediate data and restore the result in the condition code register (CCR).

Bit 7 of the immediate data is ignored because the condition code register (CCR) is 7 bits long.


OR CCR,#imm8

● Operation:

(CCR) ← (CCR) or #imm8 (Byte logical OR)

● CCR:

I: Stores bit 6 of the operation result.

S: Stores bit 5 of the operation result.

T: Stores bit 4 of the operation result.

N: Stores bit 3 of the operation result.

Z: Stores bit 2 of the operation result.

V: Stores bit 1 of the operation result.

C: Stores bit 0 of the operation result.


Byte count: 2

Cycle count: 1

I S T N Z V C

* * * * * * *


CHAPTER 9 DETAILED INSTRUCTIONS9.99 OR (Or Byte Data of Immediate Data and Condition Code Register to Condition Code Register)

● Example:

OR CCR,#57H

Before execution

0CCR 1 1 0 1 0 1I S T N Z V C

ILM × × ×ILM2 ILM1 ILM0

RP × × × × ×MSB LSB

After execution

1CCR 1 1 0 1 1 1I S T N Z V C



× × × × × × × ×A × × × × × × × ×A


CHAPTER 9 DETAILED INSTRUCTIONS9.100 ORL (Or Long Word Data of Destination and Source to

Destination)

9.100 ORL (Or Long Word Data of Destination and Source to Destination)

Take the logical OR of the long word data for the accumulator (A) and that specified by the second operand and restore the result in A.


ORL A,ear ORL A,eam

● Operation:

(A) ← (A) or (Second operand) (Long word logical OR)

● CCR:




V: Cleared

C: Unchanged


I S T N Z V C

– – – * * R –

First operand A A


Byte count 2 2+

Cycle count 2 3



CHAPTER 9 DETAILED INSTRUCTIONS9.100 ORL (Or Long Word Data of Destination and Source to Destination)

● Example:

ORL A,0FFF0H

7 2 5 D F 0 5 C A

Before execution

F F 5 D F A 5 C A

After execution

Memory Memory

F F FFF3 F F FFF35 5 FFF2 5 5 FFF2A A FFF1 A A FFF10 0 FFF0 0 0 FFF0

CCR × × × × ×T N Z V C

CCR × 1 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.101 ORW (Or Word Data of AH and AL to AL)

9.101 ORW (Or Word Data of AH and AL to AL)

Take the logical OR of the word data for AH and that for AL and restore the result in AL.


ORW A

● Operation:

(AL) ← (AH) or (AL) (Word logical OR)

● CCR:




V: Cleared

C: Unchanged


Byte count: 1

Cycle count: 1

● Example:

ORW A

I S T N Z V C

– – – * * R –

0 4 2 6 A B 9 8 A

Before execution

0 4 2 6 A F B E A

After execution

CCR × × × × ×T N Z V C

CCR × 1 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.102 ORW (Or Word Data of Destination and Source to Destination)

9.102 ORW (Or Word Data of Destination and Source to Destination)

Take the logical OR of the word data specified by the first operand and the word data specified by the second operand and restore the result in the first operand.


ORW A,#imm16

ORW A,ear ORW A,eam

ORW ear,A ORW eam,A

● Operation:

(First operand) ← (First operand) or (Second operand) (Word logical OR)

● CCR:




V: Cleared

C: Unchanged


I S T N Z V C

– – – * * R –







CHAPTER 9 DETAILED INSTRUCTIONS9.102 ORW (Or Word Data of Destination and Source to


ORW 0E001H,A


Memory Memory

8 3 E002 D B E0024 2 E001 6 3 E001

× × × × 5 9 6 3 A × × × × 5 9 6 3 A

CCR × × × × ×T N Z V C

CCR × 1 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.103 POPW (Pop Word Data of Accumulator from Stack Memory)

9.103 POPW (Pop Word Data of Accumulator from Stack Memory)

Transfer the values of bits 0 to 15 for the accumulator (A) to bits 16 to 31. Then, the word data of the memory location pointed to by the stack pointer (SP) is transferred to bits 0 to 15 of A. After the data is transferred, 0002H is word-

added to the value of SP (word data).


POPW A

● Operation:

(A) ← ((SP)) (Word transfer)

(SP) ← (SP)+2 (Word addition)

● CCR:



Byte count: 1

Cycle count: 1


I S T N Z V C

– – – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.103 POPW (Pop Word Data of Accumulator from Stack

Memory)● Example:

POPW A

0 1 2 0SP 0 1 2 2 SP


Memory

0122

Memory

01221 0 0121 1 0 0121A C 0120 A C 0120SP

SP

0 4 2 2 1 6 3 5A 1 6 3 5 1 0 A C A

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.104 POPW (Pop Word Data of AH from Stack Memory)

9.104 POPW (Pop Word Data of AH from Stack Memory)

Transfer word data from the memory location pointed to by the stack pointer (SP) to AH. Then, 0002H is word-added to the value of SP (word data).


POPW AH

● Operation:

(AH) ← ((SP)) (Word transfer)


● CCR:



Byte count: 1

Cycle count: 1


● Example:

POPW AH

I S T N Z V C

– – – – – – –

0 4 2 2 1 6 3 5 A

0 1 2 0 SP

4 3 1 4 1 6 3 5 A

0 1 2 2 SP


Memory

0122

Memory

01224 3 0121 4 3 01211 4 0120 1 4 0120SP

SP

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.105 POPW (Pop Word Data of Program Status from Stack

Memory)

9.105 POPW (Pop Word Data of Program Status from Stack Memory)

Transfer word data from the memory location pointed to by the stack pointer (SP) to the processor status (PS). Bit 7 of the word data is ignored. Then, 0002H is word-added to the value of SP (word data).


POPW PS

● Operation:

(PS) ← ((SP)) (Word transfer)


● CCR:

The values of the corresponding bits for the stack memory are transferred.


Byte count: 1



● Example:

POPW PS

I S T N Z V C

* * * * * * *

×CCR × × × × × ×I S T N Z V C



0 1 2 0SP

Before execution

Memory

01224 3 01211 4 0120SP

0CCR 0 1 0 1 0 0I S T N Z V C

ILM 0 1 0ILM2 ILM1 ILM0

RP 0 0 0 1 1MSB LSB

0 1 2 2SP

After execution

Memory

01224 3 01211 4 0120

SP


CHAPTER 9 DETAILED INSTRUCTIONS9.106 POPW (Pop Registers from Stack Memory)

9.106 POPW (Pop Registers from Stack Memory)

Transfer the data pointed to by the stack pointer (SP) to the multiple general-purpose word registers specified by the register list (rlst).

In assembler representation, register names are enumerated as a register list. After assembly,

the register list turns into byte data.


POPW rlst

● Operation:

(RWx) ← ((SP)) (Word transfer)


The above operation is repeated for all the registers specified by rlst.

● CCR:



Byte count: 2

Cycle count: (Number of transfers)

Odd address correction: (Number of transfers)

I S T N Z V C

– – – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.106 POPW (Pop Registers from Stack Memory)

● Example:

POPW (RW0,RW4)

3 4 F A SP

Before execution

34FE0 4 34FD0 3 34FC0 2 34FB

SP

× ×RW7 × ×

× ×RW0 × ×× ×RW1 × ×× ×RW2 × ×× ×RW3 × ×× ×RW4 × ×× ×RW5 × ×× ×RW6 × ×

0 1 34FA

Memory

3 4 F E SP

After execution

34FE0 4 34FD0 3 34FC0 2 34FB

SP

× ×RW7 × ×

0 2RW0 0 1× ×RW1 × ×× ×RW2 × ×× ×RW3 × ×0 4RW4 0 3× ×RW5 × ×× ×RW6 × ×

0 1 34FA

Memory


CHAPTER 9 DETAILED INSTRUCTIONS9.107 PUSHW (Push Word Data of Inherent Register to Stack Memory)

9.107 PUSHW (Push Word Data of Inherent Register to Stack Memory)

Decrement the value of the stack pointer (SP) by two words and transfer the word data of the register to the memory location pointed to by the resulting SP value.


PUSHW A

PUSHW AH

PUSHW PS

● Operation:

(SP) ← (SP)–2 (Word subtraction)

((SP)) ← (Operand) (Word transfer)

● CCR:



I S T N Z V C

– – – – – – –

Operand A AH PS

Byte count 1 1 1

Cycle count 1 1 1



CHAPTER 9 DETAILED INSTRUCTIONS9.107 PUSHW (Push Word Data of Inherent Register to Stack

Memory)● Example:

PUSHW A

0 1 2 2 SP 0 1 2 0 SP


Memory

0122

Memory

0122× × 0121 4 5 0121× × 0120 A 4 0120

SP

SP

4 5 A 4 A 4 5 A 4 A

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.108 PUSHW (Push Registers to Stack Memory)

9.108 PUSHW (Push Registers to Stack Memory)

Transfer the contents of the multiple general-purpose word registers specified by the register list (rlst) to the memory location pointed to by the stack pointer (SP).

In assembler representation, register names are enumerated as a register list. After assembly,

the register list turns into byte data.


PUSHW rlst

● Operation:

(SP) ← (SP)–2 (Word subtraction)

((SP))← (RWx) (Word transfer)

The above operation is repeated for all the registers specified by rlst.

● CCR:



Byte count: 2

Cycle count: (Number of transfers)

Odd address correction: (Number of transfers)

I S T N Z V C

– – – – – – –


CHAPTER 9 DETAILED INSTRUCTIONS9.108 PUSHW (Push Registers to Stack Memory)

● Example:

PUSHW (RW1,RW3)

3 4 F ESP

Before execution

34FE× × 34FD× × 34FC× × 34FB

SP

× ×RW7 × ×

× ×RW0 × ×3 5RW1 A 4× ×RW2 × ×6 DRW3 F 0× ×RW4 × ×× ×RW5 × ×× ×RW6 × ×

× × 34FA

Memory

3 4 F A SP

After execution

34FE6 D 34FDF 0 34FC3 5 34FB

SP

× ×RW7 × ×

× ×RW0 × ×3 5RW1 A 4× ×RW2 × ×6 DRW3 F 0× ×RW4 × ×× ×RW5 × ×× ×RW6 × ×

A 4 34FA

Memory


CHAPTER 9 DETAILED INSTRUCTIONS9.109 RET (Return from Subroutine)

9.109 RET (Return from Subroutine)

Cause a branch to the address pointed to by the stack pointer (SP).

If this instruction is used in combination with a subroutine call instruction (CALL, CALLV),

control returns to the instruction following the subroutine call instruction after the branch

operation is completed.


RET

● Operation:

(PC) ← ((SP)) (Word transfer)


● CCR:



Byte count: 1

Cycle count: 4


● Example:

RET

I S T N Z V C

– – – – – – –

Before execution

Memory

0064F C 00632 2 0062

0 0 6 2 SP

SP

F 0 0 2 PC

After execution

Memory

0064F C 00632 2 0062

0 0 6 4 SP

SP

F C 2 2 PC


CHAPTER 9 DETAILED INSTRUCTIONS9.110 RETI (Return from Interrupt)

9.110 RETI (Return from Interrupt)

This instruction returns the data in the memory that is indicated by (SSP) to PS to detect interrupt requests performed using IF or ILM.

When the next interrupt request is received, the procedure branches to the detected interruption

vector. If no next interrupt is received, the procedure will return from the interruption process.


RETI

● Operation:

(1) If the next interrupt is accepted

(PS) ← ((SSP))

(S) ← 1, (PCB), (PC) ← Interrupt vector address

(ILM) ← Accepted interrupt level

DTB, PCB, DPR, ADB, AL, and AH are not restored.

(2) If control is returned from the next interrupt

(PS) ← ((SSP)), (SSP) ← (SSP)+2;

(PC) ← ((SSP)), (SSP) ← (SSP)+2;

(DTB),(PCB) ← ((SSP)), (SSP) ← (SSP)+2;

(DPR),(ADB) ← ((SSP)), (SSP) ← (SSP)+2;

(AL) ← ((SSP)), (SSP) ← (SSP)+2;

(AH) ← ((SSP)), (SSP) ← (SSP)+2

● CCR

I: Restored to the saved I value. I: Restored to the saved I value.

S: Set S: Restored to the saved S value.

T: Restored to the saved T value. T: Restored to the saved T value.

N: Restored to the saved N value. N: Restored to the saved N value.

Z: Restored to the saved Z value. Z: Restored to the saved Z value.

V: Restored to the saved V value. V: Restored to the saved V value.

C: Restored to the saved C value. C: Restored to the saved C value.

(1) If the next interrupt is accepted (2) If control is returned from the next

interrupt


* S * * * * * * * * * * * *


CHAPTER 9 DETAILED INSTRUCTIONS9.110 RETI (Return from Interrupt)


Byte count: 1



● Example:

RETI (if control is returned from the interrupt)

× × × ×PC

× ×DTB

× × × × × × × × A

Memory

038000 F F 037FFF E E 037FFE

SSP

× ×PCB

× ×DPR

× ×ADB

× ×ILM

× ×RP

0 3SSB

7 F F 4SSP


Before execution

7 7 6 6PC

9 9DTB

F F F E D D C C A

Memory

038000F F 037FFFE E 037FFE

SSP

8 8PCB

B BDPR

A AADB

0 3ILM

0 1RP

0 3SSB

8 0 0 0SSP


After execution

CCR

I S T N Z V C

× × × × × × ×I S T N Z V C0 0 0 0 0 0 0

CCR


CHAPTER 9 DETAILED INSTRUCTIONS9.111 RETP (Return from Physical Address)

9.111 RETP (Return from Physical Address)

Cause a branch to the physical address pointed to by the stack pointer (SP).

If this instruction is used in combination with the CALLP instruction, control returns to the

instruction following the CALLP instruction after the branch operation is completed.


RETP

● Operation:

(PC) ← ((SP)), (SP) ← (SP)+2 (Word addition)

(PCB) ← ((SP)) (Byte transfer), (SP) ← (SP)+2 (Word addition)

● CCR:



Byte count: 1

Cycle count: 5


● Example:

RETP

I S T N Z V C

– – – – – – –

F 8 F CSP

Before execution

Memory

× × 15F9000 0 15F8FF

4 3 15F8FDA D 15F8FE

SP

2 2 F CPC

1 5USB0 8PCB

4 5 15F8FC

F 9 0 0SP

After execution

Memory

× × 15F9000 0 15F8FF

4 3 15F8FDA D 15F8FE

SP

4 3 4 5PC

1 5USBA DPCB

4 5 15F8FC

CCR × 0 × × × × ×I S T N Z V C

CCR × 0 × × × × ×I S T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.112 ROLC (Rotate Byte Data of Accumulator with Carry to Left)

9.112 ROLC (Rotate Byte Data of Accumulator with Carry to Left)

Rotate or shift the byte data specified by the operand to the left by one bit, including the carry bit (C). The most significant bit of the operand is placed in the carry bit (c).


ROLC A

ROLC ear ROLC eam

● Operation:

● CCR:




V: Unchanged

C: Stores the bit shifted out from the MSB of A.


I S T N Z V C

– – – * * – *

MSB LSB CA or operand

Operand A ear eam

Byte count 2 2 2+

Cycle count 1 1 3


CHAPTER 9 DETAILED INSTRUCTIONS9.112 ROLC (Rotate Byte Data of Accumulator with Carry to

Left)● Example:

ROLC A

× × × × × × 3 2 A

Before execution

× × × × × × 6 4 A

After execution

CCR × × × × 0

T N Z V C

CCR × 0 0 × 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.113 RORC (Rotate Byte Data of Accumulator with Carry to Right)

9.113 RORC (Rotate Byte Data of Accumulator with Carry to Right)

Rotate or shift the byte data specified by the operand to the right by one bit, including the carry bit (C). The least significant bit of the operand is placed in the carry bit (c).


RORC A

RORC ear RORC eam

● Operation:

● CCR:




V: Unchanged



I S T N Z V C

– – – * * – *

MSB LSB CA or operand

Operand A ear eam

Byte count 2 2 2+

Cycle count 1 1 3


CHAPTER 9 DETAILED INSTRUCTIONS9.113 RORC (Rotate Byte Data of Accumulator with Carry to

Right)● Example:

RORC A

× × × × × × 3 2

CCR

A

Before execution

× × × × × × 1 9

CCR

A

After execution

× × × × 0T N Z V C

× 0 0 × 0T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.114 SBBS (Set Bit and Branch if Bit Set)

9.114 SBBS (Set Bit and Branch if Bit Set)

Cause a branch if the bit data specified by the first operand is "1".

Control is transferred to the address resulting from word-adding the value resulting from sign-

extending the second operand to the address of the instruction following the SBBS instruction.

After the instruction has been executed, the bit specified by the first operand is set to "1".


SBBS addr16:bp,rel

● Operation:

If the condition is satisfied:

(PC) ← (PC)+<Byte count>+rel (Word addition), (addr16:bp) ← 1

If the condition is not satisfied:

(PC) ← (PC)+<Byte count> (Word addition), (addr16:bp) ← 1

● CCR:


Z: Set when the bit data is "0", cleared otherwise.

V and C: Unchanged


Byte count: 5

Cycle count: 5

● Example:

SBBS 1234H:5,20H

I S T N Z V C

– – – – * – –

Before execution

Memory

× ×7 F 1234× ×

E 1 0 0PC

After execution

Memory

× ×7 F 1234× ×

E 1 2 5PC


CHAPTER 9 DETAILED INSTRUCTIONS9.115 SCEQ, SCEQI (Scan String Byte until equal with

Increment)

9.115 SCEQ, SCEQI (Scan String Byte until equal with Increment)

Compare the byte data specified by AH in the space specified by <bank> with the data of AL. The address is incremented and RW0 is decremented until the byte data matches the data or RW0 becomes equal to "0".

Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. By default,

DTB is assumed.

If RW0 is equal to "0", comparison is not performed. If an interrupt occurs during the

execution of the instruction, the execution of the instruction is suspended to handle the

interrupt. After the interrupt has been handled, the execution of the instruction is resumed.


SCEQ [<bank>]SCEQI [<bank>] (When the address is incremented)

● Operation:

The following operation is repeated until RW0 = 0 or ((AH)) = (AL) (Byte comparison):

(AH) ← (AH)±1

(RW0) ← (RW0)–1

● CCR:


N: Unchanged if the initial value of RW0 is "0". If the initial value of RW0 is not "0",

N is set when the MSB of the last compare operation result is "1", cleared

otherwise.

Z: Unchanged if the initial value of RW0 is "0". If the initial value of RW0 is not "0",

Z is set when a match with the contents of AL is found; cleared when the

instruction terminates with RW0 being set to "0".

V: Unchanged if the initial value of RW0 is "0". If the initial value of RW0 is not "0",

V is set when an overflow has occurred as a result of the last compare operation;

cleared otherwise.

C: Unchanged if the initial value of RW0 is "0". If the initial value of RW0 is not "0",

V is set when a borrow has occurred as a result of the last compare operation;

cleared otherwise.

I S T N Z V C

– – – * * * *


CHAPTER 9 DETAILED INSTRUCTIONS9.115 SCEQ, SCEQI (Scan String Byte until equal with Increment)


Byte count: 2

Cycle count: 1 when (RW0) is "0"; 3 when (RW0) is "1"; and 2+2 × (Number of times

the comparison was performed) in all other cases

● Example:

SCEQ

0 1 0 0RW0

Before execution

0315864 6 0315854 8 031584

0 3DTB

1 5 8 0 0 0 4 6AH AL

4 9 031583

0 0 F ARW0 0 3DTB

1 5 8 6 0 0 4 6AH AL

4 D 0315824 E 0315815 4 031580AH

Memory

After execution

1315864 6 0315854 8 0315844 9 0315834 D 0315824 E 0315815 4 031580

AHMemory

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.116 SCEQD (Scan String Byte until equal with Decrement)

9.116 SCEQD (Scan String Byte until equal with Decrement)

Compare the byte data specified by AH in the space specified by <bank> with the data of AL. The address is decremented and RW0 is decremented until the byte data matches the data or RW0 becomes equal to "0".


DTB is assumed.





SCEQ [<bank>]SCEQI [<bank>] (When the address is incremented)

● Operation:

The following operation is repeated until RW0 = 0 or ((AH)) = (AL) (Byte comparison):

(AH) ← (AH)±1

(RW0) ← (RW0)–1

● CCR:




otherwise.






cleared otherwise.



cleared otherwise.

I S T N Z V C

– – – * * * *


CHAPTER 9 DETAILED INSTRUCTIONS9.116 SCEQD (Scan String Byte until equal with Decrement)


Byte count: 2

Cycle count: 1 when (RW0) is "0"; 3 when (RW0) is "1"; and 2+2 × (Number

of times the comparison was performed) in all other cases

Odd address correction: (Number of times the comparison was performed)


CHAPTER 9 DETAILED INSTRUCTIONS9.117 SCWEQ, SCWEQI (Scan String Word until equal with

Increment)

9.117 SCWEQ, SCWEQI (Scan String Word until equal with Increment)

Compare the word data specified by AH in the space specified by <bank> with the data of AL. The address is incremented and RW0 is decremented until the word data matches the data or RW0 becomes equal to "0".


DTB is assumed.





SCWEQ [<bank>] SCWEQI [<bank>]

● Operation:

The following operation is repeated until RW0 = 0 or ((AH)) = (AL) (Word comparison):

(AH) ← (AH)±2

(RW0) ← (RW0)–1

● CCR:




otherwise.






cleared otherwise.



cleared otherwise.

I S T N Z V C

– – – * * * *


CHAPTER 9 DETAILED INSTRUCTIONS9.117 SCWEQ, SCWEQI (Scan String Word until equal with Increment)


Byte count: 2

Cycle count: 1 when (RW0) is "0"; 3 when (RW0) is "1"; and 2+2 ×

(Number of times the operation was repeated) in all other cases

Odd address correction: (Number of times the operation was repeated)

● Example:

SCWEQ

0 0 0 3RW0

Before execution

E 6 DEC006E 5 DEC005E 4 DEC004

D EDTB

AH AL

E 3 DEC003

0 0 0 0RW0 D EDTB

AH AL

E 2 DEC002E 1 DEC001E 0 DEC000AH

Memory

After execution

E 6 DEC006E 5 DEC005E 4 DEC004E 3 DEC003E 2 DEC002E 1 DEC001E 0 DEC000

AH

Memory

C 0 0 0 0 0 F F C 0 0 6 0 0 F F

CCR × × × × ×T N Z V C

CCR × 1 0 0 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.118 SCWEQD (Scan String Word until equal with Decrement)

9.118 SCWEQD (Scan String Word until equal with Decrement)

Compare the word data specified by AH in the space specified by <bank> with the data of AL. The address is decremented and RW0 is decremented until the word data matches the data or RW0 becomes equal to "0".


DTB is assumed.





SCWEQD [<bank>]

● Operation:

The following operation is repeated until RW0 = 0 or ((AH)) = (AL) (Word comparison):

(AH) ← (AH)–2

(RW0) ← (RW0)–1

● CCR:




otherwise.






cleared otherwise.



cleared otherwise.

I S T N Z V C

– – – * * * *


CHAPTER 9 DETAILED INSTRUCTIONS9.118 SCWEQD (Scan String Word until equal with Decrement)


Byte count: 2

Cycle count: 1 when (RW0) is "0"; 3 when (RW0) is "1"; and 2+2 ×

(Number of times the operation was repeated) in all other cases

Odd address correction: (Number of times the operation was repeated)


CHAPTER 9 DETAILED INSTRUCTIONS9.119 SETB (Set Bit)

9.119 SETB (Set Bit)

Set the contents of the bit address specified by the operand to "1".


SETB addr16:bp

SETB dir:bp

SETB io:bp

● Operation:

(Operand) b ← 1 (Bit transfer)

● CCR:


Byte count and cycle count:

● Example:

SETB 0AA55H:4

I S T N Z V C

– – – – – – –

Operand addr16:bp dir:bp io:bp

Byte count 4 3 3

Cycle count 3 3 3

Before execution

Memory

× ×6 F AA55× ×

After execution

Memory

× ×7 F AA55× ×

0 0 0 0 0CCR

T N Z V C

0 0 0 0 0CCR

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.120 SUB (Subtract Byte Data of Source from Destination to Destination)

9.120 SUB (Subtract Byte Data of Source from Destination to Destination)

Subtract the byte data specified by the second operand from the byte data specified by the first operand and restore the result in the first operand. If the first operand is A, "0" is transferred to bits 8 to 15 of A.


SUB A,#imm8 SUB A,dir

SUB A,ear SUB A,eam

SUB ear,A SUB eam,A

● Operation:

(First operand) ← (First operand)–(Second operand) (Byte subtraction)

● CCR:







I S T N Z V C

– – – * * * *

First operand A A A A ear eam

Second operand #imm8 dir ear eam A A

Byte count 2 2 2 2+ 2 2+



CHAPTER 9 DETAILED INSTRUCTIONS9.120 SUB (Subtract Byte Data of Source from Destination to


SUB A,#22H


CCR × × × × ×T N Z V C

CCR × 1 0 0 1

T N Z V C

× × × × 4 9 0 1 A × × × × 0 0 D F A


CHAPTER 9 DETAILED INSTRUCTIONS9.121 SUBC (Subtract Byte Data of AL from AH with Carry to AL)

9.121 SUBC (Subtract Byte Data of AL from AH with Carry to AL)

Subtract the low-order byte data of AL and the carry bit (C) from the low-order byte data of AH and restore the result in AL. "0" is transferred to bits 8 to 15 of the accumulator (A).


SUBC A

● Operation:

(AL) ← (AH)–(AL)–(C) (Byte subtraction with a carry)

● CCR:







Byte count: 1

Cycle count: 1

● Example:

SUBC A

I S T N Z V C

– – – * * * *

0 5 0 5 0 0 D 4 A

Before execution

0 5 0 5 0 0 3 0 A

After execution

CCR × × × × ×T N Z V C

CCR × 1 0 0 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.122 SUBC (Subtract Byte Data of Effective Address from

Accumulator with Carry to Accumulator)

9.122 SUBC (Subtract Byte Data of Effective Address from Accumulator with Carry to Accumulator)

Subtract the byte data specified by the second operand and the carry bit (C) from the byte data of the accumulator (A) and restore the result in A. "0" is transferred to bits 8 to 15 of A.


SUBC A,ear SUBC A,eam

● Operation:

(A) ← (A)–(Second operand)–(C) (Byte subtraction with a carry)

● CCR:







I S T N Z V C

– – – * * * *

First operand A A


Byte count 2 2+

Cycle count 1 2


CHAPTER 9 DETAILED INSTRUCTIONS9.122 SUBC (Subtract Byte Data of Effective Address from Accumulator with Carry to Accumulator)

● Example:

SUBC A,R1


5 4R1 5 4R1

× × × × 0 0 3 5 A × × × × 0 0 E 1 A

CCR × × × × 0

T N Z V C

CCR × 1 0 0 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.123 SUBCW (Subtract Word Data of Effective Address from

Accumulator with Carry to Accumulator)

9.123 SUBCW (Subtract Word Data of Effective Address from Accumulator with Carry to Accumulator)

Subtract the word data specified by the second operand and the carry bit (C) from the low-order word data of the accumulator (A) and restore the result in A.


SUBCW A,ear SUBCW A,eam

● Operation:

(A) ← (A)–(Second operand)–(C) (Word subtraction with a carry)

● CCR:







I S T N Z V C

– – – * * * *

First operand A A


Byte count 2 2+

Cycle count 1 2



CHAPTER 9 DETAILED INSTRUCTIONS9.123 SUBCW (Subtract Word Data of Effective Address from Accumulator with Carry to Accumulator)

● Example:

SUBCW A,0E024H


Memory Memory

A 9 E025 A 9 E0255 B E024 5 B E024

× × × × 7 5 5 8A × × × × C B F C A

CCR × × × × 1

T N Z V C

CCR × 1 0 0 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.124 SUBDC (Subtract Decimal Data of AL from AH with Carry

to AL)

9.124 SUBDC (Subtract Decimal Data of AL from AH with Carry to AL)

Subtract the low-order byte data of AL and the carry bit (C) from the low-order byte data of AH and restore the result in AL. "0" is transferred to bits 8 to 15 of A.


SUBDC A

● Operation:

(AL) ← (AH)–(AL)–(C) (Decimal subtraction with a carry)

● CCR:




V: Undefined

C: Set when a borrow has occurred as a result of the decimal operation, cleared otherwise.


Byte count: 1

Cycle count: 2

● Example:

SUBDC A

I S T N Z V C

– – – * * * *

× × 8 6 × × 8 6 A

Before execution

× × 8 6 0 0 0 0 A

After execution

CCR × × × × 0

T N Z V C

CCR × 0 1 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.125 SUBL (Subtract Long Word Data of Source from Destination to Destination)

9.125 SUBL (Subtract Long Word Data of Source from Destination to Destination)

Subtract the long word data specified by the second operand from the long word data of the accumulator (A) and restore the result in A.


SUBL A,#imm32

SUBL A,ear SUBL A,eam

● Operation:

(First operand) ← (First operand)–(Second operand) (Long word subtraction)

● CCR:







I S T N Z V C

– – – * * * *

First operand A A A


Byte count 5 2 2+

Cycle count 2 2 3



CHAPTER 9 DETAILED INSTRUCTIONS9.125 SUBL (Subtract Long Word Data of Source from

Destination to Destination)● Example:

SUBL A,0FD12H

3 4 B 3 F 2 0 1 A

Before execution

E 2 5 4 C 0 4 4 A

After execution

Memory Memory

FD16 FD165 2 FD15 5 2 FD155 F FD14 5 F FD143 1 FD13 3 1 FD13B D FD12 B D FD12

CCR × × × × ×T N Z V C

CCR × 1 0 0 1

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.126 SUBW (Subtract Word Data of Source from Destination to Destination)

9.126 SUBW (Subtract Word Data of Source from Destination to Destination)

Subtract the word data specified by the second operand from the word data specified by the first operand and restore the result in the first operand.


SUBW A,#imm16

SUBW A,ear SUBW A,eam

SUBW ear,A SUBW eam,A

● Operation:

(First operand) ← (First operand)–(Second operand) (Word subtraction)

● CCR:







I S T N Z V C

– – – * * * *







CHAPTER 9 DETAILED INSTRUCTIONS9.126 SUBW (Subtract Word Data of Source from Destination to


SUBW @RW0+,A

× × × × 3 1 0 4 A

E 2 A 4 RW0

× × × × 3 1 0 4 A

E 2 A 6 RW0


Memory Memory

5 D E2A5 2 C E2A5A B E2A4 A 7 E2A4

CCR × × × × ×T N Z V C

CCR × 0 0 0 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.127 SUBW (Subtract Word Data of AL from AH to AL)

9.127 SUBW (Subtract Word Data of AL from AH to AL)

Subtract the word data of AL from the word data of AH and restore the result to AL.


SUBW A

● Operation:

(AL) ← (AH)–(AL) (Word subtraction)

● CCR:







Byte count: 1

Cycle count: 1

● Example:

SUBW A

I S T N Z V C

– – – * * * *

8 3 A 2 1 0 1 9 A

Before execution

8 3 A 2 7 3 8 9 A

After execution

CCR × × × × ×T N Z V C

CCR × 0 0 1 0

T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.128 SWAP (Swap Byte Data of Accumulator)

9.128 SWAP (Swap Byte Data of Accumulator)

Swap the high- and low-order bytes of the word data for the accumulator (A) with each other.


SWAP

● Operation:

(A) 0 to 7 ↔ (A) 8 to 15 (Byte swapping)

● CCR:



Byte count: 1

Cycle count: 1

● Example:

SWAP

I S T N Z V C

– – – – – – –

× × × × 0 6 9 0 A

Before execution

× × × × 9 0 0 6 A

After execution

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.129 SWAPW (Swap Word Data of Accumulator)

9.129 SWAPW (Swap Word Data of Accumulator)

Swap the high- and low-order words of the long word data for the accumulator (A) with each other.


SWAPW

● Operation:

Bits 0 to 15 of A ↔ Bits 16 to 31 of A (Word swapping)

● CCR:



Byte count: 1

Cycle count: 1

● Example:

SWAPW

I S T N Z V C

– – – – – – –

1 9 8 6 9 8 6 1 A

Before execution

9 8 6 1 1 9 8 6 A

After execution

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.130 UNLINK (Unlink and Create New Stack Frame)

9.130 UNLINK (Unlink and Create New Stack Frame)

Restore an old frame pointer from a stack.


UNLINK

● Operation:

(sp) ← (RW3), (RW3) ← ((sp)), (sp) ← (sp)+2

● CCR:



Byte count: 1

Cycle count: 1


● Example:

UNLINK

I S T N Z V C

– – – – – – –

Before execution

Memory

A 04 6 E020

E 0 0 0SP

SP × × E000

E 0 2 0RW3

E 0 2 2SP

A 0 4 6RW3

After execution

Memory

× × E022

4 6 E020

SPA 0 E021


CHAPTER 9 DETAILED INSTRUCTIONS9.131 WBTc (Wait until Bit Condition Satisfied)

9.131 WBTc (Wait until Bit Condition Satisfied)

This instruction keeps reading data from the bit address specified by the operand until that data satisfies the conditions. Once the data at the specified bit address satisfies the conditions, control is transferred to the instruction subsequent to the WBTc instruction.


WBTC io:bp

WBTS io:bp

● Operation:

Data is read from the bit address specified by io:bp until the data satisfies the condition. If the

data from the bit address satisfies the condition, control is transferred to the next instruction.

Interrupts are acceptable while the read operation is repeated with the condition not satisfied.

If an interrupt is generated in this state, the RETI instruction causes control to return to the

WBTc instruction, not to the instruction following the WBTc instruction.

● CCR:



I S T N Z V C

– – – – – – –

Instruction WBTC WBTS

Condition Bit data=0 Bit data=1

Byte count 3 3

Cycle countUndefined

(Until the condition is satisfied) Undefined

(Until the condition is satisfied)


CHAPTER 9 DETAILED INSTRUCTIONS9.131 WBTc (Wait until Bit Condition Satisfied)

● Example:

WBTS 34H:7

Before execution

Memory

× ×7 F 0034H

× ×

E 1 0 0PC

After execution

Peripheralregister

Data is read from address 34H until bit 7 is set to "1" (because of resource operation, for example). When bit 7 becomes "1", execute the next instruction.


CHAPTER 9 DETAILED INSTRUCTIONS9.132 XCH (Exchange Byte Data of Source to Destination)

9.132 XCH (Exchange Byte Data of Source to Destination)

Exchange the byte data specified by the first operand with that specified by the second operand.

If the first operand is A, the high-order byte of AL is set to 00H.


XCH A,ear XCH A,eam

XCH Ri,ear XCH Ri,eam

● Operation:

(First operand) ↔ (Second operand) (Byte exchange)

● CCR:



I S T N Z V C

– – – – – – –

First operand A A Ri Ri



Cycle count 1 2 2 2


CHAPTER 9 DETAILED INSTRUCTIONS9.132 XCH (Exchange Byte Data of Source to Destination)

● Example:

XCH R4,@RW0+

0 0 6 0RW0

F 1R4


Memory

0061

Memory

0061

2 2 0060 F 1 0060

0 0 6 1 RW0

2 2R4

RW0RW0

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.133 XCHW (Exchange Word Data of Source to Destination)

9.133 XCHW (Exchange Word Data of Source to Destination)

Exchange the word data specified by the first operand with that specified by the second operand.


XCHW A,ear XCHW A,eam

XCHW RWi,ear XCHW RWi,eam

● Operation:

(First operand) ↔ (Second operand) (Word exchange)

● CCR:



I S T N Z V C

– – – – – – –

First operand A A RWi RWi



Cycle count 1 2 2 2



CHAPTER 9 DETAILED INSTRUCTIONS9.133 XCHW (Exchange Word Data of Source to Destination)

● Example:

XCHW A,@RW0

× × × × 3 4 B 4 A

RW0

× × × × 2 D 5 8 A

RW0


Memory Memory

2 D E002 3 4 E0025 8 E001 B 4 E001RW0 RW0

E 0 0 1 E 0 0 1

CCR × × × × ×T N Z V C

CCR × × × × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.134 XOR (Exclusive Or Byte Data of Destination and Source to Destination)

9.134 XOR (Exclusive Or Byte Data of Destination and Source to Destination)

Take the logical exclusive OR of the byte data specified by the first operand and the byte data specified by the second operand and restore the result in the first operand.


XOR A,#imm8

XOR A,ear XOR A,eam

XOR ear,A XOR eam,A

● Operation:

(First operand) ← (First operand) xor (Second operand) (Byte logical exclusive OR)

● CCR:




V: Cleared

C: Unchanged


I S T N Z V C

– – – * * R –






CHAPTER 9 DETAILED INSTRUCTIONS9.134 XOR (Exclusive Or Byte Data of Destination and Source

to Destination)● Example:

XOR 0052H,A

× × × × 0 0 5 5A

Before execution

× × × × 0 0 5 5A

After execution

Memory Memory

F A 000052 A F 000052

CCR × × × × ×T N Z V C

CCR × 1 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.135 XORL (Exclusive Or Long Word Data of Destination and Source to Destination)

9.135 XORL (Exclusive Or Long Word Data of Destination and Source to Destination)

Take the logical exclusive OR of the long word data for the accumulator (A) and that specified by the second operand and restore the result in A.


XORL A,ear XORL A,eam

● Operation:

(A) ← (A) xor (Second operand) (Long word logical exclusive OR)

● CCR:




V: Cleared

C: Unchanged


I S T N Z V C

– – – * * R –

First operand A A


Byte count 2 2+

Cycle count 2 3



CHAPTER 9 DETAILED INSTRUCTIONS9.135 XORL (Exclusive Or Long Word Data of Destination and

Source to Destination)● Example:

XORL A,0FFF0H

8 2 5 2 F E A C A

Before execution

7 D 0 7 5 4 A C A

After execution

Memory Memory



CCR × × × × ×T N Z V C

CCR × 0 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.136 XORW (Exclusive Or Word Data of AH and AL to AL)

9.136 XORW (Exclusive Or Word Data of AH and AL to AL)

Take the logical exclusive OR for the word data of AH and that of AL and restore the result in AL.


XORW A

● Operation:

(AL) ← (AH) xor (AL) (Word logical exclusive OR)

● CCR:




V: Cleared

C: Unchanged


Byte count: 1

Cycle count: 1

● Example:

XORW A

I S T N Z V C

– – – * * R –

0 4 2 6 A B 9 8 A

Before execution

0 4 2 6 A F B E A

After execution

CCR × × × × ×T N Z V C

CCR × 1 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.137 XORW (Exclusive Or Word Data of Destination and

Source to Destination)

9.137 XORW (Exclusive Or Word Data of Destination and Source to Destination)

Take the logical exclusive OR of the word data specified by the first operand and the word data specified by the second operand and restore the result in the first operand.


XORW A,#imm16

XORW A,ear XORW A,eam

XORW ear,A XORW eam,A

● Operation:

(First operand) ← (First operand) xor (Second operand) (Word logical exclusive OR)

● CCR:




V: Cleared

C: Unchanged


I S T N Z V C

– – – * * R –







CHAPTER 9 DETAILED INSTRUCTIONS9.137 XORW (Exclusive Or Word Data of Destination and Source to Destination)

● Example:

XORW 0E001H,A


Memory Memory

8 3 E0024 2 E001

D A E0022 1 E001

× × × × 5 9 6 3 A × × × × 5 9 6 3 A

CCR × × × × ×T N Z V C

CCR × 1 0 0 ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.138 ZEXT (Zero Extend from Byte Data to Word Data)

9.138 ZEXT (Zero Extend from Byte Data to Word Data)

Transfer "0" to bits 8 to 15 of the accumulator (A).


ZEXT

● Operation:

Bits 8 to 15 of A ← 00H

● CCR:


N: Cleared

Z: Set when the zero-extended data is "0", cleared otherwise.

V and C: Unchanged


Byte count: 1

Cycle count: 1

● Example:

ZEXT

I S T N Z V C

– – – R * – –

× × × × × × A

Before execution

× × × × 0 0 8 0 A

After execution

8 0

CCR × × × × ×T N Z V C

CCR × 0 0 × ×T N Z V C


CHAPTER 9 DETAILED INSTRUCTIONS9.139 ZEXTW (Zero Extend from Word Data to Long Word Data)

9.139 ZEXTW (Zero Extend from Word Data to Long Word Data)

Transfer "0" to bits 16 to 31 of the accumulator (A).


ZEXTW

● Operation:

Bits 16 to 31 of A ← 0000H

● CCR:

I, S, andT: Unchanged

N: Cleared

Z: Set when the zero-extended data is "0", cleared otherwise.

V and C: Unchanged


Byte count: 1

Cycle count: 1

● Example:

ZEXTW

I S T N Z V C

– – – R * – –

× × × × F F 8 0 A

Before execution

0 0 0 0 F F 8 0A

After execution

CCR × × × × ×T N Z V C

CCR × 0 0 × ×T N Z V C


APPENDIX

This appendix includes lists and maps of

instructions for the F2MC-16FX CPU.

APPENDIX A Explanation of Instruction Lists

APPENDIX B Instruction Lists (351 Instructions)

APPENDIX C Instruction Maps

APPENDIX D Failure of String Instructions and WBTC/WBTS Instructions

APPENDIX E Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt


APPENDIX APPENDIX A Explanation of Instruction Lists

APPENDIX A Explanation of Instruction Lists

This section explains items and symbols used in each instruction list included in Instruction Lists (351 Instructions).

A.1 Items Used in Instruction Lists

A.2 Symbols Used in Instruction Lists

A.3 Effective Address Field

A.4 Calculating the Execution Cycle Count


APPENDIXAPPENDIX A Explanation of Instruction Lists

A.1 Items Used in Instruction Lists

Table A.1-1 explains the items used in the instruction lists.

Table A.1-1 Explanation of the Items Used in the Instruction Lists

Item Description

MnemonicUpper-case letters and symbols: Described as they appear in assembler.Lower-case letters: Replaced when described in assembler.Numbers after lower-case letters: Indicate the bit width within the instruction.

# Indicates the byte count.

~Indicates the cycle count.See Table A.4-1 for details about meanings of letters in items.

BIndicates the cycle count required for correcting odd addresses.The actual cycle count during instruction execution is the correction value added to the value in the "~" column.

Operation Indicates operation of instruction.

LH

Indicates special operations involving bits 15 through 08 of the accumulator.Z: Transfers "0".X: Sign-extended transfer through sign extension.- : Transfers nothing.

AH

Indicates special operations involving the high-order 16 bits in the accumulator.*: Transfers from AL to AH.- : No transferZ: Transfers 00H to AH.X: Transfers 00H or FFH to AH using sign extension AL.

I Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry).

*: Changes due to execution of instruction.- : No changeS: Set by execution of instruction.R: Reset by execution of instruction.

S

T

N

Z

V

C

RMW

Indicates whether the instruction is a read-modify-write instruction (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.).*: Instruction is a read-modify-write instruction.-: Instruction is not a read-modify-write instruction.Note:

A read-modify-write instruction cannot be used on addresses of the I/O register, etc., that have different meanings depending on whether they are read or written.



■ Execution cycle countThe cycle count required to execute instructions (execution cycle count) is the summation of

the cycle count of each instruction and the odd address correction value determined by access

conditions for data. At the actual instruction execution time, the execution cycle count may

become larger than the calculated value due to the instruction fetch delay, the data access

conflict, etc. Especially, when performing instruction fetch and data access from an external

bus by using the external bus interface, the execution cycle count becomes larger than the

calculated value.

■ Odd address correction For some instructions, the execution cycles increases when performing data access to odd

addresses. The execution cycles that increases at data access time to odd addresses is shown

under the title of "odd address correction" in item B in the instruction list.



A.2 Symbols Used in Instruction Lists

Table A.2-1 explains the symbols used in the instruction lists.

■ Explanation of the Symbols Used in the Instruction Lists

Table A.2-1 Explanation of the Symbols Used in the Instruction Lists (1 / 2)

Symbol Explanation

A

32 bit accumulator The bit length used is different for each instruction.

Byte: Lower 8 bits of ALWord: 16 bits of ALLong: 32 bits of AL and AH

AH Upper 16 bits of A

AL Lower 16 bits of A

SP Stack pointer (USP or SSP)

PC Program counter

PCB Program bank register

DTB Data bank register

ADB Additional data bank register

SSB System stack bank register

USB User stack bank register

DPR Direct page register

brg1 DTB, ADB, SSB, USB, DPR, PCB

brg2 DTB, ADB, SSB, USB, DPR

Ri R0, R1, R2, R3, R4, R5, R6, R7

Rj R0, R1, R2, R3

RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RWj RW0, RW1, RW2, RW3

RLi RL0, RL1, RL2, RL3

dir Abbreviated direct addressing

addr16 Direct addressing

addr24 Physical direct addressing

ad24 0-15 Bit0 to bit15 of address 24

ad24 16-23 Bit16 to bit23 of address 24

io I/O area (000000H to 0000FFH)



imm4 4-bit immediate data




ext (imm8) 16-bit data signed and extended from 8-bit immediate data

disp8 8-bit displacement

disp16 16-bit displacement

bp Bit offset value

vct4 Vector number (0 to 15)

vct8 Vector number (0 to 255)

( ) b Bit address

rel Branch specification relative to PC

ear Effective addressing (codes 00 to 07)

eam Effective addressing (codes 08 to 1F)

rlst Register list

Table A.2-1 Explanation of the Symbols Used in the Instruction Lists (2 / 2)

Symbol Explanation



A.3 Effective Address Field

Table A.3-1 lists address formats used in the effective address field.

Table A.3-1 Effective Address Field

Code Notation Address formatByte count of address

expansion part*

00 R0 RW0 RL0

Register direct Starting from the left, "ea" corresponds to the byte, word and long-word types.

-

01 R1 RW1 (RL0)

02 R2 RW2 RL1

03 R3 RW3 (RL1)

04 R4 RW4 RL2

05 R5 RW5 (RL2)

06 R6 RW6 RL3

07 R7 RW7 (RL3)

08 @RW0

Register indirect 009 @RW1

0A @RW2

0B @RW3

0C @RW0+

Register indirect with post-incrementing 00D @RW1+

0E @RW2+

0F @RW3+

10 @RW0+disp8


11 @RW1+disp8

12 @RW2+disp8

13 @RW3+disp8

14 @RW4+disp8

15 @RW5+disp8

16 @RW6+disp8

17 @RW7+disp8

18 @RW0+disp16


219 @RW1+disp16

1A @RW2+disp16

1B @RW3+disp16

1C @RW0+RW7 Register indirect with index 0

1D @RW1+RW7 Register indirect with index 0

1E @PC+disp16 PC indirect with 16-bit displacement 2

1F addr16 Direct address 2*: The byte count of the address expansion part is shown in the "#" (byte count) column. "numeric value+", such as "2+",

written in the detailed instructions indicates the byte count of the address expansion part added to the value.



A.4 Calculating the Execution Cycle Count

Table A.4-1 shows the method of calculating the execution cycle count of instructions.

■ Calculating the Execution Cycle Count

Table A.4-1 Execution Cycle Count for Designating Each Effective Address

Code Operand (a)* Execution cycle count for each form of addressing

00to07

RiRwiRLi

Listed in Table of Instructions

08to0B

@RWj 2

0Cto0F

@RWj+ 4

10to17

@RWi+disp8 2

18to1B

@RWj+disp16 2

1C1D1E1F

@RW0+RW7@RW1+RW7@PC+disp16addr16

4421

* : (a) is used in "~" (cycle count), (both in "APPENDIX B ", and in "CHAPTER 9 DETAILED INSTRUCTIONS".


APPENDIXAPPENDIX B Instruction Lists (351 Instructions)

APPENDIX B Instruction Lists (351 Instructions)

Instruction lists used by the assembler is shown here. For each item and symbol in the instruction lists, see “APPENDIX A Explanation of Instruction Lists”.

Table B-1 Transfer Instructions (Byte) : 41 instructions

Mnemonic operand Len Cycles Correction value operand on odd address Operation LH AH I S T N Z V C RMW

MOV A, dir 2 1 0 byte (A) ← (dir) Z * - - - * * - - -

MOV A, addr16 3 1 0 byte (A) ← (addr16) Z * - - - * * - - -

MOV A, Ri 1 1 0 byte (A) ← (Ri) Z * - - - * * - - -

MOV A, ear 2 1 0 byte (A) ← (ear) Z * - - - * * - - -

MOV A, eam 2+ 1 0 byte (A) ← (eam) Z * - - - * * - - -

MOV A, io 2 1 0 byte (A) ← (io) Z * - - - * * - - -

MOV A, #imm8 2 1 0 byte (A) ← imm8 Z * - - - * * - - -

MOV A, @A 2 1 0 byte (A) ← ((A)) Z - - - - * * - - -

MOV A, @RLi+disp8 3 1 0 byte (A) ← ((RLi)+disp8) Z * - - - * * - - -

MOVN A, #imm4 1 1 0 byte (A) ← imm4 Z * - - - R * - - -

MOVX A, dir 2 1 0 byte (A) ← (dir) X * - - - * * - - -

MOVX A, addr16 3 1 0 byte (A) ← (addr16) X * - - - * * - - -

MOVX A, Ri 2 1 0 byte (A) ← (Ri) X * - - - * * - - -

MOVX A, ear 2 1 0 byte (A) ← (ear) X * - - - * * - - -

MOVX A, eam 2+ 1 0 byte (A) ← (eam) X * - - - * * - - -

MOVX A, io 2 1 0 byte (A) ← (io) X * - - - * * - - -

MOVX A, #imm8 2 1 0 byte (A) ← imm8 X * - - - * * - - -

MOVX A, @A 2 1 0 byte (A) ← ((A)) X - - - - * * - - -

MOVX A, @RWi+disp8 2 1 0 byte (A) ← ((RWi)+disp8) X * - - - * * - - -

MOVX A, @RLi+disp8 3 1 0 byte (A) ← ((RLi)+disp8) X * - - - * * - - -

MOV dir, A 2 1 0 byte (dir) ← (A) - - - - - * * - - -

MOV addr16, A 3 1 0 byte (addr16) ← (A) - - - - - * * - - -

MOV Ri, A 1 1 0 byte (Ri) ← (A) - - - - - * * - - -

MOV ear, A 2 1 0 byte (ear) ← (A) - - - - - * * - - -

MOV eam, A 2+ 1 0 byte (eam) ← (A) - - - - - * * - - -

MOV io, A 2 1 0 byte (io) ← (A) - - - - - * * - - -

MOV @RLi+disp8, A 3 1 0 byte ((RLi)+disp8) ← (A) - - - - - * * - - -

MOV Ri, ear 2 1 0 byte (Ri) ← (ear) - - - - - * * - - -

MOV Ri, eam 2+ 1 0 byte (Ri) ← (eam) - - - - - * * - - -

MOV ear, Ri 2 1 0 byte (ear) ← (Ri) - - - - - * * - - -

MOV eam, Ri 2+ 1 0 byte (eam) ← (Ri) - - - - - * * - - -

MOV Ri, #imm8 2 1 0 byte (Ri) ← imm8 - - - - - * * - - -

MOV io, #imm8 3 1 0 byte (io) ← imm8 - - - - - - - - - -

MOV dir, #imm8 3 1 0 byte (dir) ← imm8 - - - - - - - - - -

MOV ear, #imm8 3 1 0 byte (ear) ← imm8 - - - - - * * - - -

MOV eam, #imm8 3+ 1 / 2*1 0 byte (eam) ← imm8 - - - - - - - - - -

MOV @AL, AH 2 1 0 byte ((A)) ← (AH) - - - - - * * - - -

XCH A, ear 2 1 0 byte (A) ←→ (ear) Z - - - - - - - - -

XCH A, eam 2+ 2 0 byte (A) ←→ (eam) Z - - - - - - - - -

XCH Ri, ear 2 2 0 byte (Ri) ←→ (ear) - - - - - - - - - -

XCH Ri, eam 2+ 2 0 byte (Ri) ←→ (eam) - - - - - - - - - -

*1 : 1 cycle in case of eam is Ri/@RWi/@RWi+/@RWi+RW7, 2 cycles in other case.


APPENDIX APPENDIX B Instruction Lists (351 Instructions)

Table B-2 Transfer Instructions (Word, Long Word) : 38 instructions

Mnemonic operand Len Cycles Correction value operand on odd address Operation LH AH I S T N Z V C RMW

MOVW A, dir 2 1 1 word (A) ← (dir) - * - - - * * - - -

MOVW A, addr16 3 1 1 word (A) ← (addr16) - * - - - * * - - -

MOVW A, SP 1 1 0 word (A) ← (SP) - * - - - * * - - -

MOVW A, RWi 1 1 0 word (A) ← (RWi) - * - - - * * - - -

MOVW A, ear 2 1 0 word (A) ← (ear) - * - - - * * - - -

MOVW A, eam 2+ 1 1 word (A) ← (eam) - * - - - * * - - -

MOVW A, io 2 1 1 word (A) ← (io) - * - - - * * - - -

MOVW A, @A 2 1 1 word (A) ← ((A)) - - - - - * * - - -

MOVW A, #imm16 3 1 0 word (A) ← imm16 - * - - - * * - - -

MOVW A, @RWi+disp8 2 1 1 word (A) ← ((RWi)+disp8) - * - - - * * - - -

MOVW A, @RLi+disp8 3 1 1 word (A) ← ((RLi)+disp8) - * - - - * * - - -

MOVW dir, A 2 1 1 word (dir) ← (A) - - - - - * * - - -

MOVW addr16, A 3 1 1 word (addr16) ← (A) - - - - - * * - - -

MOVW SP, A 1 1 0 word (SP) ← (A) - - - - - * * - - -

MOVW RWi, A 1 1 0 word (RWi) ← (A) - - - - - * * - - -

MOVW ear, A 2 1 0 word (ear) ← (A) - - - - - * * - - -

MOVW eam, A 2+ 1 1 word (eam) ← (A) - - - - - * * - - -

MOVW io, A 2 1 1 word (io) ← (A) - - - - - * * - - -

MOVW @RWi+disp8, A 2 1 1 word ((RWi)+disp8) ← (A) - - - - - * * - - -

MOVW @RLi+disp8, A 3 1 1 word ((RLi)+disp8) ← (A) - - - - - * * - - -

MOVW RWi, ear 2 1 0 word (RWi) ← (ear) - - - - - * * - - -

MOVW RWi, eam 2+ 1 1 word (RWi) ← (eam) - - - - - * * - - -

MOVW ear, RWi 2 1 0 word (ear) ← (RWi) - - - - - * * - - -

MOVW eam, RWi 2+ 1 1 word (eam) ← (RWi) - - - - - * * - - -

MOVW RWi, #imm16 3 1 0 word (RWi) ← imm16 - - - - - * * - - -

MOVW io, #imm16 4 1 1 word (io) ← imm16 - - - - - - - - - -

MOVW ear, #imm16 4 2 0 word (ear) ← imm16 - - - - - * * - - -

MOVW eam, #imm16 4+ 2 1 word (eam) ← imm16 - - - - - - - - - -

MOVW @AL, AH 2 1 1 word ((A)) ← (AH) - - - - - * * - - -

XCHW A, ear 2 1 0 word (A) ←→ ear - - - - - - - - - -

XCHW A, eam 2+ 2 2 word (A) ←→ eam - - - - - - - - - -

XCHW RWi, ear 2 2 0 word (RWi) ←→ ear - - - - - - - - - -

XCHW RWi, eam 2+ 2 2 word (RWi) ←→ eam - - - - - - - - - -

MOVL A, ear 2 2 0 long (A) ← (ear) - - - - - * * - - -

MOVL A, eam 2+ 2 1 long (A) ← (eam) - - - - - * * - - -

MOVL A, #imm32 5 2 0 long (A) ← imm32 - - - - - * * - - -

MOVL ear, A 2 2 0 long (ear) ← (A) - - - - - * * - - -

MOVL eam, A 2+ 3 / 2*1 1 long (eam) ← (A) - - - - - * * - - -

*1 : 3 cycle in case of eam is @RWi+, 2 cycles in other case.



Table B-3 Addition/Subtraction Instructions (Byte, Word, Long Word) : 42 instructions

Mnemonic operand Len Cycles 16FX

Correction value operand on odd address Operation LH AH I S T N Z V C RMW

ADD A, #imm8 2 1 0 byte (A) ← (A) + imm8 Z - - - - * * * * -

ADD A, dir 2 2 0 byte (A) ← (A) + (dir) Z - - - - * * * * -

ADD A, ear 2 1 0 byte (A) ← (A) + (ear) Z - - - - * * * * -

ADD A, eam 2+ 2 0 byte (A) ← (A) + (eam) Z - - - - * * * * -

ADD ear, A 2 1 0 byte (ear) ← (ear) + (A) - - - - - * * * * -

ADD eam, A 2+ 3 0 byte (eam) ← (eam) + (A) Z - - - - * * * * *

ADDC A 1 1 0 byte (A) ← (AH) + (AL) + (C) Z - - - - * * * * -

ADDC A, ear 2 1 0 byte (A) ← (A) + (ear) + (C) Z - - - - * * * * -

ADDC A, eam 2+ 2 0 byte (A) ← (A) + (eam) + (C) Z - - - - * * * * -

ADDDC A 1 2 0 byte (A) ← (AH) + (AL) + (C) : decimal Z - - - - * * * * -

SUB A, #imm8 2 1 0 byte (A) ← (A) - imm8 Z - - - - * * * * -

SUB A, dir 2 2 0 byte (A) ← (A) - (dir) Z - - - - * * * * -

SUB A, ear 2 1 0 byte (A) ← (A) - (ear) Z - - - - * * * * -

SUB A, eam 2+ 2 0 byte (A) ← (A) - (eam) Z - - - - * * * * -

SUB ear, A 2 1 0 byte (ear) ← (ear) - (A) - - - - - * * * * -

SUB eam, A 2+ 3 0 byte (eam) ← (eam) - (A) - - - - - * * * * *

SUBC A 1 1 0 byte (A) ← (AH) - (AL) - (C) Z - - - - * * * * -

SUBC A, ear 2 1 0 byte (A) ← (A) - (ear) - (C) Z - - - - * * * * -

SUBC A, eam 2+ 2 0 byte (A) ← (A) - (eam) - (C) Z - - - - * * * * -

SUBDC A 1 2 0 byte (A) ← (AH) - (AL) - (C) : decimal Z - - - - * * * * -

ADDW A 1 1 0 word (A) ← (AH) + (AL) - - - - - * * * * -

ADDW A, ear 2 1 0 word (A) ← (A) + (ear) - - - - - * * * * -

ADDW A, eam 2+ 2 1 word (A) ← (A) + (eam) - - - - - * * * * -

ADDW A, #imm16 3 1 0 word (A) ← (A) + imm16 - - - - - * * * * -

ADDW ear, A 2 1 0 word (ear) ← (ear) + (A) - - - - - * * * * -

ADDW eam, A 2+ 3 2 word (eam) ← (eam) + (A) - - - - - * * * * *

ADDCW A, ear 2 1 0 word (A) ← (A) + (ear) + (C) - - - - - * * * * -

ADDCW A, eam 2+ 2 1 word (A) ← (A) + (eam) + (C) - - - - - * * * * -

SUBW A 1 1 0 word (A) ← (AH) - (AL) - - - - - * * * * -

SUBW A, ear 2 1 0 word (A) ← (A) - (ear) - - - - - * * * * -

SUBW A, eam 2+ 2 1 word (A) ← (A) - (eam) - - - - - * * * * -

SUBW A, #imm16 3 1 0 word (A) ← (A) - imm16 - - - - - * * * * -

SUBW ear, A 2 1 0 word (ear) ← (ear) - (A) - - - - - * * * * -

SUBW eam, A 2+ 3 2 word (eam) ← (eam) - (A) - - - - - * * * * *

SUBCW A, ear 2 1 0 word (A) ← (A) - (ear) - (C) - - - - - * * * * -

SUBCW A, eam 2+ 2 1 word (A) ← (A) - (eam) - (C) - - - - - * * * * -

ADDL A, ear 2 2 0 long (A) ← (A) + (ear) - - - - - * * * * -

ADDL A, eam 2+ 3 1 long (A) ← (A) + (eam) - - - - - * * * * -

ADDL A, #imm32 5 2 0 long (A) ← (A) + imm32 - - - - - * * * * -

SUBL A, ear 2 2 0 long (A) ← (A) - (ear) - - - - - * * * * -

SUBL A, eam 2+ 3 1 long (A) ← (A) - (eam) - - - - - * * * * -

SUBL A, #imm32 5 2 0 long (A) ← (A) - imm32 - - - - - * * * * -



Table B-4 Increment/Decrement Instructions (Byte, Word, Long Word) : 12 instructions



INC ear 2 1 0 byte (ear) ← (ear) + 1 - - - - - * * * - -

INC eam 2+ 3 0 byte (eam) ← (eam) + 1 - - - - - * * * - *

DEC ear 2 1 0 byte (ear) ← (ear) - 1 - - - - - * * * - -

DEC eam 2+ 3 0 byte (eam) ← (eam) - 1 - - - - - * * * - *

INCW ear 2 1 0 word (ear) ← (ear) + 1 - - - - - * * * - -

INCW eam 2+ 3 2 word (eam) ← (eam) + 1 - - - - - * * * - *

DECW ear 2 1 0 word (ear) ← (ear) - 1 - - - - - * * * - -

DECW eam 2+ 3 2 word (eam) ← (eam) - 1 - - - - - * * * - *

INCL ear 2 2 0 long (ear) ← (ear) + 1 - - - - - * * * - -

INCL eam 2+ 4 2 long (eam) ← (eam) + 1 - - - - - * * * - *

DECL ear 2 2 0 long (ear) ← (ear) - 1 - - - - - * * * - -

DECL eam 2+ 4 2 long (eam) ← (eam) - 1 - - - - - * * * - *



Table B-5 Compare Instructions (Byte, Word, Long Word) : 11 instructions



CMP A 1 1 0 byte (AH) - (AL) - - - - - * * * * -

CMP A, ear 2 1 0 byte (A) - (ear) - - - - - * * * * -

CMP A, eam 2+ 2 0 byte (A) - (eam) - - - - - * * * * -

CMP A, #imm8 2 1 0 byte (A) - imm8 - - - - - * * * * -

CMPW A 1 1 0 word (AH) - (AL) - - - - - * * * * -

CMPW A, ear 2 1 0 word (A) - (ear) - - - - - * * * * -

CMPW A, eam 2+ 2 1 word (A) - (eam) - - - - - * * * * -

CMPW A, #imm16 3 1 0 word (A) - imm16 - - - - - * * * * -

CMPL A, ear 2 2 0 long (A) - (ear) - - - - - * * * * -

CMPL A, eam 2+ 3 1 long (A) - (eam) - - - - - * * * * -

CMPL A, #imm32 5 2 0 long (A) - imm32 - - - - - * * * * -



Table B-6 Unsigned Multiplication/Division Instructions (Word, Long Word) : 11 instructions



DIVU A 1 4 / 9*1 0 word (AH) / byte (AL)quotient → byte (AL), remainder → byte (AH)

- - - - - - - * * -

DIVU A, ear 2 4 / 9*1 0 word (A) / byte (ear) quotient → byte (A), remainder → byte (ear)

- - - - - - - * * -

DIVU A, eam 2+ 5 / 11*2 0 word (A) / byte (eam)quotient → byte (A), remainder → byte (eam)

- - - - - - - * * -

DIVUW A, ear 2 4 / 17*3 0 long (A) / word (ear)quotient → word (A), remainder → word (ear)

- - - - - - - * * -

DIVUW A, eam 2+ 5 / 19*4 2 long (A) / word (eam)quotient → word (A), remainder → word (eam)

- - - - - - - * * -

MULU A 1 2 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - -

MULU A, ear 2 2 0 byte (A) * byte (ear) → word (A) - - - - - - - - - -

MULU A, eam 2+ 3 0 byte (A) * byte (eam) → word (A) - - - - - - - - - -

MULUW A 1 4 0 word (AH) * word (AL) → long (A) - - - - - - - - - -

MULUW A, ear 2 4 0 word (A) * word (ear) → long (A) - - - - - - - - - -

MULUW A, eam 2+ 5 1 word (A) * word (eam) → long (A) - - - - - - - - - -

*1 : 4 cycles in case of overflow, 9 cycles in other case.






Table B-7 Signed Multiplication/Division Instructions (Word, Long Word) : 11 instructions



DIV A 2 5 / 11 0 word (AH) / byte (AL)quotient → byte (AL), remainder → byte (AH)

Z - - - - - - * * -

DIV A, ear 2 5 / 11 0 word (A) / byte (ear)quotient → byte (A), remainder → byte (ear)

Z - - - - - - * * -

DIV A, eam 2+ 6 / 13 0 word (A) / byte (eam)quotient → byte (A), remainder → byte (eam)

Z - - - - - - * * -

DIVW A, ear 2 5 / 19 0 long (A) / word (ear)quotient → word (A), remainder → word (ear)

- - - - - - - * * -

DIVW A, eam 2+ 6 / 21 2 long (A) / word (eam)quotient → word (A), remainder → word (eam)

- - - - - - - * * -

MUL A 2 4 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - -

MUL A, ear 2 4 0 byte (A) * byte (ear) → word (A) - - - - - - - - - -

MUL A, eam 2+ 5 0 byte (A) * byte (eam) → word (A) - - - - - - - - - -

MULW A 2 6 0 word (AH) * word (AL) → long (A) - - - - - - - - - -

MULW A, ear 2 6 0 word (A) * word (ear) → long (A) - - - - - - - - - -

MULW A, eam 2+ 7 1 word (A) * word (eam) → long (A) - - - - - - - - - -







Table B-8 Logic Instructions (Byte, Word, Long Word) : 45 instructions



AND A, #imm8 2 1 0 byte (A) ← (A) and imm8 - - - - - * * R - -

AND A, ear 2 1 0 byte (A) ← (A) and (ear) - - - - - * * R - -

AND A, eam 2+ 2 0 byte (A) ← (A) and (eam) - - - - - * * R - -

AND ear, A 2 1 0 byte (ear) ← (ear) and (A) - - - - - * * R - -

AND eam, A 2+ 3 0 byte (eam) ← (eam) and (A) - - - - - * * R - *

OR A, #imm8 2 1 0 byte (A) ← (A) or imm8 - - - - - * * R - -

OR A, ear 2 1 0 byte (A) ← (A) or (ear) - - - - - * * R - -

OR A, eam 2+ 2 0 byte (A) ← (A) or (eam) - - - - - * * R - -

OR ear, A 2 1 0 byte (ear) ← (ear) or (A) - - - - - * * R - -

OR eam, A 2+ 3 0 byte (eam) ← (eam) or (A) - - - - - * * R - *

XOR A, #imm8 2 1 0 byte (A) ← (A) xor imm8 - - - - - * * R - -

XOR A, ear 2 1 0 byte (A) ← (A) xor (ear) - - - - - * * R - -

XOR A, eam 2+ 2 0 byte (A) ← (A) xor (eam) - - - - - * * R - -

XOR ear, A 2 1 0 byte (ear) ← (ear) xor (A) - - - - - * * R - -

XOR eam, A 2+ 3 0 byte (eam) ← (eam) xor (A) - - - - - * * R - *

NOT A 1 1 0 byte (A) ← not (A) - - - - - * * R - -

NOT ear 2 1 0 byte (ear) ← not (ear) - - - - - * * R - -

NOT eam 2+ 3 0 byte (eam) ← not (eam) - - - - - * * R - *

ANDW A 1 1 0 word (A) ← (AH) and (A) - - - - - * * R - -

ANDW A, #imm16 3 1 0 word (A) ← (A) and imm16 - - - - - * * R - -

ANDW A, ear 2 1 0 word (A) ← (A) and (ear) - - - - - * * R - -

ANDW A, eam 2+ 2 1 word (A) ← (A) and (eam) - - - - - * * R - -

ANDW ear, A 2 1 0 word (ear) ← (ear) and (A) - - - - - * * R - -

ANDW eam, A 2+ 3 2 word (eam) ← (eam) and (A) - - - - - * * R - *

ORW A 1 1 0 word (A) ← (AH) or (A) - - - - - * * R - -

ORW A, #imm16 3 1 0 word (A) ← (A) or imm16 - - - - - * * R - -

ORW A, ear 2 1 0 word (A) ← (A) or (ear) - - - - - * * R - -

ORW A, eam 2+ 2 1 word (A) ← (A) or (eam) - - - - - * * R - -

ORW ear, A 2 1 0 word (ear) ← (ear) or (A) - - - - - * * R - -

ORW eam, A 2+ 3 2 word (eam) ← (eam) or (A) - - - - - * * R - *

XORW A 1 1 0 word (A) ← (AH) xor (A) - - - - - * * R - -

XORW A, #imm16 3 1 0 word (A) ← (A) xor imm16 - - - - - * * R - -

XORW A, ear 2 1 0 word (A) ← (A) xor (ear) - - - - - * * R - -

XORW A, eam 2+ 2 1 word (A) ← (A) xor (eam) - - - - - * * R - -

XORW ear, A 2 1 0 word (ear) ← (ear) xor (A) - - - - - * * R - -

XORW eam, A 2+ 3 2 word (eam) ← (eam) xor (A) - - - - - * * R - *

NOTW A 1 1 0 word (A) ← not (A) - - - - - * * R - -

NOTW ear 2 1 0 word (ear) ← not (ear) - - - - - * * R - -

NOTW eam 2+ 3 2 word (eam) ← not (eam) - - - - - * * R - *

ANDL A, ear 2 2 0 long (A) ← (A) and (ear) - - - - - * * R - -

ANDL A, eam 2+ 3 1 long (A) ← (A) and (eam) - - - - - * * R - -

ORL A, ear 2 2 0 long (A) ← (A) or (ear) - - - - - * * R - -

ORL A, eam 2+ 3 1 long (A) ← (A) or (eam) - - - - - * * R - -

XORL A, ear 2 2 0 long (A) ← (A) xor (ear) - - - - - * * R - -

XORL A, eam 2+ 3 1 long (A) ← (A) xor (eam) - - - - - * * R - -



Table B-9 Sign Inversion Instructions (Byte, Word) : 6 instructions



NEG A 1 1 0 byte (A) ← 0 - (A) X - - - - * * * * -

NEG ear 2 1 0 byte (ear) ← 0 - (ear) - - - - - * * * * -

NEG eam 2+ 3 0 byte (eam) ← 0 - (eam) - - - - - * * * * *

NEGW A 1 1 0 word (A) ← 0 - (A) - - - - - * * * * -

NEGW ear 2 1 0 word (ear) ← 0 - (ear) - - - - - * * * * -

NEGW eam 2+ 3 2 word (eam) ← 0 - (eam) - - - - - * * * * *



Table B-10 Shift/Normalization Instructions (Byte, Word, Long Word) : 19 instructions


Correction value operand

on odd addressOperation LH AH I S T N Z V C RMW

RORC A 2 1 0 byte (A) ← Right rotation of (A) with carry - - - - - * * - * -

RORC ear 2 1 0 byte (ear) ← Right rotation of (ear) with carry - - - - - * * - * -

RORC eam 2+ 3 0 byte (eam) ← Right rotation of (eam) with carry - - - - - * * - * *

ROLC A 2 1 0 byte (A) ← Left rotation of (A) with carry - - - - - * * - * -

ROLC ear 2 1 0 byte (ear) ← Right rotation of (ear) with carry - - - - - * * - * -

ROLC eam 2+ 3 0 byte (eam) ← Right rotation of (eam) with carry - - - - - * * - * *

ASR A, R0 2 1 0 byte (A) ← Arithmetic right barrel shift of (A) , (R0) bits - - - - * * * - * -

LSR A, R0 2 1 0 byte (A) ← Logical right barrel shift of (A) , (R0) bits - - - - * * * - * -

LSL A, R0 2 1 0 byte (A) ← Logical left barrel shift of (A) , (R0) bits - - - - - * * - * -

ASRW A 1 1 0 word (A) ← Arithmetic right shift of (A) , 1 bit - - - - * * * - * -

LSRW/SHRW A 1 1 0 word (A) ← Logical right shift of (A) , 1 bits - - - - * R * - * -

LSLW/SHLW A 1 1 0 word (A) ← Logical left shift of (A) , 1 bits - - - - - * * - * -

ASRW A, R0 2 1 0 word (A) ← Arithmetic right barrel shift of (A) , (R0) bits - - - - * * * - * -

LSRW A, R0 2 1 0 word (A) ← Logical right barrel shift of (A) , (R0) bits - - - - * * * - * -

LSLW A, R0 2 1 0 word (A) ← Logical left barrel shift of (A) , (R0) bits - - - - - * * - * -

ASRL A, R0 2 1 0 long (A) ← Arithmetic right barrel shift of (A) , (R0) bits - - - - * * * - * -

LSRL A, R0 2 1 0 long (A) ← Logical right barrel shift of (A) , (R0) bits - - - - * * * - * -

LSLL A, R0 2 1 0 long (A) ← Logical left barrel shift of (A) , (R0) bits - - - - - * * - * -

NRML A, R0 2 1 0 long (A) ← Shift left (A) until the MSB is "1"byte (R0) ← Shift count (the first "1" bit position)

- - - - - - * - - -



Table B-11 Branch Instructions 1 : 31 instructions



BZ/BEQ rel 2 2 0 Branch on (Z) = 1 - - - - - - - - - -

BNZ/BNE rel 2 2 0 Branch on (Z) = 0 - - - - - - - - - -

BC/BLO rel 2 2 0 Branch on (C) = 1 - - - - - - - - - -

BNC/BHS rel 2 2 0 Branch on (C) = 0 - - - - - - - - - -

BN rel 2 2 0 Branch on (N) = 1 - - - - - - - - - -

BP rel 2 2 0 Branch on (N) = 0 - - - - - - - - - -

BV rel 2 2 0 Branch on (V) = 1 - - - - - - - - - -

BNV rel 2 2 0 Branch on (V) = 0 - - - - - - - - - -

BT rel 2 2 0 Branch on (T) = 1 - - - - - - - - - -

BNT rel 2 2 0 Branch on (T) = 0 - - - - - - - - - -

BLT rel 2 2 0 Branch on (V) xor (N) = 1 - - - - - - - - - -

BGE rel 2 2 0 Branch on (V) xor (N) = 0 - - - - - - - - - -

BLE rel 2 2 0 Branch on ((V) xor (N)) or (Z) = 1 - - - - - - - - - -

BGT rel 2 2 0 Branch on ((V) xor (N)) or (Z) = 0 - - - - - - - - - -

BLS rel 2 2 0 Branch on (C) or (Z) = 1 - - - - - - - - - -

BHI rel 2 2 0 Branch on (C) or (Z) = 0 - - - - - - - - - -

BRA rel 2 2 0 Branch always (Unconditional branch) - - - - - - - - - -

JMP @A 1 2 0 word (PC) ← (A) - - - - - - - - - -

JMP addr16 3 2 0 word (PC) ← addr16 - - - - - - - - - -

JMP @ear 2 2 0 word (PC) ← (ear) - - - - - - - - - -

JMP @eam 2+ 4 1 word (PC) ← (eam) - - - - - - - - - -

JMPP @ear 2 3 0 word (PC) ← (ear), (PCB) ← (ear+2) - - - - - - - - - -

JMPP @eam 2+ 5 1 word (PC) ← (eam), (PCB) ← (eam+2) - - - - - - - - - -

JMPP addr24 4 2 0 word (PC) ← ad24 0-15, (PCB) ← ad24 16-23 - - - - - - - - - -

CALL @ear 2 3 1 word (SP) ← (SP)-2, ((SP)) ← (PC)+2word (PC) ← (ear)

- - - - - - - - - -

CALL @eam 2+ 5 1+1*a word (SP) ← (SP)-2, ((SP)) ← (PC)+ 2+word (PC) ← (eam)

- - - - - - - - - -

CALL addr16 3 3 1 word (SP) ← (SP)-2, ((SP)) ← (PC)+3word (PC) ← addr16

- - - - - - - - - -

CALLV #vct4 1 5 1 word (SP) ← (SP)-2, ((SP)) ← (PC)+1word (PC) ← (vecter_address)

- - - - - - - - - -

CALLP @ear 2 5 2 word (SP) ← (SP)-2, ((SP)) ← (PCB)word (SP) ← (SP)-2, ((SP)) ← (PC)+2word (PC) ← (ear), (PCB) ← (ear+2)

- - - - - - - - - -

CALLP @eam 2+ 7 2+1*b word (SP) ← (SP)-2, ((SP)) ← (PCB)word (SP) ← (SP)-2, ((SP)) ← (PC)+ 2+word (PC) ← (eam), (PCB) ← (eam+2)

- - - - - - - - - -

CALLP addr24 4 4 2 word (SP) ← (SP)-2, ((SP)) ← (PCB)word (SP) ← (SP)-2, ((SP)) ← (PC)+4word (PC) ← ad24 0-15, (PCB) ← ad24 16-23

- - - - - - - - - -

*a : compensation value: +1 for odd stack, +1 for odd operand address

*b : compensation value +2 for odd stack, +1 for odd operand address.



Table B-12 Branch Instructions 2 : 19 instructions


Correction value

operand on odd address

Operation LH AH I S T N Z V C RMW

CBNE A, #imm8, rel 3 5 0 Branch on byte (A) not equal to imm8 - - - - - * * * * -

CWBNE A, #imm16, rel 4 5 0 Branch on word (A) not equal to imm16 - - - - - * * * * -

CBNE ear, #imm8, rel 4 4 0 Branch on byte (ear) not equal to imm8 - - - - - * * * * -

CBNE eam, #imm8, rel 4+ 5 0 Branch on byte (eam) not equal to imm8 - - - - - * * * * -

CWBNE ear, #imm16, rel 5 5 0 Branch on word (ear) not equal to imm16 - - - - - * * * * -

CWBNE eam, #imm16, rel 5+ 6 1 Branch on word (eam) not equal to imm16 - - - - - * * * * -

DBNZ ear, rel 3 5 0 byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0 - - - - - * * * - -

DBNZ eam, rel 3+ 6 0 byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0 - - - - - * * * - *

DWBNZ ear, rel 3 5 0 word (ear) ← (ear) - 1, Branch on (ear) not equal to 0 - - - - - * * * - -

DWBNZ eam, rel 3+ 6 2 word (eam) ← (eam) - 1, Branch on (eam) not equal to 0 - - - - - * * * - *

INT #vct8 2 11 6 Software interrupt - - R S - - - - - -

INT addr16 3 8 6 Software interrupt - - R S - - - - - -

INTP addr24 4 8 6 Software interrupt - - R S - - - - - -

INT9 1 11 6 Software interrupt - - R S - - - - - -

INTE 1 12 6 Software interrupt for break point (reserved for emulator) - - R S - - - - - -

RETI 1 22 / 6*1 1 Return from interrupt - - * * * * * * * -

LINK #imm8 2 2 1 word (SP) ← (SP) - 2, ((SP)) ← (RW3), word (RW3) ← (SP), (SP) ← (SP) - imm8

- - - - - - - - - -

UNLINK 1 1 1 word (SP) ← (RW3), (RW3) ← ((SP)), word (SP) ← (SP) + 2

- - - - - - - - - -

RET 1 4 1 word (PC) ← ((SP)), (SP) ← (SP) + 2 - - - - - - - - - -

RETP 1 5 1 word (PC) ← ((SP)), (SP) ← (SP) + 2, byte (PCB) ← ((SP)), (SP) ← (SP) + 2

- - - - - - - - - -

*1 : 6 cycles in case of RP stable, 22 cycles in other case.



Table B-13 Other Control Instructions (Byte, Word, Long Word) : 28 instructions


Correction value operand on odd

addressOperation LH AH I S T N Z V C RMW

PUSHW A 1 1 1 word (SP) ← (SP) - 2, ((SP)) ← (A) - - - - - - - - - -

PUSHW AH 1 1 1 word (SP) ← (SP) - 2, ((SP)) ← (AH) - - - - - - - - - -

PUSHW PS 1 1 1 word (SP) ← (SP) - 2, ((SP)) ← (PS) - - - - - - - - - -

PUSHW rlst 2 N*1 N*a multi word (SP) ← (SP) - 2n, ((SP)) ← (rlst) - - - - - - - - - -

POPW A 1 1 1 word (A) ← ((SP)), (SP) ← (SP) + 2 - * - - - - - - - -

POPW AH 1 1 1 word (AH) ← ((SP)), (SP) ← (SP) + 2 - - - - - - - - - -

POPW PS 1 18 / 4*2 1 word (PS) ← ((SP)), (SP) ← (SP) + 2 - - * * * * * * * -

POPW rlst 2 N*1 N*a multi word (rlst) ← ((SP)), (SP) ← (SP) + 2n - - - - - - - - - -

JCTX @A 1 22 / 6*3 1 Context switch - - * * * * * * * -

AND CCR, #imm8 2 1 0 byte (CCR) ← (CCR) and imm8 - - * * * * * * * -

OR CCR, #imm8 2 1 0 byte (CCR) ← (CCR) or imm8 - - * * * * * * * -

MOV RP, #imm8 2 19 / 4*2 0 byte (RP) ← imm8 - - - - - - - - - -

MOV ILM, #imm8 2 1 0 byte (ILM) ← imm8 - - - - - - - - - -

MOVEA RWi, ear 2 1 0 word (RWi) ← ear - - - - - - - - - -

MOVEA RWi, eam 2+ 1 0 word (RWi) ← eam - - - - - - - - - -

MOVEA A, ear 2 1 0 word (A) ← ear - * - - - - - - - -

MOVEA A, eam 2+ 1 0 word (A) ← eam - * - - - - - - - -

ADDSP #imm8 2 1 0 word (SP) ← (SP) + ext(imm8) - - - - - - - - - -

ADDSP #imm16 3 1 0 word (SP) ← (SP) + imm16 - - - - - - - - - -

MOV A, brg1 2 1 0 byte (A) ← (brg1) Z * - - - * * - - -

MOV brg2, A 2 1 0 byte (brg2) ← (A) - - - - - * * - - -

NOP 1 1 0 No operation - - - - - - - - - -

ADB 1 1 0 Prefix code for AD space access - - - - - - - - - -

DTB 1 1 0 Prefix code for DT space access - - - - - - - - - -

PCB 1 1 0 Prefix code for PC space access - - - - - - - - - -

SPB 1 1 0 Prefix code for SP space access - - - - - - - - - -

NCC 1 1 0 Prefix code for flags no change - - - - - - - - - -

CMR 1 1 0 Prefix code for common register bank - - - - - - - - - -

*1 : N depends on number of registers to be saved/restored, minimum 1 cycle

*2 : 4 cycles in case of RP stable, 18 cycles in other case

*3 : 6 cycles in case of RP stable, 22 cycles in other case

*a : N depends on number of registers to be saved



Table B-14 Bit Operation Instructions : 28 instructions


Correction value

operand on odd address

Operation LH AH I S T N Z V C RMW

MOVB A, dir:bp 3 1 0 byte (A) ← (dir:bp) b Z * - - - * * - - -

MOVB A, addr16:bp 4 1 0 byte (A) ← (addr16:bp) b Z * - - - * * - - -

MOVB A, io:bp 3 1 0 byte (A) ← (io:bp) b Z * - - - * * - - -

MOVB dir:bp, A 3 3 0 bit (dir:bp) b ← (A) - - - - - * * - - *

MOVB addr16:bp 4 3 0 bit (addr16:bp) b ← (A) - - - - - * * - - *

MOVB io:bp, A 3 3 0 bit (io:bp) b ← (A) - - - - - * * - - *

SETB dir:bp 3 3 0 bit (dir:bp) b ← 1 - - - - - - - - - *

SETB addr16:bp 4 3 0 bit (addr16:bp) b ← 1 - - - - - - - - - *

SETB io:bp 3 3 0 bit (io:bp) b ← 1 - - - - - - - - - *

CLRB dir:bp 3 3 0 bit (dir:bp) b ← 0 - - - - - - - - - *

CLRB addr16:bp 4 3 0 bit (addr16:bp) b ← 0 - - - - - - - - - *

CLRB io:bp 3 3 0 bit (io:bp) b ← 0 - - - - - - - - - *

BBC dir:bp, rel 4 5 0 Branch on (dir:bp) b = 0 - - - - - - * - - -

BBC addr16:bp, rel 5 5 0 Branch on (addr16:bp) b = 0 - - - - - - * - - -

BBC io:bp, rel 4 5 0 Branch on (io:bp) b = 0 - - - - - - * - - -

BBS dir:bp, rel 4 5 0 Branch on (dir:bp) b = 1 - - - - - - * - - -

BBS addr16:bp, rel 5 5 0 Branch on (addr16:bp) b = 1 - - - - - - * - - -

BBS io:bp, rel 4 5 0 Branch on (io:bp) b = 1 - - - - - - * - - -

SBBS addr16:bp, rel 5 5 0 Branch on (addr16:bp) b = 1, bit (addr16:bp) b ← 1 - - - - - - * - - *

WBTS io:bp 3 undefined*1 0 Wait until (io:bp) b = 1 - - - - - - - - - -

WBTC io:bp 3 undefined*2 0 Wait until (io:bp) b = 0 - - - - - - - - - -

*1 : 4 cycles if the bit is set already. In other case, the cycle is undefined.

*2 : 4 cycles if the bit is cleared already. In other case, the cycle is undefined.



Table B-15 Accumulator Instructions (Byte, Word) : 6 instructions

Mnemonic operand Len Cycles 16FX Correction value operand on odd address Operation LH AH I S T N Z V C RMW

SWAP 1 1 0 byte (A) 0-7 ←→ (A) 8-15 - - - - - - - - - -

SWAPW 1 1 0 word (AH) ←→ (AL) - * - - - - - - - -

EXT 1 1 0 Byte sign extension X - - - - * * - - -

EXTW 1 1 0 Word sign extension - X - - - * * - - -

ZEXT 1 1 0 Byte zero extension Z - - - - R * - - -

ZEXTW 1 1 0 Word zero extension - Z - - - R * - - -



Table B-16 String Instructions : 10 instructions


Correction value operand

on odd addressOperation LH AH I S T N Z V C RMW

MOVS/MOVSI brg3, brg3 2 RW0*2 1 byte transfer @AH+ ← @AL+, (RW0) times - - - - - - - - - -

MOVSD brg3, brg3 2 2*RW0 0 byte transfer @AH- ← @AL-, (RW0) times - - - - - - - - - -

SCEQ/SCEQI brg3 2 2+2*N*3 0 byte search @AH+ = AL, (RW0) times or till match - - - - - * * * * -

SCEQD brg3 2 2+2*N*3 0 byte search @AH- = AL, (RW0) times or till match - - - - - * * * * -

FILS/FILSI brg3 2 RW0/2*4 1 byte fill @AH+ ← AL, (RW0) times - - - - - * * - - -

MOVSW/MOVSWI brg3, brg3 2 2*RW0 1 word transfer @AH+ ← @AL+, (RW0) times - - - - - - - - - -

MOVSWD brg3, brg3 2 2*RW0 (1+1)*RW0*a word transfer @AH- ← @AL-, (RW0) times - - - - - - - - - -

SCWEQ/SCWEQI brg3 2 2+2*N*3 N*b word search @AH+ = AL, (RW0) times or till match - - - - - * * * * -

SCWEQD brg3 2 2+2*N*3 N*b word search @AH- = AL, (RW0) times or till match - - - - - * * * * -

FILSW/FILSWI brg3 2 RW0 1 word fill @AH+ ← AL, (RW0) times - - - - - * * - - -

*1 : All String operations need 1 cycle if RW0=0.

*2 : 2*RW0 cycles if overlapping ranges, optimization can not be done.

*3 : 1 cycle if RW0=0, 3 cycles if RW0=1, N is number of items compared till match occures.

*4 : The number of cycle is round up in case of odd number of bytes.

*a : Correction is 2*RW0 if both src and dest address is odd, 1*RW0 if only src or dest is odd.

*b : N is number of items compared till match occures.


APPENDIXAPPENDIX C Instruction Maps

APPENDIX C Instruction Maps

This appendix describes F2MC-16FX CPU instruction maps.

C.1 Structure of the Instruction Map

C.2 Basic Page Map

C.3 Bit Operation Instruction Map

C.4 Character String Operation Instruction Map

C.5 2-byte Instruction Map

C.6 ea-type Instruction Map

C.7 MOVEA RWi, ea Instruction Map

C.8 MOV Ri, ea Instruction Map

C.9 MOVW RWi, ea Instruction Map

C.10 MOV ea, Ri Instruction Map

C.11 MOVW ea, RWi Instruction Map

C.12 XCH Ri, ea Instruction Map

C.13 XCHW RWi, ea Instruction Map


APPENDIX APPENDIX C Instruction Maps

C.1 Structure of the Instruction Map

The instruction code of the F2MC-16FX CPU consists of one- and two-byte instructions. The instruction map consists of more than one page that can be used for one- and two- byte instructions.

■ Structure of the Instruction MapFigure C.1-1 shows the structure of the instruction map.

Figure C.1-1 Structure of the F2MC-16FX CPU Instruction Map

The instruction code is described on the basic page map for one-byte instructions (such as the

NOP instruction). For two-byte instructions (such as the MOVS instruction), see the basic page

map to find the name of the map that describes the second byte of the instruction code to be

referenced next.

Figure C.1-2 shows the relationship between actual instruction codes and instruction maps.

Basic page map : First byte

Bit operation instruction

Character string operation instruction

2-byte instructions

ea-type instruction × 9 : Second byte



Figure C.1-2 Relationship Between Actual Instruction Codes and Instruction Maps

*: Extended page map is a generic name for bit operation instruction, character stringoperation instruction, 2-byte instruction, and ea-type instruction. More than one extendedpage map exists for each type of instruction.

May not exist for some instruction.

The length varies depending on instructions.

Instruction code First byte Second byte Operand Operand . . .

[Basic page map]

XY

+Z

[Extended page map]*

UV

+W



C.2 Basic Page Map

Table C.2-1 shows the basic page map.



Table C.2-1 Basic Page Map

Note: For the information about ea-type instruction from (1) to (9), see Table C.6-1 ".

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

NO

PC

MR

AD

DA

, dir

AD

DA

, #8

MO

VA

, dir

MO

VA

, io

BR

Are

lea

inst

ruct

ion

1M

OV

A, R

iMO

VR

i, A

MO

VR

i, #8

MO

VX

A, R

iMO

VX

A,

@R

Wi+

d8M

OV

NA

, #4

CA

LLV #v

ct4

BZ

/BE

Qre

l

+1

INT

9N

CC

SU

BA

, dir

SU

BA

, #8

MO

Vdi

r, A

MO

Vio

, AJM

P@

Aea

in

stru

ctio

n 2

BN

Z/B

NE re

l

+2

AD

DD

CA

SU

BD

CA

AD

DC

AS

UB

CA

MO

VA

, #8

MO

VA

, add

r16

JMP

addr

16ea

in

stru

ctio

n 3

BC

/BL0

rel

+3

NE

GA

JCT

X@

AC

MP

AC

MP

A, #

8M

OV

XA

, #8

MO

Vad

dr16

, AJM

PP ad

dr24

ea

inst

ruct

ion

4B

NC

/BH

S rel

+4

PC

BE

XT

AN

D CC

R, #

8A

ND

A, #

8M

OV

dir,

#8

MO

Vio

, #8

CA

LLad

dr16

ea

inst

ruct

ion

5B

Nre

l

+5

DT

BZ

EX

TO

RC

CR

, #8

OR

A, #

8M

OV

XA

, dir

MO

VX

A, i

oC

ALL

P addr

24ea

in

stru

ctio

n 6

BP

rel

+6

AD

BS

WA

PD

IVU

AX

OR

A, #

8M

OV

W A, S

PM

OV

W io, #

16R

ET

Pea

in

stru

ctio

n 7

BV

rel

+7

SP

BA

DD

SP

#8M

ULU

AN

OT

AM

OV

W SP

, AM

OV

XA

, add

r16

RE

Tea

in

stru

ctio

n 8

BN

Vre

l

+8

LIN

K#i

mm

8A

DD

L A, #

32A

DD

WA

AD

DW A

, #16

MO

VW

A, d

irM

OV

WA

, io

INT

#vct

8ea

in

stru

ctio

n 9

MO

VW A

, RW

iMO

VW R

Wi,

AM

OV

WR

Wi,

#16

MO

VW

A,

@R

Wi+

d8M

OV

W @

RW

i+d8

, AB

Tre

l

+9

UN

LIN

KS

UB

L A, #

32S

UB

WA

SU

BW A

, #16

MO

VW

dir,

AM

OV

Wio

, AIN

Tad

dr16

MO

VE

AR

Wi,

eaB

NT

rel

+A

MO

V RP

, #8

MO

V ILM

, #8

CB

NE

A,

#8, r

elC

WB

NE

A,

#16,

rel

MO

VW A

, #16

MO

VW

A,a

ddr1

6IN

TP ad

dr24

MO

VR

i, ea

BLT

rel

+B

NE

GW

AC

MP

L A, #

32C

MP

WA

CM

PW A

, #16

MO

VL A

, #32

MO

VW

addr

16, A

RE

TI

MO

VW

RW

i, ea

BG

Ere

l

+C

LSLW

AE

XT

WA

ND

WA

AN

DW A

, #16

PU

SH

WA

PO

PW

AB

it op

erat

ion

inst

ruct

ion

MO

Vea

, Ri

BLE

rel

+D

INT

EZ

EX

TW

OR

WA

OR

WA

, #16

PU

SH

WA

HP

OP

WA

HM

OV

Wea

, RW

iB

GT

rel

+E

AS

RW

AS

WA

PW

XO

RW

AX

OR

W A, #

16P

US

HW

PS

PO

PW

PS

Cha

ract

er s

tring

op

erat

ion

inst

ruct

ion

XC

HR

i, ea

BLS

rel

+F

LSR

WA

AD

DS

P#1

6M

ULU

WA

NO

TW

AP

US

HW

rlstP

OP

Wrls

t2-by

te

inst

ruct

ion

XC

HW RW

i, ea

BH

Ire

l



C.3 Bit Operation Instruction Map

Table C.3-1 shows the bit operation instruction map.



Table C.3-1 Bit Operation Instruction Map (First Byte = 6CH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

VB

A, i

o:bp

MO

VB

io:b

p, A

CLR

Bio

:bp

SE

TB

io:b

pB

BC io

;bp,

rel

BB

S io:b

p, r

elW

BT

S io:b

pW

BT

C io:b

p

+1

+2

+3

+4

+5

+6

+7

+8

MO

VB

A, d

ir:bp

MO

VB

A,

addr

16:b

pM

OV

Bdi

r:bp

, AM

OV

Bad

dr16

:bp,

AC

LRB di

r:bp

CLR

Bad

dr16

:bp

SE

TB di

r:bp

SE

TB

addr

16:b

pB

BC dir:

bp, r

elB

BC

addr

16:b

p,re

lB

BS dir:

bp, r

elB

BS

addr

16:b

p,re

lS

BB

Sad

dr16

:bp

+9

+A

+B

+C

+D +E +F



C.4 Character String Operation Instruction Map

Table C.4-1 shows the character string operation instruction map.



Table C.4-1 Character String Operation Instruction Map (First Byte = 6EH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

VS

IP

CB

, PC

BM

OV

SD

MO

VS

WI

MO

VS

WD

SC

EQ

I PC

BS

CE

QD P

CB

SC

WE

QI

PC

BS

CW

EQ

DP

CB

FIL

SI

PC

BF

ILS

WI PC

B

+1

PC

B, D

TB

DT

BD

TB

DT

BD

TB

DT

BD

TB

+2

PC

B, A

DB

AD

BA

DB

AD

BA

DB

AD

BA

DB

+3

PC

B, S

PB

SP

BS

PB

SP

BS

PB

SP

BS

PB

+4

DT

B, P

CB

+5

DT

B, D

TB

+6

DT

B, A

DB

+7

DT

B, S

PB

+8

AD

B, P

CB

+9

AD

B, D

TB

+A

AD

B, A

DB

+B

AD

B, S

PB

+C

SP

B, P

CB

+D

SP

B, D

TB

+E

SP

B, A

DB

+F

SP

B, S

PB



C.5 2-byte Instruction Map

Table C.5-1 shows the 2-byte instruction map.



Table C.5-1 2-byte Instruction Map (First Byte = 6FH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

V A, D

TB

MO

V DT

B, A

MO

VX

A, @

RL0

+d8

MO

V@

RL0

+d8,

AM

OV

A, @

RL0

+d8

+1

MO

V A, A

DB

MO

V AD

B, A

+2

MO

V A, S

SB

MO

V SS

B, A

MO

VX

A, @

RL1

+d8

MO

V@

RL1

+d8,

AM

OV

A, @

RL1

+d8

+3

MO

V A, U

SB

MO

V US

B, A

+4

MO

V A, D

PR

MO

V DP

R, A

MO

VX

A, @

RL2

+d8

MO

V@

RL2

+d8,

AM

OV

A, @

RL2

+d8

+5

MO

V A, @

AM

OV

@A

L, A

H

+6

MO

V A, P

CB

MO

V A, @

AM

OV

XA

, @R

L3+d

8M

OV

@R

L3+d

8, A

MO

VA,

@R

L3+d

8

+7

RO

LCA

RO

RC

A

+8

MO

VW

@R

L0+d

8, A

MO

VW

A, @

RL0

+d8

MU

LA

+9

MU

LWA

+A

MO

VW

@R

L1+d

8, A

MO

VW

A, @

RL1

+d8

DIV

A

+B

+C

LSLW

A, R

0LS

LLA

, R0

LSL

A, R

0M

OV

W@

RL2

+d8,

AM

OV

WA,

@R

L2+d

8

+D

MO

VW A, @

AM

OV

W@

AL,

AH

NR

ML A

, R0

+E

AS

RW A

, R0

AS

RL A

, R0

AS

RA

, R0

MO

VW

@R

L3+d

8, A

MO

VW

A, @

RL3

+d8

+F

LSR

W A, R

0LS

RL A

, R0

LSR

A, R

0



C.6 ea-type Instruction Map

ea-type instruction maps (first byte = 70H to first byte = 78H) are shown in the

following nine tables:• Table C.6-1 for ea-type instruction (1) (first byte = 70H)

• Table C.6-2 for ea-type instruction (2) (first byte = 71H)










Table C.6-1 ea-byte Instruction (1) (First Byte = 70H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

CW

BN

E ↓

CW

BN

E ↓

CB

NE

↓C

BN

E ↓

+0

AD

DL A, R

L0A

DD

L A

,@

RW

0+d8

SU

BL A, R

L0S

UB

L A

,@

RW

0+d8

RW

0,#1

6, r

el@

RW

0+d8

#16,

rel

CM

PL A, R

L0C

MP

L A

,@

RW

0+d8

AN

DL A, R

L0A

ND

L A

,@

RW

0+d8

OR

L A, R

L0O

RL

A,

@R

W0+

d8X

OR

L A, R

L0X

OR

L A

,@

RW

0+d8

R0,

#8, r

el@

RW

0+d8

,#8

, rel

+1

AD

DL A, R

L0A

DD

L A

,@

RW

1+d8

SU

BL A, R

L0S

UB

L A

,@

RW

1+d8

RW

1,#1

6, r

el@

RW

1+d8

#16,

rel

CM

PL A, R

L0C

MP

L A

,@

RW

1+d8

AN

DL A, R

L0A

ND

L A

,@

RW

1+d8

OR

L A, R

L0O

RL

A,

@R

W1+

d8X

OR

L A, R

L0X

OR

L A

,@

RW

1+d8

R1,

#8, r

el@

RW

1+d8

,#8

, rel

+2

AD

DL A, R

L1A

DD

L A

,@

RW

2+d8

SU

BL A, R

L1S

UB

L A

,@

RW

2+d8

RW

2,#1

6, r

el@

RW

2+d8

#16,

rel

CM

PL A, R

L1C

MP

L A

,@

RW

2+d8

AN

DL A, R

L1A

ND

L A

,@

RW

2+d8

OR

L A, R

L1O

RL

A,

@R

W2+

d8X

OR

L A, R

L1X

OR

L A

,@

RW

2+d8

R2,

#8, r

el@

RW

2+d8

,#8

, rel

+3

AD

DL A, R

L1A

DD

L A

,@

RW

3+d8

SU

BL A, R

L1S

UB

L A

,@

RW

3+d8

RW

3,#1

6, r

el@

RW

3+d8

#16,

rel

CM

PL A, R

L1C

MP

L A

,@

RW

3+d8

AN

DL A, R

L1A

ND

L A

,@

RW

3+d8

OR

L A, R

L1O

RL

A,

@R

W3+

d8X

OR

L A, R

L1X

OR

L A

,@

RW

3+d8

R3,

#8, r

el@

RW

3+d8

,#8

, rel

+4

AD

DL A, R

L2A

DD

L A

,@

RW

4+d8

SU

BL A, R

L2S

UB

L A

,@

RW

4+d8

RW

4,#1

6, r

el@

RW

4+d8

#16,

rel

CM

PL A, R

L2C

MP

L A

,@

RW

4+d8

AN

DL A, R

L2A

ND

L A

,@

RW

4+d8

OR

L A, R

L2O

RL

A,

@R

W4+

d8X

OR

L A, R

L2X

OR

L A

,@

RW

4+d8

R4,

#8, r

el@

RW

4+d8

,#8

, rel

+5

AD

DL A, R

L2A

DD

L A

,@

RW

5+d8

SU

BL A, R

L2S

UB

L A

,@

RW

5+d8

RW

5,#1

6, r

el@

RW

5+d8

#16,

rel

CM

PL A, R

L2C

MP

L A

,@

RW

5+d8

AN

DL A, R

L2A

ND

L A

,@

RW

5+d8

OR

L A, R

L2O

RL

A,

@R

W5+

d8X

OR

L A, R

L2X

OR

L A

,@

RW

5+d8

R5,

#8, r

el@

RW

5+d8

,#8

, rel

+6

AD

DL A, R

L3A

DD

L A

,@

RW

6+d8

SU

BL A, R

L3S

UB

L A

,@

RW

6+d8

RW

6,#1

6, r

el@

RW

6+d8

#16,

rel

CM

PL A, R

L3C

MP

L A

,@

RW

6+d8

AN

DL A, R

L3A

ND

L A

,@

RW

6+d8

OR

L A, R

L3O

RL

A,

@R

W6+

d8X

OR

L A, R

L3X

OR

L A

,@

RW

6+d8

R6,

#8, r

el@

RW

6+d8

,#8

, rel

+7

AD

DL A, R

L3A

DD

L A

,@

RW

7+d8

SU

BL A, R

L3S

UB

L A

,@

RW

7+d8

RW

7,#1

6, r

el@

RW

7+d8

#16,

rel

CM

PL A, R

L3C

MP

L A

,@

RW

7+d8

AN

DL A, R

L3A

ND

L A

,@

RW

7+d8

OR

L A, R

L3O

RL

A,

@R

W7+

d8X

OR

L A, R

L3X

OR

L A

,@

RW

7+d8

R7,

#8, r

el@

RW

7+d8

,#8

, rel

+8

AD

DL

A,@

RW

0A

DD

L A

,@

RW

0+d1

6S

UB

LA

,@R

W0

SU

BL

A,

@R

W0+

d16

@R

W0,

#16,

rel

@R

W0+

d16

#16,

rel

CM

PL

A,@

RW

0C

MP

L A

,@

RW

0+d1

6A

ND

LA

,@R

W0

AN

DL

A,

@R

W0+

d16

OR

LA

,@R

W0

OR

L A

,@

RW

0+d1

6X

OR

LA

,@R

W0

XO

RL

A,

@R

W0+

d16

@R

W0,

#8, r

el@

RW

0+d1

6,#

8, r

el

+9

AD

DL

A,@

RW

1A

DD

L A

,@

RW

1+d1

6S

UB

LA

,@R

W1

SU

BL

A,

@R

W1+

d16

@R

W1,

#16,

rel

@R

W1+

d16

#16,

rel

CM

PL

A,@

RW

1C

MP

L A

,@

RW

1+d1

6A

ND

LA

,@R

W1

AN

DL

A,

@R

W1+

d16

OR

LA

,@R

W1

OR

L A

,@

RW

1+d1

6X

OR

LA

,@R

W1

XO

RL

A,

@R

W1+

d16

@R

W1,

#8, r

el@

RW

1+d1

6,#

8, r

el

+A

AD

DL

A,@

RW

2A

DD

L A

,@

RW

2+d1

6S

UB

LA

,@R

W2

SU

BL

A,

@R

W2+

d16

@R

W2,

#16,

rel

@R

W2+

d16

#16,

rel

CM

PL

A,@

RW

2C

MP

L A

,@

RW

2+d1

6A

ND

LA

,@R

W2

AN

DL

A,

@R

W2+

d16

OR

LA

,@R

W2

OR

L A

,@

RW

2+d1

6X

OR

LA

,@R

W2

XO

RL

A,

@R

W2+

d16

@R

W2,

#8, r

el@

RW

2+d1

6,#

8, r

el

+B

AD

DL

A,@

RW

3A

DD

L A

,@

RW

3+d1

6S

UB

LA

,@R

W3

SU

BL

A,

@R

W3+

d16

@R

W3,

#16,

rel

@R

W3+

d16

#16,

rel

CM

PL

A,@

RW

3C

MP

L A

,@

RW

3+d1

6A

ND

LA

,@R

W3

AN

DL

A,

@R

W3+

d16

OR

LA

,@R

W3

OR

L A

,@

RW

3+d1

6X

OR

LA

,@R

W3

XO

RL

A,

@R

W3+

d16

@R

W3,

#8, r

el@

RW

3+d1

6,#

8, r

el

+C

AD

DL

A,@

RW

0+A

DD

L A

,@

RW

0+RW

7S

UB

LA

,@R

W0+

SU

BL

A,

@R

W0+

RW

7@

RW

0+R

W7,

#16

, rel

@R

W0+

RW

7#1

6, r

elC

MP

LA

,@R

W0+

CM

PL

A,

@RW

0+R

W7

AN

DL

A,@

RW

0+A

ND

L A

,@

RW

0+R

W7

OR

LA

,@R

W0+

OR

L A

,@

RW0+

RW

7X

OR

LA

,@R

W0+

XO

RL

A,

@R

W0+

RW

7@

RW

0+R

W7,

#8,

rel

@R

W0+

RW

7,#

8, r

el

+D

AD

DL

A,@

RW

1+A

DD

L A

,@

RW

1+RW

7S

UB

LA

,@R

W1+

SU

BL

A,

@R

W1+

RW

7@

RW

1+R

W7,

#16

, rel

@R

W1+

RW

7#1

6, r

elC

MP

LA

,@R

W1+

CM

PL

A,

@RW

1+R

W7

AN

DL

A,@

RW

1+A

ND

L A

,@

RW

1+R

W7

OR

LA

,@R

W1+

OR

L A

,@

RW1+

RW

7X

OR

LA

,@R

W1+

XO

RL

A,

@R

W1+

RW

7@

RW

1+R

W7,

#8,

rel

@R

W1+

RW

7,#

8, r

el

+E

AD

DL

A,@

RW

2+A

DD

L A

,@

PC

+d16

SU

BL

A,@

RW

2+S

UB

L A

,@

PC

+d16

@P

C+

d16,

#16,

rel

@P

C+d

16,

#16,

rel

CM

PL

A,@

RW

2+C

MP

L A

,@

PC

+d16

AN

DL

A,@

RW

2+A

ND

L A

,@

PC

+d16

OR

LA

,@R

W2+

OR

L A

,@

PC

+d16

XO

RL

A,@

RW

2+X

OR

L A

,@

PC

+d16

@P

C+

d16,

#8, r

el@

PC

+d16

,,#

8, r

el

+F

AD

DL

A,@

RW

3+A

DD

L A

,ad

dr16

SU

BL

A,@

RW

3+S

UB

L A

,ad

dr16

addr

16,

#16,

rel

addr

16,

#16,

rel

CM

PL

A,@

RW

3+C

MP

L A

,ad

dr16

AN

DL

A,@

RW

3+A

ND

L A

,ad

dr16

OR

LA

,@R

W3+

OR

L A

,ad

dr16

XO

RL

A,@

RW

3+X

OR

L A

,ad

dr16

addr

16,

#8, r

elad

dr16

,,#

8, r

el



Table C.6-2 ea-type Instruction (2) (First Byte = 71H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

JMP

P @R

L0JM

PP@

@R

W0+

d8C

ALL

P@

RL0

CAL

LP@

@R

W0+

d8IN

CL

RL0

INC

L@

RW

0+d8

DE

CL

RL0

DE

CL

@R

W0+

d8M

OV

LA

, RL0

MO

VL

A,

@R

W0+

d8M

OV

LR

L0, A

MO

VL

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MO

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#8

MO

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RW

0+d8

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AA

, RW

0M

OV

EA

A,

@R

W0+

d8

+1

JMP

P @R

L0JM

PP@

@R

W1+

d8C

ALL

P@

RL0

CAL

LP@

@R

W1+

d8IN

CL

RL0

INC

L@

RW

1+d8

DE

CL

RL0

DE

CL

@R

W1+

d8M

OV

LA

, RL0

MO

VL

A,

@R

W1+

d8M

OV

LR

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MO

VL

@R

W1+

d8,A

MO

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#8

MO

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RW

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,#8

MO

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AA

, RW

1M

OV

EA

A,

@R

W1+

d8

+2

JMP

P @R

L1JM

PP@

@R

W2+

d8C

ALL

P@

RL1

CAL

LP@

@R

W2+

d8IN

CL

RL1

INC

L@

RW

2+d8

DE

CL

RL1

DE

CL

@R

W2+

d8M

OV

LA

, RL1

MO

VL

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@R

W2+

d8M

OV

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MO

VL

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W2+

d8,A

MO

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#8

MO

V@

RW

2+d8

,#8

MO

VE

AA

, RW

2M

OV

EA

A,

@R

W2+

d8

+3

JMP

P @R

L1JM

PP@

@R

W3+

d8C

ALL

P@

RL1

CAL

LP@

@R

W3+

d8IN

CL

RL1

INC

L@

RW

3+d8

DE

CL

RL1

DE

CL

@R

W3+

d8M

OV

LA

, RL1

MO

VL

A,

@R

W3+

d8M

OV

LR

L1, A

MO

VL

@R

W3+

d8,A

MO

V R3,

#8

MO

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RW

3+d8

,#8

MO

VE

AA

, RW

3M

OV

EA

A,

@R

W3+

d8

+4

JMP

P @R

L2JM

PP@

@R

W4+

d8C

ALL

P@

RL2

CAL

LP@

@R

W4+

d8IN

CL

RL2

INC

L@

RW

4+d8

DE

CL

RL2

DE

CL

@R

W4+

d8M

OV

LA

, RL2

MO

VL

A,

@R

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d8M

OV

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L2, A

MO

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@R

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MO

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#8

MO

V@

RW

4+d8

,#8

MO

VE

AA

, RW

4M

OV

EA

A,

@R

W4+

d8

+5

JMP

P @R

L2JM

PP@

@R

W5+

d8C

ALL

P@

RL2

CAL

LP@

@R

W5+

d8IN

CL

RL2

INC

L@

RW

5+d8

DE

CL

RL2

DE

CL

@R

W5+

d8M

OV

LA

, RL2

MO

VL

A,

@R

W5+

d8M

OV

LR

L2, A

MO

VL

@R

W5+

d8,A

MO

V R5,

#8

MO

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RW

5+d8

,#8

MO

VE

AA

, RW

5M

OV

EA

A,

@R

W5+

d8

+6

JMP

P @R

L3JM

PP@

@R

W6+

d8C

ALL

P@

RL3

CAL

LP@

@R

W6+

d8IN

CL

RL3

INC

L@

RW

6+d8

DE

CL

RL3

DE

CL

@R

W6+

d8M

OV

LA

, RL3

MO

VL

A,

@R

W6+

d8M

OV

LR

L3, A

MO

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W6+

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MO

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#8

MO

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RW

6+d8

,#8

MO

VE

AA

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6M

OV

EA

A,

@R

W6+

d8

+7

JMP

P @R

L3JM

PP@

@R

W7+

d8C

ALL

P@

RL3

CAL

LP@

@R

W7+

d8IN

CL

RL3

INC

L@

RW

7+d8

DE

CL

RL3

DE

CL

@R

W7+

d8M

OV

LA

, RL3

MO

VL

A,

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d8M

OV

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MO

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MO

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#8

MO

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RW

7+d8

,#8

MO

VE

AA

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7M

OV

EA

A,

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d8

+8

JMP

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JMP

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CA

LLP

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RW

0C

ALL

P @

@R

W0+

d16

INC

L @R

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INC

L@

RW

0+d1

6D

EC

L@

RW

0D

EC

L@

RW

0+d1

6M

OV

LA

,@R

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MO

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W0+

d16

MO

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AM

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6,A

MO

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0, #

8M

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d16,

#8M

OV

EA

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A,

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d16

+9

JMP

P@

@R

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JMP

P @

@R

W1+

d16

CA

LLP

@@

RW

1C

ALL

P @

@R

W1+

d16

INC

L @R

W1

INC

L@

RW

1+d1

6D

EC

L@

RW

1D

EC

L@

RW

1+d1

6M

OV

LA

,@R

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MO

VL

A,

@R

W1+

d16

MO

VL

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AM

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6,A

MO

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1, #

8M

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OV

EA

A,@

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A,

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d16

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JMP

P@

@R

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JMP

P @

@R

W2+

d16

CA

LLP

@@

RW

2C

ALL

P @

@R

W2+

d16

INC

L @R

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INC

L@

RW

2+d1

6D

EC

L@

RW

2D

EC

L@

RW

2+d1

6M

OV

LA

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MO

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MO

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AM

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2, #

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2M

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d16

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JMP

P@

@R

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JMP

P @

@R

W3+

d16

CA

LLP

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RW

3C

ALL

P @

@R

W3+

d16

INC

L @R

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INC

L@

RW

3+d1

6D

EC

L@

RW

3D

EC

L@

RW

3+d1

6M

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MO

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d16

MO

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AM

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3, #

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d16

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JMP

P@

@R

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JMPP

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RW

0+RW

7C

ALL

P@

@R

W0+

CAL

LP @

@R

W0+

RW7

INC

L@

RW

0+IN

CL

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0+R

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CL

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DECL

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MO

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7M

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AM

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JMP

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1+RW

7C

ALL

P@

@R

W1+

CAL

LP @

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INC

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RW

1+IN

CL

@RW

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CL

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DECL

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JMP

P@

@R

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PC+d

16C

ALL

P@

@R

W2+

CAL

LP@

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INC

L@

RW

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CL

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CL

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JMP

P@

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JMP

P@

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16C

ALL

P@

@R

W3+

CA

LLP

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INC

L@

RW

3+IN

CL ad

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DE

CL

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DE

CL ad

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EA

A,

addr

16




0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

RO

LCR

0R

OLC

@R

W0+

d8R

OR

CR

0R

OR

C@

RW

0+d8

INC

R0

INC

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W0+

d8D

EC

R0

DE

C@

RW

0+d8

MO

VA

, R0

MO

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A

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RW

0+d8

MO

VR

0, A

MO

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0+d8

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X A, R

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X

A,

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0X

CH

A,

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+1

RO

LCR

1R

OLC

@R

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OR

CR

1R

OR

C@

RW

1+d8

INC

R1

INC

@R

W1+

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EC

R1

DE

C@

RW

1+d8

MO

VA

, R1

MO

V

A

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MO

VR

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A,

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RO

LCR

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OLC

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OR

CR

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OR

C@

RW

2+d8

INC

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INC

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EC

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2+d8

MO

VA

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MO

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A

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RO

LCR

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OLC

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OR

CR

3R

OR

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3+d8

INC

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INC

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RW

3+d8

MO

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MO

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A

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CR

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C@

RW

4+d8

INC

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INC

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EC

R4

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RW

4+d8

MO

VA

, R4

MO

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A

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RW

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MO

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A,

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RO

LCR

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OLC

@R

W5+

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OR

CR

5R

OR

C@

RW

5+d8

INC

R5

INC

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W5+

d8D

EC

R5

DE

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RW

5+d8

MO

VA

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MO

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A

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MO

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MO

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5+d8

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A,

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5X

CH

A,

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W5+

d8

+6

RO

LCR

6R

OLC

@R

W6+

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OR

CR

6R

OR

C@

RW

6+d8

INC

R6

INC

@R

W6+

d8D

EC

R6

DE

C@

RW

6+d8

MO

VA

, R6

MO

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A

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6+d8

MO

VR

6, A

MO

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RW

6+d8

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6M

OV

X

A,

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W6+

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CH

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6X

CH

A,

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W6+

d8

+7

RO

LCR

7R

OLC

@R

W7+

d8R

OR

CR

7R

OR

C@

RW

7+d8

INC

R7

INC

@R

W7+

d8D

EC

R7

DE

C@

RW

7+d8

MO

VA

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MO

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A

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d8

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RO

LC @R

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RO

LC@

RW

0+d1

6R

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C@

RW

0R

OR

C@

RW

0+d1

6IN

C @R

W0

INC

@R

W0+

d16

DE

C @R

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C@

RW

0+d1

6M

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1+d1

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C@

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1+d1

6IN

C @R

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INC

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d16

DE

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DE

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1+d1

6M

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2+d1

6R

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RW

2+d1

6IN

C @R

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d16

DE

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2+d1

6M

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2M

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6X

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RO

LC @R

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RO

LC@

RW

3+d1

6R

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C@

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3R

OR

C@

RW

3+d1

6IN

C @R

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INC

@R

W3+

d16

DE

C @R

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DE

C@

RW

3+d1

6M

OV

A,@

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3M

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RO

LC@

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0+R

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0+RW

7R

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RW

0+RO

RC@

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INC @

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0+IN

C@

RW

0+RW

7D

EC @R

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DEC

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MO

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RO

LC@

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1+R

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7R

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INC @

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1+RW

7D

EC @R

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DEC

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MO

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LC@

RW

2+R

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RO

RC

@R

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RO

RC

@P

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INC @

RW

2+IN

C@

PC

+d1

6D

EC @R

W2+

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C@

PC

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6M

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RO

RC ad

dr16

INC @

RW

3+IN

Cad

dr16

DE

C @R

W3+

DE

C addr

16M

OV

A,@

RW

3+M

OV

A,

addr

16M

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W3+

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OV addr

16, A

MO

VX

A,@

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3+M

OV

X

A,

addr

16X

CH

A,@

RW

3+X

CH

A,

addr

16




0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

JMP @

RW

0JM

P@

@RW

0+d8

CA

LLR

W0

CAL

L@

@RW

0+d8

INC

W RW

0IN

CW

@R

W0+

d8D

EC

W RW

0D

EC

W@

RW

0+d8

MO

VW

A, R

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d8,#

16X

CH

WA

, RW

0X

CH

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A,

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W0+

d8

+1

JMP @

RW

1JM

P@

@RW

1+d8

CA

LLR

W1

CAL

L@

@RW

1+d8

INC

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1IN

CW

@R

W1+

d8D

EC

W RW

1D

EC

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RW

1+d8

MO

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A, R

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1X

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d8

+2

JMP @

RW

2JM

P@

@RW

2+d8

CA

LLR

W2

CAL

L@

@RW

2+d8

INC

W RW

2IN

CW

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EC

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2D

EC

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RW

2+d8

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A, R

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d8,#

16X

CH

WA

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A,

@R

W2+

d8

+3

JMP @

RW

3JM

P@

@RW

3+d8

CA

LLR

W3

CAL

L@

@RW

3+d8

INC

W RW

3IN

CW

@R

W3+

d8D

EC

W RW

3D

EC

W@

RW

3+d8

MO

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A, R

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16X

CH

WA

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CH

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A,

@R

W3+

d8

+4

JMP @

RW

4JM

P@

@RW

4+d8

CA

LLR

W4

CAL

L@

@RW

4+d8

INC

W RW

4IN

CW

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W4+

d8D

EC

W RW

4D

EC

W@

RW

4+d8

MO

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A, R

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A,

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WR

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AM

OV

W@

RW

4+d8

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OV

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VW

@R

W4+

d8,#

16X

CH

WA

, RW

4X

CH

W

A,

@R

W4+

d8

+5

JMP @

RW

5JM

P@

@RW

5+d8

CA

LLR

W5

CAL

L@

@RW

5+d8

INC

W RW

5IN

CW

@R

W5+

d8D

EC

W RW

5D

EC

W@

RW

5+d8

MO

VW

A, R

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MO

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A,

@R

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d8M

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AM

OV

W@

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5+d8

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16X

CH

WA

, RW

5X

CH

W

A,

@R

W5+

d8

+6

JMP @

RW

6JM

P@

@RW

6+d8

CA

LLR

W6

CAL

L@

@RW

6+d8

INC

W RW

6IN

CW

@R

W6+

d8D

EC

W RW

6D

EC

W@

RW

6+d8

MO

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A, R

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MO

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A,

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d8M

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AM

OV

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d8,#

16X

CH

WA

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6X

CH

W

A,

@R

W6+

d8

+7

JMP @

RW

7JM

P@

@RW

7+d8

CA

LLR

W7

CAL

L@

@RW

7+d8

INC

W RW

7IN

CW

@R

W7+

d8D

EC

W RW

7D

EC

W@

RW

7+d8

MO

VW

A, R

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MO

VW

A,

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d8M

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AM

OV

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7+d8

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OV

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#16

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@R

W7+

d8,#

16X

CH

WA

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7X

CH

W

A,

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d8

+8

JMP

@@

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0JM

P @

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LL@

@R

W0

CA

LL @

@R

W0+

d16

INC

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RW

0IN

CW

@

@R

W0+

d16

DE

CW

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W0

DE

CW

@R

W0+

d16

MO

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A,@

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0M

OV

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0+d1

6M

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0,A

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RW

0+d1

6,A

MO

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@R

W0,

#16

MO

VW@

RW0+

d16,

#16

XC

HW

A,@

RW

0X

CH

W

A,

@R

W0+

d16

+9

JMP

@@

RW

1JM

P @

@R

W1+

d16

CA

LL@

@R

W1

CA

LL @

@R

W1+

d16

INC

W@

RW

1IN

CW

@

@R

W1+

d16

DE

CW

@R

W1

DE

CW

@R

W1+

d16

MO

VW

A,@

RW

1M

OV

W A

,@

RW

1+d1

6M

OV

W@

RW

1, A

MO

VW@

RW

1+d1

6,A

MO

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#16

MO

VW@

RW1+

d16,

#16

XC

HW

A,@

RW

1X

CH

W

A,

@R

W1+

d16

+A

JMP

@@

RW

2JM

P @

@R

W2+

d16

CA

LL@

@R

W2

CA

LL @

@R

W2+

d16

INC

W@

RW

2IN

CW

@

@R

W2+

d16

DE

CW

@R

W2

DE

CW

@R

W2+

d16

MO

VW

A,@

RW

2M

OV

W A

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RW

2+d1

6M

OV

W@

RW

2, A

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VW@

RW

2+d1

6,A

MO

VW

@R

W2,

#16

MO

VW@

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d16,

#16

XC

HW

A,@

RW

2X

CH

W

A,

@R

W2+

d16

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JMP

@@

RW

3JM

P @

@R

W3+

d16

CA

LL@

@R

W3

CA

LL @

@R

W3+

d16

INC

W@

RW

3IN

CW

@

@R

W3+

d16

DE

CW

@R

W3

DE

CW

@R

W3+

d16

MO

VW

A,@

RW

3M

OV

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RW

3+d1

6M

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RW

3, A

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RW

3+d1

6,A

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#16

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#16

XC

HW

A,@

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3X

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A,

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W3+

d16

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JMP

@@

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0+JM

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@R

W0+

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CA

LL@

@R

W0+

CAL

L @

@R

W0+

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W@

RW

0+IN

CW

@

@R

W0+

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DE

CW

@R

W0+

DECW

@RW

0+RW

7M

OV

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W0+

MO

VW A

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7M

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W@

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W@

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AM

OV

W@

RW

0+, #

16M

OVW

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0+RW

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6X

CH

WA

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A,@

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0+RW

7

+D

JMP

@@

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1+JM

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CA

LL@

@R

W1+

CAL

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W@

RW

1+IN

CW

@

@R

W1+

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DE

CW

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W1+

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7M

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AM

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LL@

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CAL

L@

@PC

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INC

W@

RW

2+IN

CW

@@

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EC

W@

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2+D

EC

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PC

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@@

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3+JM

P @ad

dr16

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LL@

@R

W3+

CA

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addr

16IN

CW

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INC

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EC

W@

RW

3+D

EC

W addr

16M

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MO

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addr

16M

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addr

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WA

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HW

A

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dr16




0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

AD

DA

, R0

AD

D

A

,@

RW

0+d8

SU

BA

, R0

SU

B

A

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RW

0+d8

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A, R

0O

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A,

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d8X

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A, R

0X

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A,

@R

W0+

d8D

BN

Z R0,

rD

BN

Z

@R

W0+

d8, r

+1

AD

DA

, R1

AD

D

A

,@

RW

1+d8

SU

BA

, R1

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A, R

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d8X

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A, R

1X

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A,

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d8D

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Z R1,

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Z

@R

W1+

d8, r

+2

AD

DA

, R2

AD

D

A

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RW

2+d8

SU

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A, R

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A,

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A, R

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A,

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Z

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d8, r

+3

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DA

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AD

D

A

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RW

3+d8

SU

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A, R

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A, R

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A,

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d8, r

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DA

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AD

D

A

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4+d8

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A, R

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A,

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A, R

4X

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A,

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rD

BN

Z

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d8, r

+5

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DA

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AD

D

A

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RW

5+d8

SU

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A, R

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A,

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d8X

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A, R

5X

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A,

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d8D

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Z R5,

rD

BN

Z

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W5+

d8, r

+6

AD

DA

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AD

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A

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RW

6+d8

SU

BA

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A,

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d8X

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A, R

6X

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A,

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BN

Z R6,

rD

BN

Z

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W6+

d8, r

+7

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DA

, R7

AD

D

A

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RW

7+d8

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A,

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6D

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r

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6D

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d16,

r

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AD

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A,

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W2+

d16

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6D

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2, r

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d16,

r

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BN

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3, r

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d16,

r

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AD

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0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

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0, A

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0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

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5D

IVU

A,

@R

W5+

d8D

IVU

WA

, RW

5D

IVU

W

A,

@R

W5+

d8D

IVA

, R5

DIV

A

,@

RW

5+d8

DIV

W A, R

W5

DIV

W

A,

@R

W5+

d8

+6

MU

LU A, R

6M

ULU

A

,@

RW

6+d8

MU

LUW

A, R

W6

MU

LUW

A,

@R

W6+

d8M

UL A

, R6

MU

L

A,

@R

W6+

d8M

ULW A, R

W6

MU

LW A

,@

RW

6+d8

DIV

U A, R

6D

IVU

A,

@R

W6+

d8D

IVU

WA

, RW

6D

IVU

W

A,

@R

W6+

d8D

IVA

, R6

DIV

A

,@

RW

6+d8

DIV

W A, R

W6

DIV

W

A,

@R

W6+

d8

+7

MU

LU A, R

7M

ULU

A

,@

RW

7+d8

MU

LUW

A, R

W7

MU

LUW

A,

@R

W7+

d8M

UL A

, R7

MU

L

A,

@R

W7+

d8M

ULW A, R

W7

MU

LW A

,@

RW

7+d8

DIV

U A, R

7D

IVU

A,

@R

W7+

d8D

IVU

WA

, RW

7D

IVU

W

A,

@R

W7+

d8D

IVA

, R7

DIV

A

,@

RW

7+d8

DIV

W A, R

W7

DIV

W

A,

@R

W7+

d8

+8

MU

LUA

,@R

W0

MU

LU

A,

@R

W0+

d16

MU

LUW

A,@

RW

0M

ULU

W A

,@

RW

0+d1

6M

UL

A, @

RW

0M

UL

A

,@

RW

0+d1

6M

ULW

A,@

RW

0M

ULW

A,

@R

W0+

d16

DIV

UA

,@R

W0

DIV

U

A

,@

RW

0+d1

6D

IVU

WA

,@R

W0

DIV

UW

A

,@

RW

0+d1

6D

IV A,@

RW

0D

IV

A,

@R

W0+

d16

DIV

WA

,@R

W0

DIV

W

A,

@R

W0+

d16

+9

MU

LUA

,@R

W1

MU

LU

A,

@R

W1+

d16

MU

LUW

A,@

RW

1M

ULU

W A

,@

RW

1+d1

6M

UL

A, @

RW

1M

UL

A

,@

RW

1+d1

6M

ULW

A,@

RW

1M

ULW

A,

@R

W1+

d16

DIV

UA

,@R

W1

DIV

U

A

,@

RW

1+d1

6D

IVU

WA

,@R

W1

DIV

UW

A

,@

RW

1+d1

6D

IV A,@

RW

1D

IV

A,

@R

W1+

d16

DIV

WA

,@R

W1

DIV

W

A,

@R

W1+

d16

+A

MU

LUA

,@R

W2

MU

LU

A,

@R

W2+

d16

MU

LUW

A,@

RW

2M

ULU

W A

,@

RW

2+d1

6M

UL

A, @

RW

2M

UL

A

,@

RW

2+d1

6M

ULW

A,@

RW

2M

ULW

A,

@R

W2+

d16

DIV

UA

,@R

W2

DIV

U

A

,@

RW

2+d1

6D

IVU

WA

,@R

W2

DIV

UW

A

,@

RW

2+d1

6D

IV A,@

RW

2D

IV

A,

@R

W2+

d16

DIV

WA

,@R

W2

DIV

W

A,

@R

W2+

d16

+B

MU

LUA

,@R

W3

MU

LU

A,

@R

W3+

d16

MU

LUW

A,@

RW

3M

ULU

W A

,@

RW

3+d1

6M

UL

A, @

RW

3M

UL

A

,@

RW

3+d1

6M

ULW

A,@

RW

3M

ULW

A,

@R

W3+

d16

DIV

UA

,@R

W3

DIV

U

A

,@

RW

3+d1

6D

IVU

WA

,@R

W3

DIV

UW

A

,@

RW

3+d1

6D

IV A,@

RW

3D

IV

A,

@R

W3+

d16

DIV

WA

,@R

W3

DIV

W

A,

@R

W3+

d16

+C

MU

LUA

,@R

W0+

MU

LU

A,

@R

W0+

RW

7M

ULU

WA

,@R

W0+

MU

LUW

A,

@R

W0+

RW

7M

UL

A,@

RW

0+M

UL

A

,@

RW

0+RW

7M

ULW

A,@

RW

0+M

ULW

A,

@R

W0+

RW7

DIV

UA

,@R

W0+

DIV

U

A,

@R

W0+

RW7

DIV

UW

A,@

RW

0+D

IVU

W

A,@

RW0+

RW7

DIV A,@

RW

0+D

IV

A,

@R

W0+

RW

7D

IVW

A,@

RW

0+D

IVW

A

,@

RW0+

RW

7

+D

MU

LUA

,@R

W1+

MU

LU

A,

@R

W1+

RW

7M

ULU

WA

,@R

W1+

MU

LUW

A,

@R

W1+

RW

7M

UL

A,@

RW

1+M

UL

A

,@

RW

1+RW

7M

ULW

A,@

RW

1+M

ULW

A,

@R

W1+

RW7

DIV

UA

,@R

W1+

DIV

U

A,

@R

W1+

RW7

DIV

UW

A,@

RW

1+D

IVU

W

A,@

RW1+

RW7

DIV A,@

RW

1+D

IV

A,

@R

W1+

RW

7D

IVW

A,@

RW

1+D

IVW

A

,@

RW1+

RW

7

+E

MU

LUA

,@R

W2+

MU

LU

A,

@P

C+

d16

MU

LUW

A,@

RW

2+M

ULU

W A

,@

PC

+d1

6M

UL

A,@

RW

2+M

UL

A

,@

PC

+d1

6M

ULW

A,@

RW

2+M

ULW

A,

@P

C+

d16

DIV

UA

,@R

W2+

DIV

U

A

,@

PC

+d1

6D

IVU

WA

,@R

W2+

DIV

UW

A

,@

PC

+d1

6D

IV A,@

RW

2+D

IV

A,

@P

C+

d16

DIV

WA

,@R

W2+

DIV

W

A,

@P

C+

d16

+F

MU

LUA

, @R

W3+

MU

LU

A,

addr

16M

ULU

WA

,@R

W3+

MU

LUW

A,

addr

16M

UL

A,@

RW

3+M

UL

A

,ad

dr16

MU

LWA

,@R

W3+

MU

LW A

,ad

dr16

DIV

UA

,@R

W3+

DIV

U

A

,ad

dr16

DIV

UW

A,@

RW

3+D

IVU

W

A,

addr

16D

IV A,@

RW

3+D

IV

A,

addr

16D

IVW

A,@

RW

3+D

IVW

A

,ad

dr16



C.7 MOVEA RWi, ea Instruction Map

Table C.7-1 lists MOVEA RWi, ea instruction map.



Table C.7-1 MOVEA RWi, ea Instruction (First Byte = 79H)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

VE

AR

W0,

RW

0M

OVE

A R

W0

,@RW

0+d8

MO

VE

AR

W1,

RW

0M

OVE

A RW

1,@

RW0+

d8M

OV

EA

RW

2,R

W0

MO

VEA

RW2

,@RW

0+d8

MO

VE

AR

W3,

RW

0M

OVE

A RW

3,@

RW0+

d8M

OV

EA

RW

4,R

W0

MO

VEA

RW4

,@RW

0+d8

MO

VE

AR

W5,

RW

0M

OV

EA

RW

5,@

RW

0+d8

MO

VE

AR

W6,

RW

0M

OVE

A RW

6,@

RW

0+d8

MO

VE

AR

W7,

RW

0M

OVE

A RW

7,@

RW0+

d8

+1

MO

VE

AR

W0,

RW

1M

OVE

A R

W0

,@RW

1+d8

MO

VE

AR

W1,

RW

1M

OVE

A RW

1,@

RW1+

d8M

OV

EA

RW

2,R

W1

MO

VEA

RW2

,@RW

1+d8

MO

VE

AR

W3,

RW

1M

OVE

A RW

3,@

RW1+

d8M

OV

EA

RW

4,R

W1

MO

VEA

RW4

,@RW

1+d8

MO

VE

AR

W5,

RW

1M

OV

EA

RW

5,@

RW

1+d8

MO

VE

AR

W6,

RW

1M

OVE

A RW

6,@

RW

1+d8

MO

VE

AR

W7,

RW

1M

OVE

A RW

7,@

RW1+

d8

+2

MO

VE

AR

W0,

RW

2M

OVE

A R

W0

,@RW

2+d8

MO

VE

AR

W1,

RW

2M

OVE

A RW

1,@

RW2+

d8M

OV

EA

RW

2,R

W2

MO

VEA

RW2

,@RW

2+d8

MO

VE

AR

W3,

RW

2M

OVE

A RW

3,@

RW2+

d8M

OV

EA

RW

4,R

W2

MO

VEA

RW4

,@RW

2+d8

MO

VE

AR

W5,

RW

2M

OV

EA

RW

5,@

RW

2+d8

MO

VE

AR

W6,

RW

2M

OVE

A RW

6,@

RW

2+d8

MO

VE

AR

W7,

RW

2M

OVE

A RW

7,@

RW2+

d8

+3

MO

VE

AR

W0,

RW

3M

OVE

A R

W0

,@RW

3+d8

MO

VE

AR

W1,

RW

3M

OVE

A RW

1,@

RW3+

d8M

OV

EA

RW

2,R

W3

MO

VEA

RW2

,@RW

3+d8

MO

VE

AR

W3,

RW

3M

OVE

A RW

3,@

RW3+

d8M

OV

EA

RW

4,R

W3

MO

VEA

RW4

,@RW

3+d8

MO

VE

AR

W5,

RW

3M

OV

EA

RW

5,@

RW

3+d8

MO

VE

AR

W6,

RW

3M

OVE

A RW

6,@

RW

3+d8

MO

VE

AR

W7,

RW

3M

OVE

A RW

7,@

RW3+

d8

+4

MO

VE

AR

W0,

RW

4M

OVE

A R

W0

,@RW

4+d8

MO

VE

AR

W1,

RW

4M

OVE

A RW

1,@

RW4+

d8M

OV

EA

RW

2,R

W4

MO

VEA

RW2

,@RW

4+d8

MO

VE

AR

W3,

RW

4M

OVE

A RW

3,@

RW4+

d8M

OV

EA

RW

4,R

W4

MO

VEA

RW4

,@RW

4+d8

MO

VE

AR

W5,

RW

4M

OV

EA

RW

5,@

RW

4+d8

MO

VE

AR

W6,

RW

4M

OVE

A RW

6,@

RW

4+d8

MO

VE

AR

W7,

RW

4M

OVE

A RW

7,@

RW4+

d8

+5

MO

VE

AR

W0,

RW

5M

OVE

A R

W0

,@RW

5+d8

MO

VE

AR

W1,

RW

5M

OVE

A RW

1,@

RW5+

d8M

OV

EA

RW

2,R

W5

MO

VEA

RW2

,@RW

5+d8

MO

VE

AR

W3,

RW

5M

OVE

A RW

3,@

RW5+

d8M

OV

EA

RW

4,R

W5

MO

VEA

RW4

,@RW

5+d8

MO

VE

AR

W5,

RW

5M

OV

EA

RW

5,@

RW

5+d8

MO

VE

AR

W6,

RW

5M

OVE

A RW

6,@

RW

5+d8

MO

VE

AR

W7,

RW

5M

OVE

A RW

7,@

RW5+

d8

+6

MO

VE

AR

W0,

RW

6M

OVE

A R

W0

,@RW

6+d8

MO

VE

AR

W1,

RW

6M

OVE

A RW

1,@

RW6+

d8M

OV

EA

RW

2,R

W6

MO

VEA

RW2

,@RW

6+d8

MO

VE

AR

W3,

RW

6M

OVE

A RW

3,@

RW6+

d8M

OV

EA

RW

4,R

W6

MO

VEA

RW4

,@RW

6+d8

MO

VE

AR

W5,

RW

6M

OV

EA

RW

5,@

RW

6+d8

MO

VE

AR

W6,

RW

6M

OVE

A RW

6,@

RW

6+d8

MO

VE

AR

W7,

RW

6M

OVE

A RW

7,@

RW6+

d8

+7

MO

VE

AR

W0,

RW

7M

OVE

A R

W0

,@RW

7+d8

MO

VE

AR

W1,

RW

7M

OVE

A RW

1,@

RW7+

d8M

OV

EA

RW

2,R

W7

MO

VEA

RW2

,@RW

7+d8

MO

VE

AR

W3,

RW

7M

OVE

A RW

3,@

RW7+

d8M

OV

EA

RW

4,R

W7

MO

VEA

RW4

,@RW

7+d8

MO

VE

AR

W5,

RW

7M

OV

EA

RW

5,@

RW

7+d8

MO

VE

AR

W6,

RW

7M

OVE

A RW

6,@

RW

7+d8

MO

VE

AR

W7,

RW

7M

OVE

A RW

7,@

RW7+

d8

+8

MO

VE

AR

W0,

@R

W0

MO

VEA

RW

0,@

RW0+

d16

MO

VE

AR

W1,

@R

W0

MO

VEA

RW1

,@RW

0+d1

6M

OV

EA

RW

2,@

RW

0M

OVE

A RW

2,@

RW0+

d16

MO

VE

AR

W3,

@R

W0

MO

VEA

RW3

,@RW

0+d1

6M

OV

EA

RW

4,@

RW

0M

OVE

A RW

4,@

RW0+

d16

MO

VE

AR

W5,

@R

W0

MO

VE

A R

W5

,@R

W0+

d16

MO

VE

AR

W6,

@R

W0

MO

VEA

RW6

,@R

W0+

d16

MO

VE

AR

W7,

@R

W0

MO

VEA

RW7

,@RW

0+d1

6

+9

MO

VE

AR

W0,

@R

W1

MO

VEA

RW

0,@

RW1+

d16

MO

VE

AR

W1,

@R

W1

MO

VEA

RW1

,@RW

1+d1

6M

OV

EA

RW

2,@

RW

1M

OVE

A RW

2,@

RW1+

d16

MO

VE

AR

W3,

@R

W1

MO

VEA

RW3

,@RW

1+d1

6M

OV

EA

RW

4,@

RW

1M

OVE

A RW

4,@

RW1+

d16

MO

VE

AR

W5,

@R

W1

MO

VE

A R

W5

,@R

W1+

d16

MO

VE

AR

W6,

@R

W1

MO

VEA

RW6

,@R

W1+

d16

MO

VE

AR

W7,

@R

W1

MO

VEA

RW7

,@RW

1+d1

6

+A

MO

VE

AR

W0,

@R

W2

MO

VEA

RW

0,@

RW2+

d16

MO

VE

AR

W1,

@R

W2

MO

VEA

RW1

,@RW

2+d1

6M

OV

EA

RW

2,@

RW

2M

OVE

A RW

2,@

RW2+

d16

MO

VE

AR

W3,

@R

W2

MO

VEA

RW3

,@RW

2+d1

6M

OV

EA

RW

4,@

RW

2M

OVE

A RW

4,@

RW2+

d16

MO

VE

AR

W5,

@R

W2

MO

VE

A R

W5

,@R

W2+

d16

MO

VE

AR

W6,

@R

W2

MO

VEA

RW6

,@R

W2+

d16

MO

VE

AR

W7,

@R

W2

MO

VEA

RW7

,@RW

2+d1

6

+B

MO

VE

AR

W0,

@R

W3

MO

VEA

RW

0,@

RW3+

d16

MO

VE

AR

W1,

@R

W3

MO

VEA

RW1

,@RW

3+d1

6M

OV

EA

RW

2,@

RW

3M

OVE

A RW

2,@

RW3+

d16

MO

VE

AR

W3,

@R

W3

MO

VEA

RW3

,@RW

3+d1

6M

OV

EA

RW

4,@

RW

3M

OVE

A RW

4,@

RW3+

d16

MO

VE

AR

W5,

@R

W3

MO

VE

A R

W5

,@R

W3+

d16

MO

VE

AR

W6,

@R

W3

MO

VEA

RW6

,@R

W3+

d16

MO

VE

AR

W7,

@R

W3

MO

VEA

RW7

,@RW

3+d1

6

+C

MO

VEA

RW

0,@

RW

0+M

OVE

A R

W0

,@RW

0+R

W7

MO

VEA

RW1,

@RW

0+M

OVE

A RW

1,@

RW0+

RW7

MO

VEA

RW2,

@RW

0+M

OVE

A RW

2,@

RW0+

RW7

MO

VEA

RW3,

@RW

0+M

OVE

A RW

3,@

RW0+

RW7

MO

VEA

RW4,

@RW

0+M

OVE

A RW

4,@

RW0+

RW7

MO

VEA

RW

5,@

RW

0+M

OV

EA

RW

5,@

RW

0+R

W7

MO

VEA

RW6,

@RW

0+M

OVE

A RW

6,@

RW

0+RW

7M

OVE

ARW

7,@

RW0+

MO

VEA

RW7

,@RW

0+RW

7

+D

MO

VEA

RW

0,@

RW

1+M

OVE

A R

W0

,@RW

1+R

W7

MO

VEA

RW1,

@RW

1+M

OVE

A RW

1,@

RW1+

RW7

MO

VEA

RW2,

@RW

1+M

OVE

A RW

2,@

RW1+

RW7

MO

VEA

RW3,

@RW

1+M

OVE

A RW

3,@

RW1+

RW7

MO

VEA

RW4,

@RW

1+M

OVE

A RW

4,@

RW1+

RW7

MO

VEA

RW

5,@

RW

1+M

OV

EA

RW

5,@

RW

1+R

W7

MO

VEA

RW6,

@RW

1+M

OVE

A RW

6,@

RW

1+RW

7M

OVE

ARW

7,@

RW1+

MO

VEA

RW7

,@RW

1+RW

7

+E

MO

VEA

RW

0,@

RW

2+M

OVE

A R

W0

,@PC

+d16

MO

VEA

RW1,

@RW

2+M

OVE

A RW

1,@

PC+d

16M

OVE

ARW

2,@

RW2+

MO

VEA

RW2

,@PC

+d16

MO

VEA

RW3,

@RW

2+M

OVE

A RW

3,@

PC+d

16M

OVE

ARW

4,@

RW2+

MO

VEA

RW4

,@PC

+d16

MO

VEA

RW

5,@

RW

2+M

OV

EA

RW

5,@

PC

+d16

MO

VEA

RW6,

@RW

2+M

OVE

A RW

6,@

PC+d

16M

OVE

ARW

7,@

RW2+

MO

VEA

RW7

,@PC

+d16

+F

MO

VEA

RW

0,@

RW

3+M

OV

EA

R

W0,

add

r16

MO

VEA

RW1,

@RW

3+M

OV

EA

R

W1,

add

r16

MO

VEA

RW2,

@RW

3+M

OV

EA

R

W2,

add

r16

MO

VEA

RW3,

@RW

3+M

OV

EA

R

W3,

add

r16

MO

VEA

RW4,

@RW

3+M

OV

EA

R

W4,

add

r16

MO

VEA

RW

5,@

RW

3+M

OV

EA

R

W5,

add

r16

MO

VEA

RW6,

@RW

3+M

OV

EA

R

W6,

add

r16

MO

VEA

RW7@

RW3+

MO

VE

A

RW

7, a

ddr1

6



C.8 MOV Ri, ea Instruction Map

Table C.8-1 lists MOV Ri, ea instruction map.



Table C.8-1 MOV Ri, ea Instruction (First Byte = 7AH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

V R0,

R0

MO

V

R0,

@R

W0+

d8M

OV R

1, R

0M

OV

R

1,@

RW

0+d8

MO

V R2,

R0

MO

V

R2,

@R

W0+

d8M

OV R

3, R

0M

OV

R

3,@

RW

0+d8

MO

V R4,

R0

MO

V

R4,

@R

W0+

d8M

OV R

5, R

0M

OV

R

5,@

RW

0+d8

MO

V R6,

R0

MO

V

R6,

@R

W0+

d8M

OV R

7, R

0M

OV

R

7,@

RW

0+d8

+1

MO

V R0,

R1

MO

V

R0,

@R

W1+

d8M

OV R

1, R

1M

OV

R

1,@

RW

1+d8

MO

V R2,

R1

MO

V

R2,

@R

W1+

d8M

OV R

3, R

1M

OV

R

3,@

RW

1+d8

MO

V R4,

R1

MO

V

R4,

@R

W1+

d8M

OV R

5, R

1M

OV

R

5,@

RW

1+d8

MO

V R6,

R1

MO

V

R6,

@R

W1+

d8M

OV R

7, R

1M

OV

R

7,@

RW

1+d8

+2

MO

V R0,

R2

MO

V

R0,

@R

W2+

d8M

OV R

1, R

2M

OV

R

1,@

RW

2+d8

MO

V R2,

R2

MO

V

R2,

@R

W2+

d8M

OV R

3, R

2M

OV

R

3,@

RW

2+d8

MO

V R4,

R2

MO

V

R4,

@R

W2+

d8M

OV R

5, R

2M

OV

R

5,@

RW

2+d8

MO

V R6,

R2

MO

V

R6,

@R

W2+

d8M

OV R

7, R

2M

OV

R

7,@

RW

2+d8

+3

MO

V R0,

R3

MO

V

R0,

@R

W3+

d8M

OV R

1, R

3M

OV

R

1,@

RW

3+d8

MO

V R2,

R3

MO

V

R2,

@R

W3+

d8M

OV R

3, R

3M

OV

R

3,@

RW

3+d8

MO

V R4,

R3

MO

V

R4,

@R

W3+

d8M

OV R

5, R

3M

OV

R

5,@

RW

3+d8

MO

V R6,

R3

MO

V

R6,

@R

W3+

d8M

OV R

7, R

3M

OV

R

7,@

RW

3+d8

+4

MO

V R0,

R4

MO

V

R0,

@R

W4+

d8M

OV R

1, R

4M

OV

R

1,@

RW

4+d8

MO

V R2,

R4

MO

V

R2,

@R

W4+

d8M

OV R

3, R

4M

OV

R

3,@

RW

4+d8

MO

V R4,

R4

MO

V

R4,

@R

W4+

d8M

OV R

5, R

4M

OV

R

5,@

RW

4+d8

MO

V R6,

R4

MO

V

R6,

@R

W4+

d8M

OV R

7, R

4M

OV

R

7,@

RW

4+d8

+5

MO

V R0,

R5

MO

V

R0,

@R

W5+

d8M

OV R

1, R

5M

OV

R

1,@

RW

5+d8

MO

V R2,

R5

MO

V

R2,

@R

W5+

d8M

OV R

3, R

5M

OV

R

3,@

RW

5+d8

MO

V R4,

R5

MO

V

R4,

@R

W5+

d8M

OV R

5, R

5M

OV

R

5,@

RW

5+d8

MO

V R6,

R5

MO

V

R6,

@R

W5+

d8M

OV R

7, R

5M

OV

R

7,@

RW

5+d8

+6

MO

V R0,

R6

MO

V

R0,

@R

W6+

d8M

OV R

1, R

6M

OV

R

1,@

RW

6+d8

MO

V R2,

R6

MO

V

R2,

@R

W6+

d8M

OV R

3, R

6M

OV

R

3,@

RW

6+d8

MO

V R4,

R6

MO

V

R4,

@R

W6+

d8M

OV R

5, R

6M

OV

R

5,@

RW

6+d8

MO

V R6,

R6

MO

V

R6,

@R

W6+

d8M

OV R

7, R

6M

OV

R

7,@

RW

6+d8

+7

MO

V R0,

R7

MO

V

R0,

@R

W7+

d8M

OV R

1, R

7M

OV

R

1,@

RW

7+d8

MO

V R2,

R7

MO

V

R2,

@R

W7+

d8M

OV R

3, R

7M

OV

R

3,@

RW

7+d8

MO

V R4,

R7

MO

V

R4,

@R

W7+

d8M

OV R

5, R

7M

OV

R

5,@

RW

7+d8

MO

V R6,

R7

MO

V

R6,

@R

W7+

d8M

OV R

7, R

7M

OV

R

7,@

RW

7+d8

+8

MO

VR

0,@

RW

0M

OV

R

0,@

RW

0+d1

6M

OV

R1,

@R

W0

MO

V

R1,

@R

W0+

d16

MO

VR

2,@

RW

0M

OV

R

2,@

RW

0+d1

6M

OV

R3,

@R

W0

MO

V

R3,

@R

W0+

d16

MO

VR

4,@

RW

0M

OV

R

4,@

RW

0+d1

6M

OV

R5,

@R

W0

MO

V

R5,

@R

W0+

d16

MO

VR

6,@

RW

0M

OV

R

6,@

RW

0+d1

6M

OV

R7,

@R

W0

MO

V

R7,

@R

W0+

d16

+9

MO

VR

0,@

RW

1M

OV

R

0,@

RW

1+d1

6M

OV

R1,

@R

W1

MO

V

R1,

@R

W1+

d16

MO

VR

2,@

RW

1M

OV

R

2,@

RW

1+d1

6M

OV

R3,

@R

W1

MO

V

R3,

@R

W1+

d16

MO

VR

4,@

RW

1M

OV

R

4,@

RW

1+d1

6M

OV

R5,

@R

W1

MO

V

R5,

@R

W1+

d16

MO

VR

6,@

RW

1M

OV

R

6,@

RW

1+d1

6M

OV

R7,

@R

W1

MO

V

R7,

@R

W1+

d16

+A

MO

VR

0,@

RW

2M

OV

R

0,@

RW

2+d1

6M

OV

R1,

@R

W2

MO

V

R1,

@R

W2+

d16

MO

VR

2,@

RW

2M

OV

R

2,@

RW

2+d1

6M

OV

R3,

@R

W2

MO

V

R3,

@R

W2+

d16

MO

VR

4,@

RW

2M

OV

R

4,@

RW

2+d1

6M

OV

R5,

@R

W2

MO

V

R5,

@R

W2+

d16

MO

VR

6,@

RW

2M

OV

R

6,@

RW

2+d1

6M

OV

R7,

@R

W2

MO

V

R7,

@R

W2+

d16

+B

MO

VR

0,@

RW

3M

OV

R

0,@

RW

3+d1

6M

OV

R1,

@R

W3

MO

V

R1,

@R

W3+

d16

MO

VR

2,@

RW

3M

OV

R

2,@

RW

3+d1

6M

OV

R3,

@R

W3

MO

V

R3,

@R

W3+

d16

MO

VR

4,@

RW

3M

OV

R

4,@

RW

3+d1

6M

OV

R5,

@R

W3

MO

V

R5,

@R

W3+

d16

MO

VR

6,@

RW

3M

OV

R

6,@

RW

3+d1

6M

OV

R7,

@R

W3

MO

V

R7,

@R

W3+

d16

+C

MO

V

R0,

@R

W0+

MO

V R

0,@

RW

0+RW

7M

OV

R

1,@

RW

0+M

OV

R1,

@R

W0+

RW7

MO

V

R2,

@R

W0+

MO

V R

2,@

RW0+

RW

7M

OV

R

3,@

RW

0+M

OV

R3,

@RW

0+R

W7

MO

V

R4,

@R

W0+

MO

V R

4,@

RW

0+RW

7M

OV

R

5,@

RW

0+M

OV

R5,

@R

W0+

RW7

MO

V

R6,

@R

W0+

MO

V R

6,@

RW

0+RW

7M

OV

R

7,@

RW

0+M

OV

R7,

@RW

0+R

W7

+D

MO

V

R0,

@R

W1+

MO

V R

0,@

RW

1+RW

7M

OV

R

1,@

RW

1+M

OV

R1,

@R

W1+

RW7

MO

V

R2,

@R

W1+

MO

V R

2,@

RW1+

RW

7M

OV

R

3,@

RW

1+M

OV

R3,

@RW

1+R

W7

MO

V

R4,

@R

W1+

MO

V R

4,@

RW

1+RW

7M

OV

R

5,@

RW

1+M

OV

R5,

@R

W1+

RW7

MO

V

R6,

@R

W1+

MO

V R

6,@

RW

1+RW

7M

OV

R

7,@

RW

1+M

OV

R7,

@RW

1+R

W7

+E

MO

V

R0,

@R

W2+

MO

V

R0,

@P

C+

d16

MO

V

R1,

@R

W2+

MO

V

R1,

@P

C+

d16

MO

V

R2,

@R

W2+

MO

V

R2,

@P

C+

d16

MO

V

R3,

@R

W2+

MO

V

R3,

@P

C+

d16

MO

V

R4,

@R

W2+

MO

V

R4,

@P

C+

d16

MO

V

R5,

@R

W2+

MO

V

R5,

@P

C+

d16

MO

V

R6,

@R

W2+

MO

V

R6,

@P

C+

d16

MO

V

R7,

@R

W2+

MO

V

R7,

@P

C+

d16

+F

MO

V

R0,

@R

W3+

MO

V

R0,

addr

16M

OV

R

1,@

RW

3+M

OV

R

1,ad

dr16

MO

V

R2,

@R

W3+

MO

V

R2,

addr

16M

OV

R

3,@

RW

3+M

OV

R

3,ad

dr16

MO

V

R4,

@R

W3+

MO

V

R4,

addr

16M

OV

R

5,@

RW

3+M

OV

R

5,ad

dr16

MO

V

R6,

@R

W3+

MO

V

R6,

addr

16M

OV

R

7,@

RW

3+M

OV

R

7,ad

dr16



C.9 MOVW RWi, ea Instruction Map

Table C.9-1 lists MOVW RWi, ea instruction map.



Table C.9-1 MOVW RWi, ea Instruction (First Byte = 7BH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

VW

RW

0, R

W0

MO

VW

@R

W0+

d8M

OV

WR

W1,

RW

0M

OV

W R

W1,

@R

W0+

d8M

OV

WR

W2,

RW

0M

OV

W R

W2,

@R

W0+

d8M

OV

WR

W3,

RW

0M

OV

W R

W3,

@R

W0+

d8M

OV

WR

W4,

RW

0M

OV

W R

W4,

@R

W0+

d8M

OV

WR

W5,

RW

0M

OV

W R

W5,

@R

W0+

d8M

OV

WR

W6,

RW

0M

OV

W R

W6,

@R

W0+

d8M

OV

WR

W7,

RW

0M

OV

W R

W7,

@R

W0+

d8

+1

MO

VW

RW

0, R

W1

MO

VW

@R

W1+

d8M

OV

WR

W1,

RW

1M

OV

W R

W1,

@R

W1+

d8M

OV

WR

W2,

RW

1M

OV

W R

W2,

@R

W1+

d8M

OV

WR

W3,

RW

1M

OV

W R

W3,

@R

W1+

d8M

OV

WR

W4,

RW

1M

OV

W R

W4,

@R

W1+

d8M

OV

WR

W5,

RW

1M

OV

W R

W5,

@R

W1+

d8M

OV

WR

W6,

RW

1M

OV

W R

W6,

@R

W1+

d8M

OV

WR

W7,

RW

1M

OV

W R

W7,

@R

W1+

d8

+2

MO

VW

RW

0, R

W2

MO

VW

@R

W2+

d8M

OV

WR

W1,

RW

2M

OV

W R

W1,

@R

W2+

d8M

OV

WR

W2,

RW

2M

OV

W R

W2,

@R

W2+

d8M

OV

WR

W3,

RW

2M

OV

W R

W3,

@R

W2+

d8M

OV

WR

W4,

RW

2M

OV

W R

W4,

@R

W2+

d8M

OV

WR

W5,

RW

2M

OV

W R

W5,

@R

W2+

d8M

OV

WR

W6,

RW

2M

OV

W R

W6,

@R

W2+

d8M

OV

WR

W7,

RW

2M

OV

W R

W7,

@R

W2+

d8

+3

MO

VW

RW

0, R

W3

MO

VW

@R

W3+

d8M

OV

WR

W1,

RW

3M

OV

W R

W1,

@R

W3+

d8M

OV

WR

W2,

RW

3M

OV

W R

W2,

@R

W3+

d8M

OV

WR

W3,

RW

3M

OV

W R

W3,

@R

W3+

d8M

OV

WR

W4,

RW

3M

OV

W R

W4,

@R

W3+

d8M

OV

WR

W5,

RW

3M

OV

W R

W5,

@R

W3+

d8M

OV

WR

W6,

RW

3M

OV

W R

W6,

@R

W3+

d8M

OV

WR

W7,

RW

3M

OV

W R

W7,

@R

W3+

d8

+4

MO

VW

RW

0, R

W4

MO

VW

@R

W4+

d8M

OV

WR

W1,

RW

4M

OV

W R

W1,

@R

W4+

d8M

OV

WR

W2,

RW

4M

OV

W R

W2,

@R

W4+

d8M

OV

WR

W3,

RW

4M

OV

W R

W3,

@R

W4+

d8M

OV

WR

W4,

RW

4M

OV

W R

W4,

@R

W4+

d8M

OV

WR

W5,

RW

4M

OV

W R

W5,

@R

W4+

d8M

OV

WR

W6,

RW

4M

OV

W R

W6,

@R

W4+

d8M

OV

WR

W7,

RW

4M

OV

W R

W7,

@R

W4+

d8

+5

MO

VW

RW

0, R

W5

MO

VW

@R

W5+

d8M

OV

WR

W1,

RW

5M

OV

W R

W1,

@R

W5+

d8M

OV

WR

W2,

RW

5M

OV

W R

W2,

@R

W5+

d8M

OV

WR

W3,

RW

5M

OV

W R

W3,

@R

W5+

d8M

OV

WR

W4,

RW

5M

OV

W R

W4,

@R

W5+

d8M

OV

WR

W5,

RW

5M

OV

W R

W5,

@R

W5+

d8M

OV

WR

W6,

RW

5M

OV

W R

W6,

@R

W5+

d8M

OV

WR

W7,

RW

5M

OV

W R

W7,

@R

W5+

d8

+6

MO

VW

RW

0, R

W6

MO

VW

@R

W6+

d8M

OV

WR

W1,

RW

6M

OV

W R

W1,

@R

W6+

d8M

OV

WR

W2,

RW

6M

OV

W R

W2,

@R

W6+

d8M

OV

WR

W3,

RW

6M

OV

W R

W3,

@R

W6+

d8M

OV

WR

W4,

RW

6M

OV

W R

W4,

@R

W6+

d8M

OV

WR

W5,

RW

6M

OV

W R

W5,

@R

W6+

d8M

OV

WR

W6,

RW

6M

OV

W R

W6,

@R

W6+

d8M

OV

WR

W7,

RW

6M

OV

W R

W7,

@R

W6+

d8

+7

MO

VW

RW

0, R

W7

MO

VW

@R

W7+

d8M

OV

WR

W1,

RW

7M

OV

W R

W1,

@R

W7+

d8M

OV

WR

W2,

RW

7M

OV

W R

W2,

@R

W7+

d8M

OV

WR

W3,

RW

7M

OV

W R

W3,

@R

W7+

d8M

OV

WR

W4,

RW

7M

OV

W R

W4,

@R

W7+

d8M

OV

WR

W5,

RW

7M

OV

W R

W5,

@R

W7+

d8M

OV

WR

W6,

RW

7M

OV

W R

W6,

@R

W7+

d8M

OV

WR

W7,

RW

7M

OV

W R

W7,

@R

W7+

d8

+8

MO

VW

RW

0,@

RW

0M

OV

W@

RW

0+d1

6M

OV

WR

W1,

@R

W0

MO

VW

RW

1,@

RW

0+d1

6M

OV

WR

W2,

@R

W0

MO

VW

RW

2,@

RW

0+d1

6M

OV

WR

W3,

@R

W0

MO

VW

RW

3,@

RW

0+d1

6M

OV

WR

W4,

@R

W0

MO

VW

RW

4,@

RW

0+d1

6M

OV

WR

W5,

@R

W0

MO

VW

RW

5,@

RW

0+d1

6M

OV

WR

W6,

@R

W0

MO

VW

RW

6,@

RW

0+d1

6M

OV

WR

W7,

@R

W0

MO

VW

RW

7,@

RW

0+d1

6

+9

MO

VW

RW

0,@

RW

1M

OV

W@

RW

1+d1

6M

OV

WR

W1,

@R

W1

MO

VW

RW

1,@

RW

1+d1

6M

OV

WR

W2,

@R

W1

MO

VW

RW

2,@

RW

1+d1

6M

OV

WR

W3,

@R

W1

MO

VW

RW

3,@

RW

1+d1

6M

OV

WR

W4,

@R

W1

MO

VW

RW

4,@

RW

1+d1

6M

OV

WR

W5,

@R

W1

MO

VW

RW

5,@

RW

1+d1

6M

OV

WR

W6,

@R

W1

MO

VW

RW

6,@

RW

1+d1

6M

OV

WR

W7,

@R

W1

MO

VW

RW

7,@

RW

1+d1

6

+A

MO

VW

RW

0,@

RW

2M

OV

W@

RW

2+d1

6M

OV

WR

W1,

@R

W2

MO

VW

RW

1,@

RW

2+d1

6M

OV

WR

W2,

@R

W2

MO

VW

RW

2,@

RW

2+d1

6M

OV

WR

W3,

@R

W2

MO

VW

RW

3,@

RW

2+d1

6M

OV

WR

W4,

@R

W2

MO

VW

RW

4,@

RW

2+d1

6M

OV

WR

W5,

@R

W2

MO

VW

RW

5,@

RW

2+d1

6M

OV

WR

W6,

@R

W2

MO

VW

RW

6,@

RW

2+d1

6M

OV

WR

W7,

@R

W2

MO

VW

RW

7,@

RW

2+d1

6

+B

MO

VW

RW

0,@

RW

3M

OV

W@

RW

3+d1

6M

OV

WR

W1,

@R

W3

MO

VW

RW

1,@

RW

3+d1

6M

OV

WR

W2,

@R

W3

MO

VW

RW

2,@

RW

3+d1

6M

OV

WR

W3,

@R

W3

MO

VW

RW

3,@

RW

3+d1

6M

OV

WR

W4,

@R

W3

MO

VW

RW

4,@

RW

3+d1

6M

OV

WR

W5,

@R

W3

MO

VW

RW

5,@

RW

3+d1

6M

OV

WR

W6,

@R

W3

MO

VW

RW

6,@

RW

3+d1

6M

OV

WR

W7,

@R

W3

MO

VW

RW

7,@

RW

3+d1

6

+C

MO

VW

RW

0,@

RW

0+M

OV

W@

RW

0+R

W7

MO

VW

RW

1,@

RW

0+M

OV

W R

W1,

@R

W0+

RW

7M

OV

WR

W2,

@R

W0+

MO

VW

RW

2,@

RW

0+R

W7

MO

VW

RW

3,@

RW

0+M

OV

W R

W3,

@R

W0+

RW

7M

OV

WR

W4,

@R

W0+

MO

VW

RW

4,@

RW

0+R

W7

MO

VW

RW

5,@

RW

0+M

OV

W R

W5,

@R

W0+

RW

7M

OV

WR

W6,

@R

W0+

MO

VW

RW

6,@

RW

0+R

W7

MO

VW

RW

7,@

RW

0+M

OV

W R

W7,

@R

W0+

RW

7

+D

MO

VWRW

0, @

RW1+

MO

VW

@R

W1+

RW

7M

OVW

RW

1, @

RW

1+M

OV

W R

W1,

@R

W1+

RW

7M

OVW

RW

2, @

RW

1+M

OV

W R

W2,

@R

W1+

RW

7M

OVW

RW3,

@RW

1+M

OV

W R

W3,

@R

W1+

RW

7M

OVW

RW

4, @

RW

1+M

OV

W R

W4,

@R

W1+

RW

7M

OVW

RW

5, @

RW

1+M

OV

W@

RW

1+R

W7

MO

VWRW

6, @

RW1+

MO

VW

RW

6,@

RW

1+R

W7

MO

VWR

W7,

@R

W1+

MO

VW

RW

7,@

RW

1+R

W7

+E

MO

VWR

W0,

@R

W2+

MO

VW

@P

C+

d16

MO

VWR

W1,

@R

W2+

MO

VW

RW

1,@

PC

+d16

MO

VWRW

2, @

RW2+

MO

VW

RW

2,@

PC

+d16

MO

VWR

W3,

@R

W2+

MO

VW

RW

3,@

PC

+d16

MO

VWR

W4,

@R

W2+

MO

VW

RW

4,@

PC

+d16

MO

VWRW

5, @

RW2+

MO

VW

@P

C+

d16

MO

VWR

W6,

@R

W2+

MO

VW

RW

6,@

PC

+d16

MO

VWR

W7,

@RW

2+M

OV

W R

W7,

@P

C+d

16

+F

MO

VWR

W0,

@R

W3+

MO

VW

RW

0, a

ddr1

6M

OVW

RW

1, @

RW

3+M

OV

WR

W1,

add

r16

MO

VWRW

2, @

RW3+

MO

VW

RW

2, a

ddr1

6M

OVW

RW

3, @

RW

3+M

OV

WR

W3,

add

r16

MO

VWR

W4,

@R

W3+

MO

VW

RW

4, a

ddr1

6M

OVW

RW5,

@RW

3+M

OV

WR

W5,

add

r16

MO

VWR

W6,

@R

W3+

MO

VW

RW

6, a

ddr1

6M

OVW

RW

7, @

RW3+

MO

VW

RW

7, a

ddr1

6



C.10 MOV ea, Ri Instruction Map

Table C.10-1 lists MOV ea, Ri instruction map.



Table C.10-1 MOV ea, Ri Instruction (First Byte = 7CH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

V R0,

R0

MO

V@

RW

0+d8

, R0

MO

V R0,

R1

MO

V@

RW

0+d8

, R1

MO

V R0,

R2

MO

V@

RW

0+d8

, R2

MO

V R0,

R3

MO

V@

RW

0+d8

, R3

MO

V R0,

R4

MO

V@

RW

0+d8

, R4

MO

V R0,

R5

MO

V@

RW

0+d8

, R5

MO

V R0,

R6

MO

V@

RW

0+d8

, R6

MO

V R0,

R7

MO

V@

RW

0+d8

, R7

+1

MO

V R1,

R0

MO

V@

RW

1+d8

, R0

MO

V R1,

R1

MO

V@

RW

1+d8

, R1

MO

V R1,

R2

MO

V@

RW

1+d8

, R2

MO

V R1,

R3

MO

V@

RW

1+d8

, R3

MO

V R1,

R4

MO

V@

RW

1+d8

, R4

MO

V R1,

R5

MO

V@

RW

1+d8

, R5

MO

V R1,

R6

MO

V@

RW

1+d8

, R6

MO

V R1,

R7

MO

V@

RW

1+d8

, R7

+2

MO

V R2,

R0

MO

V@

RW

2+d8

, R0

MO

V R2,

R1

MO

V@

RW

2+d8

, R1

MO

V R2,

R2

MO

V@

RW

2+d8

, R2

MO

V R2,

R3

MO

V@

RW

2+d8

, R3

MO

V R2,

R4

MO

V@

RW

2+d8

, R4

MO

V R2,

R5

MO

V@

RW

2+d8

, R5

MO

V R2,

R6

MO

V@

RW

2+d8

, R6

MO

V R2,

R7

MO

V@

RW

2+d8

, R7

+3

MO

V R3,

R0

MO

V@

RW

3+d8

, R0

MO

V R3,

R1

MO

V@

RW

3+d8

, R1

MO

V R3,

R2

MO

V@

RW

3+d8

, R2

MO

V R3,

R3

MO

V@

RW

3+d8

, R3

MO

V R3,

R4

MO

V@

RW

3+d8

, R4

MO

V R3,

R5

MO

V@

RW

3+d8

, R5

MO

V R3,

R6

MO

V@

RW

3+d8

, R6

MO

V R3,

R7

MO

V@

RW

3+d8

, R7

+4

MO

V R4,

R0

MO

V@

RW

4+d8

, R0

MO

V R4,

R1

MO

V@

RW

4+d8

, R1

MO

V R4,

R2

MO

V@

RW

4+d8

, R2

MO

V R4,

R3

MO

V@

RW

4+d8

, R3

MO

V R4,

R4

MO

V@

RW

4+d8

, R4

MO

V R4,

R5

MO

V@

RW

4+d8

, R5

MO

V R4,

R6

MO

V@

RW

4+d8

, R6

MO

V R4,

R7

MO

V@

RW

4+d8

, R7

+5

MO

V R5,

R0

MO

V@

RW

5+d8

, R0

MO

V R5,

R1

MO

V@

RW

5+d8

, R1

MO

V R5,

R2

MO

V@

RW

5+d8

, R2

MO

V R5,

R3

MO

V@

RW

5+d8

, R3

MO

V R5,

R4

MO

V@

RW

5+d8

, R4

MO

V R5,

R5

MO

V@

RW

5+d8

, R5

MO

V R5,

R6

MO

V@

RW

5+d8

, R6

MO

V R5,

R7

MO

V@

RW

5+d8

, R7

+6

MO

V R6,

R0

MO

V@

RW

6+d8

, R0

MO

V R6,

R1

MO

V@

RW

6+d8

, R1

MO

V R6,

R2

MO

V@

RW

6+d8

, R2

MO

V R6,

R3

MO

V@

RW

6+d8

, R3

MO

V R6,

R4

MO

V@

RW

6+d8

, R4

MO

V R6,

R5

MO

V@

RW

6+d8

, R5

MO

V R6,

R6

MO

V@

RW

6+d8

, R6

MO

V R6,

R7

MO

V@

RW

6+d8

, R7

+7

MO

V R7,

R0

MO

V@

RW

7+d8

, R0

MO

V R7,

R1

MO

V@

RW

7+d8

, R1

MO

V R7,

R2

MO

V@

RW

7+d8

, R2

MO

V R7,

R3

MO

V@

RW

7+d8

, R3

MO

V R7,

R4

MO

V@

RW

7+d8

, R4

MO

V R7,

R5

MO

V@

RW

7+d8

, R5

MO

V R7,

R6

MO

V@

RW

7+d8

, R6

MO

V R7,

R7

MO

V@

RW

7+d8

, R7

+8

MO

V@

RW

0, R

0M

OV

@RW

0+d1

6, R

0M

OV

@R

W0,

R1

MO

V@

RW

0+d1

6, R

1M

OV

@R

W0,

R2

MO

V@

RW

0+d1

6, R

2M

OV

@R

W0,

R3

MO

V@

RW

0+d1

6, R

3M

OV

@R

W0,

R4

MO

V@

RW

0+d1

6, R

4M

OV

@R

W0,

R5

MO

V@

RW

0+d1

6, R

5M

OV

@R

W0,

R6

MO

V@

RW

0+d1

6,

R6

MO

V@

RW

0, R

7M

OV

@RW

0+d1

6, R

7

+9

MO

V@

RW

1, R

0M

OV

@RW

1+d1

6, R

0M

OV

@R

W1,

R1

MO

V@

RW

1+d1

6, R

1M

OV

@R

W1,

R2

MO

V@

RW

1+d1

6, R

2M

OV

@R

W1,

R3

MO

V@

RW

1+d1

6, R

3M

OV

@R

W1,

R4

MO

V@

RW

1+d1

6, R

4M

OV

@R

W1,

R5

MO

V@

RW

1+d1

6, R

5M

OV

@R

W1,

R6

MO

V@

RW

1+d1

6, R

6M

OV

@R

W1,

R7

MO

V@

RW1+

d16,

R7

+A

MO

V@

RW

2, R

0M

OV

@RW

2+d1

6, R

0M

OV

@R

W2,

R1

MO

V@

RW

2+d1

6, R

1M

OV

@R

W2,

R2

MO

V@

RW

2+d1

6, R

2M

OV

@R

W2,

R3

MO

V@

RW

2+d1

6, R

3M

OV

@R

W2,

R4

MO

V@

RW

2+d1

6, R

4M

OV

@R

W2,

R5

MO

V@

RW

2+d1

6, R

5M

OV

@R

W2,

R6

MO

V@

RW

2+d1

6, R

6M

OV

@R

W2,

R7

MO

V@

RW2+

d16,

R7

+B

MO

V@

RW

3, R

0M

OV

@RW

3+d1

6, R

0M

OV

@R

W3,

R1

MO

V@

RW

3+d1

6, R

1M

OV

@R

W3,

R2

MO

V@

RW

3+d1

6, R

2M

OV

@R

W3,

R3

MO

V@

RW

3+d1

6, R

3M

OV

@R

W3,

R4

MO

V@

RW

3+d1

6, R

4M

OV

@R

W3,

R5

MO

V@

RW

3+d1

6, R

5M

OV

@R

W3,

R6

MO

V@

RW

3+d1

6, R

6M

OV

@R

W3,

R7

MO

V@

RW3+

d16,

R7

+C

MO

V@

RW

0+, R

0M

OV

@RW

0+R

W7,

R0

MO

V@

RW

0+, R

1M

OV

@R

W0+

RW

7, R

1M

OV

@R

W0+

, R2

MO

V@

RW

0+R

W7,

R2

MO

V@

RW

0+, R

3M

OV

@R

W0+

RW

7, R

3M

OV

@R

W0+

, R4

MO

V@

RW

0+R

W7,

R4

MO

V@

RW

0+, R

5M

OV

@R

W0+

RW

7, R

5M

OV

@R

W0+

, R6

MO

V@

RW

0+RW

7, R

6M

OV

@R

W0+

, R7

MO

V@

RW0+

RW7,

R7

+D

MO

V@

RW

1+, R

0M

OV

@RW

1+R

W7,

R0

MO

V@

RW

1+, R

1M

OV

@R

W1+

RW

7, R

1M

OV

@R

W1+

, R2

MO

V@

RW

1+R

W7,

R2

MO

V@

RW

1+, R

3M

OV

@R

W1+

RW

7, R

3M

OV

@R

W1+

, R4

MO

V@

RW

1+R

W7,

R4

MO

V@

RW

1+, R

5M

OV

@R

W1+

RW

7, R

5M

OV

@R

W1+

, R6

MO

V@

RW

1+RW

7, R

6M

OV

@R

W1+

, R7

MO

V@

RW1+

RW7,

R7

+E

MO

V@

RW

2+, R

0M

OV

@P

C+d

16, R

0M

OV

@R

W2+

, R1

MO

V@

PC

+d16

, R1

MO

V@

RW

2+, R

2M

OV

@P

C+d

16, R

2M

OV

@R

W2+

, R3

MO

V@

PC

+d16

, R3

MO

V@

RW

2+, R

4M

OV

@P

C+d

16, R

4M

OV

@R

W2+

, R5

MO

V@

PC

+d16

, R5

MO

V@

RW

2+, R

6M

OV

@P

C+d

16, R

6M

OV

@R

W2+

, R7

MO

V@

PC

+d16

, R7

+F

MO

V@

RW

3+, R

0M

OV

addr

16, R

0M

OV

@R

W3+

, R1

MO

Vad

dr16

, R1

MO

V@

RW

3+, R

2M

OV

addr

16, R

2M

OV

@R

W3+

, R3

MO

Vad

dr16

, R3

MO

V@

RW

3+, R

4M

OV

addr

16, R

4M

OV

@R

W3+

, R5

MO

Vad

dr16

, R5

MO

V@

RW

3+, R

6M

OV

addr

16, R

6M

OV

@R

W3+

, R7

MO

Vad

dr16

, R7



C.11 MOVW ea, RWi Instruction Map

Table C.11-1 lists MOVW ea, RWi instruction map.



Table C.11-1 MOVW ea, RWi Instruction (First Byte = 7DH)

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

MO

VW

RW

0, R

W0

MO

VW@

RW

0+d8

, RW

0M

OV

WR

W0,

RW

1M

OVW

@RW

0+d8

, RW

1M

OV

WR

W0,

RW

2M

OVW

@RW

0+d8

, RW

2M

OV

WR

W0,

RW

3M

OVW

@R

W0+

d8, R

W3

MO

VW

RW

0, R

W4

MO

VW@

RW

0+d8

, RW

4M

OV

WR

W0,

RW

5M

OVW

@RW

0+d8

, RW

5M

OV

WR

W0,

RW

6M

OVW

@RW

0+d8

, RW

6M

OV

WR

W0,

RW

7M

OVW

@R

W0+

d8, R

W7

+1

MO

VW

RW

1, R

W0

MO

VW@

RW

1+d8

, RW

0M

OV

WR

W1,

RW

1M

OVW

@RW

1+d8

, RW

1M

OV

WR

W1,

RW

2M

OVW

@RW

1+d8

, RW

2M

OV

WR

W1,

RW

3M

OVW

@R

W1+

d8, R

W3

MO

VW

RW

1, R

W4

MO

VW@

RW

1+d8

, RW

4M

OV

WR

W1,

RW

5M

OVW

@RW

1+d8

, RW

5M

OV

WR

W1,

RW

6M

OVW

@RW

1+d8

, RW

6M

OV

WR

W1,

RW

7M

OVW

@R

W1+

d8, R

W7

+2

MO

VW

RW

2, R

W0

MO

VW@

RW

2+d8

, RW

0M

OV

WR

W2,

RW

1M

OVW

@RW

2+d8

, RW

1M

OV

WR

W2,

RW

2M

OVW

@RW

2+d8

, RW

2M

OV

WR

W2,

RW

3M

OVW

@R

W2+

d8, R

W3

MO

VW

RW

2, R

W4

MO

VW@

RW

2+d8

, RW

4M

OV

WR

W2,

RW

5M

OVW

@RW

2+d8

, RW

5M

OV

WR

W2,

RW

6M

OVW

@RW

2+d8

, RW

6M

OV

WR

W2,

RW

7M

OVW

@R

W2+

d8, R

W7

+3

MO

VW

RW

3, R

W0

MO

VW@

RW

3+d8

, RW

0M

OV

WR

W3,

RW

1M

OVW

@RW

3+d8

, RW

1M

OV

WR

W3,

RW

2M

OVW

@RW

3+d8

, RW

2M

OV

WR

W3,

RW

3M

OVW

@R

W3+

d8, R

W3

MO

VW

RW

3, R

W4

MO

VW@

RW

3+d8

, RW

4M

OV

WR

W3,

RW

5M

OVW

@RW

3+d8

, RW

5M

OV

WR

W3,

RW

6M

OVW

@RW

3+d8

, RW

6M

OV

WR

W3,

RW

7M

OVW

@R

W3+

d8, R

W7

+4

MO

VW

RW

4, R

W0

MO

VW@

RW

4+d8

, RW

0M

OV

WR

W4,

RW

1M

OVW

@RW

4+d8

, RW

1M

OV

WR

W4,

RW

2M

OVW

@RW

4+d8

, RW

2M

OV

WR

W4,

RW

3M

OVW

@R

W4+

d8, R

W3

MO

VW

RW

4, R

W4

MO

VW@

RW

4+d8

, RW

4M

OV

WR

W4,

RW

5M

OVW

@RW

4+d8

, RW

5M

OV

WR

W4,

RW

6M

OVW

@RW

4+d8

, RW

6M

OV

WR

W4,

RW

7M

OVW

@R

W4+

d8, R

W7

+5

MO

VW

RW

5, R

W0

MO

VW@

RW

5+d8

, RW

0M

OV

WR

W5,

RW

1M

OVW

@RW

5+d8

, RW

1M

OV

WR

W5,

RW

2M

OVW

@RW

5+d8

, RW

2M

OV

WR

W5,

RW

3M

OVW

@R

W5+

d8, R

W3

MO

VW

RW

5, R

W4

MO

VW@

RW

5+d8

, RW

4M

OV

WR

W5,

RW

5M

OVW

@RW

5+d8

, RW

5M

OV

WR

W5,

RW

6M

OVW

@RW

5+d8

, RW

6M

OV

WR

W5,

RW

7M

OVW

@R

W5+

d8, R

W7

+6

MO

VW

RW

6, R

W0

MO

VW@

RW

6+d8

, RW

0M

OV

WR

W6,

RW

1M

OVW

@RW

6+d8

, RW

1M

OV

WR

W6,

RW

2M

OVW

@RW

6+d8

, RW

2M

OV

WR

W6,

RW

3M

OVW

@R

W6+

d8, R

W3

MO

VW

RW

6, R

W4

MO

VW@

RW

6+d8

, RW

4M

OV

WR

W6,

RW

5M

OVW

@RW

6+d8

, RW

5M

OV

WR

W6,

RW

6M

OVW

@RW

6+d8

, RW

6M

OV

WR

W6,

RW

7M

OVW

@R

W6+

d8, R

W7

+7

MO

VW

RW

7, R

W0

MO

VW@

RW

7+d8

, RW

0M

OV

WR

W7,

RW

1M

OVW

@RW

7+d8

, RW

1M

OV

WR

W7,

RW

2M

OVW

@RW

7+d8

, RW

2M

OV

WR

W7,

RW

3M

OVW

@R

W7+

d8, R

W3

MO

VW

RW

7, R

W4

MO

VW@

RW

7+d8

, RW

4M

OV

WR

W7,

RW

5M

OVW

@RW

7+d8

, RW

5M

OV

WR

W7,

RW

6M

OVW

@RW

7+d8

, RW

6M

OV

WR

W7,

RW

7M

OVW

@R

W7+

d8, R

W7

+8

MO

VW

@R

W0,

RW

0M

OV

W@

RW

0+d

16, R

W0

MO

VW

@R

W0,

RW

1M

OV

W@

RW

0+d

16, R

W1

MO

VW

@R

W0,

RW

2M

OV

W@

RW

0+d

16, R

W2

MO

VW

@R

W0,

RW

3M

OV

W@

RW

0+d

16, R

W3

MO

VW

@R

W0,

RW

4M

OV

W@

RW

0+d

16, R

W4

MO

VW

@R

W0,

RW

5M

OV

W@

RW

0+d

16, R

W5

MO

VW

@R

W0,

RW

6M

OV

W@

RW

0+d

16, R

W6

MO

VW

@R

W0,

RW

7M

OV

W@

RW

0+d

16, R

W7

+9

MO

VW

@R

W1,

RW

0M

OV

W@

RW

1+d

16, R

W0

MO

VW

@R

W1,

RW

1M

OV

W@

RW

1+d

16, R

W1

MO

VW

@R

W1,

RW

2M

OV

W@

RW

1+d

16, R

W2

MO

VW

@R

W1,

RW

3M

OV

W@

RW

1+d

16, R

W3

MO

VW

@R

W1,

RW

4M

OV

W@

RW

1+d

16, R

W4

MO

VW

@R

W1,

RW

5M

OV

W@

RW

1+d

16, R

W5

MO

VW

@R

W1,

RW

6M

OV

W@

RW

1+d

16, R

W6

MO

VW

@R

W1,

RW

7M

OV

W@

RW

1+d

16, R

W7

+A

MO

VW

@R

W2,

RW

0M

OV

W@

RW

2+d

16, R

W0

MO

VW

@R

W2,

RW

1M

OV

W@

RW

2+d

16, R

W1

MO

VW

@R

W2,

RW

2M

OV

W@

RW

2+d

16, R

W2

MO

VW

@R

W2,

RW

3M

OV

W@

RW

2+d

16, R

W3

MO

VW

@R

W2,

RW

4M

OV

W@

RW

2+d

16, R

W4

MO

VW

@R

W2,

RW

5M

OV

W@

RW

2+d

16, R

W5

MO

VW

@R

W2,

RW

6M

OV

W@

RW

2+d

16, R

W6

MO

VW

@R

W2,

RW

7M

OV

W@

RW

2+d

16, R

W7

+B

MO

VW

@R

W3,

RW

0M

OV

W@

RW

3+d

16, R

W0

MO

VW

@R

W3,

RW

1M

OV

W@

RW

3+d

16, R

W1

MO

VW

@R

W3,

RW

2M

OV

W@

RW

3+d

16, R

W2

MO

VW

@R

W3,

RW

3M

OV

W@

RW

3+d

16, R

W3

MO

VW

@R

W3,

RW

4M

OV

W@

RW

3+d

16, R

W4

MO

VW

@R

W3,

RW

5M

OV

W@

RW

3+d

16, R

W5

MO

VW

@R

W3,

RW

6M

OV

W@

RW

3+d

16, R

W6

MO

VW

@R

W3,

RW

7M

OV

W@

RW

3+d

16, R

W7

+C

MO

VW@

RW0+

,RW

0M

OV

W@

RW

0+R

W7,

RW

0M

OVW

@RW

0+, R

W1

MO

VW

@R

W0

+RW

7,R

W1

MO

VW@

RW0+

,RW

2M

OV

W@

RW

0+R

W7,

RW

2M

OVW

@RW

0+,R

W3

MO

VW

@R

W0

+RW

7,R

W3

MO

VW@

RW

0+,R

W4

MO

VW

@R

W0

+RW

7,R

W4

MO

VW@

RW

0+,R

W5

MO

VW

@R

W0

+RW

7,R

W5

MO

VW@

RW0+

,RW

6M

OV

W@

RW

0+R

W7,

RW

6M

OVW

@RW

0+,R

W7

MO

VW

@R

W0

+RW

7,R

W7

+D

MO

VW@

RW1+

,RW

0M

OV

W@

RW

1+R

W7,

RW

0M

OV

W@

RW

1+,R

W1

MO

VW

@R

W1

+RW

7,R

W1

MO

VW@

RW1+

,RW

2M

OV

W@

RW

1+R

W7,

RW

2M

OVW

@RW

1+,R

W3

MO

VW

@R

W1

-+R

W7,

RW

3M

OVW

@R

W1+

,RW

4M

OV

W@

RW

1+R

W7,

RW

4M

OVW

@R

W1+

,RW

5M

OV

W@

RW

1+R

W7,

RW

5M

OVW

@RW

1+,R

W6

MO

VW

@R

W1

+RW

7,R

W6

MO

VW@

RW1+

,RW

7M

OV

W@

RW

1+R

W7,

RW

7

+E

MO

VW@

RW2+

,RW

0M

OV

W@

PC

+d1

6, R

W0

MO

VW

@R

W2+

,RW

1M

OV

W@

PC

+d1

6, R

W1

MO

VW@

RW2+

,RW

2M

OV

W@

PC

+d1

6, R

W2

MO

VW@

RW2+

,RW

3M

OV

W@

PC

+d1

6, R

W3

MO

VW@

RW

2+,R

W4

MO

VW

@P

C+

d16,

RW

4M

OVW

@R

W2+

,RW

5M

OV

W@

PC

+d1

6, R

W5

MO

VW@

RW2+

,RW

6M

OV

W @

PC

+d1

6, R

W6

MO

VW@

RW2+

,RW

7M

OV

W@

PC

+d1

6, R

W7

+F

MO

VW@

RW3+

,RW

0M

OV

Wad

dr16

, RW

0M

OV

W@

RW

3+,R

W1

MO

VW

addr

16, R

W1

MO

VW@

RW3+

,RW

2M

OV

Wad

dr16

, RW

2M

OVW

@RW

3+,R

W3

MO

VW

addr

16, R

W3

MO

VW@

RW

3+,R

W4

MO

VW

addr

16, R

W4

MO

VW@

RW

3+,R

W5

MO

VW

addr

16, R

W5

MO

VW@

RW3+

,RW

6M

OV

Wad

dr16

, RW

6M

OVW

@RW

3+,R

W7

MO

VW

addr

16, R

W7



C.12 XCH Ri, ea Instruction Map

Table C.12-1 lists XCH Ri, ea instruction map.



Table C.12-1 XCH Ri, ea Instruction (First Byte = 7EH)

0010

2030

4050

6070

8090

AB

0C

0D

0E

0F

0

+0

XC

H R0,

R0

XC

H

R0,

@R

W0+

d8X

CH R

1, R

0X

CH

R

1,@

RW

0+d8

XC

H R2,

R0

XC

H

R2,

@R

W0+

d8X

CH R

3, R

0X

CH

R

3,@

RW

0+d8

XC

H R4,

R0

XC

H

R4,

@R

W0+

d8X

CH R

5, R

0X

CH

R

5,@

RW

0+d8

XC

H R6,

R0

XC

H

R6,

@R

W0+

d8X

CH R

7, R

0X

CH

R

7,@

RW

0+d8

+1

XC

H R0,

R1

XC

H

R0,

@R

W1+

d8X

CH R

1, R

1X

CH

R

1,@

RW

1+d8

XC

H R2,

R1

XC

H

R2,

@R

W1+

d8X

CH R

3, R

1X

CH

R

3,@

RW

1+d8

XC

H R4,

R1

XC

H

R4,

@R

W1+

d8X

CH R

5, R

1X

CH

R

5,@

RW

1+d8

XC

H R6,

R1

XC

H

R6,

@R

W1+

d8X

CH R

7, R

1X

CH

R

7,@

RW

1+d8

+2

XC

H R0,

R2

XC

H

R0,

@R

W2+

d8X

CH R

1, R

2X

CH

R

1,@

RW

2+d8

XC

H R2,

R2

XC

H

R2,

@R

W2+

d8X

CH R

3, R

2X

CH

R

3,@

RW

2+d8

XC

H R4,

R2

XC

H

R4,

@R

W2+

d8X

CH R

5, R

2X

CH

R

5,@

RW

2+d8

XC

H R6,

R2

XC

H

R6,

@R

W2+

d8X

CH R

7, R

2X

CH

R

7,@

RW

2+d8

+3

XC

H R0,

R3

XC

H

R0,

@R

W3+

d8X

CH R

1, R

3X

CH

R

1,@

RW

3+d8

XC

H R2,

R3

XC

H

R2,

@R

W3+

d8X

CH R

3, R

3X

CH

R

3,@

RW

3+d8

XC

H R4,

R3

XC

H

R4,

@R

W3+

d8X

CH R

5, R

3X

CH

R

5,@

RW

3+d8

XC

H R6,

R3

XC

H

R6,

@R

W3+

d8X

CH R

7, R

3X

CH

R

7,@

RW

3+d8

+4

XC

H R0,

R4

XC

H

R0,

@R

W4+

d8X

CH R

1, R

4X

CH

R

1,@

RW

4+d8

XC

H R2,

R4

XC

H

R2,

@R

W4+

d8X

CH R

3, R

4X

CH

R

3,@

RW

4+d8

XC

H R4,

R4

XC

H

R4,

@R

W4+

d8X

CH R

5, R

4X

CH

R

5,@

RW

4+d8

XC

H R6,

R4

XC

H

R6,

@R

W4+

d8X

CH R

7, R

4X

CH

R

7,@

RW

4+d8

+5

XC

H R0,

R5

XC

H

R0,

@R

W5+

d8X

CH R

1, R

5X

CH

R

1,@

RW

5+d8

XC

H R2,

R5

XC

H

R2,

@R

W5+

d8X

CH R

3, R

5X

CH

R

3,@

RW

5+d8

XC

H R4,

R5

XC

H

R4,

@R

W5+

d8X

CH R

5, R

5X

CH

R

5,@

RW

5+d8

XC

H R6,

R5

XC

H

R6,

@R

W5+

d8X

CH R

7, R

5X

CH

R

7,@

RW

5+d8

+6

XC

H R0,

R6

XC

H

R0,

@R

W6+

d8X

CH R

1, R

6X

CH

R

1,@

RW

6+d8

XC

H R2,

R6

XC

H

R2,

@R

W6+

d8X

CH R

3, R

6X

CH

R

3,@

RW

6+d8

XC

H R4,

R6

XC

H

R4,

@R

W6+

d8X

CH R

5, R

6X

CH

R

5,@

RW

6+d8

XC

H R6,

R6

XC

H

R6,

@R

W6+

d8X

CH R

7, R

6X

CH

R

7,@

RW

6+d8

+7

XC

H R0,

R7

XC

H

R0,

@R

W7+

d8X

CH R

1, R

7X

CH

R

1,@

RW

7+d8

XC

H R2,

R7

XC

H

R2,

@R

W7+

d8X

CH R

3, R

7X

CH

R

3,@

RW

7+d8

XC

H R4,

R7

XC

H

R4,

@R

W7+

d8X

CH R

5, R

7X

CH

R

5,@

RW

7+d8

XC

H R6,

R7

XC

H

R6,

@R

W7+

d8X

CH R

7, R

7X

CH

R

7,@

RW

7+d8

+8

XC

HR

0,@

RW

0X

CH

R

0,@

RW

0+d1

6X

CH

R1,

@R

W0

XC

H

R1,

@R

W0+

d16

XC

HR

2,@

RW

0X

CH

R

2,@

RW

0+d1

6X

CH

R3,

@R

W0

XC

H

R3,

@R

W0+

d16

XC

HR

4,@

RW

0X

CH

R

4,@

RW

0+d1

6X

CH

R5,

@R

W0

XC

H

R5,

@R

W0+

d16

XC

HR

6,@

RW

0X

CH

R

6,@

RW

0+d1

6X

CH

R7,

@R

W0

XC

H

R7,

@R

W0+

d16

+9

XC

HR

0,@

RW

1X

CH

R

0,@

RW

1+d1

6X

CH

R1,

@R

W1

XC

H

R1,

@R

W1+

d16

XC

HR

2,@

RW

1X

CH

R

2,@

RW

1+d1

6X

CH

R3,

@R

W1

XC

H

R3,

@R

W1+

d16

XC

HR

4,@

RW

1X

CH

R

4,@

RW

1+d1

6X

CH

R5,

@R

W1

XC

H

R5,

@R

W1+

d16

XC

HR

6,@

RW

1X

CH

R

6,@

RW

1+d1

6X

CH

R7,

@R

W1

XC

H

R7,

@R

W1+

d16

+A

XC

HR

0,@

RW

2X

CH

R

0,W

2+d1

6, A

XC

HR

1,@

RW

2X

CH

R

1,W

2+d1

6, A

XC

HR

2,@

RW

2X

CH

R

2,W

2+d1

6, A

XC

HR

3,@

RW

2X

CH

R

3,W

2+d1

6, A

XC

HR

4,@

RW

2X

CH

R

4,W

2+d1

6, A

XC

HR

5,@

RW

2X

CH

R

5,W

2+d1

6, A

XC

HR

6,@

RW

2X

CH

R

6,W

2+d1

6, A

XC

HR

7,@

RW

2X

CH

R

7,W

2+d1

6, A

+B

XC

HR

0,@

RW

3X

CH

R

0,@

RW

3+d1

6X

CH

R1,

@R

W3

XC

H

R1,

@R

W3+

d16

XC

HR

2,@

RW

3X

CH

R

2,@

RW

3+d1

6X

CH

R3,

@R

W3

XC

H

R3,

@R

W3+

d16

XC

HR

4,@

RW

3X

CH

R

4,@

RW

3+d1

6X

CH

R5,

@R

W3

XC

H

R5,

@R

W3+

d16

XC

HR

6,@

RW

3X

CH

R

6,@

RW

3+d1

6X

CH

R7,

@R

W3

XC

H

R7,

@R

W3+

d16

+C

XC

HR

0,@

RW

0+XC

H

R0,

@R

W0+

RW

7X

CH

R1,

@R

W0+

XCH

R

1,@

RW

0+R

W7

XC

HR

2,@

RW

0+XC

H

R2,

@R

W0+

RW

7X

CH

R3,

@R

W0+

XCH

R

3,@

RW

0+R

W7

XC

HR

4,@

RW

0+XC

H

R4,

@R

W0+

RW7

XC

HR

5,@

RW

0+XC

H

R5,

@R

W0+

RW

7X

CH

R6,

@R

W0+

XCH

R

6,@

RW

0+R

W7

XC

HR

7,@

RW

0+XC

H

R7,

@R

W0+

RW

7

+D

XC

HR

0,@

RW

1+XC

H

R0,

@R

W1+

RW

7X

CH

R1,

@R

W1+

XCH

R

1,@

RW

1+R

W7

XC

HR

2,@

RW

1+XC

H

R2,

@R

W1+

RW

7X

CH

R3,

@R

W1+

XCH

R

3,@

RW

1+R

W7

XC

HR

4,@

RW

1+XC

H

R4,

@R

W1+

RW7

XC

HR

5,@

RW

1+XC

H

R5,

@R

W1+

RW

7X

CH

R6,

@R

W1+

XCH

R

6,@

RW

1+R

W7

XC

HR

7,@

RW

1+XC

H

R7,

@R

W1+

RW

7

+E

XC

HR

0,@

RW

2+X

CH

R

0,@

PC

+d1

6X

CH

R1,

@R

W2+

XC

H

R1,

@P

C+

d16

XC

HR

2,@

RW

2+X

CH

R

2,@

PC

+d1

6X

CH

R3,

@R

W2+

XC

H

R3,

@P

C+

d16

XC

HR

4,@

RW

2+X

CH

R

4,@

PC

+d1

6X

CH

R5,

@R

W2+

XC

H

R5,

@P

C+

d16

XC

HR

6,@

RW

2+X

CH

R

6,@

PC

+d1

6X

CH

R7,

@R

W2+

XC

H

R7,

@P

C+

d16

+F

XC

HR

0,@

RW

3+X

CH

R0,

add

r16

XC

HR

1,@

RW

3+X

CH

R1,

add

r16

XC

HR

2,@

RW

3+X

CH

R2,

add

r16

XC

HR

3,@

RW

3+X

CH

R3,

add

r16

XC

HR

4,@

RW

3+X

CH

R4,

add

r16

XC

HR

5,@

RW

3+X

CH

R5,

add

r16

XC

HR

6,@

RW

3+X

CH

R6,

add

r16

XC

HR

7,@

RW

3+X

CH

R7,

add

r16



C.13 XCHW RWi, ea Instruction Map

Table C.13-1 lists XCHW RWi, ea instruction map.



Table C.13-1 XCHW RWi, ea Instruction (First Byte = 7FH)

Note: R0 is also used as a barrel shift counter or normalizing instruction counter.

0010

2030

4050

6070

8090

A0

B0

C0

D0

E0

F0

+0

XC

HW

RW

0, R

W0

XC

HW

RW

0,@

RW

0+d8

XC

HW

RW

1, R

W0

XC

HW

RW

1,@

RW

0+d8

XC

HW

RW

2, R

W0

XC

HW

RW

2,@

RW

0+d8

XC

HW

RW

3, R

W0

XC

HW

RW

3,@

RW

0+d8

XC

HW

RW

4, R

W0

XC

HW

RW

4,@

RW

0+d8

XC

HW

RW

5, R

W0

XC

HW

RW

5,@

RW

0+d8

XC

HW

RW

6, R

W0

XC

HW

RW

6,@

RW

0+d8

XC

HW

RW

7, R

W0

XC

HW

RW

7,@

RW

0+d8

+1

XC

HW

RW

0, R

W1

XC

HW

RW

0,@

RW

1+d8

XC

HW

RW

1, R

W1

XC

HW

RW

1,@

RW

1+d8

XC

HW

RW

2, R

W1

XC

HW

RW

2,@

RW

1+d8

XC

HW

RW

3, R

W1

XC

HW

RW

3,@

RW

1+d8

XC

HW

RW

4, R

W1

XC

HW

RW

4,@

RW

1+d8

XC

HW

RW

5, R

W1

XC

HW

RW

5,@

RW

1+d8

XC

HW

RW

6, R

W1

XC

HW

RW

6,@

RW

1+d8

XC

HW

RW

7, R

W1

XC

HW

RW

7,@

RW

1+d8

+2

XC

HW

RW

0, R

W2

XC

HW

RW

0,@

RW

2+d8

XC

HW

RW

1, R

W2

XC

HW

RW

1,@

RW

2+d8

XC

HW

RW

2, R

W2

XC

HW

RW

2,@

RW

2+d8

XC

HW

RW

3, R

W2

XC

HW

RW

3,@

RW

2+d8

XC

HW

RW

4, R

W2

XC

HW

RW

4,@

RW

2+d8

XC

HW

RW

5, R

W2

XC

HW

RW

5,@

RW

2+d8

XC

HW

RW

6, R

W2

XC

HW

RW

6,@

RW

2+d8

XC

HW

RW

7, R

W2

XC

HW

RW

7,@

RW

2+d8

+3

XC

HW

RW

0, R

W3

XC

HW

RW

0,@

RW

3+d8

XC

HW

RW

1, R

W3

XC

HW

RW

1,@

RW

3+d8

XC

HW

RW

2, R

W3

XC

HW

RW

2,@

RW

3+d8

XC

HW

RW

3, R

W3

XC

HW

RW

3,@

RW

3+d8

XC

HW

RW

4, R

W3

XC

HW

RW

4,@

RW

3+d8

XC

HW

RW

5, R

W3

XC

HW

RW

5,@

RW

3+d8

XC

HW

RW

6, R

W3

XC

HW

RW

6,@

RW

3+d8

XC

HW

RW

7, R

W3

XC

HW

RW

7,@

RW

3+d8

+4

XC

HW

RW

0, R

W4

XC

HW

RW

0,@

RW

4+d8

XC

HW

RW

1, R

W4

XC

HW

RW

1,@

RW

4+d8

XC

HW

RW

2, R

W4

XC

HW

RW

2,@

RW

4+d8

XC

HW

RW

3, R

W4

XC

HW

RW

3,@

RW

4+d8

XC

HW

RW

4, R

W4

XC

HW

RW

4,@

RW

4+d8

XC

HW

RW

5, R

W4

XC

HW

RW

5,@

RW

4+d8

XC

HW

RW

6, R

W4

XC

HW

RW

6,@

RW

4+d8

XC

HW

RW

7, R

W4

XC

HW

RW

7,@

RW

4+d8

+5

XC

HW

RW

0, R

W5

XC

HW

RW

0,@

RW

5+d8

XC

HW

RW

1, R

W5

XC

HW

RW

1,@

RW

5+d8

XC

HW

RW

2, R

W5

XC

HW

RW

2,@

RW

5+d8

XC

HW

RW

3, R

W5

XC

HW

RW

3,@

RW

5+d8

XC

HW

RW

4, R

W5

XC

HW

RW

4,@

RW

5+d8

XC

HW

RW

5, R

W5

XC

HW

RW

5,@

RW

5+d8

XC

HW

RW

6, R

W5

XC

HW

RW

6,@

RW

5+d8

XC

HW

RW

7, R

W5

XC

HW

RW

7,@

RW

5+d8

+6

XC

HW

RW

0, R

W6

XC

HW

RW

0,@

RW

6+d8

XC

HW

RW

1, R

W6

XC

HW

RW

1,@

RW

6+d8

XC

HW

RW

2, R

W6

XC

HW

RW

2,@

RW

6+d8

XC

HW

RW

3, R

W6

XC

HW

RW

3,@

RW

6+d8

XC

HW

RW

4, R

W6

XC

HW

RW

4,@

RW

6+d8

XC

HW

RW

5, R

W6

XC

HW

RW

5,@

RW

6+d8

XC

HW

RW

6, R

W6

XC

HW

RW

6,@

RW

6+d8

XC

HW

RW

7, R

W6

XC

HW

RW

7,@

RW

6+d8

+7

XC

HW

RW

0, R

W7

XC

HW

RW

0,@

RW

7+d8

XC

HW

RW

1, R

W7

XC

HW

RW

1,@

RW

7+d8

XC

HW

RW

2, R

W7

XC

HW

RW

2,@

RW

7+d8

XC

HW

RW

3, R

W7

XC

HW

RW

3,@

RW

7+d8

XC

HW

RW

4, R

W7

XC

HW

RW

4,@

RW

7+d8

XC

HW

RW

5, R

W7

XC

HW

RW

5,@

RW

7+d8

XC

HW

RW

6, R

W7

XC

HW

RW

6,@

RW

7+d8

XC

HW

RW

7, R

W7

XC

HW

RW

7,@

RW

7+d8

+8

XC

HW

RW

0,@

RW

0X

CH

W R

W0,

@R

W0+

d16

XC

HW

RW

1,@

RW

0X

CH

W R

W1,

@R

W0+

d16

XC

HW

RW

2,@

RW

0X

CH

W R

W2,

@R

W0+

d16

XC

HW

RW

3,@

RW

0X

CH

W R

W3,

@R

W0+

d16

XC

HW

RW

4,@

RW

0X

CH

W R

W4,

@R

W0+

d16

XC

HW

RW

5,@

RW

0X

CH

W R

W5,

@R

W0+

d16

XC

HW

RW

6,@

RW

0X

CH

W R

W6,

@R

W0+

d16

XC

HW

RW

7,@

RW

0X

CH

W R

W7,

@R

W0+

d16

+9

XC

HW

RW

0,@

RW

1X

CH

W R

W0,

@R

W1+

d16

XC

HW

RW

1,@

RW

1X

CH

W R

W1,

@R

W1+

d16

XC

HW

RW

2,@

RW

1X

CH

W R

W2,

@R

W1+

d16

XC

HW

RW

3,@

RW

1X

CH

W R

W3,

@R

W1+

d16

XC

HW

RW

4,@

RW

1X

CH

W R

W4,

@R

W1+

d16

XC

HW

RW

5,@

RW

1X

CH

W R

W5,

@R

W1+

d16

XC

HW

RW

6,@

RW

1X

CH

W R

W6,

@R

W1+

d16

XC

HW

RW

7,@

RW

1X

CH

W R

W7,

@R

W1+

d16

+A

XC

HW

RW

0,@

RW

2X

CH

W R

W0,

@R

W2+

d16

XC

HW

RW

1,@

RW

2X

CH

W R

W1,

@R

W2+

d16

XC

HW

RW

2,@

RW

2X

CH

W R

W2,

@R

W2+

d16

XC

HW

RW

3,@

RW

2X

CH

W R

W3,

@R

W2+

d16

XC

HW

RW

4,@

RW

2X

CH

W R

W4,

@R

W2+

d16

XC

HW

RW

5,@

RW

2X

CH

W R

W5,

@R

W2+

d16

XC

HW

RW

6,@

RW

2X

CH

W R

W6,

@R

W2+

d16

XC

HW

RW

7,@

RW

2X

CH

W R

W7,

@R

W2+

d16

+B

XC

HW

RW

0,@

RW

3X

CH

W R

W0,

@R

W3+

d16

XC

HW

RW

1,@

RW

3X

CH

W R

W1,

@R

W3+

d16

XC

HW

RW

2,@

RW

3X

CH

W R

W2,

@R

W3+

d16

XC

HW

RW

3,@

RW

3X

CH

W R

W3,

@R

W3+

d16

XC

HW

RW

4,@

RW

3X

CH

W R

W4,

@R

W3+

d16

XC

HW

RW

5,@

RW

3X

CH

W R

W5,

@R

W3+

d16

XC

HW

RW

6,@

RW

3X

CH

W R

W6,

@R

W3+

d16

XC

HW

RW

7,@

RW

3X

CH

W R

W7,

@R

W3+

d16

+C

XC

HW

RW

0,@

RW

0+X

CH

W R

W0,

@R

W0+

RW

7X

CH

WR

W1,

@R

W0+

XC

HW

RW

1,@

RW

0+R

W7

XC

HW

RW

2,@

RW

0+X

CH

W R

W2,

@R

W0+

RW

7X

CH

WR

W3,

@R

W0+

XC

HW

RW

3,@

RW

0+R

W7

XC

HW

RW

4,@

RW

0+X

CH

W R

W4,

@R

W0+

RW

7X

CH

WR

W5,

@R

W0+

XC

HW

RW

5,@

RW

0+R

W7

XC

HW

RW

6,@

RW

0+X

CH

W R

W6,

@R

W0+

RW

7X

CH

WR

W7,

@R

W0+

XC

HW

RW

7,@

RW

0+R

W7

+D

XC

HW

RW

0,@

RW

1+X

CH

W R

W0,

@R

W1+

RW

7X

CH

WR

W1,

@R

W1+

XC

HW

RW

1,@

RW

1+R

W7

XC

HW

RW

2,@

RW

1+X

CH

W R

W2,

@R

W1+

RW

7X

CH

WR

W3,

@R

W1+

XC

HW

RW

3,@

RW

1+R

W7

XC

HW

RW

4,@

RW

1+X

CH

W R

W4,

@R

W1+

RW

7X

CH

WR

W5,

@R

W1+

XC

HW

RW

5,@

RW

1+R

W7

XC

HW

RW

6,@

RW

1+X

CH

W R

W6,

@R

W1+

RW

7X

CH

WR

W7,

@R

W1+

XC

HW

RW

7,@

RW

1+R

W7

+E

XC

HW

RW

0,@

RW

2+X

CH

W R

W0,

@P

C+d

16X

CH

WR

W1,

@R

W2+

XC

HW

RW

1,@

PC

+d16

XC

HW

RW

2,@

RW

2+X

CH

W R

W2,

@P

C+d

16X

CH

WR

W3,

@R

W2+

XC

HW

RW

3,@

PC

+d16

XC

HW

RW

4,@

RW

2+X

CH

W R

W4,

@P

C+d

16X

CH

WR

W5,

@R

W2+

XC

HW

RW

5,@

PC

+d16

XC

HW

RW

6,@

RW

2+X

CH

W R

W6,

@P

C+d

16X

CH

WR

W7,

@R

W2+

XC

HW

RW

7,@

PC

+d16

+F

XC

HW

RW

0,@

RW

3+X

CH

WR

W0,

add

r16

XC

HW

RW

1,@

RW

3+X

CH

WR

W1,

add

r16

XC

HW

RW

2,@

RW

3+X

CH

WR

W2,

add

r16

XC

HW

RW

3,@

RW

3+X

CH

WR

W3,

add

r16

XC

HW

RW

4,@

RW

3+X

CH

WR

W4,

add

r16

XC

HW

RW

5,@

RW

3+X

CH

WR

W5,

add

r16

XC

HW

RW

6,@

RW

3+X

CH

WR

W6,

add

r16

XC

HW

RW

7,@

RW

3+X

CH

WR

W7,

add

r16


APPENDIX APPENDIX D Failure of String Instructions and WBTC/WBTS Instructions

APPENDIX D Failure of String Instructions and WBTC/WBTS Instructions

D.1 Problem DescriptionWe identified failure in string instructions (MOVS, MOVSD, SCEQ, SCEQD, FILS,

MOVSW, MOVSWD, SCWEQ, SCWEQD, FILSW) and WBTC/WBTS instructions of the

F2MC-16FX family, thus we would like to make a report about it. Note that the SCEQ,

SCEQD, SCWEQ, SCWEQD, and WBTC/WBTS instructions are not used by Softune C

compiler and library.

The MOVS, MOVSD, FILS, MOVSW, MOVSWD, and FILSW instructions are used by

Softune C compiler and library, but it is confirmed that any code pattern concerned with the

failure is not generated.

In addition to that, the failure does not occur in the following cases.

• Only the C language is used for programming.

• The assembly language is used but any instruction concerned with the failure (see D.1.2) isnot used.

• Interrupt disabling (see D.1.1) is performed only in interrupt processing routines.

• The instructions concerned with the failure are used but there is no interrupt disablingimmediately before them (within 4 CPU clock cycles). (The MOVS and FILS instructionsare used in start.asm usually supplied with Softune, but they are not used in a manner thatcauses the failure to occur.)

D.1.1 Interrupt DisablingInterrupt disabling refers to the following processes.

• Clear interrupt source flags of peripheral functions.

• Set interrupt enable/disable bits of peripheral functions.

• Set the interrupt level setting value of a peripheral function (ILR/ICR) to the ILM value or

higher. [ILR/ICR value < ILM value]

• Allow a peripheral function for which an interrupt setting has been configured to performDMA transfer.

• (This means that the interrupt requested destination is changed from the CPU to DMA, thusit is regarded as interrupt request disabled status as viewed from the CPU.)

* Note that I flag/P flag clearing and interrupt mask processing by ILM change are not

included in the interrupt disabling mentioned above.

D.1.2 Instructions concerned with the failureMOVS, MOVSD, SCEQ, SCEQD, FILS, MOVSW, MOVSWD, SCWEQ, SCWEQD, FILSW,

WBTC, and WBTS

If you employed the assembly language, we would like to ask you to check the following.


APPENDIXAPPENDIX D Failure of String Instructions and WBTC/WBTS

Instructions

D.2 List of affected Devices

Series Product name

MB96310 series MB96F313RWA, MB96F313YWA, MB96F313RSA, MB96F313YSA, MB96F315RWA, MB96F315YWA, MB96F315RSA, MB96F315YSA

MB96320 series MB96F326RWA, MB96F326YWA, MB96F326RSA, MB96F326YSA, MB96F326RWB, MB96F326YWB, MB96F326RSB, MB96F326YSB

MB96330 series MB96F338RWA, MB96F338UWA, MB96F338YWA, MB96F338RSA, MB96F338USA, MB96F338YSA

MB96340 series MB96345RWA, MB96345YWA, MB96345RSA, MB96345YSA, MB96346RWA, MB96346YWA, MB96346RSA, MB96346YSA, MB96F346AWA, MB96F346RWA, MB96F346YWA, MB96F346ASA, MB96F346RSA, MB96F346YSA, MB96F346AWB, MB96F346RWB, MB96F346YWB, MB96F346ASB, MB96F346RSB, MB96F346YSB, MB96F347AWA, MB96F347RWA, MB96F347YWA, MB96F347ASA, MB96F347RSA, MB96F347YSA, MB96F347AWB, MB96F347RWB, MB96F347YWB, MB96F347ASB, MB96F347RSB, MB96F347YSB, MB96F348AWA, MB96F348RWA, MB96F348YWA, MB96F348ASA, MB96F348RSA, MB96F348YSA, MB96F348AWB, MB96F348RWB, MB96F348YWB, MB96F348ASB, MB96F348RSB, MB96F348YSB, MB96F348HWA, MB96F348TWA, MB96F348HSA, MB96F348TSA, MB96F348CWB, MB96F348HWB, MB96F348TWB, MB96F348CWB, MB96F348HSB, MB96F348TSB, MB96F348CWC, MB96F348HWC, MB96F348TWC, MB96F348CSC, MB96F348HSC, MB96F348TSC, MB96F345DS, MB96F345DW, MB96F345FS, MB96F345FW

MB96350 series MB96F356RWA, MB96F356YWA, MB96F356RSA, MB96F356YSA, MB96F356RWB, MB96F356YWB, MB96F356RSB, MB96F356YSB, MB96F355RWA, MB96F355YWA, MB96F355RSA, MB96F355YSA


MB96380 series MB96F386RWA, MB96F386YWA, MB96F386RSA, MB96F386YSA, MB96F387RWA, MB96F387YWA, MB96F387RSA, MB96F387YSA, MB96F386RWB, MB96F386YWB, MB96F386RSB, MB96F386YSB, MB96F387RWB, MB96F387YWB, MB96F387RSB, MB96F387YSB, MB96384RWA, MB96384YWA, MB96384RSA, MB96384YSA, MB96385RWA, MB96385YWA, MB96385RSA, MB96385YSA, MB96F388RWA, MB96F388YWA, MB96F388RSA, MB96F388YSA, MB96F389RWA, MB96F389YWA, MB96F389RSA, MB96F389YSA

Evaluation chip MB96V300B, MB96V300



D.3 Details of the FailureThis failure occurs when there is interrupt disabling immediately before the instructions

concerned with the failure (within 4 CPU clock cycles); an interrupt that takes place during

execution of the instruction concerned with the failure causes the execution of the instruction to

end before completion and execution of the next instruction to start. In addition to that, due to

this phenomenon, to the CPU program counter (PC), the instruction queue counter increases by

1. Consequently, it causes the microprocessor to start executing the next instruction without

resuming the instruction concerned with the failure, and the CPU results in running, having

inconsistency between the instruction code and PC. A relative branch in that situation causes

the MCU to malfunction.

D.3.1 Instructions concerned with the failure and their faulty operations

In addition to that, this faulty phenomenon causes the instruction queue counter to incorrectly

increase by 1.

The figure below shows the faulty operation in the CPU pipeline model.

An interrupt event occurs and an IRQ is set.

Instructions concerned with

the failureFaulty operation

MOVS, MOVSD,MOVSW,MOVSWD

The next instruction is executed while array transfer remains imperfect.

FILS, FILSW The next instruction is executed while array initialization remains imperfect.

SCEQ, SCWEQ Array scan ends in imperfect state, and then the next instruction is executed.

WBTC, WBTS Bit wait status is cancelled, and then the next instruction is executed.

CLR IRQ

CLR IRQ

CLR IRQ

CLR IRQ

String Instruction

String Instruction

String Instruction

String InstructionStage 3 (WB)

Stage 2 (EX)

Stage 1 (D1)

Stage 0 (D0)

IRQ1

suspend next instruction

next

3

2

IRQacceptance

4

5

1


APPENDIXAPPENDIX D Failure of String Instructions and WBTC/WBTS

InstructionsBy the IRQ, the processing of the instruction concerned with the failure on Stage 0 (string

instruction) is interrupted.

The interrupt disabling immediately before (CLR IRQ) it reaches Stage 3 and this causes

the IRQ to be cleared.

The interrupt generated by that event is never accepted, but the string instruction remains

interrupted.

The instruction queue counter increases by 1 while the interrupted string instruction keeps

on being not resumed, and then the next instruction is executed. A relative branch in that

situation causes the MCU to malfunction.

2

3

4

5



D.4 Possible workaroundIf the instructions concerned with the failure are used in assembly language representation,

please take any of the following measures to prevent the failure.

1. Write the program by not using the instructions concerned with the failure.

2. Perform interrupt disabling only in interrupt processing routines.

3. To perform interrupt disabling before an instruction concerned with the failure, secure aspace of 4 instructions or more.

(Example)

* It is confirmed that any code pattern concerned with the failure is not generated by Softune C

compiler and library. The MOVS and FILS instructions are used in start.asm usually supplied

with Softune, but they are not used in a manner that causes the failure to occur.

CLRB ENIR0:0 //interrupt disabling

NOP //

NOP //secure a space of 4 instructions or more.

NOP //

NOP //

MOVS DTB, ADB //instruction concerned with the failure


APPENDIXAPPENDIX E Wrong execution of scan string instruction SCEQ/

SCWEQ at Interrupt

APPENDIX E Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt

E.1 OverviewThe instructions to scan for occurrence of a bit pattern (SCEQ: character byte, SCWEQ: 16 bit

word) in a field of data do not work reliable together with interrupts. Cases exist, where an

existing match in a bit pattern may not be found.

E.1.1 Affected are the following instructions:

Mnemonic First byte opcode Second byte opcode

SCEQI 6EH 80H, 81H, 82H, 83H

SCEQD 6EH 90H, 91H, 92H, 93H

SCWEQI 6EH A0H, A1H, A2H, A3H

SCWEQD 6EH B0H, B1H, B2H, B3H


APPENDIX APPENDIX E Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt

E.2 List of affected Devices

Series Product name


MB96330 series MB96F338RWA, MB96F338UWA,MB96F338YWA, MB96F338RSA, MB96F338USA, MB96F338YSA

MB96340 series MB96345RWA, MB96345YWA, MB96345RSA, MB96345YSA, MB96346RWA, MB96346YWA, MB96346RSA, MB96346YSA, MB96F346AWA, MB96F346RWA, MB96F346YWA, MB96F346ASA, MB96F346RSA, MB96F346YSA, MB96F346AWB, MB96F346RWB, MB96F346YWB, MB96F346ASB, MB96F346RSB, MB96F346YSB, MB96F347AWA, MB96F347RWA, MB96F347YWA, MB96F347ASA, MB96F347RSA, MB96F347YSA, MB96F347AWB, MB96F347RWB, MB96F347YWB, MB96F347ASB, MB96F347RSB, MB96F347YSB, MB96F348AWA, MB96F348RWA, MB96F348YWA, MB96F348ASA, MB96F348RSA, MB96F348YSA, MB96F348AWB, MB96F348RWB, MB96F348YWB, MB96F348ASB, MB96F348RSB, MB96F348YSB, MB96F348HWA, MB96F348TWA, MB96F348HSA, MB96F348TSA, MB96F348CWB, MB96F348HWB, MB96F348TWB, MB96F348CWB, MB96F348HSB, MB96F348TSB, MB96F348CWC, MB96F348HWC, MB96F348TWC, MB96F348CSC, MB96F348HSC, MB96F348TSC



MB96380 series MB96F386RWA, MB96F386YWA, MB96F386RSA, MB96F386YSA, MB96F387RWA, MB96F387YWA, MB96F387RSA, MB96F387YSA, MB96F386RWB, MB96F386YWB, MB96F386RSB, MB96F386YSB, MB96F387RWB, MB96F387YWB, MB96F387RSB, MB96F387YSB, MB96384RWA, MB96384YWA, MB96384RSA, MB96384YSA, MB96385RWA, MB96385YWA, MB96385RSA, MB96385YSA, MB96F388RWA, MB96F388YWA, MB96F388RSA, MB96F388YSA, MB96F389RWA, MB96F389YWA, MB96F389RSA, MB96F389YSA

Evaluation chip MB96V300BRB-ES, MB96V300RB-ES


APPENDIXAPPENDIX E Wrong execution of scan string instruction SCEQ/

SCWEQ at Interrupt

E.3 Detailed explanationAll string instructions have the feature to suspend operation at interrupt occurrence.

The phenomenon happens, if the interrupt request is issued at the same time when the specified

byte or word in AL is found in the field of data. In such a case the CPU branches to interrupt

service and resumes operation of the string scan instruction.

The information that the specified byte or word was found is discarded. Effectively data in AH,

RW0 and the Flags are wrong at the end of the execution of the string scan instructions.

The match could not be found in some cases, if there is an IRQ occurring during the execution

of SCEQ/SCWEQ. The instruction may stop either at the next occurrence of the specified

element or it runs until the end without finding the element where the interrupt occurs.

E.3.1 Operands and specification of SCEQ/SCWEQ:

The instruction should finish if either the specified element was found or the end of the field of

data was reached (RW0 = 0).

Register / flag Operation

AH Pointer to the actual position of an element in a field of data with automatic increment/decrement at each step of comparison

AL Compare value to be searched for (byte or word)

RW0 Number of elements to compare; will be decremented at each step of comparison

FLAGS NZVC will be influenced by the comparison. In case of the element was found, the zero flag (Z) will be set.


APPENDIX APPENDIX E Wrong execution of scan string instruction SCEQ/SCWEQ at Interrupt

E.4 Possible workaroundA) Do not use SCEQ/SCWEQ instructions. Implement searching the element by using other

instructions.

B) Do not allow interrupts during the use of SCEQ/SCWEQ instructions.

CM44-00203-1E

FUJITSU MICROELECTRONICS • CONTROLLER MANUAL

F2MC-16FX

16-BIT MICROCONTROLLER

PROGRAMMING MANUAL

December 2008 the first edition

Published FUJITSU MICROELECTRONICS LIMITEDEdited Sales Promotion Dept.

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