16-bit microcontroller programming …...i contents objectives and intended readership the f2mc-16fx...
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FUJITSU MICROELECTRONICSCONTROLLER MANUAL
F2MC-16FX16-BIT MICROCONTROLLER
PROGRAMMING MANUAL
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
F2MC-16FX16-BIT MICROCONTROLLER
PROGRAMMING MANUAL
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CONTENTS
■ Objectives and Intended ReadershipThe F2MC-16FX series products are original 16-bit one-chip microcontrollers that support
application specific ICs (ASICs). They are suitable for use in various types of industrial
equipment, office-automation equipment, on-vehicle equipment, and other equipment that is
required to operate at high speed in real-time mode.
■ Trademark
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
The company names and brand names herein are the trademarks or registered trademarks of
their respective owners.
■ Intended ReadershipThis manual is written for engineers involved in the development of products using the F2MC-
16FX series microcontrollers. It is designed specially for programmers working in assembly
language for use with F2MC-16FX series assemblers, and describes the various instructions
used with the F2MC-16FX series products. Be sure to read the entire manual carefully.
■ Configuration of this ManualThis manual contains the following 8 chapters and appendix.
CHAPTER 1 CPU
This chapter describes an overview of the F2MC-16FX CPU core and its sample
configuration.
CHAPTER 2 MEMORY SPACE
This chapter describes memory spaces in the F2MC-16FX CPU.
CHAPTER 3 DEDICATED REGISTER
This chapter describes the dedicated registers of the F2MC-16FX CPU.
CHAPTER 4 GENERAL-PURPOSE REGISTERS
This chapter describes the general-purpose registers of the F2MC-16FX CPU.
CHAPTER 5 PREFIX CODES
This chapter describes the prefix codes.
CHAPTER 6 INTERRUPTS
This chapter describes the interrupt functions and operations of the F2MC-16FX.
CHAPTER 7 ADDRESSING
This chapter describes the addressing mode for each instruction of the F2MC-16FX.
CHAPTER 8 DETAILED INSTRUCTIONS
This chapter describes each execution instruction used in the assembler in a reference
format. The execution instructions are presented in alphabetical order.
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APPENDIX
The appendix section includes lists and maps of instructions for the F2MC-16FX.
■ ReferencesThe following manuals should be referred along with this manual:
• F2MC-16FX/16L/16/16H/16F Assembler Manual
• F2MC-16FX Model-Specific Hardware Manual
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Copyright ©2008-2010 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
• The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presentedsolely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICSdevice; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to usebased on such information. When you develop equipment incorporating the device based on such information, youmust assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICSassumes no liability for any damages whatsoever arising out of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not beconstrued as license of the use or exercise of any intellectual property right, such as patent right or copyright, orany other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICSwarrant non-infringement of any third-party's intellectual property right or other right by using such information.FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights orother rights of third parties which would result from the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for generaluse, including without limitation, ordinary industrial use, general office use, personal use, and household use, butare not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangersthat, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly todeath, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch controlin weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificialsatellite).Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for anyclaims or damages arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or lossfrom such failures by incorporating safety design measures into your facility and equipment such as redundancy,fire protection, and prevention of over-current levels and other abnormal operating conditions.
• Exportation/release of any products described in this document may require necessary procedures in accordancewith the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export controllaws.
• The company names and brand names herein are the trademarks or registered trademarks of their respectiveowners.
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CONTENTS
CHAPTER 1 CPU .................................................................................................. 11.1 Overview of CPU ................................................................................................................. 21.2 Sample Configuration .......................................................................................................... 4
CHAPTER 2 MEMORY SPACE ............................................................................ 92.1 CPU Memory Space .......................................................................................................... 102.2 Linear Addressing Mode .................................................................................................... 112.3 Bank Addressing Mode ..................................................................................................... 122.4 Memory Space Divided into Banks and Value in Each Bank Register .............................. 142.5 Data Configuration of and Access to Multi-byte Data in Memory ...................................... 15
CHAPTER 3 DEDICATED REGISTER ............................................................... 173.1 Structure of the Dedicated Registers ................................................................................. 183.2 Accumulator (A) ................................................................................................................. 203.3 User Stack Pointer (USP) and System Stack Pointer (SSP) ............................................. 223.4 Processor Status (PS) ....................................................................................................... 243.5 Program Counter (PC) ....................................................................................................... 293.6 Direct Page Register (DPR) .............................................................................................. 303.7 Bank register (PCB, DTB, ADB, USB, SSB) ..................................................................... 31
CHAPTER 4 GENERAL-PURPOSE REGISTERS .............................................. 334.1 Register Banks in RAM ..................................................................................................... 344.2 Calling General-purpose Registers in RAM ....................................................................... 36
CHAPTER 5 PREFIX CODES ............................................................................. 375.1 Bank Select Prefix ............................................................................................................. 385.2 Common Register Bank Prefix (CMR) ............................................................................... 405.3 Flag Change Inhibit Prefix Code (NCC) ............................................................................ 415.4 Constraints Related to the Prefix Codes ........................................................................... 42
CHAPTER 6 INTERRUPTS ................................................................................. 456.1 Overview of Interrupts ....................................................................................................... 466.2 Interrupt Vector .................................................................................................................. 486.3 Interrupt Control Registers (ICR) ....................................................................................... 516.4 Non Maskable Interrupt (NMI) ........................................................................................... 536.5 Interrupt Flow ..................................................................................................................... 556.6 Hardware Interrupts ........................................................................................................... 576.7 Software Interrupts ............................................................................................................ 616.8 Multiple interrupts .............................................................................................................. 636.9 Exceptions ......................................................................................................................... 66
CHAPTER 7 ADDRESSING ................................................................................ 717.1 Effective Address Field ...................................................................................................... 727.2 Direct Addressing .............................................................................................................. 73
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7.3 Indirect Addressing ............................................................................................................ 75
CHAPTER 8 DETAILED INSTRUCTIONS .......................................................... 798.1 Instruction Overview .......................................................................................................... 808.2 ADD (Add Byte Data of Destination and Source to Destination) ....................................... 838.3 ADDC (Add Byte Data of AL and AH with Carry to AL) ..................................................... 858.4 ADDC (Add Byte Data of Accumulator and Effective Address with Carry to Accumulator) 868.5 ADDCW (Add Word Data of Accumulator and Effective Address with Carry to Accumulator)
........................................................................................................................................... 888.6 ADDDC (Add Decimal Data of AL and AH with Carry to AL) ............................................ 908.7 ADDL (Add Long Word Data of Destination and Source to Destination) ........................... 918.8 ADDSP (Add Word Data of Stack Pointer and Immediate Data to Stack Pointer) ............ 938.9 ADDW (Add Word Data of AL and AH to AL) .................................................................... 948.10 ADDW (Add Word Data of Destination and Source to Destination) .................................. 958.11 AND (And Byte Data of Destination and Source to Destination) ....................................... 978.12 AND (And Byte Data of Immediate Data and Condition Code Register) ........................... 998.13 ANDL (And Long Word Data of Destination and Source to Destination) ......................... 1018.14 ANDW (And Word Data of AH and AL to AL) .................................................................. 1038.15 ANDW (And Word Data of Destination and Source to Destination) ................................ 1048.16 ASR (Arithmetic Shift Byte Data of Accumulator to Right) .............................................. 1068.17 ASRL (Arithmetic Shift Long Word Data of Accumulator to Right) .................................. 1088.18 ASRW (Arithmetic Shift Word Data of Accumulator to Right) .......................................... 1108.19 ASRW (Arithmetic Shift Word Data of Accumulator to Right) .......................................... 1128.20 BBcc (Branch if Bit Condition satisfied) ........................................................................... 1148.21 Bcc (Branch relative if Condition satisfied) ...................................................................... 1168.22 CALL (Call Subroutine) .................................................................................................... 1188.23 CALLP (Call Physical Address) ....................................................................................... 1208.24 CALLV (Call Vectored Subroutine) .................................................................................. 1228.25 CBNE (Compare Byte Data and Branch if not Equal) ..................................................... 1248.26 CLRB (Clear Bit) .............................................................................................................. 1268.27 CMP (Compare Byte Data of Destination and Source) ................................................... 1278.28 CMPL (Compare Long Word Data of Destination and Source) ....................................... 1298.29 CMPW (Compare Word Data of Destination and Source) .............................................. 1318.30 CWBNE (Compare Word Data and Branch if not Equal) ................................................ 1338.31 DBNZ (Decrement Byte Data and Branch if not Zero) .................................................... 1358.32 DEC (Decrement Byte Data) ........................................................................................... 1378.33 DECL (Decrement Long Word Data) ............................................................................... 1388.34 DECW (Decrement Word Data) ...................................................................................... 1398.35 DIV (Divide Word Data by Byte Data) ............................................................................. 1418.36 DIVW (Divide Long Word Data by Word Data) ................................................................ 1438.37 DIVU (Divide unsigned Word Data by unsigned Byte Data) ............................................ 1458.38 DIVUW (Divide unsigned Long Word Data by unsigned Word Data) .............................. 1478.39 DWBNZ (Decrement Word Data and Branch if not Zero) ................................................ 1498.40 EXT (Sign Extend from Byte Data to Word Data) ............................................................ 1518.41 EXTW (Sign Extend from Word Data to Long Word Data) .............................................. 1528.42 FILS, FILSI (Fill String Byte) ............................................................................................ 1538.43 FILSW, FILSWI (Fill String Word) .................................................................................... 1558.44 INC (Increment Byte Data (Address Specification)) ........................................................ 1578.45 INCL (Increment Long Word Data) .................................................................................. 158
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8.46 INCW (Increment Word Data) ......................................................................................... 1598.47 INT (Software Interrupt) ................................................................................................... 1618.48 INT (Software Interrupt (Vector Specification)) ................................................................ 1638.49 INT9 (Software Interrupt) ................................................................................................. 1658.50 INTP (Software Interrupt) ................................................................................................ 1678.51 JCTX (Jump Context) ...................................................................................................... 1698.52 JMP (Jump Destination Address) .................................................................................... 1718.53 JMPP (Jump Destination Physical Address) ................................................................... 1728.54 LINK (Link and Create New Stack Frame) ...................................................................... 1738.55 LSL (Logical Shift Byte Data of Accumulator to Left) ...................................................... 1748.56 LSLL (Logical Shift Long Word Data of Accumulator to Left) .......................................... 1768.57 LSLW (Logical Shift Word Data of Accumulator to Left) .................................................. 1788.58 LSLW (Logical Shift Word Data of Accumulator to Left) .................................................. 1798.59 LSR (Logical Shift Byte Data of Accumulator to Right) ................................................... 1818.60 LSRL (Logical Shift Long Word Data of Accumulator to Right) ....................................... 1838.61 LSRW (Logical Shift Word Data of Accumulator to Right) ............................................... 1858.62 LSRW (Logical Shift Word Data of Accumulator to Right) ............................................... 1878.63 MOV (Move Byte Data from Source to Accumulator) ...................................................... 1898.64 MOV (Move Byte Data from Accumulator to Destination) ............................................... 1918.65 MOV (Move Byte Immediate Data to Destination) ........................................................... 1938.66 MOV (Move Byte Data from Source to Destination) ........................................................ 1958.67 MOV (Move Byte Data from AH to Memory) ................................................................... 1978.68 MOVB (Move Bit Data from Bit Address to Accumulator) ............................................... 1988.69 MOVB (Move Bit Data from Accumulator to Bit Address) ............................................... 2008.70 MOVEA (Move Effective Address to Destination) ........................................................... 2028.71 MOVL (Move Long Word Data from Source to Accumulator) ......................................... 2048.72 MOVL (Move Long Word Data from Accumulator to Destination) ................................... 2068.73 MOVN (Move Immediate Nibble Data to Accumulator) ................................................... 2088.74 MOVS, MOVSI (Move String Byte with Increment) ......................................................... 2098.75 MOVSD (Move String Byte with Decrement) ................................................................... 2118.76 MOVSW, MOVSWI (Move String Word with Increment) ................................................. 2128.77 MOVSWD (Move String Word with Decrement) .............................................................. 2148.78 MOVW (Move Word Data from Source to Accumulator) ................................................. 2158.79 MOVW (Move Word Data from Accumulator to Destination) ........................................... 2178.80 MOVW (Move Immediate Word Data to Destination) ...................................................... 2198.81 MOVW (Move Word Data from Source to Destination) ................................................... 2218.82 MOVW (Move Immediate Word Data to io) ..................................................................... 2238.83 MOVW (Move Word Data from AH to Memory) .............................................................. 2248.84 MOVX (Move Byte Data with Sign Extension from Source to Accumulator) ................... 2258.85 MUL (Multiply Byte Data of Accumulator) ........................................................................ 2278.86 MUL (Multiply Byte Data of Accumulator and Effective Address) .................................... 2288.87 MULW (Multiply Word Data of Accumulator) ................................................................... 2298.88 MULW (Multiply Word Data of Accumulator and Effective Address) ............................... 2308.89 MULU (Multiply Unsigned Byte Data of Accumulator) ..................................................... 2318.90 MULU (Multiply Unsigned Byte Data of Accumulator and Effective Address) ................. 2328.91 MULUW (Multiply Unsigned Word Data of Accumulator) ................................................ 2338.92 MULUW (Multiply Unsigned Word Data of Accumulator and Effective Address) ............ 2348.93 NEG (Negate Byte Data of Destination) .......................................................................... 2358.94 NEGW (Negate Word Data of Destination) ..................................................................... 236
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8.95 NOP (No Operation) ........................................................................................................ 2378.96 NOT (Not Byte Data of Destination) ................................................................................ 2388.97 NOTW (Not Word Data of Destination) ........................................................................... 2408.98 NRML (NORMALIZE Long Word) ................................................................................... 2418.99 OR (Or Byte Data of Destination and Source to Destination) .......................................... 2428.100 OR (Or Byte Data of Immediate Data and Condition Code Register to
Condition Code Register) ................................................................................................ 2448.101 ORL (Or Long Word Data of Destination and Source to Destination) ............................. 2468.102 ORW (Or Word Data of AH and AL to AL) ...................................................................... 2488.103 ORW (Or Word Data of Destination and Source to Destination) ..................................... 2498.104 POPW (Pop Word Data of Accumulator from Stack Memory) ......................................... 2518.105 POPW (Pop Word Data of AH from Stack Memory) ....................................................... 2538.106 POPW (Pop Word Data of Program Status from Stack Memory) .................................... 2548.107 POPW (Pop Registers from Stack Memory) ................................................................... 2568.108 PUSHW (Push Word Data of Inherent Register to Stack Memory) ................................. 2588.109 PUSHW (Push Registers to Stack Memory) ................................................................... 2608.110 RET (Return from Subroutine) ......................................................................................... 2628.111 RETI (Return from Interrupt) ............................................................................................ 2638.112 RETP (Return from Physical Address) ............................................................................ 2658.113 ROLC (Rotate Byte Data of Accumulator with Carry to Left) ........................................... 2678.114 RORC (Rotate Byte Data of Accumulator with Carry to Right) ........................................ 2698.115 SBBS (Set Bit and Branch if Bit Set) ............................................................................... 2718.116 SCEQ, SCEQI (Scan String Byte until equal with Increment) ......................................... 2728.117 SCEQD (Scan String Byte until equal with Decrement) .................................................. 2748.118 SCWEQ, SCWEQI (Scan String Word until equal with Increment) ................................. 2768.119 SCWEQD (Scan String Word until Equal with Decrement) ............................................. 2788.120 SETB (Set Bit) ................................................................................................................. 2808.121 SUB (Subtract Byte Data of Source from Destination to Destination) ............................. 2818.122 SUBC (Subtract Byte Data of AL from AH with Carry to AL) ........................................... 2838.123 SUBC (Subtract Byte Data of Effective Address from Accumulator with Carry to Accumulator)
......................................................................................................................................... 2848.124 SUBCW (Subtract Word Data of Effective Address from Accumulator with Carry to
Accumulator) ................................................................................................................... 2868.125 SUBDC (Subtract Decimal Data of AL from AH with Carry to AL) ................................... 2888.126 SUBL (Subtract Long Word Data of Source from Destination to Destination) ................. 2898.127 SUBW (Subtract Word Data of Source from Destination to Destination) ........................ 2918.128 SUBW (Subtract Word Data of AL from AH to AL) .......................................................... 2938.129 SWAP (Swap Byte Data of Accumulator) ........................................................................ 2948.130 SWAPW (Swap Word Data of Accumulator) ................................................................... 2958.131 UNLINK (Unlink and Create New Stack Frame) .............................................................. 2968.132 WBTc (Wait until Bit Condition Satisfied) ........................................................................ 2978.133 XCH (Exchange Byte Data of Source to Destination) ..................................................... 2998.134 XCHW (Exchange Word Data of Source to Destination) ................................................. 3018.135 XOR (Exclusive Or Byte Data of Destination and Source to Destination) ....................... 3038.136 XORL (Exclusive Or Long Word Data of Destination and Source to Destination) ........... 3058.137 XORW (Exclusive Or Word Data of AH and AL to AL) .................................................... 3078.138 XORW (Exclusive Or Word Data of Destination and Source to Destination) .................. 3088.139 ZEXT (Zero Extend from Byte Data to Word Data) ......................................................... 3108.140 ZEXTW (Zero Extend from Word Data to Long Word Data) ........................................... 311
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APPENDIX ............................................................................................................. 313APPENDIX A Explanation of Instruction Lists ............................................................................. 314
A.1 Items Used in Instruction Lists ........................................................................................ 315A.2 Symbols Used in Instruction Lists ................................................................................... 317A.3 Effective Address Field ................................................................................................... 319
APPENDIX B Instruction Lists (351 Instructions) ........................................................................ 320APPENDIX C Instruction Maps .................................................................................................... 336
C.1 Structure of the Instruction Map ...................................................................................... 337C.2 Basic Page Map .............................................................................................................. 339C.3 Bit Operation Instruction Map .......................................................................................... 341C.4 Character String Operation Instruction Map .................................................................... 343C.5 2-byte Instruction Map ..................................................................................................... 345C.6 ea-type Instruction Map ................................................................................................... 347C.7 MOVEA RWi, ea Instruction Map .................................................................................... 357C.8 MOV Ri, ea Instruction Map ............................................................................................ 359C.9 MOVW RWi, ea Instruction Map ..................................................................................... 361C.10 MOV ea, Ri Instruction Map ............................................................................................ 363C.11 MOVW ea, RWi Instruction Map ..................................................................................... 365C.12 XCH Ri, ea Instruction Map ............................................................................................. 367C.13 XCHW RWi, ea Instruction Map ...................................................................................... 369
INDEX ......................................................................................................................371
x
xi
Main changes in this edition
Page Changes (For details, refer to main body.)
20 CHAPTER 3 DEDICATED REGISTER3.2 Accumulator (A)■ Accumulator (A)
Changed the register name.A register → Accumulator (A)
39 CHAPTER 5 PREFIX CODES5.1 Bank Select Prefix■ Bank Select Prefix
Added LINK, UNLINK instructions to Other types of control instructions (stack manipulation).
41 5.3 Flag Change Inhibit Prefix Code (NCC)
■ Flag Change Inhibit Prefix Code (NCC)
Corrected the instruction.FISW → FILSW
Deleted the MOVE and MOVSW instructions.
Corrected an explanation.
49 CHAPTER 6 INTERRUPTS6.2 Interrupt Vector■ Interrupt Vector● Interrupt Vector Table
Corrected the instructions.CALLV 14 → CALLV 14/15
51 6.3 Interrupt Control Registers (ICR)
■ Interrupt Control Register (ICR)
Corrected the initial value of IX."0" → 0CH
69 6.9 Exceptions■ Hardware Exceptions (Non
Maskable Interrupts)● Instruction break (VEIB, system
reserved, only available with DSU)
Corrected an explanation.before execution → after instruction execution
73 CHAPTER 7 ADDRESSING7.2 Direct Addressing■ Direct Addressing● Direct branch address (addr16)
Corrected the register name.program bank register (PCB) → program counter bank register (PCB)
76 7.3 Indirect Addressing■ Indirect Addressing● Program counter indirect with
displacement (@PC+disp16)
Corrected the register name.program bank register (PCB) → program counter bank register (PCB)
● Program counter relative branch address (rel)
- CHAPTER 8 DETAILED INSTRUCTIONS
Changed the flag name in "CHAPTER 8 DETAILED INSTRUCTIONS".Carry bit (C) → Carry flag (C)
81 8.1 Instruction Overview■ Symbols (Abbreviations) Used
in Detailed InstructionsTable 8.1-1
Added brg3.
xii
83 8.2 ADD (Add Byte Data of Destination and Source to Destination)
Corrected the explanation.bit 8 to 15 of A → upper byte of AL
86 8.4 ADDC (Add Byte Data of Accumulator and Effective Address with Carry to Accumulator)
Corrected an explanation.bit 8 to 15 of A → upper byte of AL
● Operation: Corrected an explanation.(ea) → (second operand)
88 8.5 ADDCW (Add Word Data of Accumulator and Effective Address with Carry to Accumulator)
● Operation:
Corrected an explanation.(ea) → (second operand)
114 8.20 BBcc (Branch if Bit Condition satisfied)
● Assembler format:
Corrected explanations.<First operand> → addr16:bp<First operand> → dir:bp<First operand> → io:bp
119 8.22 CALL (Call Subroutine)● Example:
Changed an instruction.CALL @RW0 → CALL @@RW0
141 8.35 DIV (Divide Word Data by Byte Data)
Corrected the explanation when the overflow is occur. AL are destroyed → AL are undefined
142 ● Example: Changed Figure of Example.EC D8 → 00 C7
143 8.36 DIV (Divide Long Word Data by Word Data)
Corrected the explanation when the overflow is occur.AL are destroyed → AL are undefined
152 8.41 EXTW (Sign Extend from Word Data to Long Word Data)
● Operation:
Corrected an explanation.bits 16 to 31 of A → AH
178 8.57 LSLW (Logical Shift Word Data of Accumulator to Left)
Added the following explanations.The least significant bit of the accumulator (A) is set to "0".
198 8.68 MOVB (Move Bit Data from Bit Address to Accumulator)
Added the following descriptions summary sentence.The value in AL is transferred to AH.
202 8.70 MOVEA (Move Effective Address to Destination)
● Assembler format:
Corrected operands. <destination> → A<destination> → RWi
214 8.77 MOVSWD (Move String Word with Decrement)
Corrected the instructions name.MOVSWI → MOVSWD
● Assembler format:
225 8.84 MOVX (Move Byte Data with Sign Extension from Source to Accumulator)
● Byte count and cycle count:
Corrected the byte count of "MOVX A,Ri" instruction.2 → 1
Page Changes (For details, refer to main body.)
xiii
235 8.93 NEG (Negate Byte Data of Destination)
Corrected a summary sentence.bits 8 to 15 of A → upper byte of AL
252 8.104 POPW (Pop Word Data of Accumulator from Stack Memory)
Corrected summary sentences.bits 16 to 31 for the accumulator (A) → AHbits 0 to 15 for the accumulator (A) → AL
273 8.116 SCEQ, SCEQI (Scan String Byte until equal with Increment)
● Assembler format:
Deleted the following explanation.(When the address is incremented)
275 8.117 SCEQD (Scan String Byte until equal with Decrement)
Deleted the following explanation.(When the address is decremented)
282 8.121 SUB (Subtract Byte Data of Source from Destination to Destination)
Corrected a summary sentence.bits 8 to 15 of A → upper byte of AL
284 8.122 SUBC (Subtract Byte Data of AL from AH with Carry to AL)
Corrected a summary sentence.bits 8 to 15 of the accumulator (A). → upper byte of AL
285 8.123 SUBC (Subtract Byte Data of Effective Address from Accumulator with Carry to Accumulator)
Corrected a summary sentence.bits 8 to 15 of A → upper byte of AL
289 8.125 SUBDC (Subtract Decimal Data of AL from AH with Carry to AL)
Corrected a summary sentence.bits 8 to 15 of A → upper byte of AL
295 8.129 SWAP (Swap Byte Data of Accumulator)
● Operation:
Changed an explanation.
296 8.130 SWAPW (Swap Word Data of Accumulator)
● Operation:
Changed an explanation.
300 8.133 XCH (Exchange Byte Data of Source to Destination)
● Operation:
Changed an explanation.
302 8.134 XCHW (Exchange Word Data of Source to Destination)
Changed an explanation.
311 8.139 ZEXT (Zero Extend from Byte Data to Word Data)
Corrected a summary sentence.bits 8 to 15 of the accumulator (A) → upper byte of AL
● Operation: Corrected an explanation.Bits 8 to 15 of A → AL[15:8]
312 8.140 ZEXTW (Zero Extend from Word Data to Long Word Data)
Corrected a summary sentence.bits 16 to 31 of the accumulator (A) → AH
● Operation: Corrected an explanation.Bits 16 to 31 of A → AH
Page Changes (For details, refer to main body.)
xiv
The vertical lines marked in the left side of the page show the changes.
320 APPENDIXAPPENDIX B Instruction Lists
(351 Instructions)Table B-1
Corrected the byte count (#) of "MOVX A,Ri" instruction.2 → 1
333 Table B-14 Corrected the operand of MOVB instruction.MOVB addr16:bp → MOVB addr16:bp, A
Page Changes (For details, refer to main body.)
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 1
CHAPTER 1CPU
This chapter describes an overview of the
F2MC-16FX CPU core and its sample configuration.
1.1 Overview of CPU
1.2 Sample Configuration
F2MC-16FX Family
2 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 1 CPU1.1 Overview of CPU
1.1 Overview of CPU
The F2MC-16FX CPU core is a 16-bit CPU designed for applications that require high-speed real-time processing, such as home-use or vehicle-mounted
electronic appliances. The F2MC-16FX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing.
■ Overview of CPU
In addition to 16-bit data, the F2MC-16FX CPU core can process 32-bit data by using an
internal 32-bit accumulator. 32-bit data can be processed with some instructions. Up to 16
MBytes of memory space can be used, which can be accessed by either the linear pointer or
bank method. The instruction set is compatible to F2MC-16LX. The instruction set is
compatible with high-level languages, has a rich set of addressing modes, multiplication and
division instructions, and bit processing. The features of the F2MC-16FX CPU are explained
below.
● Fast execution speed
• Minimum instruction execution time: 16 ns (when operating at an internal frequency of 64MHz)
• Basic instructions are executed in one cycle
• High speed processing using a 5 stage pipeline
• 8 byte instruction queue
● General purpose registers: 32 banks x 8 words x 16 bits
● Memory space: 16 MBytes, accessed in linear or bank method
● Instruction set optimized for controller applications
• High code efficiency
• Rich data types: Bit, byte, word, long word
• Extended addressing modes: 23 types
• High-precision operation (32-bit length) based on 32-bit accumulator
• Signed and unsigned multiplication and division instructions
● Powerful interrupt functions
• Fast response speed (about 10 clock cycles CLKB)
• Eight priority levels (programmable)
• Non maskable interrupt (NMI)
• DMA transfer can serve interrupt requests (16 channels max.) without involving CPU
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 3
CHAPTER 1 CPU1.1 Overview of CPU
● Instruction set compatible with high-level language (C)/multitasking
• System stack pointer
• Instruction set symmetry
• Barrel shift instructions
F2MC-16FX Family
4 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 1 CPU1.2 Sample Configuration
1.2 Sample Configuration
A sample configuration of the F2MC-16FX CPU and that of the MCU device are shown.
■ Hardware Configuration of the F2MC-16FX CPU
● Figure 1.2-1 shows the block diagram of the F2MC-16FX CPU.
Figure 1.2-1 Block diagram of F2MC-16FX CPU
● CPU Pipeline Operation
To execute most instructions in one clock cycle, the CPU uses a five-stage instruction pipeline.
The pipeline consists of the following stages:
• Instruction fetch (IF): Fetches the instruction from instruction queue.
• Instruction decode 1 (D1): Decodes the instruction and controls address operation.
• Instruction decode 2 (D2): Decodes the instruction and selects operands and data operation.
• Execution (EX): Executes the operation.
• Write back (WB): Writes the operation result to a register or memory location.
Direct Page Register
DPR
Bank Register
USB, SSB, DTB, ADB
Stack Pointer
USP, SSP
GeneralPurpose
Register
Ri, RWi, RLi
Program Counter
PCB, PC
Processor Status
PS
Accumulator
AH, AL
Instruction
Queue
ALU
Decode Address
Operation
Operation
Decode Data
Fetch stage
Decode stage 1
Decode Stage 2
F2MC-16FX CPU
Execution stage
Write Back stage
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 5
CHAPTER 1 CPU1.2 Sample Configuration
Figure 1.2-2 Instruction Pipeline
Instructions are not executed out of order. Therefore, if instruction A enters the pipeline ahead
of instruction B, instruction A always reaches write back stage before instruction B.
The standard instruction execution speed is one instruction per cycle. However, transfer
instructions that involve memory wait, branch instructions and multi-cycle instructions require
more than one cycle to execute. The instruction execution speed also drops if the delivery of
instructions during code fetch is slow.
● Instruction Queue
The CPU has an instruction queue of 8 byte.
The instruction queue is filled by the fetch unit. Prefetch is used on consecutive addresses for
code fetch. The prefetch mechanism removes drawbacks due to the latency of the pipelined
implementation of the CPU and the system bus of the 16FX core.
● Program counter
The program counter bank (PCB, upper 8 bits of the program address) and the program counter
(PC, lower 16 bits of the program address) are controlled by the decode stage 1.
The instruction that is executed next is specified by a 24-bit address {PCB, PC} where the
program counter bank (PCB) and the program counter (PC) are concatenated.
● ALU
The ALU is controlled by decode stage 2. The operation mode of the ALU is selected and the
operands are loaded. The execution of the operation is performed in the next cycle.
The ALU is used for logical and arithmetical operations. Multiplication and division are
included.
● CPU registers and memory access
In the write back stage, the result of the operation is written to CPU registers and/or to a
memory location. All CPU registers except the program counter are assigned to the last
pipeline stage.
EX
D2
D1
IF
EX
D2
D1
IF
EX
D2
D1
WB
EX
D2
WB
EX WB
WB
WB
WB
Instruction 6
Instruction 5
Instruction 4
Instruction 3
Instruction 2
Instruction 1
CLK
F2MC-16FX Family
6 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 1 CPU1.2 Sample Configuration
■ Sample Hardware configuration of F2MC-16FX Family MCU
Figure 1.2-3 shows a sample hardware configuration of the MCU device based on the F2MC-
16FX CPU.
Figure 1.2-3 MCU Device based on the F2MC-16FX Core
● Interrupt Controller
The interrupt controller evaluates the priority of incoming interrupt requests (IRQ) and selects
the interrupt number with the highest priority. If accepted, the selected interrupt service is
processed by the CPU. Each hardware IRQ has its own interrupt level register to control its
priority.
● DMA Controller
The DMA controller can also serve IRQs, but without interrupting the actual program
execution of the CPU. This can be used to automate data transfer between peripherals and
memory.
Depending on the device, up to 16 DMA channels are usable. Each DMA channel can select an
IRQ number to be served.
RAM
(data area)
ROM
(program area)
Boot ROMF2MC-16FX
CPU
Interrupt
Controller
DMA
Controller
Clock and
Mode Control
External Bus
Interface
Peripheral
Bus Bridge
Peripheral
Bus Bridge
CAN
Timer Serial ADC
16
FX
Co
re B
us
F2MC-16FX Core
User Ports
Peripheral Bus 2
Peripheral Bus 1
MCU Device
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 7
CHAPTER 1 CPU1.2 Sample Configuration
● Clock and Mode Control
This unit has control over the operation mode and monitors correct operation of the device. It
supplies all units with their appropriate clock, depending on the operation mode.
● External Bus Interface
The external bus interface is an optional component. Its availability depends on the
configuration of the specific device.
● Boot ROM
After device initialization by reset, the program counter points to the boot ROM. Then, the
CPU starts the execution of the boot ROM program. After further device initialization the reset
vector is fetched and the boot ROM code branches to user program execution starting at the
reset vector.
● Peripheral Bus Bridge
The peripheral bus bridge acts as an interface between the system bus of the F2MC-16FX core
and the peripheral bus connecting to all other MCU internal peripheral resources.
The peripheral bus bridge synchronizes between core clock and peripheral clock domains.
F2MC-16FX Family
8 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 1 CPU1.2 Sample Configuration
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 9
CHAPTER 2MEMORY SPACE
This chapter describes memory spaces in the
F2MC-16FX CPU.
2.1 CPU Memory Space
2.2 Linear Addressing Mode
2.3 Bank Addressing Mode
2.4 Memory Space Divided into Banks and Value in Each Bank Register
2.5 Data Configuration of and Access to Multi-byte Data in Memory
F2MC-16FX Family
10 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 2 MEMORY SPACE2.1 CPU Memory Space
2.1 CPU Memory Space
All data, programs, and I/O areas managed in the CPU are allocated in its 16-Mbyte memory space. The CPU can access these resources using an address on the 24-bit address bus (see Figure 2.1-1 ).
The F2MC-16FX addressing mode can be classified either as a linear or bank mode. The linear mode specifies an entire 24-bit address using a instruction. The bank mode specifies the upper 8 bits of each address using a bank register, and the remaining 16-bit address using an instruction.
■ CPU Memory Space
Figure 2.1-1 Example of Relationship between the F2MC-16FX System and Memory Map
F2MC-16FX
FFFFFFH
FF8000H
810000H
800000H
0000C0H
0000B0H
000020H
000000H
Program area
Data area
Interrupt controller
Peripheral circuit
CPU
Interrupt
Data
Program
[Device]General-purpose port
⎨⎧⎩
⎨⎧⎩
⎨⎧⎩
⎨⎧⎩
⎨⎪⎧
⎩⎪⎪
⎪
General-purpose
Peripheralcircuit
port
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 11
CHAPTER 2 MEMORY SPACE2.2 Linear Addressing Mode
2.2 Linear Addressing Mode
The linear addressing mode of the F2MC-16FX specifies an entire 24-bit address using an instruction.
■ Linear Addressing Mode
The linear addressing mode of the F2MC-16FX specifies an entire 24-bit address using an
instruction. The address mode of the F2MC-16FX is determined according to the specification
of the effective address or instruction code (implied) of an instruction.
The linear addressing mode can operate in two different ways. In the first way, an operand of
an instruction directly specifies an entire 24-bit address. In the second way, the lower 24-bit of
a 32-bit general-purpose register is referred as an address (see Figure 2.2-1 ).
Figure 2.2-1 Examples of Generating an Address in the Linear Addressing Mode
Previous content of452D
17452DHJMPP 123456H
123456H
17program counter plus
Next instructionLatest content of
345612program counter plus
program bank
program bank
Example 2: Indirect Addressing Based on 32-bit Register in the Linear Addressing Mode
MOV A @RL1+7
090700H
+7
RL1(Upper 8 bits are ignored.)
XXXX
003A
3A
240906F9
Previous content of the AL
Latest contentof the AL
Example 1: 24-bit Operand Specification in the Linear Addressing Mode
JMPP 123456H
F2MC-16FX Family
12 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 2 MEMORY SPACE2.3 Bank Addressing Mode
2.3 Bank Addressing Mode
The bank addressing mode of the F2MC-16FX specifies the upper 8 bits of an address using a bank register for use, and the remaining 16 bits using an instruction.
■ Bank Addressing ModeIn the bank addressing mode, the 16-Mbyte memory space is divided into 256 banks of 64-
Kbyte, and the corresponding bank to each space is specified by the following 4 bank registers.
● Program counter bank register (PCB)
A 64-Kbyte bank specified using the PCB register is called a program (PC) space. It is used to
hold mainly instruction codes, vector tables, and immediate data.
● Data bank register (DTB)
A 64-Kbyte bank specified using the DTB register is called a data (DT) space. It is used to
hold mainly readable/writable data and control/data registers for internal and external
resources.
● User stack bank register (USB) and system stack bank register (SSB)
A 64-Kbyte bank specified using the USB or SSB register is called a stack (SP) space. It is
accessed when the execution of a push or pop instruction or interrupt handling is performed to
save register contents and a stack access occurs. And which to be used, the USB or SSB
register, is determined according to the stack flag (S) in the condition code register (CCR).
● Additional data bank register (ADB)
A 64-Kbyte bank specified using the ADB register is called an additional (AD) space. It is
used to hold mainly data overflowing from the DT space.
Each instruction is assigned with one of the default spaces by each addressing listed in Table
2.3-1 to improve instruction code efficiency.
Table 2.3-1 Default Spaces
Default space Addressing
Program space PC-indirect, program access, branch type
Data space @A, addr16, dir, or addressing using @RW0, @RW1, @RW4, or @RW5
Stack space Addressing using PUSHW, POPW, @RW3, @RW7, or @SP
Additional space Addressing using @RW2 or @RW6
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 13
CHAPTER 2 MEMORY SPACE2.3 Bank Addressing Mode
If a space other than a default space is used, an arbitrary bank space corresponding to a prefix
code can be accessed by specifying the prefix code before the instruction.
Table 2.3-2 lists bank select prefixes and the memory space selected using each prefix.
The DTB, USB, SSB, and ADB registers are initialized to 00H at a reset. The PCB register is
initialized to FFH at a reset. After a reset, the data, stack, and additional spaces are allocated in
bank 00H (000000H to 00FFFFH), and the program space is allocated in bank FFH (FF0000H to
FFFFFFH).
Table 2.3-2 Bank Selection Prefix
Bank select prefix Selected space
PCB Program space
DTB Data space
ADB Additional space
SPBSystem or user stack space depending on the contents of the selected stack flag (S)
F2MC-16FX Family
14 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 2 MEMORY SPACE2.4 Memory Space Divided into Banks and Value in Each Bank Register
2.4 Memory Space Divided into Banks and Value in Each Bank Register
Figure 2.4-1 shows an example of a memory space divided into banks and a value in each register bank.
■ Memory Space Divided into Banks and Values in Each Register Bank
Figure 2.4-1 Example of the Physical Addresses of Each Space
Phy
sica
l Add
ress
FFFFFFH
FF0000H
B3FFFFH
B30000H
92FFFFH
920000H
68FFFFH
680000H
4BFFFFH
4B0000H
000000H
Program space
Additional space
User stack space
Data space
System stack space
FFH : PCB (program counter bank register)
B3H : ADB (additional data bank register)
92H : USB (user stack bank register)
68H : DTB (data bank register)
4BH : SSB (system stack bank register)
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 15
CHAPTER 2 MEMORY SPACE2.5 Data Configuration of and Access to Multi-byte Data in
Memory
2.5 Data Configuration of and Access to Multi-byte Data in Memory
Multi-byte data is written to memory starting at the lowest address. If the multi-byte data is 32-bit long, the lower 16 bits are written to memory first and then upper 16 bits.
■ Multi-byte Data Layout in a Memory SpaceMulti-byte data is written to memory starting at the lowest address. If the multi-byte data is
32-bit length, the lower 16 bits are written to memory first and then upper 16 bits.
If a reset signal is input immediately after the low-order data is written to memory, the high-
order data may not be written. To keep the data in integrity, it is necessary to input a reset
signal after the high-order data is written.
Figure 2.5-1 shows the layout of multi-byte data in memory. The lower 8 bits are placed at
address n, the next lower 8 bits are placed at address n + 1, and the next lower 8 bits are placed
at address n + 2, and so on.
Figure 2.5-1 Multi-byte Data Layout in Memory
H
Address n
L
01010101
MSB LSB
11001100 11111111 00010100
01010101
11001100
11111111
00010100
F2MC-16FX Family
16 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 2 MEMORY SPACE2.5 Data Configuration of and Access to Multi-byte Data in Memory■ Access to Multi-byte Data
When multi-byte data is accessed, it is assumed that all parts of the multi-byte data are within a
single bank. To put it another way, an instruction accessing multi-byte data assumes that an
address that follows address FFFFH is 0000H in the same bank as for FFFFH.
Figure 2.5-2 shows an execution example of an instruction accessing multi-byte data.
Figure 2.5-2 Execution Example of an Instruction (MOVW A, 080FFFFH) Accessing Multi-byte Data
Higher address
80FFFFH
800000H
AL before execution
Lower address
?? ??
AL after execution 23H 01H
···
23H
01H
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 17
CHAPTER 3DEDICATED REGISTER
The F2MC-16FX CPU registers are classified into two types: dedicated registers and general-purpose registers. This chapter describes the
dedicated registers of the F2MC-16FX CPU. The dedicated registers are dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture. These registers can be accessed without using an address. The register operations are defined by specific instructions.
3.1 Structure of the Dedicated Registers
3.2 Accumulator (A)
3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)
3.4 Processor Status (PS)
3.5 Program Counter (PC)
3.6 Direct Page Register (DPR)
3.7 Bank register (PCB, DTB, ADB, USB, SSB)
F2MC-16FX Family
18 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 3 DEDICATED REGISTER3.1 Structure of the Dedicated Registers
3.1 Structure of the Dedicated RegistersThe F2MC-16FX CPU has the following dedicated registers:
• Accumulator (A=AH:AL): Two 16-bit accumulators (can be used as a single 32-bit accumulator)
• User stack pointer (USP): 16-bit user stack pointer
• System stack pointer (SSP): 16-bit system stack pointer
• Processor status (PS): 16-bit register indicating the system status
• Program counter (PC): 16-bit register holding the address of the next instruction to be executed
• Program counter bank register (PCB): 8-bit register indicating the program counter bank
• Data bank register (DTB): 8-bit register indicating the data bank
• User stack bank register (USB): 8-bit register indicating the user stack bank
• System stack bank register (SSB): 8-bit register indicating the system stack bank
• Additional data bank register (ADB): 8-bit register indicating the additional data bank
• Direct page register (DPR): 8-bit register indicating the page for direct access
F2MC-16FX Family
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CHAPTER 3 DEDICATED REGISTER3.1 Structure of the Dedicated Registers
Figure 3.1-1 shows a diagram of the dedicated registers.
Figure 3.1-1 Dedicated registers
Accumulator
User stack pointer
System stack pointer
Processor status
Program counter
Direct page register
Program counter bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
USP
SSP
PS
PC
DPR
PCB
DTB
USB
SSB
ADB
8 bit16 bit
32 bit
AH AL
F2MC-16FX Family
20 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 3 DEDICATED REGISTER3.2 Accumulator (A)
3.2 Accumulator (A)
The accumulator (A) consists of two 16-bit arithmetic operation registers (AH and AL), and is used as a temporary storage for operation results and transfer data.
■ Accumulator (A)The Accumulator (A) consists of two 16-bit arithmetic operation registers (AH and AL). The
Accumulator (A) is used as a temporary storage for operation results and transfer data. During
32-bit data processing, AH and AL are used together. Only AL is used for word processing in
16-bit data processing mode or for byte processing in 8-bit data processing mode (see Figure
3.2-1 and Figure 3.2-2).
The data stored in the Accumulator (A) can be operated upon with the data in memory or
registers (Ri, Rwi, or RLi). In the same manner as with the F2MC-16LX, when a word or
shorter data item is transferred to AL, the previous data item in AL is automatically sent to AH
(data preservation function). The data preservation function and operation between AL and AH
help to improve processing efficiency.
When a byte or shorter data item is transferred to AL, the data is sign-extended or zero-
extended and stored as a 16-bit data item in AL. The data in AL can be handled either as word
or byte.
When a byte-processing arithmetic operation instruction is executed on AL, the high-order
eight bits of AL before the operation are ignored. After the operation the high-order eight bits
become zero.
The Accumulator (A) is not initialized by a reset. The Accumulator (A) holds an undefined
value immediately after a reset.
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 21
CHAPTER 3 DEDICATED REGISTER3.2 Accumulator (A)
Figure 3.2-1 Example of a 32-bit data transfer
Figure 3.2-2 Example of AL-AH transfer by means of data preservation
+6
MSB
A61540H
A6153EH
RW1
8FH 74H
2BH 52H
15H 38H
LSB
A6HDTB
AH AL
Previous contentof the A register
Latest contentof the A register 8F74H 2B52H
XXXXH XXXXH
MOVL A, @RW1+6
+6
MSB
A61540H
A6153EH
RW1
XXXXH 1234H 8FH 74H
2BH 52H
15H 38H
LSB
A6HDTB
1234H 2B52H
AH AL
Previous contentof the A register
Latest contentof the A register
MOVW A, @RW1+6
F2MC-16FX Family
22 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 3 DEDICATED REGISTER3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)
3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data when a push/pop instruction or subroutine is executed.
■ User Stack Pointer (USP) and System Stack Pointer (SSP)USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring
data in the event of a push/pop instruction or subroutine execution. The USP and SSP registers
are used by stack instructions.
The USP register is enabled when the stack flag (S) in the processor status (PS) is “0”, and the
SSP register is enabled when the S flag is “1” (see Figure 3.3-1). Since the S flag is set when
an interrupt is accepted, register values are always saved in the memory area indicated by the
SSP register during interrupt processing. The SSP register is used for stack processing in an
interrupt routine, while the USP register is used for stack processing outside an interrupt
routine. If the stack space is not divided, use only the SSP register.
During stack processing, the high-order eight bits of an address are indicated by system stack
bank register (SSB) for the SSP register or user stack bank register (USB) for the USP register.
The USP and SSP registers are not initialized by a reset. Instead, the values of these registers
are undefined.
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 23
CHAPTER 3 DEDICATED REGISTER3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)
Figure 3.3-1 Stack manipulation instruction and stack pointer
Note:
Specify an even-numbered address in the stack pointer whenever possible. An odd-numbered address will be cause of drawback in stack performance.
AL A624 H USB USP
SSPSSB0
C6 H
56H
F328 H
1234 H
C6F326 H XXXX
AL A624 H USB USP
SSPSSB0
C6 H
56H
F326 H
1234 H C6F326 H 24HA6 H
AL A624 H USB USP
SSPSSB
C6 H
56H
F328 H
1234 H
561232 H XXXX
1
AL A624 H USB USP
SSPSSB1
C6 H
56H
F328 H
1232 H
561232 H 24HA6 H
Example 1 PUSHW A when the S flag is "0"
Before execution
S flag
After executionUser stack is used because
Example 2 PUSHW A when the S flag is "1"
System stack is used becausethe S flag is "1".
the S flag is "0".
MSB LSB
F2MC-16FX Family
24 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 3 DEDICATED REGISTER3.4 Processor Status (PS)
3.4 Processor Status (PS)
The PS register consists of the bits controlling the CPU Operation and indicating the CPU status.
■ Processor Status (PS)As shown in Figure 3.4-1, the high-order byte of the PS register consists of a register bank
pointer (RP) and an interrupt level mask (ILM). The RP indicates the start address of a register
bank. The low-order byte of the PS register is a condition code register (CCR), containing the
flags to be set or reset depending on the results of instruction execution or interrupt
occurrences.
Figure 3.4-1 Processor status (PS) structure
ILM RPPS
bit
CCR
15 13 12 8 7 0
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 25
CHAPTER 3 DEDICATED REGISTER3.4 Processor Status (PS)
■ Condition Code Register (CCR)Figure 3.4-2 shows the diagram of the condition code register (CCR) configuration.
Figure 3.4-2 Condition code register (CCR) configuration
● P: Privileged mode flag
The privileged mode flag (P) indicates user or system mode of CPU status.
When the P flag is "1", CPU is in the user mode.
When the P flag is "0", CPU is in the privileged mode.
The P flag is cleared by a reset. However, the P flag will be set during execution of the Boot
ROM code.
Only NMI, HW-INT9 (EDSU) and DSU interrupts will clear the P flag and disable all other
hardware interrupts. If the P flag is cleared, the interrupt level mask (ILM) defines system
interrupt levels of the privileged mode (P0 to P7). These interrupt levels have higher priority
than any ILM register setting in user mode (U0 to U7).
The P flag can be set by dedicated instructions (OR CCR, #imm8 / POPW PS) or by restoring
the processor status (RETI / JCTX @A). Restoring in the privileged mode (P=0) is not
accepted, if the P flag has been "1" before.
● I: Interrupt enable flag
Interrupts other than software interrupts are enabled when the I flag is "1" and are disabled
when the I flag is "0". The I flag is cleared by a reset.
● S: Stack flag
When the S flag is "0", USP is enabled as the stack pointer. When the S flag is "1", SSP is
enabled as the stack pointer. The S flag is set by an interrupt reception or a reset.
● T: Sticky bit flag
A value of "1" is set in the T flag when there is at least one "1" in the data shifted out from the
carry after execution of a logical right/arithmetic right shift instruction, otherwise, "0" is set in
the T flag. In addition, "0" is set in the T flag when the shift amount is zero.
● N: Negative flag
The N flag is set when the MSB of the operation result is "1", and is otherwise cleared.
● Z: Zero flag
The Z flag is set when the operation result is all zeroes, and is otherwise cleared.
0 0 1 0 00 0 0 initial value after reset
0 11 X X X X X value after Boot ROM execution
07 6 5 4 3 2 1
P I S T N Z V C PS: CCR
bit
F2MC-16FX Family
26 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 3 DEDICATED REGISTER3.4 Processor Status (PS)
● V: Overflow flag
The V flag is set when an overflow of a signed value occurs as a result of operation execution
and is otherwise cleared.
● C: Carry flag
The C flag is set when a carry-up or carry-down from the MSB or LSB occurs as a result of
operation execution, and is otherwise cleared.
■ Register Bank Pointer (RP)The RP register indicates the relationship between the general-purpose registers and the
internal RAM addresses. Specifically, the RP register indicates the first memory address of the
currently used register bank in the following conversion expression: [00180H + (RP) × 10H].
The RP register consists of five bits, and can take a value between 00H and 1FH. Register banks
can be allocated at addresses from 000180H to 00037FH in memory.
Figure 3.4-3 Register bank pointer (RP)
The RP register is initialized to all zeroes by a reset. An instruction may transfer an eight-bit
immediate value to the RP register; however, only the low-order five bits of that data are used.
0 00 0 0
RP
initial value
B4 B3 B2 B1 B0
15 14 13 12 11 10 9 8bit
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 27
CHAPTER 3 DEDICATED REGISTER3.4 Processor Status (PS)
■ Interrupt Level Mask (ILM)
The Interrupt Level Mask (ILM) consists of three bits, indicating the CPU interrupt masking
level. An interrupt request is accepted only when the priority of the interrupt is higher than that
indicated by the ILM register and the privileged mode flag (P).
Highest priority interrupt is level P0 and lowest priority is level U7. Therefore, for an interrupt
to be accepted, its level value must be smaller than the current ILM register value (see Figure
3.4-4 ). In addition, the P flag has to be considered. When an interrupt is accepted, the level
value of that interrupt is set in the P flag and ILM register. Thus, an interrupt of the same or
lower priority cannot be accepted subsequently.
Figure 3.4-4 Interrupt level (ILM)
ILM is initialized to 100B by a reset. However, during execution of the Boot ROM program
ILM is set to 000B.
An instruction may transfer an eight-bit immediate value to the ILM register, but only the low-
order three bits of that data are used (MOV ILM, #imm8 / POPW PS / RETI / JCTX @A). If
CPU is in user mode (P=1), any ILM register change is possible. If CPU is privileged mode
(P=0), an ILM register change is only accepted, if the new value defines a user level U0 to U7
(with P=1) or if the privileged level (P0 to P7) is increased. The lower levels of the privileged
mode P0 to P7 can not be reached by execution of an instruction from a higher level. Writing
"0" to the P flag and reducing the level with P=0 is only possible by NMI, HW-INT9 or a DSU
interrupt.
Note:
The P flag can be understood as bit extension of the ILM register. Then it defines themost significant bit of the interrupt level mask {P, ILM}.
After initialization with reset the CPU is in level P4. This disables all interrupts, including
NMI, except for the DSU. After execution of the Boot ROM program the CPU is in level U0.
Peripheral interrupts are disabled.
All privileged mode levels P0 to P7 are locked against entering or decreasing the level by an
instruction. The levels P0 to P7 can only be increased. This protects the operation of HW-
INT9, NMI and DSU operation. Only DSU can interrupt the NMI or mask its acceptance
during a debug session.
The user levels U0 to U7 are backward compatible to F2MC-16LX interrupt levels 0 to 7. The
P flag is not writable in a user level.
15 14 13 12 11 10 9 8
ILM2 ILM1 ILM0 PS: ILM
0 initial value after reset1 0
0 0 value after Boot ROM execution0
bit
F2MC-16FX Family
28 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 3 DEDICATED REGISTER3.4 Processor Status (PS)
Table 3.4-1 Levels indicated by the privileged mode flag (P) and interrupt level mask (ILM)
Level P flag ILM value Acceptable interrupt level
P0 0 0 none Interrupts disabled
P1 0 1 Level < P1 Interrupts disabled
P2 0 2 Level < P2 Interrupts disabled
P3 0 3 Level < P3 DSU
P4 0 4 Level < P4 DSU
P5 0 5 Level < P5 NMI, DSU
P6 0 6 Level < P6 NMI, DSU
P7 0 7 Level < P7 HW-INT9, NMI, DSU
U0 1 0 Level < U0 User Interrupts disabled HW-INT9, NMI, DSU
U1 1 1 Level < U1 User level 0
U2 1 2 Level < U2 User level 0, 1
U3 1 3 Level < U3 User level 0 to 2
U4 1 4 Level < U4 User level 0 to 3
U5 1 5 Level < U5 User level 0 to 4
U6 1 6 Level < U6 User level 0 to 5
U7 1 7 Level < U7 User level 0 to 6
F2MC-16FX Family
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CHAPTER 3 DEDICATED REGISTER3.5 Program Counter (PC)
3.5 Program Counter (PC)
The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU.
■ Program Counter (PC)The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address
of an instruction code to be executed by the CPU. The high-order eight bits of the address are
indicated by the program counter bank register (PCB).
The PC register is updated by a branch instruction, subroutine call instruction, interrupt or
reset. Within a linear program segment, the PC is incremented by the number of bytes of the
last instruction.
The PC register can also be used as a base pointer for operand access.
Figure 3.5-1"Program counter" shows the program counter.
Figure 3.5-1 Program counter
The reset address is fixed to the Boot ROM program start address of 0F:FC00H. At reset, the
PC register is initialized to FC00H and the PCB register is initialized to 0FH.
In external vector mode a value specified by the reset vector on address FF:FFDCH is loaded
when leaving the Boot ROM code execution. In internal vector mode the PCB and PC registers
are loaded with fixed values defined by the product.
PCB PCFE H ABCD H
FEABCD H
Next instruction to be executed
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CHAPTER 3 DEDICATED REGISTER3.6 Direct Page Register (DPR)
3.6 Direct Page Register (DPR)
The direct page register (DPR) specifies bits 8 to 15 of the operand address for direct addressing instructions.
■ Direct Page Register (DPR)The DPR register specifies bits 8 to 15 of the instruction operands in direct addressing mode as
shown in Figure 3.6-1.
Figure 3.6-1 Generating a physical address in direct addressing mode
The DPR register is eight bits long, and is initialized to 01H by a reset. The DPR register can be
read or written to by an instruction.
α α α α α α α α β β β β β β β β γ γ γ γ γ γ γ γ
α α α α α α α α β β β β β β β β γ γ γ γ γ γ γ γ
MSB
DTB register
24-bit physicaladdress
LSB
DPR register Direct address during instruction
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CHAPTER 3 DEDICATED REGISTER3.7 Bank register (PCB, DTB, ADB, USB, SSB)
3.7 Bank register (PCB, DTB, ADB, USB, SSB)
Each bank register indicates a memory bank where a program space, data space, user stack space or additional data space is allocated.
■ Bank RegisterAll bank registers are one byte long. Each bank register (PCB, DTB, USP, SSP, ADB)
indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is
allocated.
Bank registers other than PCB can be read and written to. PCB can be read but cannot be
written to. The PCB register is updated upon the JMPP or CALLP instruction, branching to the
entire 16 MByte space, upon the RETP or RETI instruction or upon an interrupt.
For details of the operation of bank registers, see section "2.3 Bank Addressing Mode".
● Program counter bank register (PCB)
Initial value: 0FH after reset, and later a value from reset vector at user program start.
● Data bank register (DTB)
Initial value: 00H.
● User stack bank register (USB)
Initial value: 00H.
● System stack bank register (SSB)
Initial value: 00H.
● Additional data bank register (ADB)
Initial value: 00H.
F2MC-16FX Family
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CHAPTER 3 DEDICATED REGISTER3.7 Bank register (PCB, DTB, ADB, USB, SSB)
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 33
CHAPTER 4GENERAL-PURPOSE
REGISTERS
The registers of the F2MC-16FX can be grouped into two major categories: dedicated registers in the CPU and general-purpose registers allocated in memory.
This chapter describes the F2MC-16FX general-purpose registers. These registers are allocated in a RAM in address space of the CPU. Similarly to the dedicated registers, the general-purpose registers can be accessed without specifying their address. However, the user can specify the purpose for which they are used in the same manner as for ordinary memory.
4.1 Register Banks in RAM
4.2 Calling General-purpose Registers in RAM
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CHAPTER 4 GENERAL-PURPOSE REGISTERS4.1 Register Banks in RAM
4.1 Register Banks in RAM
Each register bank consists of 8 words (16 bytes). They can be used as general-purpose registers (byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3) for performing various types of operations and specifying pointers. RL0 to RL3 can be used also as a linear pointer to gain direct access to all spaces in memory.
■ Register Banks in RAMTable 4.1-1 lists the function of each register, and Table 4.1-2 shows relationships between the
registers.
Table 4.1-1 Functions of Each Register
Register name Function
R0 to R7Used to hold an operand in various types of instructions.Note: R0 is also used as a barrel shift counter and a counter of normalize instruction.
RW0 to RW7Used to hold a pointer.Used to hold an operand in various types of instructions.Note: RW0 is used also as a string instruction counter.
RL0 to RL3Used to hold a long pointer.Used to hold an operand in various types of instructions.
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CHAPTER 4 GENERAL-PURPOSE REGISTERS4.1 Register Banks in RAM
Table 4.1-2 Relationship between Registers
Address Byte register Word register Long word register
000180H + RP × 10H + 0RW0
RL0000180H + RP × 10H + 1
000180H + RP × 10H + 2RW1
000180H + RP × 10H + 3
000180H + RP × 10H + 4RW2
RL1000180H + RP × 10H + 5
000180H + RP × 10H + 6RW3
000180H + RP × 10H + 7
000180H + RP × 10H + 8 R0RW4
RL2000180H + RP × 10H + 9 R1
000180H + RP × 10H + 10 R2RW5
000180H + RP × 10H + 11 R3
000180H + RP × 10H + 12 R4RW6
RL3000180H + RP × 10H + 13 R5
000180H + RP × 10H + 14 R6RW7
000180H + RP × 10H + 15 R7
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CHAPTER 4 GENERAL-PURPOSE REGISTERS4.2 Calling General-purpose Registers in RAM
4.2 Calling General-purpose Registers in RAM
For general-purpose registers, the register bank pointer (RP) is used to specify where in internal RAM between 000180H and 00037FH the register bank
currently in use is allocated.
■ Calling General-purpose Registers in RAMThe general-purpose registers are allocated in internal RAM between 000180H and 00037FH
(in maximum configuration). The register bank pointer (RP) is used to indicate where in
internal RAM between 000180H and 00037FH the register bank currently in use is allocated.
Each bank contains the following 3 different registers. These registers are not independent of
one another. Instead, they have the relationships shown in Figure 4.2-1 .
• R0 to R7: 8-bit general-purpose registers
• RW0 to RW7:16-bit general-purpose registers
• RL0 to RL3: 32-bit general-purpose registers
Figure 4.2-1 General-purpose Registers
The relationships among the high- and low-order bytes in word registers (RW4 to RW7) and
byte registers (R0 to R7) are represented using the following expression:
RW (i + 4) = R (i × 2 + 1) × 256 + R (i × 2) [where i = 0 to 3]
The relationships among the high- and low-order bytes in long registers (RL0 to RL3) and
word registers (RW0 to RW7) are represented using the following expression:
RL (i) = RW (i × 2 + 1) × 65536 + RW (i × 2) [where i = 0 to 3]
For example, if the data in R1 and the data in R0 are arranged as high- and low-order bytes,
respectively, the resulting data equals the data (2 bytes) in RW4.
Start address of a Lower order
MSB LSB
RW4
RL0RW0RW1RW2
R1 R0R3 R2R5 R4R7 R6
16 bits
Higher order
RW5RW6RW7
⎨⎧⎩
⎨⎧⎩
⎨⎧⎩
⎨⎧⎩
RL1
RL2
RL3
general-purpose register
000180H + RP × 10H
RW3
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 37
CHAPTER 5PREFIX CODES
The operation of an instruction can be modified by prefixing it with prefix code. The following 3 types of prefix codes are available.• Bank select prefix• Common register bank prefix• Flag change inhibit prefix codeThis chapter describes these prefixes.
5.1 Bank Select Prefix
5.2 Common Register Bank Prefix (CMR)
5.3 Flag Change Inhibit Prefix Code (NCC)
5.4 Constraints Related to the Prefix Codes
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CHAPTER 5 PREFIX CODES5.1 Bank Select Prefix
5.1 Bank Select Prefix
Placing a bank select prefix before an instruction enables selecting the memory space accessed by the instruction regardless of what the current addressing mode is.
■ Bank Select PrefixThe memory space of data to be accessed is determined according to the addressing mode.
Placing a bank select prefix before an instruction enables to select the memory space accessed
by the instruction regardless of what the current addressing mode is. Table 5.1-1 lists the bank
select prefixes and the memory space selected according to each bank select prefix.
The effect of the prefix codes is different for the following instructions.
• Transfer instructions (I/O access)
MOV A,io MOV io, A MOVX A,io MOVW A,ioMOVW io,A MOV io,#imm8 MOVW io,#imm16
These instructions access the I/O space regardless of whether there is a prefix before them.
• Branch instruction
RETI
The system stack bank register (SSB) is used regardless of whether there is a prefix beforethe branch instruction.
• Bit manipulation instructions (I/O access)
MOVB A,io:bp MOVB io:bp,A SETB io:bp
CLRB io:bp BBC io:bp,rel BBS io:bp,rel
WBTC WBTS
The I/O space is accessed regardless of whether there is a prefix before those instructions.
• String manipulation instructions
MOVS MOVSW SCEQ SCWEQFILS FILSW
A bank register specified in the operand is used regardless of whether there is a prefix beforethese instructions.
Table 5.1-1 Bank Select Prefixes
Bank select prefix Memory space to be selected
PCB Program counter space
DTB Data space
ADB Additional space
SPB System or user stack space depending on the state of the stack flag
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CHAPTER 5 PREFIX CODES5.1 Bank Select Prefix
• Other types of control instructions (stack manipulation)
PUSHW POPW POPW PS LINK
UNLINK
The system stack bank register (SSB) or user stack bank register (USB) is used depending onthe state of the stack flag (S), regardless of whether there is a prefix before these instructions.
In the following cases, the prefix of an instruction affects not only that instruction but also an
instruction that follows it.
• Other types of control instructions (flag change)
AND CCR,#imm8 OR CCR,#imm8
The operations of these instructions are performed normally. The prefix of each of theseinstructions affects not only the instructions but also an instruction that follows them.
• Another type of control instruction (interrupt control)
MOV ILM,#imm8
The operation of the instruction is performed normally. The prefix of the instruction affectsnot only that instruction but also an instruction that follows it.
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CHAPTER 5 PREFIX CODES5.2 Common Register Bank Prefix (CMR)
5.2 Common Register Bank Prefix (CMR)
Placing a common register bank prefix (CMR) before an instruction accessing a register bank enables to change that the instruction is to access only the registers in a common bank (register bank selected when RP = 0) allocated between 000180H and 00018FH, regardless of what the current value of the
register bank pointer (RP) is.
■ Common Register Bank Prefix (CMR)To make data exchange among tasks easier, it is necessary to use a method that can access a
certain specified register bank relatively easily no matter what value the register bank pointer
(RP) holds. To meet this requirement, the F2MC-16FX has a register bank that can be used by
all tasks in common. It is called a common bank. The common bank is allocated in memory
between address 000180H and 00018FH. It is selected when the RP register contains a value of
"0".
Placing the common register bank prefix (CMR) before an instruction accessing a register bank
enables to change that the instruction is to access only the registers in a common bank
regardless of what the current value of the RP register is.
The effect of the prefix codes is different for the following instructions.
• String instructions
MOVS NOVSW SCEQ FILSFILSW
If an interrupt is requested during execution of a string manipulation instruction attachedwith a prefix code, the prefix becomes ineffective for the string manipulation instruction aftera return is made from the interrupt handling routine, possibly resulting in a malfunction. Donot place the CMR prefix before these string manipulation instructions.
• Other types of control instructions (flag change)
AND CCR,#imm8 OR CCR,#imm8 POPW PS
The operations of these instructions are performed normally. The prefix of each of theseinstructions affects not only the instructions but also an instruction that follows them.
• Another type of control instruction (interrupt control)
MOV ILM, #imm8
The operation of the instruction is performed normally. The prefix of the instruction affectsnot only that instruction but also an instruction that follows it.
F2MC-16FX Family
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CHAPTER 5 PREFIX CODES5.3 Flag Change Inhibit Prefix Code (NCC)
5.3 Flag Change Inhibit Prefix Code (NCC)
Placing the flag change inhibit prefix code (NCC) before an instruction inhibits flags from changing during execution of the instruction.
■ Flag Change Inhibit Prefix Code (NCC)The flag change inhibit prefix code (NCC) is used to suppress undesired changes to flags.
Placing the NCC prefix before an instruction inhibits flags from changing during execution of
the instruction.
The effect of the prefix codes is different for the following instructions.
• Branch instructions
INT #vct8 INT9 INT addr16
INTP addr24 RETI
These instructions change the flags in the condition code register (CCR) regardless ofwhether there is a prefix before them.
• String instructions
SCEQ SCWEQ FILS FILSW
Placing a NCC prefix before the string instructions listed above is ignored. Flags in thecondition code register (CCR) are changing according to the instruction specifications,regardless of a NCC prefix is specified or not.
• Another type of control instruction (task switching)
JCTX @A
This instruction changes the flags in the condition code register (CCR) regardless of whetherthere is a prefix before it.
• Other types of control instructions (flag change)
AND CCR,#imm8 OR CCR,#imm8 POPW PS
These instructions change the flags in the CCR register regardless of whether there is a prefixbefore them. The prefix of each of these instructions affects not only the instructions butalso an instruction that follows them.
• Another type of control instruction (interrupt control)
MOV ILM,#imm8
The operation of the instruction is performed normally. The prefix of the instruction affectsnot only that instruction but also an instruction that follows it.
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CHAPTER 5 PREFIX CODES5.4 Constraints Related to the Prefix Codes
5.4 Constraints Related to the Prefix Codes
If a prefix code is placed before an instruction where interrupt and hold requests are inhibited, the effect of the prefix code lasts until an instruction where neither an interrupt nor hold request is inhibited appears for the first time.If a prefix is followed by conflicting prefix codes, the last one is valid.
■ Relationships between Instructions Rejecting Interrupt Requests and Prefix Codes
The following 10 instructions/prefix codes reject interrupt and hold requests.
• MOV ILM,#imm8 • AND CCR,#imm8
• OR CCR,#imm8 • POPW PS
• PCB • ADB
• NCC • DTB
• SPB • CMR
If an interrupt or hold request is issued during execution of any of the above instructions, the
request is accepted only after any instruction not listed above appears for the first time after
that instruction and is executed, as shown in Figure 5.4-1 .
Figure 5.4-1 Instructions Rejecting Interrupt and Hold Requests
If a prefix code is placed before an instruction rejecting interrupt and hold requests, its effect
lasts until an instruction other than instructions rejecting interrupt and hold requests appears for
the first time after the prefix code and is executed, as shown in Figure 5.4-2 .
Figure 5.4-2 Instructions Rejecting Interrupt and Hold Requests and Prefix Code
Instructions rejecting interrupt and hold requests
(a)
Interrupt request issued Interrupt accepted (a): Ordinary instruction
• • • • • • • • • • •
Instructions rejecting interrupt and hold requests
ADD A,01H• • • •MOV A,FFHCCR: XXX10XX
The NCC protects the
NCC MOV ILM,#imm8CCR: XXX10XX
CCR from changing.
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CHAPTER 5 PREFIX CODES5.4 Constraints Related to the Prefix Codes
■ If Two or More Prefix Codes Appear in Succession
If a prefix is followed by conflicting prefix codes, the last one is valid (see Figure 5.4-3 ).
Figure 5.4-3 Consecutive Prefix Codes
The term "conflicting prefix codes" indicates PCB, ADB, DTB, and SPB in the above figure.
Prefix codes
ADB• • • • • • • • • DTB PCB ADD A,01H
The PCB prefix code is valid for this instruction.
F2MC-16FX Family
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CHAPTER 5 PREFIX CODES5.4 Constraints Related to the Prefix Codes
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CHAPTER 6INTERRUPTS
This chapter describes the interrupt functions and operations.
6.1 Overview of Interrupts
6.2 Interrupt Vector
6.3 Interrupt Control Registers (ICR)
6.4 Non Maskable Interrupt (NMI)
6.5 Interrupt Flow
6.6 Hardware Interrupts
6.7 Software Interrupts
6.8 Multiple interrupts
6.9 Exceptions
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CHAPTER 6 INTERRUPTS6.1 Overview of Interrupts
6.1 Overview of Interrupts
The F2MC-16FX has interrupt functions that terminate the currently executed program and transfer control to another specified program when a specific event occurs. There are four types of interrupt functions:• Hardware interrupt: Interrupt processing due to an internal resource event• Software interrupt: Interrupt processing due to a software event (instruction)• Exception: Handling of an operation exception• DMA: Data transfer without CPU interaction due to an internal resource event.
■ Hardware InterruptsA hardware interrupt is activated by an interrupt request from an internal resource. A hardware
interrupt request occurs when both the interrupt request flag and the interrupt enable flag in an
internal resource are set.
● Specifying an interrupt level
An interrupt level can be specified for the hardware interrupt. To specify an interrupt level, use
the level setting bits (IL0, IL1, and IL2) in the interrupt control register (ICR).
For each hardware interrupt its own interrupt level (IL) can be specified. Access to a dedicated
IL can be done by setting the index IX. Both IX and IL are accessible through the interrupt
control register (ICR).
● Masking a hardware interrupt request
A hardware interrupt request can be masked by using the interrupt enable flag (I) and the
interrupt level mask (ILM). The interrupt is executed only, when the I flag is set and the value
of the interrupt level (IL) is smaller than the interrupt level mask (ILM). In addition the
privileged mode flag (P) has to be set for hardware interrupt acceptance. The P flag, I flag and
ILM register are parts of the processor status (PS) of the CPU.
When an unmasked interrupt request occurs, the CPU saves 12 bytes of data that consists of
registers PS, PC, PCB, DTB, ADB, DPR, and A in the memory area indicated by the system
stack bank register (SSB) and system stack pointer (SSP).
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CHAPTER 6 INTERRUPTS6.1 Overview of Interrupts
■ Software InterruptsInterrupts requested by executing the INT instruction are software interrupts. An interrupt
request by the INT instruction does not have an interrupt request or enable flag. An interrupt
request is issued always by executing the INT instruction.
No interrupt level is assigned to the INT instruction. Therefore, the ILM register is not updated
when the INT instruction is used. Instead, the interrupt enable flag (I) is cleared and the
continuing interrupt requests are suspended.
■ Exceptions
Following software exceptions can be processed:
• Undefined instruction
• INT9
• INTE (only available on the EVA device)
Following hardware exceptions can be processed:
• NMI
• HW-INT9 (embedded debug support)
• DSU break factors (only available on the EVA device)
Exception processing is basically the same as interrupt processing. When an exception is
detected during instruction execution, exception processing is performed. In general, exception
processing occurs as a result of an unexpected operation. Therefore, use exception processing
only for debugging programs or for activating recovery software in an emergency case.
■ Direct Memory Access (DMA)
● DMA Function
F2MC-16FX offers a DMA function to automatically transfer data between peripheral
resources and memory upon an interrupt. The number of DMA channels is device dependent.
When a DMA data transfer of a specified count is completed, an interrupt processing program
is automatically executed on the original IRQ channel. The handling of such an interrupt by
DMA completion is same as for standard type of hardware interrupts.
For a detailed description of DMA, refer to the hardware manual for each device.
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CHAPTER 6 INTERRUPTS6.2 Interrupt Vector
6.2 Interrupt Vector
Hardware and software interrupts use the same vector table. The execution of interrupt service routines can be triggered by asserting the specific IRQ line or by executing the INT instruction and specifying the number of the interrupt vector. Interrupt vectors are allocated between addresses as shown in Table 6.2-2 . The location of the Interrupt vector table can be selected by the Table base register.
■ Interrupt Vector
● Interrupt Vector Table Base Register (TBR)
Figure 6.2-1 Interrupt vector Table base register (TBR)
The Table Base Register (TBR) allows to relocate the interrupt vector table to any memory
location in steps of 1 kbytes.
The value of the TBR register defines the high-order 14 bits TB[23:10] of the 24 bit start
address of the interrupt vector table. The low-order bits of TB[9:0] are fixed to "0".
The table base register (TBR) is initialized with FFFCH at reset, which results in an initial table
base TB[23:0] = FFFC00H.
The interrupt vector table has a size of 1 Kbyte (256 vector entries).
R:R/W:
readablereadable and writable
Address:
Initial Value:
Read/Write: R/W R/W R/W R/W R/W R/W R/WR/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W
0 0
R/W
TBRH, TBRL
R R
1 1 1 1 1 1 1 1 1 1 1 1 1 1
TB23 TB22 TB21 TB20 TB19 TB18 TB17 TB16 TB15 TB14 TB13 TB12 TB11 TB103A3H, 3A2H
bit
Table 6.2-1 Examples for TBR
TBR valuestart address of
Interrupt vector table (table base)
end of Interrupt vector table
Comment
FFFCH FF:FC00H FF:FFFFH as F2MC-16FX (default)
FB00H FB:0000H FB:03FFH start of ROM bank FB
00FCH 00:FC00H 00:FFFFH end of bank 00 (can be external memory)
0010H 00:1000H 00:13FFH inside of RAM-area
0000H 00:0000H 00:03FFH do not use, because of IO-area
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CHAPTER 6 INTERRUPTS6.2 Interrupt Vector
● Interrupt Vector Table
The interrupt vector table referenced during interrupt processing is assigned to addresses "256 ×TBR to 256 × TBR + 3FFH" in memory. The reset defaults are from FFFC00H to FFFFFFH for
the location of the vector table. If the vector table should not be located at top of ROM memory,
another TBR value has to be configured.
Hardware interrupts, exceptions and software interrupts share the same vector table. Hence the
interrupt service routine can either be called by a hardware interrupt or by the corresponding
software interrupt.
The three bytes of each start address of the interrupt service routines have to be written to the
appropriate interrupt vectors (VecAddr = 4 × (255-INT#) + 256 × TBR).
Table 6.2-2 Interrupt vector table (1 / 2)
Interrupt / Vector number Vector address Index of level
register in ICRHardware IRQ / Interrupt cause
INT 0CALLV 0/1 *
(TBR × 256)+3FCH -- --
INT 1CALLV 2/3 *
(TBR × 256)+3F8H -- --
INT 2CALLV 4/5 *
(TBR × 256)+3F4H -- --
INT 3CALLV 6/7 *
(TBR × 256)+3F0H -- --
INT 4CALLV 8/9 *
(TBR × 256)+3ECH -- --
INT 5CALLV 10/11 *
(TBR × 256)+3E8H -- --
INT 6CALLV 12/13 *
(TBR × 256)+3E4H -- --
INT 7CALLV 14/15 *
(TBR × 256)+3E0H -- --
INT 8MODE Byte
(TBR × 256)+3DCH -- Reset
INT 9 (TBR × 256)+3D8H -- INT9 instruction
INT 10 (TBR × 256)+3D4H -- Undefined Instruction Exception
INT 11 (TBR × 256)+3D0H -- NMI
INT 12 (TBR × 256)+3CCH IL12 Delayed Interrupt
INT 13 (TBR × 256)+3C8H IL13 RC clock Timer
INT 14 (TBR × 256)+3C4H IL14 Main Clock Timer
INT 15 (TBR × 256)+3C0H IL15 Sub Clock Timer
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CHAPTER 6 INTERRUPTS6.2 Interrupt Vector
*: When the program counter bank register (PCB) is same as TBR:TB[23:16] and TBR:TB[15:10] is equal to
111111B, the CALLV instruction vector area overlaps the vector table of the "INT #0" to "INT #7"
instruction. Ensure that the CALLV instruction does not use the same address as that of the "INT #0" to "INT
#7" instruction, or do not use "INT #0" to "INT #7" instruction.
INT 16 (TBR × 256)+3BCH IL16 <reserved for PLL Unlock>
INT 17 (TBR × 256)+3B8H IL17
Device specific peripheral.INT 18 (TBR × 256)+3B4H IL18
INT 19 (TBR × 256)+3B0H IL19
... ... ...
INT 254 (TBR × 256)+004H -- --
INT 255 (TBR × 256)+000H -- --
Table 6.2-2 Interrupt vector table (2 / 2)
Interrupt / Vector number Vector address Index of level
register in ICRHardware IRQ / Interrupt cause
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CHAPTER 6 INTERRUPTS6.3 Interrupt Control Registers (ICR)
6.3 Interrupt Control Registers (ICR)
For each peripheral resource that has an interrupt function, there is an interrupt control register (ICR). The interrupt control register (ICR) sets the interrupt level (IL) for the peripheral resource it is assigned to.
■ Interrupt Control Register (ICR)Figure 6.3-1 shows a diagram of the bit configuration of the interrupt control register (ICR).
Figure 6.3-1 Interrupt control register (ICR)
[bit15 to bit8] IX[7:0] : Index of the interrupt level (IL) to be accessed
These bits are readable and writable, and specify the index of the interrupt level of the
corresponding internal resource. It selects the number of the interrupt level to be accessed.
IL[n] belongs to the peripheral interrupt request number IRQ[n], which both are related to
the interrupt INT[n].
The system interrupts INT0 to INT11 have a fixed priority and thus have no interrupt levels.
Writing to interrupt levels below the index of 12 has no effect, reading returns an undefined
value. The same restriction applies for not available hardware interrupts above a device
dependent maximum interrupt number.
The IX[7:0] bits is initialized to 0CH at reset.
Figure 6.3-2 illustrates the access to level registers by the IX pointer. The dashed line around
IX and the selected IL shows the actual contents of the ICR.
Level configuration is written to or read from IL, where IX points to. To write the level
configuration to a dedicated IL, specify the according index by writing IX before or
simultaneously by word access. To read from a dedicated IL, IX must be written before
reading IL.
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
IL2 IL1 IL0
IX0IX1IX2IX3IX4IX5IX6IX7
R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0
R/W
0
R/W R/W R/W
X X X X X 1 1 1
ICR: IL
ICR: IX
R/W: readable and writable: no access
1 1
Address:
Initial Value:
Read/Write:
Address:
Initial Value:
Read/Write:
3A1H
3A0H
bit
bit
F2MC-16FX Family
52 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 6 INTERRUPTS6.3 Interrupt Control Registers (ICR)
Caution for the use of concurrent tasks:
In the case of concurrent tasks accessing the interrupt level information, be careful at the
handling of the indexed access:
- Use word access to write information to ICR:IX and ICR:IL simultaneously.
- At read access, set the index ICR:IX and read the whole ICR register using word access.
Check the ICR:IX value to match the intended index to be read for validation of the
correct ICR:IL entry.
[bit7 to bit3]: Unused bits
Read access returns an undefined value. Write always 0 to these bits.
[bit2 to bit0] IL[2:0] : Interrupt level setting bits
These bits are readable and writable, and specify the interrupt level of the corresponding
internal resources. Upon a reset, these bits are initialized to level 7 (no interrupt). Table 6.3-1
describes the relationship between the interrupt level setting bits and interrupt levels.
Figure 6.3-2 Relationship between index (IX), level (IL) and IRQ number, example for IX = 20
Table 6.3-1 Interrupt level setting bits and interrupt levels
IL2 IL1 IL0 Level
0 0 0 0 (Strongest)
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6 (Weakest)
1 1 1 7 (No interrupt)
ICR IRQ16
IRQ21
IRQ20
IRQ18
IRQ17
IRQ19
IL16
IL17
IL18
IL19
IL20
IL21
IX=20
F2MC-16FX Family
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CHAPTER 6 INTERRUPTS6.4 Non Maskable Interrupt (NMI)
6.4 Non Maskable Interrupt (NMI)
The F2MC-16FX CPU has a non maskable interrupt. The feature of the external NMI pin can be enabled, it’s level can be defined and a register to quit the NMI request is provided.
■ NMI Control Status Register (NMI)Figure 6.4-1 is a diagram of the bit configuration of the NMI control status register.
Figure 6.4-1 NMI control status register (NMI)
[bit7 to bit4]: Unused bits
Read access returns an undefined value. Write always 0 to these bits.
[bit3] FIX9 : Fix the location of the INT9 vector
The FIX9 bit changes to an alternative location of the interrupt vector of INT9. If it is set to
"1", the interrupt vector is obtained from address 0F:FFD8H. If it is set to "0" the INT9
vector location is defined by the TBR+3D8H. At reset the FIX9 bit is initialized to "0".
The function is used by the firmware executed at device startup. Making the interrupt vector
of INT9 independent from the table base register (TBR) improves the reliability of the
embedded debug support unit (EDSU).
[bit2] LEV : Signal activity level of the NMI pin
The LEV bit defines the signal activity level of the NMI pin. A value of "1" defines logic
high active input, a value of "0" define logic low active input of the NMI pin.
If the EN bit is not set, the LEV bit is readable and writable. If the EN bit is set, the state of
LEV is locked. In that case LEV can only be read, writing to LEV with EN=1 has no effect.
At reset the LEV bit is initialized to "1", thus the NMI pin is active high by default.
7 6 5 4 3 2 1 0
R/W
0
Address:
Initial Value:
Read/Write:
LEV EN FLAG NMI
R/W1 R/W0
1 X
R/W: readable and writable: no access
R/W1:R/W0:
readable, bit can be set onlyreadable, bit can be cleared only
3A5HFIX9
R/W
0
bit
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CHAPTER 6 INTERRUPTS6.4 Non Maskable Interrupt (NMI)
[bit1] EN : Non Maskable Interrupt feature enable bit
The EN bit enables the feature to have a dedicated NMI pin. If the EN bit is set to "0" the
device has no NMI. The CPU will not react on signal level change at the NMI input. The pin
can be used for an other function or general purpose. If the EN bit is set to "1", the NMI pin
is enabled. The CPU branches to the NMI exception processing, if an active signal level is
detected at the NMI pin (defined by the LEV bit).
If the EN bit is set to "1", both the LEV and EN bits are locked for writing. Neither the signal
level can be changed nor the NMI can be disabled after the NMI feature was enabled once.
Only a device reset can change the EN bit back to "0".
At reset the EN bit is initialized to "0", thus the NMI feature is not enabled by default.
The LEV and EN bits must not be activated at same time (changed using the same access).
The EN bit must be enabled individually at last. Otherwise, an NMI can be caused due to
relaxation time of the spike filter.
[bit0] FLAG : Non Maskable Interrupt Flag
The FLAG bit stores an asynchronous event of the NMI occurrence at the NMI pin.
A spike filter is used to filter out short pulses for spike suppression. The polarity of the
pulses depends on the definition in the LEV bit.
The FLAG bit is set by the hardware event (NMI occurrence) and can be cleared by software
to quit the interrupt. An interrupt is only caused, if both the EN and FLAG bits are set.
The FLAG bit can be read and cleared. Writing "1" to the FLAG bit is ignored. Read
operation of read modify write (RMW) instructions returns always "1" for the FLAG bit.
The FLAG bit is undefined after reset. Before enabling the NMI, the FLAG bit should be
cleared.
Figure 6.4-2 Operation of the NMI control/status register
level selectionand spike filter
16FX Bus EN
SynchronizationCLKB
Wakeup
SLEEP || STOP || TIMER
1
0
NMI to CPU
lock function
NMI pin
EN
[9]
[10]
[8]
NMI:LEV
NMI:EN
NMI:FLAGASET
SCLR
ASET: asynchronous setSCLR: synchronous clear
F2MC-16FX Family
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CHAPTER 6 INTERRUPTS6.5 Interrupt Flow
6.5 Interrupt Flow
Figure 6.5-2 shows the interrupt flow.
■ Interrupt FlowThe interrupt processing flow is entered at occurrence of hardware interrupts, software
interrupts or exceptions. For a detailed interrupt flow chart see Figure 6.5-2 .
The CPU special registers are saved on the stack before the interrupt is processed (see Figure
6.5-1 ).
Figure 6.5-1 Register saving during interrupt processing
At the end of the interrupt processing, the context of the CPU registers is restored while
executing the RETI instruction. The CPU returns to normal program execution.
PC
PS
DPR
DTB
ADB
PCB
AL
AH
H
SSP
SSP (value before interrupt)
SSP (value after interrupt)
Word (16 bits)MSB LSB
L
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CHAPTER 6 INTERRUPTS6.5 Interrupt Flow
Figure 6.5-2 Interrupt flow
Fetching and decodingthe next instruction
INT instruction
Executing an ordinaryinstruction
Completion ofstring instruction
repetition
Updating PC
Saving PS, PC, PCB, DTB,ADB, DPR and A into thesystem stack (SSP) and
setting I = 0
S = 1Fetching the interrupt vector
I/O service byDMA processing
Saving PS, PC, PCB, DTB,ADB, DPR and A into thesystem stack (SSP) and
setting ILM = IL
IF & IE = 1and DER = 1 and
DISEL = IRQ#
STARTI, ILM: Interrupt flag and interrupt level mask in the program status (PS)
Internal resource interrupt request flag and enableIF, IE:DER: DMA enable register of the related DMA channel
Level configuration of the IRQ channel by ICR/ILRIL:S: System stack flag in the CCR/PSDISEL: DMA intserrupt select register
YES
YES
NO
YES
NO
NO
YES
NO
IF & IE = 1
I=1 & IL<ILMand
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CHAPTER 6 INTERRUPTS6.6 Hardware Interrupts
6.6 Hardware Interrupts
In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user.
■ Hardware InterruptsA hardware interrupt occurs when the relevant conditions are satisfied as a result of two
operations:
• Comparison between the interrupt request level (IL) and the value in the interrupt levelmask (ILM) of program status (PS), and
• Hardware reference to the I flag value of PS.
The CPU performs the following processing when a hardware interrupt occurs:
• Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPUto the system stack.
• The stack flag (S) is set.
• Sets ILM in the PS register. The currently requested interrupt level (IL) is automatically set.
• Fetches the corresponding interrupt vector and branches to the processing indicated by thatvalue.
If the device is in standby mode, a hardware interrupt with IL<7 generates a wake-up event to
the clock and mode control unit.
■ Structure of the Hardware Interrupt SystemThe interrupt status is indicated by internal resources, the ICR for the interrupt controller, and
the PS value of the CPU. To use a hardware interrupt, make the following set-up:
• Interrupt vector (in memory)
- Consider the TBR value for a non-default location of the vector table.
- The start address of the interrupt service routine has to be written to the appropriate
interrupt vector (VecAddr = 4 × (255-INT#) + 256 × TBR).
• Peripheral resource
- Use the Interrupt enable and request bits to control interrupt requests from peripheral
resources.
• Interrupt controller
- Assign interrupt levels (ICR:IL) for each interrupt, which can occur.
- If interrupts occur simultaneously, a higher priority is defined by lower interrupt levels.
IL=7 disables the interrupt.
- If multiple requests are at the same level, the interrupt controller selects the request with
the lowest interrupt number. In the case of same levels configured, the delayed interrupt
has the lowest priority, independent from its interrupt number.
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CHAPTER 6 INTERRUPTS6.6 Hardware Interrupts
- There is a fixed relationship between the interrupt requests and the ILs. A level can be
defined by IL[n] for each hardware interrupt request IRQ[n] (for n >= 12).
• CPU
- ILM and I in the PS register are used to compare the requested interrupt level (IL) with
the current interrupt level mask (ILM) and to identify the interrupt enable status (I). For
acceptance of hardware interrupts, the I flag has to be set and ILM has to be larger than
IL.
- During interrupt processing, the CPU saves 12 bytes to the memory area indicated by
SSB and SSP. Thus the system stack pointer has to be initialized before using interrupts.
- The CPU fetches three bytes of the interrupt vector and loads them onto PC and PCB.
The interrupt handler routine has to start at this location. As a result, the interrupt
processing program defined by the user is executed next. Normal operation is resumed at
execution of the RETI instruction.
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CHAPTER 6 INTERRUPTS6.6 Hardware Interrupts
■ Hardware Interrupt OperationInterrupt requests (IRQs) from peripheral resources are fed through the DMA controller before
connecting to the interrupt controller. The DMA controller decides depending on it’s channel
configuration (DMA interrupt request select register DISEL and DMA enable DER:ENx bit), if
the IRQ is handled by DMA transfer or passed to the interrupt controller. DMA transfers are
accepted regardless of the status of the I flag and the interrupt level. The DMA controller has a
fixed priority scheme, channel 0 has highest priority and channel 15 has lowest priority.
Figure 6.6-1 shows the processing flow from the occurrence of a hardware interrupt to the
release of the interrupt request in an interrupt processing program.
Figure 6.6-1 Occurrence and release of hardware interrupt
(1) An interrupt cause occurs in a peripheral.
(2) The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, theperipheral issues an interrupt request (IRQ).
(3) The DMA controller checks, if the IRQ should be handled by DMA. It evaluates for eachchannel, if the interrupt number of the asserted IRQ is selected and if DMA is enabled.
- If the evaluation is true, the transfer is handled by DMA (3a). If the evaluation is false,
interrupt processing is done by the interrupt controller, proceeding with step (4).
- At the end of the DMA transfer, the interrupt bit is cleared in the peripheral (3b).
- If the final transfer count is reached, the DMA completion interrupt is processed by the
interrupt controller.
(4) The interrupt controller receives the interrupt request.
(5) The interrupt controller determines the priority levels of simultaneously requestedinterrupts.
(6) The interrupt controller transfers the highest priority interrupt level and the correspondinginterrupt number to the CPU.
(7) The interrupt level requested by the interrupt controller is compared with the ILM value ofthe processor status register.
(8) If the comparison shows that the requested level is higher than the current interruptprocessing level (IL<ILM), the I flag value of the same processor status register ischecked.
Enable FF (IE)
Source FF (I)
Peripheral
(1)
Execution Pipeline
Register File
F2 M
C-1
6FX
Bus
rator
InterruptLevelsIL
InterruptController
INT LevelINT Number
PS I
IRQ
(2)
Peripherals with IRQ
control of data transfer (3a) and IRQ clear (3b)
(4)Compa?Level
ControllerDMA(3) (5)
(6)
Comparator(7)
Check(8)
F2MC-16FX CPU
S ILM
(9a)
(9b)(9c)
(10)
(12)
Int (9)
StackOp.
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CHAPTER 6 INTERRUPTS6.6 Hardware Interrupts
(9) If the check in step 5 shows, that the I flag indicates interrupt enable status, interruptprocessing is performed as soon as the currently executing instruction is completed.
- To save the CPU status, special CPU registers are transferred to the system stack (9a).
- The S bit is set to "1" (9b).
- The requested level is written to the ILM bits (9c).
- The interrupt vector is fetched.
- Then control is transferred to the interrupt processing routine (branch to the address read
as interrupt vector).
(10) When the interrupt cause of step (1) is cleared by software in the user interrupt processingroutine, the interrupt request is completed.
(11) The RETI instruction is used to return from the interrupt processing routine as its lastinstruction.
(12) The CPU status is restored from system stack and normal program execution is resumed.
■ Hardware Interrupt Processing TimeThe time required for the CPU to execute the interrupt processing (stack operation, interrupt
vector fetch, branch to the interrupt vector) is shown below. The value is valid if stack
operation and interrupt vector fetch are executed without any wait cycles.
• Interrupt start: 10 cycles + c
• Interrupt return: 9 cycles + c (RETI instruction)
In addition wait cycles for bus transfers have to be added, if any (e.g. access to vector table in
slower ROM memory or external area).
Table 6.6-1 Compensation values (c) for interrupt processing cycle count
Address indicated by the stack pointer Compensation value
Internal area, even-numbered address 0
Internal area, odd-numbered address +2
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CHAPTER 6 INTERRUPTS6.7 Software Interrupts
6.7 Software Interrupts
In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. This is called the software interrupt function. A software interrupt occurs always when the software interrupt instruction is executed.
■ Software InterruptsA software interrupt request issued by the INT instruction has no interrupt request or enable
flag. A software interrupt request is always issued and accepted by executing the INT
instruction.
The INT instruction does not have an interrupt level. Therefore, the INT instruction does not
update the interrupt level mask (ILM). The INT instruction clears the interrupt enable flag (I)
to suspend subsequent hardware interrupt requests.
The CPU performs the following processing when a software interrupt occurs:
• Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPUto the system stack.
• The S flag is set.
• Clears I flag in the PS register. Hardware interrupts are automatically disabled.
• Fetches the corresponding interrupt vector and branches to the processing indicated by thatvalue.
■ Structure of the Software Interrupt SystemSoftware interrupts are fully handled within the CPU. To use a software interrupt, make the
following set-up:
• Interrupt vector (in memory)
- Consider the TBR value for a non-default location of the vector table.
- The start address of the interrupt service routine has to be written to the appropriate
interrupt vector (VecAddr = 4 × (255-INT#) + 256 × TBR).
• CPU
- During interrupt processing, the CPU saves 12 bytes to the memory area indicated by
SSB and SSP. Thus the system stack pointer has to be initialized before using interrupts.
- The CPU fetches three bytes of the interrupt vector and loads them onto PC and PCB.
The interrupt handler routine has to start at this location. As a result, the interrupt
processing program defined by the user is executed next. Normal operation is resumed at
execution of the RETI instruction.
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CHAPTER 6 INTERRUPTS6.7 Software Interrupts
■ Software Interrupt Operation
When the CPU fetches and executes the software interrupt instruction, the software interrupt
processing sequence is activated. The software interrupt processing sequence saves 12 bytes
(PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The
sequence then fetches three bytes of interrupt vector and loads them into the program counter
(PC) and program counter bank register (PCB), clears the interrupt enable flag (I), and sets the
stack flag (S) flag. Then, the sequence performs branch processing. As a result, the interrupt
processing program defined by the user application program is executed next.
Figure 6.7-1 illustrates the flow from the occurrence of a software interrupt until the return
from the interrupt processing program.
Figure 6.7-1 Occurrence and release of software interrupt
(1)The software interrupt instruction is executed.
(2) Interrupt processing is performed by the CPU according to the software interruptinstruction.
- To save the CPU status, special CPU registers are transferred to the system stack (2a).
- The S flag is set to "1" (2b).
- The I flag is cleared to disable hardware interrupts (2c).
- The interrupt vector is fetched.
- Then control is transferred to the interrupt processing routine (branch to the address read
as interrupt vector).
(3)The Interrupt service routine is processed by the CPU.
(4)The interrupt processing is completed with the RETI instruction in the user interruptprocessing routine.
(5)The CPU restores its context of special registers from system stack.
(6)The CPU proceeds program execution with the next instruction after the INT instruction.
StackOp.
PS ILMI
Execution Pipeline
Register File
F2MC-16FX CPUQueue
F2 M
C-1
6FX
Bus
(5)Instruction
Instruction (1)INT
Instruction (4)RETI
Routine (3)Interrupt ServiceProcessing of the
S
INT (1)(2a)
clear (2c)
(2b)
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CHAPTER 6 INTERRUPTS6.8 Multiple interrupts
6.8 Multiple interrupts
The F2MC-16FX CPU supports multiple interrupts (simultaneous occurring interrupts and nested interrupt processing).
■ Multiple Hardware InterruptsIf an hardware interrupt of a higher priority (lower level value) occurs while another interrupt
is being processed, control is transferred to the higher priority interrupt after the currently
executing instruction is completed. After processing of the higher priority interrupt is
completed, the original interrupt processing is resumed.
An interrupt of the same or lower priority may be generated while another interrupt is being
processed. If this happens, the new interrupt request is suspended until the current interrupt
processing is completed, unless the interrupt level mask (ILM) value or interrupt enable flag (I)
is changed by an instruction.
A DMA transfer cannot be interrupted and activated from multiple sources. While a DMA
transfer is being processed, all other DMA requests are suspended. At simultaneous occurrence
of requests for the DMA controller, the lowest channel number is processed first.
For a detailed description of DMA, refer to the hardware manual for each device.
■ Multiple Software InterruptsSoftware interrupts can not occur simultaneously. They are entered by executing the INT
instruction and are always accepted. However, if an INT instruction is placed within an
interrupt service routine, nested execution of software interrupts is possible.
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CHAPTER 6 INTERRUPTS6.8 Multiple interrupts
■ Interrupt Acceptance Priority
Following table lists all interrupts with conditions for their acceptance.
IL and ILM: Interrupt level and Interrupt level mask
I: Interrupt enable flag (in CCR of PS)
S: Stack flag (in CCR of PS)
P: Privileged mode flag (in CCR of PS)
Table 6.8-1 Control of interrupt acceptance priority
Event INT# Type Level Acceptance condition Action, if accepted
-Instruction Break (VEIB)system reserved
P2Current instruction execution is finished,ILM>2 || P == 1
Save CPU status to system stack
S = 1
Branch to interrupt vector
P = 0ILM = 2
-Tool Break (VENMI)system reserved
P2
Current instruction execution is finished, string instruction is interrupted,ILM>2 || P == 1
P = 0ILM = 2
11 NMI P4
Current instruction execution is finished, string instruction is interrupted,ILM>4 || P == 1
P = 0ILM = 4
9Address match detection (HW-INT9)
P6
Current instruction execution is finished, string instruction is interrupted,ILM>6 || P == 1
P = 0ILM = 6
from 13 on
Peripheral IRQIL
U0...U7
Current instruction execution is finished, string instruction is interrupted,ILM > ILP == 1I == 1For multiple requests with same IL, smallest IRQ number is accepted.
ILM = IL
12 Delayed INTIL
U0...U7
Current instruction execution is finished, string instruction is interrupted,ILM > ILP == 1I == 1No peripheral IRQs pending with same IL.
ILM = IL
-Software Instruction Break (INTE)system reserved
P2
always accepted
P = 0ILM = 2I = 0
9 INT9 - I = 0
10Undefined instruction exception
- I = 0
all INT instruction - I = 0
- RETI instruction -restore CPU status (including P, I, S, ILM)
Har
dwar
e ev
ent
Soft
war
e ev
ent (
Inst
ruct
ion)
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CHAPTER 6 INTERRUPTS6.8 Multiple interrupts
Following table defines the naming of the interrupt levels, its corresponding P flag and ILM
values. It also lists the interrupt cause, which can request the interrupt level.
Table 6.8-2 Interrupt levels
Name Category P flag ILM value Priority Remarks
P0 Privileged mode 0 0 Highest -
P1 0 1 -
P2 0 2 DSU
P3 0 3 -
P4 0 4 NMI
P5 0 5 -
P6 0 6 HW-INT9
P7 0 7 -
U0 User mode 1 0 Peripherals
U1 1 1
U2 1 2
U3 1 3
U4 1 4
U5 1 5
U6 1 6
U7 1 7 Lowest no request
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CHAPTER 6 INTERRUPTS6.9 Exceptions
6.9 Exceptions
The F2MC-16FX performs exception processing at occurrence of various software and hardware events.
■ Software Exceptions (Op-Code)Software exceptions are always accepted. Same as software interrupts, software exceptions
disable any hardware interrupt acceptance. The software exceptions occur at code execution of
following specific op-codes:
● Execution of an undefined instruction
All codes that are not defined in the instruction map are handled as undefined instructions.
When an undefined instruction is executed, processing similar to the INT #10 software
interrupt instruction is performed. Specifically, the program counter (PC) value saved in the
stack is the address at which the undefined instruction is stored. Processing can be restored by
the RETI instruction, however it is of no use, because the same exception occurs again.
Operation:
SSP ← SSP-2, (SSP) ← AH
SSP ← SSP-2, (SSP) ← AL
SSP ← SSP-2, (SSP) ← DPR:ADB
SSP ← SSP-2, (SSP) ← DTB:PCB
SSP ← SSP-2, (SSP) ← PC
SSP ← SSP-2, (SSP) ← PS
S ← 1, I ← 0
PCB ← Vector #10 address (upper byte)
PC ← Vector #10 address (lower word)
● INT9
This instruction branches to the interrupt processing routine indicated by vector #9. Executing
the RETI instruction in the interrupt routine restores the processing subsequent to the INT9
instruction.
Operation:
SSP ← SSP-2, (SSP) ← AH
SSP ← SSP-2, (SSP) ← AL
SSP ← SSP-2, (SSP) ← DPR:ADB
SSP ← SSP-2, (SSP) ← DTB:PCB
SSP ← SSP-2, (SSP) ← PC+1
SSP ← SSP-2, (SSP) ← PS
S ← 1, I ← 0
PCB ← Vector #9 address (upper byte)
PC ← Vector #9 address (lower word)
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CHAPTER 6 INTERRUPTS6.9 Exceptions
● INTE (System reserved, only available with DSU)
INTE is used to insert a software break point for the debug system, using the in circuit
emulator (ICE). At insertion of a software instruction break, the first byte of the original
instruction is replaced by INTE.
This instruction branches to the interrupt processing routine indicated by a fixed vector defined
by the DSU. The PC value saved in the stack is the address at which INTE is stored. Executing
the RETI instruction in the interrupt routine restores the processing at this location (INTE can
be replaced by the original instruction at removal of the software break point).
The privileged mode flag (P) is cleared and the ILM register is set to 2 (enters level P2). This
disables all hardware interrupts and exceptions. The P flag and ILM are restored at execution
of the RETI instruction.
Operation:
SSP ← SSP-2, (SSP) ← AH
SSP ← SSP-2, (SSP) ← AL
SSP ← SSP-2, (SSP) ← DPR:ADB
SSP ← SSP-2, (SSP) ← DTB:PCB
SSP ← SSP-2, (SSP) ← PC
SSP ← SSP-2, (SSP) ← PS
S ← 1, I ← 0, P ← 0, ILM ← 2
PCB ← Fixed vector from DSU (upper byte, 00H, address is ignored by DSU)
PC ← Fixed vector from DSU (lower word, 0400H, address is ignored by DSU)
Without the DSU, INTE is handled same as the undefined instruction exception. Interrupt
vector #10 is referenced. The P flag is not cleared and ILM is not updated.
■ Hardware Exceptions (Non Maskable Interrupts)Hardware exceptions are external events, which are not maskable by any software instruction.
Hardware exceptions with a higher level number, than the actual processed one, are suspended
until execution of the RETI instruction restores the previous level. In addition, hardware
exceptions disable any hardware interrupt acceptance.
At occurrence of multiple hardware exceptions at the same time, they will be accepted with
following priority: VEIB > VENMI > NMI > HW-INT9. If the current interrupt level mask and
P flag setting allows it, hardware exceptions are accepted at the end of each instruction
execution and during execution of string instructions.
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CHAPTER 6 INTERRUPTS6.9 Exceptions
● HW-INT9
HW-INT9 is used by the address match detection function. With that function embedded debug
support (operand address break or data value break) or a simple memory protection can be
provided.
The privileged mode flag (P) is cleared and interrupt level mask (ILM) is set to 6 (enters level
P6). This disables all hardware interrupts from peripherals. The P flag and ILM are restored at
the execution of the RETI instruction.
Operation:
SSP ← SSP-2, (SSP) ← AH
SSP ← SSP-2, (SSP) ← AL
SSP ← SSP-2, (SSP) ← DPR:ADB
SSP ← SSP-2, (SSP) ← DTB:PCB
SSP ← SSP-2, (SSP) ← PC
SSP ← SSP-2, (SSP) ← PS
S ← 1, P ← 0, ILM ← 6
PCB ← Vector #9 address (upper byte)
PC ← Vector #9 address (lower word)
● NMI
The non maskable interrupt (NMI) provides external hardware exception handling.
The privileged mode flag (P) is cleared and interrupt level mask (ILM) is set to 4 (enters level
P4). This disables all hardware interrupts from peripherals and the HW-INT9. The P flag and
ILM are restored at execution of the RETI instruction.
Operation:
SSP ← SSP-2, (SSP) ← AH
SSP ← SSP-2, (SSP) ← AL
SSP ← SSP-2, (SSP) ← DPR:ADB
SSP ← SSP-2, (SSP) ← DTB:PCB
SSP ← SSP-2, (SSP) ← PC
SSP ← SSP-2, (SSP) ← PS
S ← 1, P ← 0, ILM ← 4
PCB ← Vector #11 address (upper byte)
PC ← Vector #11 address (lower word)
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CHAPTER 6 INTERRUPTS6.9 Exceptions
● Tool break (VENMI, system reserved, only available with DSU)
VENMI is provided for debugging with DSU. It implements various break factors.
The privileged mode flag (P) is cleared and interrupt level mask (ILM) is set to 2 (enters level
P2). This disables all hardware interrupts and exceptions. The P flag and ILM are restored at
execution of the RETI instruction.
Operation:
SSP ← SSP-2, (SSP) ← AH
SSP ← SSP-2, (SSP) ← AL
SSP ← SSP-2, (SSP) ← DPR:ADB
SSP ← SSP-2, (SSP) ← DTB:PCB
SSP ← SSP-2, (SSP) ← PC
SSP ← SSP-2, (SSP) ← PS
S ← 1, P ← 0, ILM ← 2
PCB ← Fixed vector from DSU (upper byte, 00H, address is ignored by DSU)
PC ← Fixed vector from DSU (lower word, 0400H, address is ignored by DSU)
● Instruction break (VEIB, system reserved, only available with DSU)
VEIB is provided for debugging with DSU. It implements the instruction break after
instruction execution. Opposed to other hardware exceptions, VEIB is not accepted during
execution of a string instruction.
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CHAPTER 6 INTERRUPTS6.9 Exceptions
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CHAPTER 7ADDRESSING
This chapter describes addressing for the
F2MC-16FX instructions.Addressing specifies the data to be used and an address.
In F2MC-16FX, effective addressing or an used instruction code determines the address format (absolute address or relative address). When the address format is determined by the instruction code itself, an address must be specified in compliance with the used instruction code.Some instructions enable several types of addressing to be specified.
7.1 Effective Address Field
7.2 Direct Addressing
7.3 Indirect Addressing
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CHAPTER 7 ADDRESSING7.1 Effective Address Field
7.1 Effective Address Field
Table 7.1-1 lists the address formats that may be specified in the effective address field.
■ Effective Address FieldTable 7.1-1 Effective Address Field
Code Coding Address format Default bank
00H
01H
02H
03H
04H
05H
06H
07H
R0R1R2R3R4R5R6R7
RW0RW1RW2RW3RW4RW5RW6RW7
RL0(RL0)RL1
(RL1)RL2
(RL2)RL3
(RL3)
Register direct
Note: The general purpose register name on the left notation corresponds to the byte, word and long-word types.
None
08H
09H
0AH
0BH
@RW0@RW1@RW2@RW3
Register indirect
DTBDTBADBSPB
0CH
0DH
0EH
0FH
@RW0 +@RW1 +@RW2 +@RW3 +
Register indirect with post-increment
DTBDTBADBSPB
10H
11H
12H
13H
@RW0 + disp8@RW1 + disp8@RW2 + disp8@RW3 + disp8
Register indirect with 8-bit displacement
DTBDTBADBSPB
14H
15H
16H
17H
@RW4 + disp8@RW5 + disp8@RW6 + disp8@RW7 + disp8
DTBDTBADBSPB
18H
19H
1AH
1BH
@RW0 + disp16@RW1 + disp16@RW2 + disp16@RW3 + disp16
Register indirect with 16-bit displacement
DTBDTBADBSPB
1CH
1DH
1EH
1FH
@RW0 + RW7@RW1 + RW7@PC + disp16addr16
Register indirect with indexRegister indirect with indexPC indirect with 16-bit displacementDirect address
DTBDTBPCBDTB
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CHAPTER 7 ADDRESSING7.2 Direct Addressing
7.2 Direct Addressing
In direct addressing, a value, register, and address must be directly specified for the operands.
■ Direct Addressing
● Immediate data (#imm)
Directly specify an operand value. There are four types of immediate data according to data
length as below:
• #imm4
• #imm8
• #imm16
• #imm32
● Register direct
Directly specify a register for the operand. Registers that can be specified are as below:
• General-purpose registers (Byte): R0, R1, R2, R3, R4, R5, R6, R7
(Word): RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
(Long word):RL0, RL1, RL2, RL3
• Dedicated registers (Accumulator): A, AL
(Pointer): SP *
(Bank): PCB, DTB, USB, SSB, ADB
(Page): DPR
(Control): PS, CCR, RP, ILM
*: For SP, either user stack pointer (USP) or system stack pointer (SSP) is selected for use,
according to the value of the S flag in the condition code register (CCR). For branch
instructions, program counter (PC) is not described in the operand of the instruction, but
it is automatically specified.
● Direct branch address (addr16)
Directly specify an address to which the execution will branch by means of displacement. The
address length with displacement is 16 bits and the address indicates the destination of the
branch in the logical space. This addressing is applied to an unconditional branch instruction
and a subroutine call instruction. Bits 16 to 23 of the address are given by the program counter
bank register (PCB).
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CHAPTER 7 ADDRESSING7.2 Direct Addressing
● Physical direct branch address (addr24)
Directly specify a physical address to which the execution will branch by means of
displacement. The data length with displacement is 24 bits. This addressing is applied to an
unconditional branch instruction, a subroutine call instruction, and a software interrupt
instruction.
● I/O direct (io)
Directly specify a memory address in the operand by means of 8-bit displacement.
Independently of the respective values for data bank register (DTB) and direct page register
(DPR), the I/O space with physical addresses 000000H to 0000FFH is accessible. It is invalid
to describe the bank select prefix to specify a bank before an instruction using this addressing.
● Abbreviated direct address (dir)
Specify lower eight bits of a memory address in the operand. Bits 8 to 15 of the address are
given by the direct page register (DPR). Bits 16 to 23 of the address are given by the data bank
register (DTB).
● Direct address (addr16)
Specify lower 16 bits of a memory address in the operand. Bits 16 to 23 of the address are
given by the data bank register (DTB).
● I/O direct bit address (io:bp)
Directly specify a bit within the range of physical addresses 000000H to 0000FFH. Bit position
is represented by :bp. The higher number is the most significant bit and the lower number is
the least significant bit.
● Abbreviated direct bit address (dir:bp)
Directly specify lower eight bits of a memory address in the operand. Bits 8 to 15 of the
address are given by the direct page register (DPR). Bits 16 to 23 of the address are given by
the data bank register (DTB). Bit position is represented by :bp. The higher number is the
most significant bit and the lower number is the least significant bit.
● Direct bit address (addr16:bp)
Directly specify an arbitrary bit within 64 Kbytes. Bits 16 to 23 of the address are given by the
data bank register (DTB). Bit position is represented by :bp. The higher number is the most
significant bit and the lower number is the least significant bit.
● Vector address (#vct)
The address to which the execution will branch is determined by the content of the vector that
is specified herein. The vector number data length may be either four bits or eight bits. This
addressing is applied to a subroutine call instruction and a software interrupt instruction.
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CHAPTER 7 ADDRESSING7.3 Indirect Addressing
7.3 Indirect Addressing
In indirect addressing, the data indicated by the operand you coded indirectly gives an address.
■ Indirect Addressing
● Register indirect (@RWj j = 0 to 3)
The register indirect addressing is used to access a memory location whose address is specified
by the content of general-purpose register RWj. Bits 16 to 23 of the address are given by the
data bank register (DTB) if RW0 and RW1 are used, by the SPB if RW3 is used, and by the
additional data bank register (ADB) if RW2 is used.
● Register indirect with post-increment (@RWj+ j = 0 to 3)
This addressing is also used to access a memory location whose address is specified by the
content of general-purpose register RWj. After the execution of the operand operation, RWj is
incremented by the operand data length (1 for byte, 2 for word, and 4 for long word). Bits 16
to 23 of the address are given by the data bank register (DTB) if RW0 and RW1 are used, by
the SPB if RW3 is used, and by the additional data bank register (ADB) if RW2 is used.
If the value resulting from post-increment indicates the address of the increment-specified
register itself, the value of this register is incremented when referred subsequently. Then, if a
data write instruction is issued to the register, the priority is given to the data write instruction,
so that the register value, which would otherwise be incremented, becomes the written data.
● Register indirect with displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j = 0 to 3)
This addressing is used to access a memory location whose address is specified by the
displacement added to the content of general-purpose register RWj. Displacement may be
either byte or word and is added as a signed value. Bits 16 to 23 of the address are given by
the data bank register (DTB) if RW0, RW1, RW4, and RW5 are used. Bits 16 to 23 are given
by the SPB if RW3 and RW7 and by the additional data bank register (ADB) if RW2 and RW6
are used.
● Long register indirect with displacement (@RLi+disp8 i = 0 to 3)
This addressing is used to access a memory location whose address is specified by the lower 24
bits that result from the displacement added to the content of general-purpose register RLi.
Displacement is eight bits and added as a signed value.
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CHAPTER 7 ADDRESSING7.3 Indirect Addressing
● Program counter indirect with displacement (@PC+disp16)
This addressing is used to access a memory location whose address is specified by (address of
instruction + 4 + disp16). Displacement is a word length. Bits 16 to 23 of the address are
given by the program counter bank register (PCB).
Note that respective operand addresses of the instructions listed next are not regarded as being
(next instruction address + disp16):
• DBNZ eam, rel
• DWBNQ eam, rel
• CBNE eam, #imm8, rel
• CWBNE eam, #imml16, rel
• MOV eam, #imm8
• MOVM eam, #imm16
● Register indirect with base index (@RW0+RW7, @RW1+RW7)
This addressing is used to access a memory location whose address is specified by a value
obtained by adding the content of RW0 or RW1 to the content of general-purpose register
RW7. Bits 16 to 23 of the address are given by the data bank register (DTB).
● Program counter relative branch address (rel)
The address to which the execution will branch is determined by a value obtained by adding
the 8-bit displacement to the value of the program counter (PC). If the result of the addition
exceeds 16 bits, the bank register is not incremented or decremented and the part of excess is
ignored. Consequently, the address falls within the closed bank of 64 Kbytes. This addressing
is applied to an unconditional or conditional branch instruction. Bits 16 to 23 of the address
are given by the program counter bank register (PCB).
● Register List (rlst)
This addressing specifies a register subjected to push/pop for the stack (see Figure 7.3-1 ).
Figure 7.3-1 Configuration of Register List
● Accumulator indirect (@A)
This addressing is used to access a memory location whose address is specified by the content
of the lower words of the accumulator (AL). Bits 16 to 23 of the address are given by the data
bank register (DTB).
MSB LSB
When the bit is "1", the associated register is selected. When the bit is "0", the associated register is not selected.
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
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CHAPTER 7 ADDRESSING7.3 Indirect Addressing
● Accumulator indirect branch address (@A)
The address to which the execution will branch is determined by the content for the lower
words of the accumulator (AL). This address indicates the destination of the branch within the
bank space. Bits 16 to 23 of the address are given by the program bank register (PCB). In the
case of the jump context (JCTX) instruction, however, bits 16 to 23 of the address are given by
the data bank register (DTB). This addressing is applied to an unconditional branch instruction.
● Indirectly specified branch address (@ear)
The word data with the address specified by ear corresponds to the address to which the
execution will branch.
● Indirectly specified branch address (@eam)
The word data with the address specified by eam corresponds to the address to which the
execution will branch.
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CHAPTER 7 ADDRESSING7.3 Indirect Addressing
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CHAPTER 8DETAILED
INSTRUCTIONS
This chapter describes each execution instruction used in the assembler in a reference format. The execution instructions are presented in alphabetical order.
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CHAPTER 8 DETAILED INSTRUCTIONS8.1 Instruction Overview
8.1 Instruction Overview
In "CHAPTER 8 DETAILED INSTRUCTIONS", the following items are described for each instruction.
■ Instruction Overview
● Assembler format
The format for coding each instruction into an assembler source program is presented.
• Upper case letters and symbols: Write them as they are into a source program.
• Lower case letters: Rewrite them into a source program.
• Number after a lower case letter: Indicates a bit width in the instruction.
● Operation
The operation for registers and data by instruction execution is presented.
● CCR
The status of each flag (I, S, T, N, Z, V and C) of the condition code register (CCR) is
presented.
• *: Denotes that the flag changes with the instruction execution.
• –: Denotes that the flag does not change.
• S: Denotes that the flag is set with the instruction execution.
• R: Denotes that the flag is clear with the instruction execution.
● Byte count, cycle count
The byte count of an instruction, the cycle count at instruction execution time, and the cycle
count for correcting odd addresses are shown.
● Example
An example of each instruction is presented.
All numeric values of the data given in any example are hexadecimal numbers. Any numeric
value of the data given in the operand represents a hexadecimal number with suffix (H).
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CHAPTER 8 DETAILED INSTRUCTIONS8.1 Instruction Overview
■ Symbols (Abbreviations) Used in Detailed InstructionsTable 8.1-1 lists the symbols used in the detailed instructions.
Table 8.1-1 Symbols (abbreviations) Used in Detailed Instructions (1 / 2)
Coding Meaning
A
32-bit accumulatorThe length of used bits varies depending on the instruction. Byte: Lower 8 bits of AL Word: 16 bits of AL Long word: 32 bits of AL and AH
AHAL
Upper 16 bits of ALower 16 bits of A
SP Stack pointer (USP or SSP)
PC Program counter
PCB Program bank register
DTB Data bank register
ADB Additional data bank register
SSB System stack bank register
USB User stack bank register
DPR Direct page register
brg1 DTB, ADB, SSB, USB, DPR, PCB
brg2 DTB, ADB, SSB, USB, DPR
brg3 DTB, ADB, PCB, SPB
Ri R0, R1, R2, R3, R4, R5, R6, R7
Rj R0, R1, R2, R3
RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj RW0, RW1, RW2, RW3
RLi RL0, RL1, RL2, RL3
dir Abbreviated direct addressing
addr16addr24
ad24 0-15ad24 16-23
Direct addressingPhysical direct addressingBits 0 to 15 of addr24Bits 16 to 23 of addr24
io I/O area (000000H to 0000FFH)
imm4imm8
imm16imm32
ext (imm8)
4-bit immediate data8-bit immediate data16-bit immediate data32-bit immediate data16-bit data resulting from the signed extension of 8-bit immediate data
disp8disp16
8-bit displacement16-bit displacement
bp Bit offset value
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CHAPTER 8 DETAILED INSTRUCTIONS8.1 Instruction Overview
■ Execution CyclesThe cycle count required for the execution of an instruction is obtained by adding up the "cycle
count" specific to each instruction, a value of "odd addresses correction", which is determined
according to the condition.
At the actual instruction execution time, the execution cycles may become larger than the
calculated value due to the instruction fetch delay, the data access conflict, etc. Especially,
when performing instruction fetch and data access from an external bus by using the external
bus interface, the execution cycles becomes larger than the calculated value.
■ Odd Address CorrectionFor some instructions, the execution cycles increases when performing data access to odd
addresses. The execution cycles that increases at data access time to odd addresses is shown
under the title of "odd address correction" in item B in the instruction list.
vct4vct8
Vector number (0 to 15)Vector number (0 to 255)
( )b Bit address
re1 Specifies a PC relative branch.
eaream
Effective addressing (codes 00H to 07H)Effective addressing (codes 08H to 1FH)
r1st Register list
Table 8.1-1 Symbols (abbreviations) Used in Detailed Instructions (2 / 2)
Coding Meaning
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CHAPTER 8 DETAILED INSTRUCTIONS8.2 ADD (Add Byte Data of Destination and Source to
Destination)
8.2 ADD (Add Byte Data of Destination and Source to Destination)
Add the byte data specified by the second operand to the byte data specified by the first operand and store the result in the first operand.
If the first operand is the accumulator (A), 00H are transferred to upper byte of AL.
● Assembler format:
ADD A,#imm8 ADD A,dir
ADD A,ear ADD A,eam
ADD ear,A ADD eam,A
● Operation:
(First operand) ← (First operand)+(Second operand) [Byte addition]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – * * * *
First operand A A A A ear eam
Second operand #imm8 dir ear eam A A
Byte count 2 2 2 2+ 2 2+
Cycle count 1 2 1 2 1 3
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CHAPTER 8 DETAILED INSTRUCTIONS8.2 ADD (Add Byte Data of Destination and Source to Destination)
● Example:
ADD A,0E021H
In this example, the byte data (ABH) at address E021H is added to the low-order byte data
(46H) of AL.
× × × × A 0 4 6 A
Before execution
× × × × 0 0 F 1 A
After execution
Memory
A B E021
Memory
A B E021
CCR × × × × ×T N Z V C
CCR × 1 0 0 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.3 ADDC (Add Byte Data of AL and AH with Carry to AL)
8.3 ADDC (Add Byte Data of AL and AH with Carry to AL)
Add the low-order byte data of AL, low-order byte data of AH, and carry flag (C) together and restore the result in AL. 00H are transferred to the high-order byte
of AL.
● Assembler format:
ADDC A
● Operation:
(AL) ← (AH)+(AL)+(C) [Byte addition with a carry]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
ADDC A
In this example, the low-order byte data (D4H) of AL and the C flag ("0") are added to the low-
order byte data (05H) of AH.
I S T N Z V C
– – – * * * *
0 5 0 5 0 0 D 4 A
Before execution
0 5 0 5 0 0 D 9 A
After execution
CCR × × × × 0
T N Z V C
CCR × 1 0 0 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.4 ADDC (Add Byte Data of Accumulator and Effective Address with Carry to Accumulator)
8.4 ADDC (Add Byte Data of Accumulator and Effective Address with Carry to Accumulator)
Add the byte data and the carry flag (C) to the lowest-order byte data, and store the result to the lowest-order byte of the accumulator (A). 00H are transferred to
upper byte of AL.
● Assembler format:
ADDC A, ear
ADDC A, eam
● Operation:
(A) ← (A)+(second operand)+(C) [Byte addition with a carry]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – * * * *
First operand A A
Second operand ear eam
Byte count 2 2+
Cycle count 1 2
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CHAPTER 8 DETAILED INSTRUCTIONS8.4 ADDC (Add Byte Data of Accumulator and Effective Address
with Carry to Accumulator)● Example:
ADDC A, 0E035H
In this example, the word data (8952H) and C flag ("1") at the address (E024H) specified by
the second operand (@RW0+) are added to the word data (2068H) of AL.
× × × × A 0 4 6 A
Before execution
× × × × 0 0 2 C A
After execution
Memory
D 5 E035
Memory
D 5 E035
CCR × × × × 1
T N Z V C
CCR × 0 0 0 1
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.5 ADDCW (Add Word Data of Accumulator and Effective Address with Carry to Accumulator)
8.5 ADDCW (Add Word Data of Accumulator and Effective Address with Carry to Accumulator)
Add the low-order word data (AL) of the accumulator (A), word data specified by the second operand, and carry flag (C) together and restore the result in the low-order word of A.
● Assembler format:
ADDCW A, ear
ADDCW A, eam
● Operation:
(A) ← (A)+(second operand)+(C) [Word addition with a carry]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – * * * *
First operand A A
Second operand ear eam
Byte count 2 2+
Cycle count 1 2
Odd address correction 0 1
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CHAPTER 8 DETAILED INSTRUCTIONS8.5 ADDCW (Add Word Data of Accumulator and Effective
Address with Carry to Accumulator)● Example:
ADDCW A,@RW0+
In this example, the word data (8952H) at the address (E024H) specified by the second operand
(@RW0+) and the C flag ("1") are added to the word data (2068H) of AL.
× × × × 2 0 6 8 A
Before execution
× × × × A 9 B B A
After execution
Memory
8 9 E025
Memory
8 9 E025
E 0 2 4RW0 E 0 2 6RW0
5 2 E024 5 2 E024
CCR × × × × 1
T N Z V C
CCR × 1 0 0 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.6 ADDDC (Add Decimal Data of AL and AH with Carry to AL)
8.6 ADDDC (Add Decimal Data of AL and AH with Carry to AL)
Add the low-order byte data of AL, low-order byte data of AH, and carry flag (C) together in decimal and restore the result in the low-order byte of AL. 00H are
transferred to the high-order byte of AL.
● Assembler format:
ADDDC A
● Operation:
(AL) ← (AH)+(AL)+(C) [Decimal addition with a carry]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Undefined
C: Set when a carry has occurred as a result of the decimal operation, cleared otherwise.
● Byte count and cycle count:
Byte count: 1
Cycle count: 2
● Example:
ADDDC A
In this example, the low-order byte data (58H) and the flag C ("0") are added to the low-order
byte (62H) of AL in decimal operation.
I S T N Z V C
– – – * * * *
× × 6 2 × × 5 8 A
Before execution
× × 6 2 0 0 2 0 A
After execution
CCR × × × × 0
T N Z V C
CCR × 0 0 × 1
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.7 ADDL (Add Long Word Data of Destination and Source to
Destination)
8.7 ADDL (Add Long Word Data of Destination and Source to Destination)
Add the long word data specified by the second operand to the long word data specified by the first operand and restore the result in the first operand.
● Assembler format:
ADDL A,#imm32
ADDL A,ear ADDL A,eam
● Operation:
(First operand) ← (First operand)+(Second operand) [Long word addition]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – * * * *
First operand A A A
Second operand #imm32 ear eam
Byte count 5 2 2+
Cycle count 2 2 3
Odd address correction 0 0 1
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CHAPTER 8 DETAILED INSTRUCTIONS8.7 ADDL (Add Long Word Data of Destination and Source to Destination)
● Example:
ADDL A,0E077H
In this example, the long word data (357F41ABH) at address E077H is added to the long word
data (85B7A073H) of the accumulator (A).
Before execution After execution
Memory
3 5 E07A7 F E0794 1 E078A B E077
Memory
3 5 E07A7 F E0794 1 E078A B E077
8 5 B 7 A 0 7 3 A B B 3 6 E 2 1 E A
CCR × × × × ×T N Z V C
CCR × 1 0 0 0
T N Z V C
AH AL AH AL
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 93
CHAPTER 8 DETAILED INSTRUCTIONS8.8 ADDSP (Add Word Data of Stack Pointer and Immediate
Data to Stack Pointer)
8.8 ADDSP (Add Word Data of Stack Pointer and Immediate Data to Stack Pointer)
Add 16-bit immediate data or the value resulting from sign-extending 8-bit immediate data to the word data pointed to by SP (stack pointer) and restore the result in SP. If the addition result exceeds 16 bits, an underflow occurs.
CCR does not indicate whether an underflow has occurred.
● Assembler format:
(1) ADDSP #imm8
(2) ADDSP #imm16
● Operation:
(1) (SP) ← (SP)+Sign-extended imm8 [Word addition]
(2) (SP) ← (SP)+imm16 [Word addition]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
● Example:
ADDSP #89BAH
In this example, the 16-bit immediate data (89BAH) is added with a sign to SP. The addition
result exceeds 16 bits, causing an underflow.
I S T N Z V C
– – – – – – –
Operand #imm8 #imm16
Byte count 2 3
Cycle count 1 1
E 2 A 4
× 0 0 0 0CCR
SP
T N Z V C
Before execution
6 C 5 E
× 0 0 0 0CCR
SP
T N Z V CAfter execution
F2MC-16FX Family
94 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.9 ADDW (Add Word Data of AL and AH to AL)
8.9 ADDW (Add Word Data of AL and AH to AL)
Add the word data of AH and that of AL together and restore the result to AL.
● Assembler format:
ADDW A
● Operation:
(AL) ← (AH)+(AL) [Word addition]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
ADDW A
In this example, the word data (83A2H) of AH is added to the word data (7F23H) of AL. An
overflow occurs, causing the C flag to be set.
I S T N Z V C
– – – * * * *
8 3 A 2 7 F 2 3 A
Before execution
8 3 A 2 0 2 C 5 A
After execution
CCR × × × × ×T N Z V C
CCR × 0 0 0 1
T N Z V C
AH AL AH AL
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.10 ADDW (Add Word Data of Destination and Source to
Destination)
8.10 ADDW (Add Word Data of Destination and Source to Destination)
Add the word data specified by the second operand to the word data specified by the first operand and restore the result in the first operand.
● Assembler format:
ADDW A,#imm16
ADDW A,ear ADDW A,eam
ADDW ear,A ADDW eam,A
● Operation:
(First operand) ← (First operand)+(Second operand) [Word addition]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – * * * *
First operand A A A ear eam
Second operand #imm16 ear eam A A
Byte count 3 2 2+ 2 2+
Cycle count 1 1 2 1 3
Odd address correction 0 0 1 0 2
F2MC-16FX Family
96 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.10 ADDW (Add Word Data of Destination and Source to Destination)
● Example:
ADDW @RW0+1,A
In this example, the word data (CD04H) of AL is added to the word data (315DH) of the
address (E2A5H) specified by the first operand (@RW0+1).
Before execution After execution
Memory
3 1 E2A6
Memory
F E E2A6
E 2 A 4RW0 E 2 A 4RW0
5 D E2A5 6 1 E2A5X X E2A4 × × E2A4
× × × × C D 0 4 A × × × × C D 0 4 A
CCR × × × × ×T N Z V C
CCR × 1 0 0 0
T N Z V C
AH AL AH AL
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 97
CHAPTER 8 DETAILED INSTRUCTIONS8.11 AND (And Byte Data of Destination and Source to
Destination)
8.11 AND (And Byte Data of Destination and Source to Destination)
Take the logical AND operation of the byte data specified by the first operand and the byte data specified by the second operand and restore the result in the first operand.
● Assembler format:
AND A,#imm8
AND A,ear AND A,eam
AND ear,A AND eam,A
● Operation:
(First operand) ← (First operand) and (Second operand) [Byte logical AND]
The logical AND operation of the byte data specified by the first operand and the byte data
specified by the second operand is taken on a bit-by-bit basis and the result is restored in the
first operand.
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * R –
First operand A A A ear eam
Second operand #imm8 ear eam A A
Byte count 2 2 2+ 2 2+
Cycle count 1 1 2 1 3
F2MC-16FX Family
98 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.11 AND (And Byte Data of Destination and Source to Destination)
● Example:
AND 0052H,A
In this example, the logical AND operation is taken between the byte data (FAH) at address
0052H and the low-order byte data (55H) of AL.
× × × × 0 0 5 5 A
Before execution
× × × × 0 0 5 5 A
After execution
Memory
F A 0052
Memory
5 0 0052
CCR × × × × ×T N Z V C
CCR × 0 0 0 ×T N Z V C
AH AL AH AL
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 99
CHAPTER 8 DETAILED INSTRUCTIONS8.12 AND (And Byte Data of Immediate Data and Condition
Code Register)
8.12 AND (And Byte Data of Immediate Data and Condition Code Register)
Take the logical AND operation of the byte data of the condition code register (CCR) and 8-bit immediate data and restore the result in CCR.
In the logical AND operation, the most significant bit of the byte data is not taken into
consideration.
● Assembler format:
AND CCR,#imm8
● Operation:
(CCR) ← (CCR) and imm8 [Byte logical AND]
● CCR:
I: Stores bit 6 of the operation result.
S: Stores bit 5 of the operation result.
T: Stores bit 4 of the operation result.
N: Stores bit 3 of the operation result.
Z: Stores bit 2 of the operation result.
V: Stores bit 1 of the operation result.
C: Stores bit 0 of the operation result.
●Byte count and cycle count:
Byte count: 2
Cycle count: 1
I S T N Z V C
* * * * * * *
F2MC-16FX Family
100 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.12 AND (And Byte Data of Immediate Data and Condition Code Register)
● Example:
AND CCR,#57H
In this example, the logical AND operation is taken between the CCR value (0110101B) and
the immediate data (57H).
× × × × × × × ×
CCR
A
ILM
Before execution
0I
1S
1T
0N
1Z
0V
1C
×ILM2
×ILM1
×ILM0
×MSB
× × × ×LSB
RP
× × × × × × × ×
CCR
A
ILM
After execution
0I
0S
1T
0N
1Z
0V
1C
×ILM2
×ILM1
×ILM0
×MSB
× × × ×LSB
RP
AH AL AH AL
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 101
CHAPTER 8 DETAILED INSTRUCTIONS8.13 ANDL (And Long Word Data of Destination and Source to
Destination)
8.13 ANDL (And Long Word Data of Destination and Source to Destination)
Take the logical AND operation for the long word data of the accumulator (A) and that specified by the second operand in a bit-by-bit basis and restore the result in A.
● Assembler format:
ANDL A,ear ANDL A,eam
● Operation:
(A) ← (A) and (Second operand) [Long word logical AND]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * R –
First operand A A
Second operand ear eam
Byte count 2 2+
Cycle count 2 3
Odd address correction 0 1
F2MC-16FX Family
102 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.13 ANDL (And Long Word Data of Destination and Source to Destination)
● Example:
ANDL A,0FFF0H
In this example, the logical AND operation is taken between the long word data (8252FEACH)
of the accumulator (A) and the long word data (FF55AA00H) at address FFF0H.
Before execution After execution
Memory
F F FFF35 5 FFF2A A FFF10 0 FFF0
Memory
F F FFF35 5 FFF2A A FFF10 0 FFF0
8 2 5 2 F E A C A 8 2 5 0 A A 0 0 A
CCR × × × × ×T N Z V C
CCR × 1 0 0 ×T N Z V C
AH AL AH AL
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.14 ANDW (And Word Data of AH and AL to AL)
8.14 ANDW (And Word Data of AH and AL to AL)
Take the logical AND operation of the word data of AH and that of AL and restore the result in AL.
● Assembler format:
ANDW A
● Operation:
(AL) ← (AH) and (AL) [Word logical AND]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
ANDW A
In this example, the logical AND operation is taken between the word data (AB98H) of AL and
the word data (0426H) of AH.
I S T N Z V C
– – – * * R –
0 4 2 6 A B 9 8 A
Before execution
0 4 2 6 0 0 0 0 A
After execution
CCR × × × × ×T N Z V C
CCR × 0 1 0 ×T N Z V C
AH AL AH AL
F2MC-16FX Family
104 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.15 ANDW (And Word Data of Destination and Source to Destination)
8.15 ANDW (And Word Data of Destination and Source to Destination)
Take the logical AND operation of the word data specified by the first operand and the word data specified by the second operand and restore the result in the first operand.
● Assembler format:
ANDW A,#imm16
ANDW A,ear ANDW A,eam
ANDW ear,A ANDW eam,A
● Operation:
(First operand) ← (First operand) and (Second operand) [Word logical AND]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * R –
First operand A A A ear eam
Second operand #imm16 ear eam A A
Byte count 3 2 2+ 2 2+
Cycle count 1 1 2 1 3
Odd address correction 0 0 1 0 2
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.15 ANDW (And Word Data of Destination and Source to
Destination)● Example:
ANDW 0E001H,A
In this example, the logical AND operation is taken between the word data (8342H) at address
0E001H and the word data (5963H) of AL.
× × × × 5 9 6 3 A
Before execution
× × × × 5 9 6 3 A
After execution
Memory
8 3 E002
Memory
0 1 E0024 2 E001 4 2 E001
CCR × × × × ×T N Z V C
CCR × 0 0 0 ×T N Z V C
AH AL AH AL
F2MC-16FX Family
106 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.16 ASR (Arithmetic Shift Byte Data of Accumulator to Right)
8.16 ASR (Arithmetic Shift Byte Data of Accumulator to Right)
Shift the least significant byte data of the accumulator (A) arithmetically to the right by the number of bits specified by the second operand. The most significant bit of the least significant byte data for A is not changed.
The bit last shifted out from the least significant bit is stored in the carry flag (C) of the
condition code register (CCR).
● Assembler format:
ASR A,R0
● Operation:
● CCR:
I and S: Unchanged
T: Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N: Set when the MSB of the shifting result is "1", cleared otherwise.
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
Byte count: 2
Cycle count: 1
I S T N Z V C
– – * * * – *
AL
MSB LSB
1
C T
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.16 ASR (Arithmetic Shift Byte Data of Accumulator to Right)
● Example:
ASR A,R0
In this example, the low-order byte data (96H) of AL is shifted arithmetically to the right by the
number of bits (3 bits) specified by R0.
× × × × × × 9 6A
Before execution
0 3R0
× × × × × × F 2A
After execution
0 3R0CCR × × × × ×T N Z V C
CCR 1 1 0 × 1
T N Z V C
AH AL AH AL
F2MC-16FX Family
108 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.17 ASRL (Arithmetic Shift Long Word Data of Accumulator to Right)
8.17 ASRL (Arithmetic Shift Long Word Data of Accumulator to Right)
Shift the long word data of the accumulator (A) arithmetically to the right by the number of bits specified by the second operand.
The most significant bit of A is not changed. The bit last shifted out from the least significant
bit is stored in the carry flag (C) of the condition code register (CCR).
● Assembler format:
ASRL A,R0
● Operation:
● CCR:
I and S: Unchanged
T: Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N: Set when the MSB of the shifting result is "1", cleared otherwise.
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
Byte count: 2
Cycle count: 1
I S T N Z V C
– – * * * – *
A
MSB LSB
1
C T
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.17 ASRL (Arithmetic Shift Long Word Data of Accumulator to
Right)● Example:
ASRL A,R0
In this example, the long word data (12345678H) of the accumulator (A) is shifted
arithmetically to the right by the number of bits (2 bits) specified by R0.
1 2 3 4 5 6 7 8A
Before execution
0 2R0
0 4 8 D 1 5 9 EA
After execution
0 2R0
CCR × × × × 0T N Z V C
CCR 1 0 0 × 0T N Z V C
AH AL AH AL
F2MC-16FX Family
110 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.18 ASRW (Arithmetic Shift Word Data of Accumulator to Right)
8.18 ASRW (Arithmetic Shift Word Data of Accumulator to Right)
Shift the low-order word data of the accumulator (A) arithmetically to the right by one bit.
The most significant bit of the low-order word data for A is not changed. The bit shifted out
from the least significant bit is stored in the carry flag (C).
● Assembler format:
ASRW A
● Operation:
● CCR:
I and S: Unchanged
T: Set when the old carry value is equal to "1" or the old T value is equal to "1", cleared
otherwise.
N: Set when the MSB of the shifting result is "1", cleared otherwise.
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit shifted out from the LSB of A.
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
I S T N Z V C
– – * * * – *
AL
MSB LSB
1
C T
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.18 ASRW (Arithmetic Shift Word Data of Accumulator to Right)
● Example:
ASRW A
In this example, the word data (A096H) of AL is shifted arithmetically to the right by one bit.
× × × × A 0 9 6 A
Before execution
× × × × D 0 4 B A
After execution
CCR 0 × × × 1
T N Z V C
CCR 1 1 0 × 0
T N Z V C
AH AL AH AL
F2MC-16FX Family
112 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.19 ASRW (Arithmetic Shift Word Data of Accumulator to Right)
8.19 ASRW (Arithmetic Shift Word Data of Accumulator to Right)
Shift the low-order word data of the accumulator (A) arithmetically to the right by the number of bits specified by the second operand.
The most significant bit of the low-order word data for A is not changed. The bit last shifted
out from the least significant bit is stored in the carry flag (C) of the condition code register
(CCR).
● Assembler format:
ASRW A,R0
● Operation:
● CCR:
I and S: Unchanged
T: Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N: Set when the MSB of the shifting result is "1", cleared otherwise.
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
Byte count: 2
Number of states: 1
I S T N Z V C
– – * * * – *
AL
MSB LSB
1
C T
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.19 ASRW (Arithmetic Shift Word Data of Accumulator to Right)
● Example:
ASRW A,R0
In this example, the word data (A096H) of AL is shifted arithmetically to the right by the
number of bits (2 bits) specified by R0.
× × × × A 0 9 6A
Before execution
0 2R0
× × × × E 8 2 5 A
After execution
0 2R0CCR × × × × 0
T N Z V C
CCR 0 1 0 × 1
T N Z V C
AH AL AH AL
F2MC-16FX Family
114 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.20 BBcc (Branch if Bit Condition satisfied)
8.20 BBcc (Branch if Bit Condition satisfied)
Cause a branch if the bit data specified by the first operand satisfies the condition.
Control is transferred to the address resulting from word-adding the sign-extended data,
specified by the second operand, to the address of the instruction following the BBcc
instruction.
● Assembler format:
BBC addr16:bp, rel BBS addr16:bp, rel
BBC dir:bp, rel BBS dir:bp, rel
BBC io:bp, rel BBS io:bp, rel
● Operation:
If the condition is satisfied: (PC) ← (PC) + <Byte count> + rel [Word addition]
If the condition is not satisfied: (PC) ← (PC)+<Byte count> [Word addition]
● CCR:
I, S, T, and N: Unchanged
Z: Set when the bit data is "0"; cleared when "1".
V and C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – – * – –
BBcc BBC BBS
Condition Bit data = 0 Bit data = 1
First operand addr16:bp dir:bp io:bp addr16:bp dir:bp io:bp
Byte count 5 4 4 5 4 4
Cycle count 5 5 5 5 5 5
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.20 BBcc (Branch if Bit Condition satisfied)
● Example:
BBC 1234H:7,12H
In this example, a branch is caused if bit 7 in the byte data (7FH) at address 1234H is equal to
"0" (condition satisfied).
E 1 0 0 PC
Before execution
Memory
× ×7 F 1234 : bit7 = 0× ×
E 1 1 7 PC
After execution
Memory
× ×7 F 1234× ×
+ (12 + number of bytes 5)
F2MC-16FX Family
116 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.21 Bcc (Branch relative if Condition satisfied)
8.21 Bcc (Branch relative if Condition satisfied)
Each instruction causes a branch if the condition determined for that instruction is satisfied.
Control is transferred to the address resulting from word-adding the sign-extended data,
specified by the operand, to the address of the instruction following the BBcc instruction.
● Assembler format:
BZ/BEQ rel BNZ/BNE rel
BC/BLO rel BNC/BHS rel
BN rel BP rel
BV rel BNV rel
BT rel BNT rel
BLT rel BGE rel
BLE rel BGT rel
BLS rel BHI rel
BRA rel
● Operation:
If the condition is satisfied: (PC) ← (PC)+2+rel [Word addition]
If the condition is not satisfied: (PC) ← (PC)+2 [Word addition]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 2
Cycle count: 2
I S T N Z V C
– – – – – – –
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.21 Bcc (Branch relative if Condition satisfied)
● Branch instruction and condition:
● Example:
BHI 50H
In this example, a branch is caused if the C or Z flag of the condition code register (CCR) is
equal to "0" (condition satisfied).
Bcc BZ/BEQ
BNZ/BNE
BC/BLO
BNC/BHS
BN BP BV BNV BT BNT BRA
Condition Z=1 Z=0 C=1 C=0 N=1 N=0 V=1 V=0 T=1 T=0Always satisfied
Bcc BLT BGE BLE BGT BLS BHI
Condition V xor N = 1 V xor N = 0(V xor N) or
Z = 1(V xor N) or
Z = 0C or Z = 1 C or Z = 0
PC PC+(2+50)
CCR CCRC or Z = 0, then
Before execution After execution
E 2 0 0
0 1 0 1 0
T N Z V C
E 2 5 2
0 1 0 1 0
T N Z V C
F2MC-16FX Family
118 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.22 CALL (Call Subroutine)
8.22 CALL (Call Subroutine)
Cause a branch to the address specified by the operand. By executing the RET instruction in the subroutine to which control has been transferred, control returns to the instruction following the CALL instruction.
● Assembler format:
CALL @ear CALL @eam
CALL addr16
● Operation:
(SP) ← (SP)–2 [Word subtraction], ((SP)) ← (PC)+<Byte count>
(PC) ← <Operand>
● CCR:
None of the flags is changed.
● Byte count and cycle count:
I S T N Z V C
– – – – – – –
Operand @ear @eam addr16
Byte count 2 2+ 3
Cycle count 3 5 3
Odd address correction 1 1+1 1
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.22 CALL (Call Subroutine)
● Example:
CALL @@RW0
In this example, a branch is caused to the address (DC08H) indicated by the word data at the
address (F340H) specified by the operand (@@RW0) after the address (E55AH) of the next
instruction has been pushed to the stack specified by SP.
E 5 5 8PC
Before execution
Memory
D C F3410 8 F340
× × 0124
F 3 4 0RW0 0 1 2 4SP
× × 0123× × 0122
SP
D C 0 8PC
After execution
Memory
D C F3410 8 F340
× × 0124
F 3 4 0RW0 0 1 2 2SP
E 5 01235 A 0122SP
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.23 CALLP (Call Physical Address)
8.23 CALLP (Call Physical Address)
Cause a branch to the physical address specified by the operand. By executing the RETP instruction in the subroutine to which control has been transferred, control returns to the instruction following the CALLP instruction.
The program counter bank register (PCB) stores the most significant byte of the data specified
by the operand.
● Assembler format:
CALLP @ear CALLP @eam
CALLP addr24
● Operation:
(SP) ← (SP)–2 [Word subtraction], ((SP)) ← (PCB) [Zero extension]
(SP) ← (SP)–2 [Word subtraction], ((SP)) ← (PC)+<Byte count>
(PCB) ← Physical address to branch to (High-order byte)
(PC) ← Physical address to branch to (Low-order word)
● CCR:
None of the flags is changed.
● Byte count and cycle count:
I S T N Z V C
– – – – – – –
Operand @ear @eam addr24
Byte count 2 2+ 4
Cycle count 5 7 4
Odd address correction 5 2+1 2
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CHAPTER 8 DETAILED INSTRUCTIONS8.23 CALLP (Call Physical Address)
● Example:
CALLP 080711H
In this example, a branch is caused to address 080711H after PCB and the address (4349H) of
the next instruction have been pushed to the stack specified by USB and SP. The most
significant byte (08H) in the operand is set to PCB.
4 3 4 5PC
Before execution
Memory
× × 15F900× × 15F8FF× × 15F8FE
A DPCB
F 9 0 0SP
× × 15F8FD× × 15F8FC
SP
1 5USB
0 7 1 1PC
After execution
Memory
× × 15F9000 0 15F8FFA D 15F8FE
0 8PCB
F 8 F CSP
4 3 15F8FD4 9 15F8FCSP
1 5USB
CCR × 0 × × × × ×I S T N Z V C
CCR × 0 × × × × ×I S T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.24 CALLV (Call Vectored Subroutine)
8.24 CALLV (Call Vectored Subroutine)
Cause a branch to the address pointed to by the interrupt vector specified by the operand. By executing the RET instruction in the subroutine to which control has been transferred, control returns to the instruction following the CALLV instruction.
The RET instruction is the same as that used with the CALL instruction.
● Assembler format:
CALLV #vct4
● Operation:
(SP) ← (SP)–2 [Word subtraction] ((SP)) ← (PC) + 1
(PC) ← Vector address
Note:
When the value of the program counter bank register (PCB) is equal to upper 8 bits of theinterrupt vector table register (TBR:TB[23:16]) and lower 6 bits of the TBR (TBR:TB[15:0])is 111111B, the vector area for "CALLV #vct4" instruction is also used as the vector areafor "INT #vct8" (#0 to #7) instruction. (See Table 8.24-1 .)
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 1
Cycle count: 5
Odd address correction: 1
I S T N Z V C
– – – – – – –
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CHAPTER 8 DETAILED INSTRUCTIONS8.24 CALLV (Call Vectored Subroutine)
● Example:
CALLV #15
In this example, a branch is caused to the address specified by the interrupt vector of #15 after
the address (F4A8H) of the next instruction has been pushed to the stack specified by SP.
* : XX is replaced by the value of the program counter bank register (PCB).
F 4 A 7PC
Before execution
Memory
E 1 FFE15 4 FFE0
× × 0102
0 1 0 2SP
× × 0101× × 0100
SP
E 1 5 4PC
After execution
Memory
E 1 FFE15 4 FFE0
× × 0102
0 1 0 0SP
F 4 0101A 8 0100SP
Table 8.24-1 CALLV Vector List
Instruction Vector address L* Vector address H*
CALLV #0 XXFFFEH XXFFFFH
CALLV #1 XXFFFCH XXFFFDH
CALLV #2 XXFFFAH XXFFFBH
CALLV #3 XXFFF8H XXFFF9H
CALLV #4 XXFFF6H XXFFF7H
CALLV #5 XXFFF4H XXFFF5H
CALLV #6 XXFFF2H XXFFF3H
CALLV #7 XXFFF0H XXFFF1H
CALLV #8 XXFFEEH XXFFEFH
CALLV #9 XXFFECH XXFFEDH
CALLV #10 XXFFEAH XXFFEBH
CALLV #11 XXFFE8H XXFFE9H
CALLV #12 XXFFE6H XXFFE7H
CALLV #13 XXFFE4H XXFFE5H
CALLV #14 XXFFE2H XXFFE3H
CALLV #15 XXFFE0H XXFFE1H
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CHAPTER 8 DETAILED INSTRUCTIONS8.25 CBNE (Compare Byte Data and Branch if not Equal)
8.25 CBNE (Compare Byte Data and Branch if not Equal)
Perform byte comparison on the first and second operands (8-bit immediate data) and cause a branch if the first and second operands are not equal. A branch is not taken if the first and second operands are equal.
Control is transferred to the address equal to the address of the instruction following the CBNE
instruction plus the word value resulting from sign-extending the third operand.
Note that, when the first operand is @PC + disp16, the operand address is equal to the "address
of the location containing the machine instruction for the CBNE instruction + 4 + disp16", not
the "address of the location containing the machine instruction for the instruction following the
CBNE instruction 4 + disp16".
● Assembler format:
CBNE A,#imm8,rel
CBNE ear,#imm8,rel
CBNE eam,#imm8,rel
● Operation:
(First operand)≠imm8 [Byte comparison] : (PC) ← (PC)+<Byte count>+rel
(First operand)=imm8 [Byte comparison] : (PC) ← (PC)+<Byte count>
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the compare operation result is "1", cleared otherwise.
Z: Set when (First operand) = imm8, cleared otherwise.
V: Set when an overflow has occurred as a result of the compare operation, cleared
otherwise.
C: Set when a borrow has occurred as a result of the compare operation, cleared
otherwise.
I S T N Z V C
– – – * * * *
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CHAPTER 8 DETAILED INSTRUCTIONS8.25 CBNE (Compare Byte Data and Branch if not Equal)
● Byte count and cycle count:
● Example:
CBNE A, #0F4H,55H
In this example, the low-order byte data (F3H) of AL is compared with the 8-bit immediate
data (F4H). A branch is caused because the first and second operands are not equal.
First operand A ear eam
Second operand #imm8 #imm8 #imm8
Third operand rel rel rel
Byte count 3 4 4+
Cycle count 5 4 5
× × × × 0 0 F 3A
Before execution
E 3 1 0PC
× × × × 0 0 F 3 A
After execution
E 3 6 8 PC
F3H≠F4H
+(55H+Byte count: 3)
CCR × × × × ×T N Z V C
CCR × 1 0 0 1
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.26 CLRB (Clear Bit)
8.26 CLRB (Clear Bit)
Clear the bit specified by bp to "0", in the memory location specified by the operand.
● Assembler format:
CLRB dir:bp
CLRB io:bp
CLRB addr16:bp
● Operation:
(Operand) b ← 0 [Bit transfer]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
● Example:
CLRB 0AA55H:3
In this example, bit 3 in data (FFH) at address AA55H is set to "0".
I S T N Z V C
– – – – – – –
Operand dir:bp io:bp addr16:bp
Byte count 3 3 4
Cycle count 3 3 3
Before execution
Memory
× ×F F AA55× ×
After execution
Memory
× ×F 7 AA55× ×
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CHAPTER 8 DETAILED INSTRUCTIONS8.27 CMP (Compare Byte Data of Destination and Source)
8.27 CMP (Compare Byte Data of Destination and Source)
Compare the byte data specified by the first operand with that specified by the second operand and set the flag changes in the condition code register (CCR).
The data specified by the first operand and that by the second operand are not changed.
If only the accumulator (A) is specified as an operand, AH and AL are compared.
● Assembler format:
(1) CMP A,#imm8
CMP A,ear CMP A,eam
(2) CMP A
● Operation:
(1) (First operand)–(Second operand) [Byte comparison]
(2) (AH)–(AL) [Byte comparison]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – * * * *
First operand A A A A
Second operand #imm8 ear eam –
Byte count 2 2 2+ 1
Cycle count 1 1 2 1
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CHAPTER 8 DETAILED INSTRUCTIONS8.27 CMP (Compare Byte Data of Destination and Source)
● Example:
CMP A,#7FH
In this example, the low-order byte data (22H) of AL is compared with the 8-bit immediate data
(7FH).
× × × × A 0 2 2 A
Before execution
× × × × A 0 2 2A
After execution
CCR × × × × ×T N Z V C
CCR × 1 0 0 1
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.28 CMPL (Compare Long Word Data of Destination and
Source)
8.28 CMPL (Compare Long Word Data of Destination and Source)
Compare the long word data specified by the first operand with that specified by the second operand and set the result in the condition code register (CCR).
The data specified by the first operand and that specified by the second are not changed.
● Assembler format:
CMPL A,#imm32
CMPL A,ear CMPL A,eam
● Operation:
(First operand)–(Second operand) [Long word comparison]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – * * * *
First operand A A A
Second operand #imm32 ear eam
Byte count 5 2 2+
Cycle count 2 2 3
Odd address correction 0 0 1
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CHAPTER 8 DETAILED INSTRUCTIONS8.28 CMPL (Compare Long Word Data of Destination and Source)
● Example:
CMPL A,#12345678H
In this example, the long-word data (12345678H) of the accumulator (A) is compared with the
32-bit immediate data (12345678H).
1 2 3 4 5 6 7 8 A
Before execution
1 2 3 4 5 6 7 8 A
After execution
CCR × × × × ×T N Z V C
CCR × 0 1 0 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.29 CMPW (Compare Word Data of Destination and Source)
8.29 CMPW (Compare Word Data of Destination and Source)
Compare the word data specified by the first operand with that specified by the second operand and set the result in the condition code register (CCR).
The data specified by the first operand and that specified by the second operand are not
changed. If only A is specified as an operand, AH and AL are compared.
● Assembler format:
(1) CMPW A,#imm16
CMPW A,ear CMPW A,eam
(2) CMPW A
● Operation:
(1) (First operand)–(Second operand) [Word comparison]
(2) (AH)–(AL) [Word comparison]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – * * * *
First operand A A A A
Second operand #imm16 ear eam –
Byte count 3 2 2+ 1
Cycle count 1 1 2 1
Odd address correction 0 0 1 0
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CHAPTER 8 DETAILED INSTRUCTIONS8.29 CMPW (Compare Word Data of Destination and Source)
● Example:
CMPW A,RW0
In this example, the word data (ABCDH) of AL is compared with the word data (ABCCH) of
RW0.
× × × × A B C DA
Before execution
A B C CRW0
× × × × A B C DA
After execution
A B C CRW0
CCR × × × × ×T N Z V C
CCR × 0 0 0 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.30 CWBNE (Compare Word Data and Branch if not Equal)
8.30 CWBNE (Compare Word Data and Branch if not Equal)
Perform word comparison on the first and second operands (16-bit immediate data) and cause a branch if the first and second operands are not equal. A branch is not taken if the first and second operands are equal.
Control is transferred to the address equal to the address of the instruction following the
CWBNE instruction plus the word data resulting from sign-extending the third operand.
When the first operand is @PC + disp16, the operand address is equal to the "address of the
location containing the machine instruction for the CWBNE instruction + 4 + disp16", not the
"address of the location containing the machine instruction for the instruction following the
CWBNE instruction + disp16".
● Assembler format:
CWBNE A,#imm16,rel
CWBNE ear,#imm16,rel
CWBNE eam,#imm16,rel
● Operation:
(First operand)≠imm16 [Word comparison] : (PC) ← (PC)+<Byte count>+rel
(First operand)=imm16 [Word comparison] : (PC) ← (PC)+<Byte count>
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the comparison result is "1", cleared otherwise.
Z: Set when (First operand) = imm16, cleared otherwise.
V: Set when an overflow has occurred as a result of the compare operation, cleared
otherwise.
C: Set when a borrow has occurred as a result of the compare operation, cleared
otherwise.
I S T N Z V C
– – – * * * *
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CHAPTER 8 DETAILED INSTRUCTIONS8.30 CWBNE (Compare Word Data and Branch if not Equal)
● Byte count and cycle count:
● Example:
CWBNE A,#0E5E5H,30H
In this example, the word data (5EE5H) of AL is compared with the 16-bit immediate data
(E5E5H). A branch is caused because the first and second operands are not equal.
First operand A ear eam
Second operand #imm16 #imm16 #imm16
Third operand rel rel rel
Byte count 4 5 5+
Cycle count 5 5 6
Odd address correction 0 0 1
× × × × 5 E E 5A
Before execution
D 8 5 6PC
× × × × 5 E E 5 A
After execution
D 8 8 A PC
CCR × × × × ×T N Z V C
CCR × 0 0 0 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.31 DBNZ (Decrement Byte Data and Branch if not Zero)
8.31 DBNZ (Decrement Byte Data and Branch if not Zero)
Decrement the data specified by the first operand by one byte, and if the result is not equal to 00H, a branch is generated. If the decrement result is equal to
00H, control is transferred to the next instruction.
Control is transferred to the address equal to the address of the instruction following the DBNZ
instruction plus the word data resulting from sign-extending the data specified by the second
operand. When the first operand is @PC + disp16, the operand address is equal to the "address
of the location containing the machine instruction for the DBNZ instruction + 4 + disp16", not
the "address of the location containing the machine instruction for the instruction following the
DBNZ instruction + disp16".
● Assembler format:
DBNZ ear,rel DBNZ eam,rel
● Operation:
(ea) ← (ea)–1 [Byte subtraction]
if (ea) ≠ 0 : (PC) ← (PC)+<Byte count>+rel
if (ea) = 0 : (PC) ← (PC)+<Byte count>
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * * –
First operand ear eam
Second operand rel rel
Byte count 3 3+
Cycle count 5 6
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CHAPTER 8 DETAILED INSTRUCTIONS8.31 DBNZ (Decrement Byte Data and Branch if not Zero)
● Example:
DBNZ @RW0+2,40H
In this example, the byte data (03H) at the address (0122H) specified by the first operand
(@RW0+2) is decremented by one. A branch is caused because the operation result is not "0".
E 3 5 8 PC
Before execution
Memory
0 3 0122× × 0121× × 0120
0 1 2 0 RW0
RW0+2
E 3 9 C PC
After execution
Memory
0 2 0122× × 0121× × 0120
0 1 2 0 RW0
RW0+2
CCR 0 0 0 0 1T N Z V C
CCR 0 0 1 0 1T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.32 DEC (Decrement Byte Data)
8.32 DEC (Decrement Byte Data)
Decrement the byte data specified by the operand by one and store the result in the operand.
● Assembler format:
DEC ear DEC eam
● Operation:
(ea) ← (ea)–1 [Byte subtraction]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Unchanged
● Byte count and cycle count:
● Example:
DEC R1
In this example, the byte data (80H) of R1 is decremented by one.
I S T N Z V C
– – – * * * –
Operand ear eam
Byte count 2 2+
Cycle count 1 3
Before execution
8 0R1
After execution
7 FR1
CCR × 0 0 1 ×T N Z V C
CCR × × × × ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.33 DECL (Decrement Long Word Data)
8.33 DECL (Decrement Long Word Data)
Decrement the long word data specified by the operand by one and restore the result in the operand.
● Assembler format:
DECL ear DECL eam
● Operation:
(ea) ← (ea)–1 [Long word subtraction]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Unchanged
● Byte count and cycle count:
● Example:
DECL RL0
In this example, the long word data (00001000H) of RL0 is decremented by one.
I S T N Z V C
– – – * * * –
Operand ear eam
Byte count 2 2+
Cycle count 2 4
Odd address correction 0 2
0 0 0 0 1 0 0 0 RL0
Before execution
0 0 0 0 0 F F F RL0
After execution
CCR × × × × ×T N Z V C
CCR × 0 0 0 ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.34 DECW (Decrement Word Data)
8.34 DECW (Decrement Word Data)
Decrement the word data specified by the operand by one and restore the result in the operand.
● Assembler format:
DECW ear DECW eam
● Operation:
(ea) ← (ea)–1 [Word subtraction]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * * –
Operand ear eam
Byte count 2 2+
Cycle count 1 3
Odd address correction 0 2
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CHAPTER 8 DETAILED INSTRUCTIONS8.34 DECW (Decrement Word Data)
● Example:
DECW @RW0+1000H
In this example, the word data (0001H) at the address (7780H) specified by the operand
(@RW0+1000H) is decremented by one.
Before execution
Memory
0 0 77810 1 7780× × 777F
6 7 8 0 RW0
RW0+1000H
After execution
Memory
0 0 77810 0 7780× × 777F
6 7 8 0 RW0
RW0+1000H
CCR × × × × ×T N Z V C
CCR × 0 0 1 ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.35 DIV (Divide Word Data by Byte Data)
8.35 DIV (Divide Word Data by Byte Data)
Divide the word data specified by the first operand by the byte data specified by the second operand and store the quotient (byte data) in the first operand and the remainder (byte data) in the second operand. The operation assumes that the values are signed ones.
If only A is specified by an operand, the word data of AH is divided by the byte data of AL and
the quotient (byte data) is stored in AL and the remainder (byte data) in AH. The operation
assumes that the values are signed ones.
If division by zero occurs, the second operand or AL retains the value it had immediately
before the instruction was executed. If an overflow occurs, the contents of AL are undefined.
● Assembler format:
(1) DIV A,ear DIV A,eam
(2) DIV A
● Operation:
(1) word (A) / byte (ea), Quotient → byte (A), Remainder → byte (ea)
(2) word (AH) / byte (AL), Quotient → byte (AL), Remainder → byte (AH)
● CCR:
I, S, T, N, and Z: Unchanged
V: Set when an overflow has occurred as a result of the operation or the divisor
is zero, cleared otherwise.
C: Set when the divisor is zero, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – – – * *
First operand A A A
Second operand – ear eam
Byte count 2 2 2+
Cycle countOverflow: 5
Normal termination: 11Overflow: 5
Normal termination: 11Overflow: 6
Normal termination: 13
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CHAPTER 8 DETAILED INSTRUCTIONS8.35 DIV (Divide Word Data by Byte Data)
● Example:
DIV A
In this example, the word data (1357H) of AH is divided by the byte data (AAH) of AL with a
sign. The quotient is set to the low-order byte of AL and the remainder to the low-order byte of
AH.
1 3 5 7 0 0 A AA
Before execution
0 0 3 1 0 0 C 7A
After execution
AH AHAL AL
CCR × × × × ×T N Z V C
CCR × × × 0 0
T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.36 DIVW (Divide Long Word Data by Word Data)
8.36 DIVW (Divide Long Word Data by Word Data)
Divide the long word data specified by the first operand (A) by the word data specified by the second operand and store the quotient (word data) in A and the remainder (word data) in the second operand. The operation assumes that the values are signed ones.
If division by zero occurs, the second operand or AL retains the value it had immediately
before the instruction was executed. If an overflow occurs, the contents of AL are undefined.
● Assembler format:
DIVW A,ear DIVW A,eam
● Operation:
long word (A) / word (ea), Quotient → word (A), Remainder → word (ea)
● CCR:
I, S, T, N, and Z: Unchanged
V: Set when an overflow has occurred as a result of the operation or the divisor
is zero, cleared otherwise.
C: Set when the divisor is zero, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – – – * *
First operand A A
Second operand ear eam
Byte count 2 2+
Cycle countOverflow: 5
Normal termination: 19Overflow: 6
Normal termination: 21
Odd address correction 0 2
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CHAPTER 8 DETAILED INSTRUCTIONS8.36 DIVW (Divide Long Word Data by Word Data)
● Example:
DIVW A,7254H
In this example, the long word data (00001357H) of the accumulator (A) is divided by the word
data (00AAH) at address 7254H with a sign. The quotient is set to AL and the remainder to
address 7254H.
0 0 0 0 1 3 5 7 A
Before execution
0 0 0 0 0 0 1 D A
After execution
Memory
0 0 7255
Memory
0 0 7255A A 7254 1 5 7254
AH AL AH AL
CCR × × × × ×T N Z V C
CCR × × × 0 0
T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.37 DIVU (Divide unsigned Word Data by unsigned Byte Data)
8.37 DIVU (Divide unsigned Word Data by unsigned Byte Data)
Divide the word data specified by the first operand by the byte data specified by the second operand and store the quotient (byte data) in the first operand and the remainder (byte data) in the second operand. The operation assumes that the values are unsigned ones.
If only A is specified by an operand, the word data of AH is divided by the byte data of AL and
the quotient (byte data) is stored in AL and the remainder (byte data) in AH. The operation
assumes that the values are unsigned ones.
If an overflow or division by zero occurs, the second operand or AL retains the value it had
immediately before the instruction was executed.
● Assembler format:
(1) DIVU A,ear DIVU A,eam
(2) DIVU A
● Operation:
(1) word (A) / byte (ea), Quotient → byte (A), Remainder → byte (ea)
(2) word (AH) / byte (AL), Quotient → byte (AL), Remainder → byte (AH)
● CCR:
I, S, T, N, and Z: Unchanged
V: Set when an overflow has occurred as a result of the operation or the divisor
is zero, cleared otherwise.
C: Set when the divisor is zero, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – – – * *
First operand A A A
Second operand – ear eam
Byte count 1 2 2+
Cycle countOverflow: 4
Normal termination: 9Overflow: 4
Normal termination: 9Overflow: 5
Normal termination: 11
F2MC-16FX Family
146 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.37 DIVU (Divide unsigned Word Data by unsigned Byte Data)
● Example:
DIVU A
In this example, the word data (1357H) of AH is divided by the byte data (AAH) of AL without
a sign. The quotient is set to AL and the remainder to AH.
1 3 5 7 0 0 A A A
Before execution
0 0 1 5 0 0 1 DA
After execution
CCR × × × × ×T N Z V C
CCR × × × 0 0
T N Z V C
AH AL AH AL
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.38 DIVUW (Divide unsigned Long Word Data by unsigned
Word Data)
8.38 DIVUW (Divide unsigned Long Word Data by unsigned Word Data)
Divide the long word data specified by the first operand (A) by the word data specified by the second operand and store the quotient (word data) in A and the remainder (word data) in the second operand. The operation assumes that the values are unsigned ones.
If an overflow or division by zero occurs, the second operand or AL retains the value it had
immediately before the instruction was executed.
● Assembler format:
DIVUW A,ear DIVUW A,eam
● Operation:
long word (A) / word (ea), Quotient → word (A), Remainder → word (ea)
● CCR:
I, S, T, N, and Z: Unchanged
V: Set when an overflow has occurred as a result of the operation or the divisor
is zero, cleared otherwise.
C: Set when the divisor is zero, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – – – * *
First operand A A
Second operand ear eam
Byte count 2 2+
Cycle countOverflow: 4
Normal termination: 17Overflow: 5
Normal termination: 19
Odd address correction 0 2
F2MC-16FX Family
148 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.38 DIVUW (Divide unsigned Long Word Data by unsigned Word Data)
● Example:
DIVUW A,7254H
In this example, the long word data (00001357H) of the accumulator (A) is divided by the word
data (00AAH) at address 7254H without a sign. The quotient is set to AL and the remainder to
address 7254H.
0 0 0 0 1 3 5 7 A
Before execution
0 0 0 0 0 0 1 DA
After execution
Memory
0 0 7255
Memory
0 0 7255A A 7254 1 5 7254
CCR × × × × ×T N Z V C
CCR × × × 0 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.39 DWBNZ (Decrement Word Data and Branch if not Zero)
8.39 DWBNZ (Decrement Word Data and Branch if not Zero)
Decrement the data specified by the first operand by one word, and if the result is not equal to zero, cause a branch. If the decrement result is equal to zero, control is transferred to the instruction following the DWBNZ instruction.
Control is transferred to the address equal to the address of the instruction following the
DWBNZ instruction plus the word data resulting from sign-extending the data specified by the
second operand.
When the first operand is @PC + disp16, the operand address is equal to the "address of the
location containing the machine instruction for the DWBNZ instruction + 4 + disp16", not the
"address of the location containing the machine instruction for the instruction following the
DWBNZ instruction + disp16".
● Assembler format:
DWBNZ ear,rel DWBNZ eam,rel
● Operation:
(First operand) ← (First operand)–1 [Word subtraction]
When (First operand)≠0, (PC) ← (PC)+<Byte count>+second operand
(PC) ← (PC)+<Byte count>
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * * –
First operand ear eam
Second operand rel rel
Byte count 3 3+
Cycle count 5 6
Odd address correction 0 2
F2MC-16FX Family
150 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.39 DWBNZ (Decrement Word Data and Branch if not Zero)
● Example:
DWBNZ RW0,30H
In this example, the word data (0001H) of RW0 is decremented by one. A branch is not caused
because the operation result is "0".
F 8 2 0PC
Before execution
0 0 0 1RW0
F 8 2 3PC
After execution
0 0 0 0RW0
CCR × × × × ×T N Z V C
CCR × 0 0 0 ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.40 EXT (Sign Extend from Byte Data to Word Data)
8.40 EXT (Sign Extend from Byte Data to Word Data)
Extend the lower byte data of AL to word data as a signed binary number.
● Assembler format:
EXT
● Operation:
When bit 7 of AL=0, bits 8 to 15 of AL ← 00H
When bit 7 of AL≠0, bits 8 to 15 of AL ← FFH
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the sign-extended data is "1", cleared otherwise.
Z: Set when the sign-extended data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
EXT
In this example, the high-order byte (bits 8 to 15) of AL is extended with FFH because the most
significant bit of the low-order byte data (80H) of AL is "1".
I S T N Z V C
– – – * * – –
× × × × × × 8 0 A
Before execution
× × × × F F 8 0 A
After execution
CCR × × × × ×T N Z V C
CCR × 1 0 × ×T N Z V C
AH AL AH AL
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152 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.41 EXTW (Sign Extend from Word Data to Long Word Data)
8.41 EXTW (Sign Extend from Word Data to Long Word Data)
Extend the low-order word data of A to long word data as a signed binary number.
● Assembler format:
EXTW
● Operation:
When bit15 of A=0, (AH) ← 0000H
When bit15 of A≠0, (AH) ← FFFFH
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the sign-extended data is "1", cleared otherwise.
Z: Set when the sign-extended data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
EXTW
In this example, AH (bits 16 to 31 of A) is extended with FFFFH because the most significant
bit of the word data (FF80H) of AL is "1".
I S T N Z V C
– – – * * – –
× × × × F F 8 0 A
Before execution
F F F F F F 8 0 A
After execution
CCR × × × × ×T N Z V C
CCR × 1 0 × ×T N Z V C
AH AL AH AL
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.42 FILS, FILSI (Fill String Byte)
8.42 FILS, FILSI (Fill String Byte)
Transfer the contents of AL to the RW0-byte area that starts from the address whose high-order eight bits are specified by the bank register specified by <bank> and whose low-order 16 bits are specified by the contents of AH.
If RW0 is equal to zero, transfer is not performed. If an interrupt occurs during the execution
of the instruction, the execution of the instruction is suspended. After the interrupt has been
handled, the execution of the instruction is resumed.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. If <bank> is
omitted, DTB is assumed.
● Assembler format:
FILS [<bank>]
FILSI [<bank>]
● Operation:
While RW0 ≠ 0, the following operation is repeated:
((AH)) ← (AL) [Byte transfer], (AH) ← (AH)+1,
(RW0) ← (RW0)–1
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the transferred data is "1", cleared otherwise.
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
Byte count: 2
Cycle count: (RW0 + 1) / 2
Odd address correction: 1
I S T N Z V C
– – – * * – –
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154 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.42 FILS, FILSI (Fill String Byte)
● Example:
FILS
In this example, the low-order byte data (E5H) of AL is transferred from the address
(94BC00H) specified by DTB and AH to the number of bytes (0100H) specified by RW0.
0 1 0 0RW0
Before execution
Memory
× × 94BD00× × 94BCFF× × 94BCFE
9 4DTB
× × 94BC02× × 94BC01
AH
B C 0 0 0 0 E 5 AH AL
× × 94BC00
0 0 0 0RW0
Memory
× × 94BD00E 5 94BCFFE 5 94BCFE
9 4DTB
E 5 94BC02E 5 94BC01
AH
B D 0 0 0 0 E 5 AH AL
E 5 94BC00
After execution
... ... ... ...
CCR × × × × ×T N Z V C
CCR × 1 0 × ×T N Z V C
A A
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.43 FILSW, FILSWI (Fill String Word)
8.43 FILSW, FILSWI (Fill String Word)
Transfer the contents of AL to the RW0-word area that starts from the address whose high-order eight bits are specified by the bank register specified by <bank> and whose low-order 16 bits are specified by the contents of AH.
If RW0 is equal to zero, transfer is not performed. If an interrupt occurs during the execution
of the instruction, the execution of the instruction is suspended. After the interrupt has been
handled, the execution of the instruction is resumed.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. If <bank> is
omitted, DTB is assumed.
● Assembler format:
FILSW [<bank>]
FILSWI [<bank>]
● Operation:
While RW0 ≠ 0, the following operation is repeated:
((AH)) ← (AL) [Word transfer], (AH) ← (AH)+2,
(RW0) ← (RW0)–1
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the transferred data is "1", cleared otherwise.
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
Byte count: 2
Cycle count: 1 cycle when RW0 is zero; RW0 cycle(s) in all other cases
Odd address correction: 1
I S T N Z V C
– – – * * – –
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156 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.43 FILSW, FILSWI (Fill String Word)
● Example:
FILSW ADB
In this example, the word data (E55EH) of AL is transferred from the address (49ABFEH)
specified by ADB and AH to the number of words (0080H) specified by RW0.
0 0 8 0RW0
Before execution
Memory
× × 49ACFF× × 49ACFE× × 49ACFD
4 9ADB
× × 49AC00× × 49ABFF
AH
A B F E E 5 5 EAH AL
× × 49ABFE
0 0 0 0RW0
Memory
× × 49ACFF× × 49ACFEE 5 49ACFD
4 9ADB
5 E 49AC00E 5 49ABFF
AH
A C F E E 5 5 EAH AL
5 E 49ABFE
After execution
... ... ... ...
CCR × × × × ×T N Z V C
CCR × 0 0 × ×T N Z V C
A A
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.44 INC (Increment Byte Data (Address Specification))
8.44 INC (Increment Byte Data (Address Specification))
Increment the byte data specified by the operand by one and restore the result in the operand.
● Assembler format:
INC ear INC eam
● Operation:
(Operand) ← (Operand)+1 [Byte increment]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Unchanged
● Byte count and cycle count:
● Example:
INC R0
In this example, "1" is added to the byte data (FFH) of R0.
I S T N Z V C
– – – * * * –
Operand ear eam
Byte count 2 2+
Cycle count 1 3
Before execution
F FR0
After execution
0 0R0
CCR × × × × ×T N Z V C
CCR × 0 1 0 ×T N Z V C
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158 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.45 INCL (Increment Long Word Data)
8.45 INCL (Increment Long Word Data)
Increment the long word data specified by the operand by one and restore the result in the operand.
● Assembler format:
INCL ear INCL eam
● Operation:
(Operand) ← (Operand)+1 [Long word increment]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Unchanged
● Byte count and cycle count:
● Example:
INCL RL0
In this example, "1" is added to the long word data (7FFFFFFFH) of RL0.
I S T N Z V C
– – – * * * –
Operand ear eam
Byte count 2 2+
Cycle count 2 4
Odd address correction 0 2
7 F F F F F F FRL0
Before execution
8 0 0 0 0 0 0 0RL0
After execution
CCR × × × × ×T N Z V C
CCR × 1 0 1 ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.46 INCW (Increment Word Data)
8.46 INCW (Increment Word Data)
Increment the word data specified by the operand by one and restore the result in the operand.
● Assembler format:
INCW ear INCW eam
● Operation:
(Operand) ← (Operand)+1 [Word increment]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * * –
Operand ear eam
Byte count 2 2+
Cycle count 1 3
Odd address correction 0 2
F2MC-16FX Family
160 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.46 INCW (Increment Word Data)
● Example:
INCW @RW0+
In this example, "1" is added to the word data (0101H) at the address (0354H) specified by the
operand (@RW0+).
Before execution
Memory
× × 0357× × 03560 1 0355
0 3 5 4 RW0
RW0
After execution
0 3 5 6 RW0
0 1 0354
Memory
× × 0357× × 03560 1 0355
RW0
0 2 0354
CCR × × × × ×T N Z V C
CCR × 0 0 0 ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.47 INT (Software Interrupt)
8.47 INT (Software Interrupt)
Cause a branch to the interrupt handling routine at the specified address in the bank 0FFH. By executing the RETI instruction in the interrupt handling routine
to which control has been transferred, control returns to the instruction following this instruction.
● Assembler format:
INT addr16
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP)) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB) [DPR and ADB are saved as a set, DPR as
the high-order byte and ADB as the low-
order byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB) [DTB and PCB are saved as a set, DTB as the
high-order byte and PCB as the low-order
byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (PC+3), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0, (PCB) ← 0FFH, (PC) ← addr16
● CCR:
I: Cleared
S: Set
T, N, Z, V, and C: Unchanged
● Byte count and cycle count:
Byte count: 3
Cycle count: 8
Odd address correction: 6
I S T N Z V C
R S – – – – –
F2MC-16FX Family
162 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.47 INT (Software Interrupt)
● Example:
INT 020F2H
In this example, a branch is caused to the interrupt handling routine at address FF20F2H. FFH
is set to PCB.
7 7 6 6PC
9 9DTB
F F E E D D C CAH
Memory038000
× × 037FFF× × 037FFE
SSP
8 8PCB
B BDPR
A AADB
0 3ILM
1 0RP
0 3SSB
8 0 0 0SSP
× × 037FFD× × 037FFC× × 037FFB× × 037FFA× × 037FF9× × 037FF8× × 037FF7× × 037FF6× × 037FF5× × 037FF4
Before execution
2 0 F 2PC
9 9DTB
F F E E D D C C
Memory038000
F F 037FFFE E 037FFE
SSP
F FPCB
B BDPR
A AADB
0 3ILM
1 0RP
0 3SSB
7 F F 4 SSP
D D 037FFDC C 037FFCB B 037FFBA A 037FFA9 9 037FF98 8 037FF87 7 037FF76 9 037FF67 0 037FF58 5 037FF4
After execution
CCR CCR
I S T N Z V C0 1 0 0 1 0 1
I S T N Z V C0 0 0 0 1 0 1
AL AH ALA A
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.48 INT (Software Interrupt (Vector Specification))
8.48 INT (Software Interrupt (Vector Specification))
Cause a branch to the interrupt handling routine pointed to by the interrupt vector specified by the operand.
● Assembler format:
INT #vct8
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB) [DPR and ADB are saved as a set, DPR as
the high-order byte and ADB as the low-
order byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB) [DTB and PCB are saved as a set, DTB as the
high-order byte and PCB as the low-order
byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (PC+2), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0, (PCB) ← Vector address (High-order byte)
(PC) ← Vector address (Low-order word)
● CCR:
I: Cleared
S: Set
T, N, Z, V, and C: Unchanged
● Byte count and cycle count:
Byte count: 2
Cycle count: 12
Odd address correction: 6
I S T N Z V C
R S – – – – –
F2MC-16FX Family
164 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.48 INT (Software Interrupt (Vector Specification))
● Example:
INT #11
In this example, a branch is caused to the interrupt handling routine specified by the interrupt
vector of #11.
7 7 6 6PC
9 9DTB
CCR
038000× × 037FFF× × 037FFE
SSP
8 8PCB
B BDPR
A AADB
0 2ILM
1 5RP
0 3SSB
8 0 0 0SSP
× × 037FFD× × 037FFC× × 037FFB× × 037FFA× × 037FF9× × 037FF8× × 037FF7× × 037FF6× × 037FF5× × 037FF4
Before execution
E 7 9 5PC
9 9DTB
CCR
F F 037FFFE E 037FFE
SSP
8 9PCB
B BDPR
A AADB
0 2ILM
1 5RP
0 3SSB
7 F F 4SSP
D D 037FFDC C 037FFCB B 037FFBA A 037FFA9 9 037FF98 8 037FF87 7 037FF76 8 037FF65 5 037FF58 5 037FF4
After execution
Memory
8 9 FFFFD2E 7 FFFFD19 5 FFFFD0
Memory
8 9 FFFFD2E 7 FFFFD19 5 FFFFD0
I S T N Z V C0 1 0 0 1 0 1
I S T N Z V C0 0 0 0 1 0 1
F F E E D D C C F F E E D D C C
AH AL AH ALA A
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.49 INT9 (Software Interrupt)
8.49 INT9 (Software Interrupt)
Cause a branch to the interrupt handling routine pointed to by the vector. By executing the RETI instruction in the interrupt handling routine to which control has been transferred, control returns to the instruction following this instruction.
● Assembler format:
INT9
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP)) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB) [DPR and ADB are saved as a set, DPR as
the high-order byte and ADB as the low-
order byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB) [DTB and PCB are saved as a set, DTB as the
high-order byte and PCB as the low-order
byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (PC+1), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0, (PCB) ← Vector address (High-order byte)
(PC) ← Vector address (Low-order word)
● CCR:
I: Cleared
S: Set
T, N, Z, V, and C: Unchanged
● Byte count and cycle count:
Byte count: 1
Cycle count: 12
Odd address correction: 6
I S T N Z V C
R S – – – – –
F2MC-16FX Family
166 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.49 INT9 (Software Interrupt)
● Example:
INT9
In this example, a branch is caused to the interrupt handling routine specified by the interrupt
vector of #9.
9 9 A APC
7 7DTB
038000× × 037FFF× × 037FFE
SSP
8 8PCB
5 5DPR
6 6ADB
0 2ILM
1 5RP
0 3SSB
8 0 0 0 SSP
× × 037FFD× × 037FFC× × 037FFB× × 037FFA× × 037FF9× × 037FF8× × 037FF7× × 037FF6× × 037FF5× × 037FF4
Before execution
E 7 9 5PC
7 7DTB
1 1 037FFF2 2 037FFE
SSP
8 9PCB
5 5DPR
6 6ADB
0 2ILM
1 5RP
0 3SSB
7 F F 4 SSP
3 3 037FFD4 4 037FFC5 5 037FFB6 6 037FFA7 7 037FF98 8 037FF89 9 037FF7A B 037FF65 5 037FF58 5 037FF4
After execution
Memory
8 9 FFFFDAE 7 FFFFD99 5 FFFFD8
Memory
8 9 FFFFDAE 7 FFFFD99 5 FFFFD8
1 1 2 2 3 3 4 4 1 1 2 2 3 3 4 4
CCR CCR
I S T N Z V C0 1 0 0 1 0 1
I S T N Z V C0 0 0 0 1 0 1
AH AL AH ALA A
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.50 INTP (Software Interrupt)
8.50 INTP (Software Interrupt)
Cause a branch to the interrupt handling routine at the 24-bit physical address specified by the operand. Any address in the entire 16Mbyte space can be specified. By executing the RETI instruction in the interrupt handling routine to which control has been transferred, control returns to the instruction following this instruction.
● Assembler format:
INTP addr24
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP)) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB) [DPR: High-order byte, ADB: Low-order byte]
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB) [DTB: High-order byte, PCB: Low-order byte]
(SSP) ← (SSP)–2, ((SSP)) ← (PC+4), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0, (PCB) ← Most significant byte of addr24,
(PC) ← Low-order word of addr24
● CCR:
I: Cleared
S: Set
T, N, Z, V, and C: Unchanged
● Byte count and cycle count:
Byte count: 4
Cycle count: 8
Odd address correction: 6
I S T N Z V C
R S – – – – –
F2MC-16FX Family
168 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.50 INTP (Software Interrupt)
● Example:
INTP 0C8F220H
In this example, a branch is caused to the interrupt handling routine at address C8F220H. C8H
is set to PCB.
9 9 A APC
7 7DTB
1 1 2 2 3 3 4 4
Memory038000
× × 037FFF× × 037FFE
SSP
8 8PCB
5 5DPR
6 6ADB
0 3ILM
1 0RP
0 3SSB
8 0 0 0SSP
× × 037FFD× × 037FFC× × 037FFB× × 037FFA× × 037FF9× × 037FF8× × 037FF7× × 037FF6× × 037FF5× × 037FF4
Before execution
F 2 2 0PC
7 7DTB
Memory038000
1 1 037FFF2 2 037FFE
SSP
C 8PCB
5 5DPR
6 6ADB
0 3ILM
1 0RP
0 3SSB
7 F F 4 SSP
3 3 037FFD4 4 037FFC5 5 037FFB6 6 037FFA7 7 037FF98 8 037FF89 9 037FF7A E 037FF67 0 037FF58 5 037FF4
After execution
1 1 2 2 3 3 4 4
CCR CCR
I S T N Z V C0 1 0 0 1 0 1
I S T N Z V C0 0 0 0 1 0 1
AH AL AH ALA A
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CHAPTER 8 DETAILED INSTRUCTIONS8.51 JCTX (Jump Context)
8.51 JCTX (Jump Context)
Restore register contents or an address saved in memory.
● Assembler format:
JCTX @A
● Operation:
(temp) ← (AL)
(PS) ← ((temp)) : (temp) ← (temp)+2
(PC) ← ((temp)) : (temp) ← (temp)+2
(DTB), (PCB) ← ((temp)) : (temp) ← (temp)+2
(DPR), (ADB) ← ((temp)) : (temp) ← (temp)+2
(AL) ← ((temp)) : (temp) ← (temp)+2
(AH) ← ((temp))
● CCR:
I: Stores bit 6 of the address indicated by AL.
S: Stores bit 5 of the address indicated by AL.
T: Stores bit 4 of the address indicated by AL.
N: Stores bit 3 of the address indicated by AL.
Z: Stores bit 2 of the address indicated by AL.
V: Stores bit 1 of the address indicated by AL.
C: Stores bit 0 of the address indicated by AL.
● Byte count and cycle count:
Byte count: 1
Cycle count: 23 cycles when the content of RP changes; 6 cycles in all other cases
I S T N Z V C
* * * * * * *
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CHAPTER 8 DETAILED INSTRUCTIONS8.51 JCTX (Jump Context)
● Example:
JCTX @A
In this example, a context is returned from the address (09E020H) specified by DTB and AL.
× × × ×PC
0 9DTB
Memory09E02C
C B 09E02B7 5 09E02A
AL
× ×PCB
× ×DPR
× ×ADB
× ×ILM
× ×RP
0 2 09E0295 0 09E0280 8 09E027C E 09E0268 0 09E0255 0 09E0248 8 09E0230 1 09E022F 6 09E0218 A 09E020
Before execution
8 8 0 1PC
8 0DTB
5 0PCB
0 8DPR
C EADB
0 7ILM
1 6RP
Memory09E02C
C B 09E02B7 5 09E02A0 2 09E0295 0 09E0280 8 09E027C E 09E0268 0 09E0255 0 09E0248 8 09E0230 1 09E022F 6 09E0218 A 09E020
After execution
CCR CCR
I S T N Z V C0 0 0 1 0 1 0
I S T N Z V C
× × × × × × ×
× × × × E 0 2 0 C B 7 5 0 2 5 0
AH AL AH ALA A
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CHAPTER 8 DETAILED INSTRUCTIONS8.52 JMP (Jump Destination Address)
8.52 JMP (Jump Destination Address)
Read the word data from the address specified by the operand and cause a branch to the address specified by the word data.
● Assembler format:
JMP @A JMP addr16
JMP @ear JMP @eam
● Operation:
(PC) ← (Operand)
● CCR:
None of the flags is changed.
● Byte count and cycle count:
● Example:
JMP @@ RW0+2
In this example, a branch is caused to the address (DB80H) specified by the word data at the
address (A0A2H) specified by the operand (@RW0+2).
I S T N Z V C
– – – – – – –
Operand @A @ear @eam addr16
Byte count 1 2 2+ 3
Cycle count 2 2 4 2
Odd address correction 0 0 1 0
Before execution
Memory
D B A0A38 0 A0A2× × A0A1
E 0 0 0 PC
RW0+2
× × A0A0
A 0 A 0 RW0
After execution
Memory
D B A0A38 0 A0A2× × A0A1
D B 8 0 PC
RW0+2
× × A0A0
A 0 A 0 RW0
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CHAPTER 8 DETAILED INSTRUCTIONS8.53 JMPP (Jump Destination Physical Address)
8.53 JMPP (Jump Destination Physical Address)
If the operand is addr24, this instruction causes a branch to the physical address specified by addr24. If the operand is @ea, the instruction causes a branch to the physical address specified by the contents of the operand.
● Assembler format:
(1) JMPP addr24
(2) JMPP @ear JMPP @eam
● Operation:
(1): (PC) ← Low-order word of addr24
(PCB) ← Most significant byte of addr24
(2): (PC) ← (ea) [Word transfer]
(PCB) ← (ea+2) [Byte transfer]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
● Example:
JMPP 0FFC850H
In this example, a branch is caused to FFC850H. FFH is set to PCB.
I S T N Z V C
– – – – – – –
Operand addr24 @ear @eam
Byte count 4 2 2+
Cycle count 2 3 5
Odd address correction 0 0 1
1 2 4 8 PC
Before execution3 4PCB
C 8 5 0 PC
After executionF FPCB
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CHAPTER 8 DETAILED INSTRUCTIONS8.54 LINK (Link and Create New Stack Frame)
8.54 LINK (Link and Create New Stack Frame)
Store the current value of the frame pointer (RW3) in a stack and set a new frame pointer. This allows an area for a new local variable to be reserved. This instruction is used before a function is called.
● Assembler format:
LINK #imm8
● Operation:
(SP) ← (SP)–2 ; ((SP)) ← (RW3) ; (RW3) ← (SP) ; (SP) ← (SP)–imm8
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 2
Cycle count: 2
Odd address correction: 1
● Example:
LINK #20H
In this example, RW3 is pushed to the stack specified by SP. Then, the 8-bit immediate data
(20H) is subtracted from the SP value (E020H).
I S T N Z V C
– – – – – – –
Before execution
Memory
× × E022
E 0 2 2SP
SP
A 0 4 6RW3
After execution
Memory
A 04 6 E020
E 0 0 0SP
SP × × E000
E 0 2 0RW3
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CHAPTER 8 DETAILED INSTRUCTIONS8.55 LSL (Logical Shift Byte Data of Accumulator to Left)
8.55 LSL (Logical Shift Byte Data of Accumulator to Left)
Shift the least significant byte data of the accumulator (A) to the left by the number of bits specified by the second operand.
The least significant bit of A is set to "0". The bit last shifted out from the most significant bit
of the least significant byte data for A is stored in the carry flag (C).
● Assembler format:
LSL A,R0
● Operation:
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the shifting result is "1", cleared otherwise.
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit last shifted out from the MSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
Byte count: 2
Cycle count: 1
I S T N Z V C
– – – * * – *
MSB LSBC A
0
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CHAPTER 8 DETAILED INSTRUCTIONS8.55 LSL (Logical Shift Byte Data of Accumulator to Left)
● Example:
LSL A,R0
In this example, the low-order byte data (FEH) of AL is shifted to the left by the number of bits
(2 bits) specified by R0.
CCR
Before execution
CCR
After execution
0 2R0 0 2R0
× × × × × × F F A × × × × × × F C A
× × × × ×T N Z V C
× 1 0 × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.56 LSLL (Logical Shift Long Word Data of Accumulator to Left)
8.56 LSLL (Logical Shift Long Word Data of Accumulator to Left)
Shift the long word data of the accumulator (A) to the left by the number of bits specified by the second operand.
The least significant bit of the accumulator (A) is set to "0". The bit last shifted out from the
most significant bit is stored in the carry flag (C).
● Assembler format:
LSLL A,R0
● Operation:
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the shifting result is "1", cleared otherwise.
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit last shifted out from the MSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
Byte count: 2
Cycle count: 1
I S T N Z V C
– – – * * – *
MSB LSBC A
0
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CHAPTER 8 DETAILED INSTRUCTIONS8.56 LSLL (Logical Shift Long Word Data of Accumulator to Left)
● Example:
LSLL A,R0
In this example, the long word data (33333333H) of the accumulator (A) is shifted to the left by
the number of bits (2 bits) specified by R0.
3 3 3 3 3 3 3 3A
Before execution
C C C C C C C C A
After execution
0 2R0 0 2R0
CCR × × × × ×T N Z V C
CCR × 1 0 × 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.57 LSLW (Logical Shift Word Data of Accumulator to Left)
8.57 LSLW (Logical Shift Word Data of Accumulator to Left)
Shift the low-order word data of the accumulator (A) to the left by one bit. The least significant bit of the accumulator (A) is set to "0".
The least significant bit of the accumulator (A) is set to "0". The bit shifted out from the most
significant bit of the low-order word data for the accumulator (A) is stored in the carry flag (C).
● Assembler format:
LSLW A/SHLW A
● Operation:
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the shifting result is "1", cleared otherwise.
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit shifted out from the MSB of A.
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
LSLW A
In this example, the word data (AA55H) of AL is shifted to the left by one bit.
I S T N Z V C
– – – * * – *
MSB LSBALC
0
Before execution After execution
× × × × A A 5 5 A × × × × 5 5 A A A
CCR × × × × ×T N Z V C
CCR × 0 0 × 1
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.58 LSLW (Logical Shift Word Data of Accumulator to Left)
8.58 LSLW (Logical Shift Word Data of Accumulator to Left)
Shift the low-order word data of the accumulator (A) to the left by the number of bits specified by the second operand.
The least significant bit of the accumulator (A) is set to "0". The bit last shifted out from the
most significant bit of the low-order word data for the accumulator (A) is stored in the carry
flag (C).
● Assembler format:
LSLW A,R0
● Operation:
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the shifting result is "1", cleared otherwise.
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit last shifted out from the MSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
Byte count: 2
Cycle count: 1
I S T N Z V C
– – – * * – *
MSB LSBALC
0
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CHAPTER 8 DETAILED INSTRUCTIONS8.58 LSLW (Logical Shift Word Data of Accumulator to Left)
● Example:
LSLW A,R0
In this example, the word data (AA55H) of AL is shifted to the left by the number of bits (4
bits) specified by R0.
× × × × A A 5 5 A
Before execution
× × × × A 5 5 0 A
After execution
0 4R0 0 4R0
CCR × × × × ×T N Z V C
CCR × 1 0 × 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.59 LSR (Logical Shift Byte Data of Accumulator to Right)
8.59 LSR (Logical Shift Byte Data of Accumulator to Right)
Shift the least significant byte data of the accumulator (A) to the right by the number of bits specified by the second operand.
The most significant bit of the least significant byte of the accumulator (A) is set to "0". The
bit last shifted out from the least significant bit is stored in the carry flag (C).
● Assembler format:
LSR A,R0
● Operation:
● CCR:
I and S: Unchanged
T: Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is "0".
N: Set when the MSB of the shifting result is "1", cleared otherwise.
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
Byte count: 2
Cycle count: 1
I S T N Z V C
– – * * * – *
MSB LSB CAL
0
T1
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CHAPTER 8 DETAILED INSTRUCTIONS8.59 LSR (Logical Shift Byte Data of Accumulator to Right)
● Example:
LSR A,R0
In this example, the low-order byte data (FFH) of AL is shifted to the right by the number of
bits (5 bits) specified by R0.
× × × × × × F F A
Before execution
× × × × × × 0 7 A
After execution
0 5 R0 0 5 R0
CCR × × × × ×T N Z V C
CCR 1 1 0 × 1
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.60 LSRL (Logical Shift Long Word Data of Accumulator to
Right)
8.60 LSRL (Logical Shift Long Word Data of Accumulator to Right)
Shift the long word data of the accumulator (A) to the right by the number of bits specified by the second operand.
The most significant bit of the accumulator (A) is set to "0". The bit last shifted out from the
least significant bit of the accumulator (A) is stored in the carry flag (C).
● Assembler format:
LSRL A,R0
● Operation:
● CCR:
I and S: Unchanged
T: Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N: Set when the MSB of the shifting result is "1", cleared otherwise.
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
Byte count: 2
Cycle count: 1
I S T N Z V C
– – * * * – *
MSB LSB CA
0
T1
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CHAPTER 8 DETAILED INSTRUCTIONS8.60 LSRL (Logical Shift Long Word Data of Accumulator to Right)
● Example:
LSRL A,R0
In this example, the long word data (33333333H) of the accumulator (A) is shifted to the right
by the number of bits (16 bits) specified by R0.
3 3 3 3 3 3 3 3 A
Before execution
0 0 0 0 3 3 3 3 A
After execution
1 0R0 1 0R0
CCR × × × × ×T N Z V C
CCR 1 0 0 × 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.61 LSRW (Logical Shift Word Data of Accumulator to Right)
8.61 LSRW (Logical Shift Word Data of Accumulator to Right)
Shift the low-order word data of the accumulator (A) to the right by one bit.
The most significant bit of the low-order word data of the accumulator (A) is set to "0". The
least significant bit is stored in the carry flag (C).
● Assembler format:
LSRW A/SHRW A
● Operation:
● CCR:
I and S: Unchanged
T: Stores the OR of the shifted-out data from the carry and the old T flag value.
N: Cleared
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit shifted out from the LSB of A.
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
I S T N Z V C
– – * R * – *
MSB LSBAL C
0
T1
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CHAPTER 8 DETAILED INSTRUCTIONS8.61 LSRW (Logical Shift Word Data of Accumulator to Right)
● Example:
LSRW A
In this example, the word data (AAAAH) of AL is shifted to the right by one bit.
× × × × A A A A A
Before execution
× × × × 5 5 5 5 A
After execution
CCR 1 × × × 0
T N Z V C
CCR 1 0 0 × 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.62 LSRW (Logical Shift Word Data of Accumulator to Right)
8.62 LSRW (Logical Shift Word Data of Accumulator to Right)
Shift the low-order word data of the accumulator (A) to the right by the number of bits specified by the second operand.
The most significant bit of the low-order word data of the accumulator (A) is set to "0". The
bit last shifted out from the least significant bit is stored in the carry flag (C).
● Assembler format:
LSRW A,R0
● Operation:
● CCR:
I and S: Unchanged
T: Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N: Set when the MSB of the shifting result is "1", cleared otherwise.
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
Byte count: 2
Cycle count: 1
I S T N Z V C
– – * * * – *
MSB LSBAL C
0
T1
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CHAPTER 8 DETAILED INSTRUCTIONS8.62 LSRW (Logical Shift Word Data of Accumulator to Right)
● Example:
LSRW A,R0
In this example, the word data (AAAAH) of AL is shifted to the right by the number of bits (12
bits) specified by R0.
× × × × A A A A A
Before execution
× × × × 0 0 0 A A
After execution
0 CR0 0 CR0
CCR × × × × ×T N Z V C
CCR 1 0 0 × 1
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.63 MOV (Move Byte Data from Source to Accumulator)
8.63 MOV (Move Byte Data from Source to Accumulator)
The value in AL is transferred to AH. And then 00H is transferred to the upper
bytes of AL; the byte data in the second operand is transferred to the lower bytes of AL.
If the second operand is @A, transfer to AH is not performed.
● Assembler format:
MOV A,#imm8 MOV A,Ri
MOV A,@A MOV A,dir
MOV A,@RLi + disp8 MOV A,addr16
MOV A,io MOV A,brg1
MOV A,eam MOV A,ear
● Operation:
(A) ← (Second operand) [Byte transfer]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the transferred data is "1", cleared otherwise.
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * – –
First operand A A A A A A A A A A
Second operand #imm8 @A @RLi+disp8 io addr16 Ri dir ear eam brg1
Byte count 2 2 3 2 3 1 2 2 2+ 2
Cycle count 1 1 1 1 1 1 1 1 1 1
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CHAPTER 8 DETAILED INSTRUCTIONS8.63 MOV (Move Byte Data from Source to Accumulator)
● Example:
MOV A,0092H
In this example, the word data (A046H) of AL is transferred to AH, and then the byte data
(71H) at address 0092H is transferred to AL.
× × × × A 0 4 6 A
Before execution
A 0 4 6 0 0 7 1 A
After execution
Memory
7 1 0092
Memory
7 1 0092
CCR × × × × ×T N Z V C
CCR × 0 0 × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.64 MOV (Move Byte Data from Accumulator to Destination)
8.64 MOV (Move Byte Data from Accumulator to Destination)
Transfer the least significant byte data of the accumulator (A) to the address specified by the first operand.
● Assembler format:
MOV dir,A MOV Ri,A
MOV @RLi+disp8,A MOV io,A
MOV addr16,A MOV brg2,A
MOV ear,A MOV eam,A
● Operation:
(First operand) ← (A) [Byte transfer]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the transferred data is "1", cleared otherwise.
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * – –
First operand dir @RLi+disp8 addr16 io Ri ear eam brg2
Second operand A A A A A A A A
Byte count 2 3 3 2 1 2 2+ 2
Cycle count 1 1 1 1 1 1 1 1
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CHAPTER 8 DETAILED INSTRUCTIONS8.64 MOV (Move Byte Data from Accumulator to Destination)
● Example:
MOV R1,A
In this example, the low-order byte data (32H) of AL is transferred to R1.
× × × × 4 9 3 2 A
Before execution
× × × × 4 9 3 2A
After execution
× ×R1 3 2R1CCR × × × × ×T N Z V C
CCR × 0 0 × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.65 MOV (Move Byte Immediate Data to Destination)
8.65 MOV (Move Byte Immediate Data to Destination)
Transfer the 8-bit immediate data specified by the second operand to the address specified by the first operand.
When the first operand is @PC + disp16, the data is transferred to the "address of the location
containing the machine instruction for the MOV instruction + 4 + rel", not the "address of the
location containing the machine instruction for the instruction following the MOV instruction +
rel".
● Assembler format:
MOV RP,#imm8 MOV ILM,#imm8
MOV io,#imm8 MOV dir,#imm8
MOV ear,#imm8 MOV eam,#imm8
● Operation:
(First operand) ← imm8
● CCR:
I, S, and T: Unchanged
N: Unchanged if the data is transferred to a register other than the general-purpose
registers. If the data is transferred to the general-purpose register, N is set when
the MSB of the transferred data is "1", cleared otherwise.
Z: Unchanged if the data is transferred to a register other than the general-purpose
registers. If the data is transferred to the general-purpose register, Z is set when the
transferred data is zero, cleared otherwise.
V and C: Unchanged
If the data is transferred to a general-
purpose registers (R0 to R7) or bank
register
If the data is transferred to a register other
than the general-purpose registers (R0 to
R7) and the bank register
I S T N Z V C I S T N Z V C
– – – * * – – – – – – – – –
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CHAPTER 8 DETAILED INSTRUCTIONS8.65 MOV (Move Byte Immediate Data to Destination)
● Byte count and cycle count:
● Example:
MOV 009FH,#22H
In this example, the 8-bit immediate data (22H) is transferred to address 009FH in bytes.
First operand RP ILM dir io ear eam
Second operand #imm8 #imm8 #imm8 #imm8 #imm8 #imm8
Byte count 2 2 3 3 3 3+
Cycle count19 when the content of RP
changes; 4 in all other cases1 1 1 1 1
× × × × × × × × A
Before execution
× × × × × × × × A
After execution
Memory Memory
7 1 009F 2 2 009F
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.66 MOV (Move Byte Data from Source to Destination)
8.66 MOV (Move Byte Data from Source to Destination)
Transfer the byte data specified by the second operand to the first operand.
MOV Ri, #imm8, described below, is an instruction contained in the basic page map (see C.1
Table C.2-1 ), with code different from that contained in MOV ear, #imm8.
● Assembler format:
MOV Ri,#imm8
MOV Ri,ear MOV Ri,eam
MOV ear,Ri MOV eam,Ri
● Operation:
(First operand) ← (Second operand) [Byte transfer]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the transferred data is "1", cleared otherwise.
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * – –
First operand Ri Ri Ri ear eam
Second operand #imm8 ear eam Ri Ri
Byte count 2 2 2+ 2 2+
Cycle count 1 1 1 1 1
F2MC-16FX Family
196 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.66 MOV (Move Byte Data from Source to Destination)
● Example:
MOV R3,@RW0
In this example, the byte data (71H) at the address (E001H) specified by the second operand
(@RW0) is transferred to R3.
Before execution After execution
Memory
7 1 E001
E 0 0 1RW0
× ×R3
E 0 0 1RW0
7 1R3
Memory
7 1 E001
CCR × × × × ×T N Z V C
CCR × × 0 0 ×T N Z V C
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.67 MOV (Move Byte Data from AH to Memory)
8.67 MOV (Move Byte Data from AH to Memory)
Transfer the low-order byte data of AH to the memory location specified by the contents of AL.
● Assembler format:
MOV @AL,AH
● Operation:
((AL)) ← (AH) [Byte transfer]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the transferred data is "1", cleared otherwise.
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
Byte count: 2
Cycle count: 1
● Example:
MOV @AL,AH
In this example, the low-order byte data (22H) of AH is transferred to the address (E084H)
specified by the word data of AL in bytes.
I S T N Z V C
– – – * * – –
0 1 2 2 E 0 8 4 A
Before execution
0 1 2 2 E 0 8 4 A
After execution
Memory Memory
7 1 E084 2 2 E084
CCR × × × × ×T N Z V C
CCR × 0 0 × ×T N Z V C
AH AL AH AL
F2MC-16FX Family
198 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.68 MOVB (Move Bit Data from Bit Address to Accumulator)
8.68 MOVB (Move Bit Data from Bit Address to Accumulator)
The value in AL is transferred to AH. And then transfer zeros to bits 8 to 15 of the accumulator (A). 00H is transferred to bits 0 to 7 of A if the bit of the
address specified by the second operand is equal to 00H and FFH is transferred
if the bit is equal to "1".
● Assembler format:
MOVB A,addr16:bp
MOVB A,dir:bp
MOVB A,io:bp
● Operation:
If (Second operand)=0 : (A) ← 00H [Byte transfer]
If (Second operand)=1 : (A) ← FFH [Byte transfer]
● CCR:
I, S, and T: Unchanged
N: Set when the transferred bit is "1", cleared when "0".
Z: Set when the transferred bit is "0", cleared when "1".
V and C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * – –
First operand A A A
Second operand addr16:bp dir:bp io:bp
Byte count 4 3 3
Cycle count 1 1 1
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.68 MOVB (Move Bit Data from Bit Address to Accumulator)
● Example:
MOVB A,32H:3
In this example, 00FFH is set to AL because bit 3 of the byte data (7FH) at address 32H is equal
to "1".
× × × × × × × × A
Before execution
× × × × 0 0 F F A
After execution
Memory
× ×
Memory
7 F 0032× ×
× ×7 F 0032× ×
CCR × × × × ×T N Z V C
CCR × 1 0 × ×T N Z V C
AH AL AH AL
F2MC-16FX Family
200 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.69 MOVB (Move Bit Data from Accumulator to Bit Address)
8.69 MOVB (Move Bit Data from Accumulator to Bit Address)
Transfer bit data 0 to the bit address specified by the first operand if the least significant byte data of the accumulator (A) is 00H.
Bit data 1 is transferred to the bit address specified by the first operand if the least significant byte data of A is not 00H.
● Assembler format:
MOVB addr16:bp,A
MOVB dir:bp,A
MOVB io:bp,A
● Operation:
If the byte data of (A) is 00H : (First operand) b=0 [Bit transfer]
If the byte data of (A) is not 00H : (First operand) b=1 [Bit transfer]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the byte data for A is "1", cleared otherwise.
Z: Set when the byte data of A is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * – –
First operand addr16:bp dir:bp io:bp
Second operand A A A
Byte count 4 3 3
Cycle count 3 3 3
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.69 MOVB (Move Bit Data from Accumulator to Bit Address)
● Example:
MOVB 765FH: 7,A
In this example, bit 7 at address 765FH is set to "1" because the low-order byte data of AL is
not equal to 00H.
× × × × × × 0 1 A
Before execution
× × × × × × 0 1 A
After execution
Memory
× ×7 F 765F× ×
Memory
× ×F F 765F× ×
CCR × × × × ×T N Z V C
CCR × 0 0 × ×T N Z V C
AH AL AH AL
F2MC-16FX Family
202 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.70 MOVEA (Move Effective Address to Destination)
8.70 MOVEA (Move Effective Address to Destination)
Transfer the value specified by the second operand (effective address) to the first operand.
If a general-purpose register is specified by the second operand, the address of the general-
purpose register is transferred. If the destination (first operand) is the accumulator (A), the
value in AL before the address transfer is transferred to AH.
● Assembler format:
MOVEA A,ear MOVEA A,eam
MOVEA RWi,ear MOVEA RWi,eam
● Operation:
First operand ← ea [Word transfer]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
I S T N Z V C
– – – – – – –
First operand A A RWi RWi
Second operand ear eam ear eam
Byte count 2 2+ 2 2+
Cycle count 1 1 1 1
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.70 MOVEA (Move Effective Address to Destination)
● Example:
MOVEA RW2,@RW0+2
In this example, the address value (006BH) specified by the second operand (@RW0+2) is
transferred to RW2.
Before execution
× × × ×RW2
After execution
0 0 6 BRW2
0 0 6 9RW0 0 0 6 9RW0
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
F2MC-16FX Family
204 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.71 MOVL (Move Long Word Data from Source to Accumulator)
8.71 MOVL (Move Long Word Data from Source to Accumulator)
Transfer the long word data specified by the second operand to the accumulator (A).
● Assembler format:
MOVL A,#imm32
MOVL A,ear MOVL A,eam
● Operation:
(A) ← (Second operand) [Long word transfer]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the transferred data is "1", cleared otherwise.
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * – –
First operand A A A
Second operand #imm32 ear eam
Byte count 5 2 2+
Cycle count 2 2 2
Odd address correction 0 0 1
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CHAPTER 8 DETAILED INSTRUCTIONS8.71 MOVL (Move Long Word Data from Source to Accumulator)
● Example:
MOVL A,#0053FF64H
In this example, the 32-bit immediate data (0053FF64H) is transferred to the accumulator (A)
as long word data.
× × × × × × × ×A
Before execution
0 0 5 3 F F 6 4A
After execution
CCR × × × × ×T N Z V C
CCR × 0 0 × ×T N Z V C
AH AL AH AL
F2MC-16FX Family
206 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.72 MOVL (Move Long Word Data from Accumulator to Destination)
8.72 MOVL (Move Long Word Data from Accumulator to Destination)
Transfer the long word data of the accumulator (A) to the first operand.
● Assembler format:
MOVL ear,A MOVL eam,A
● Operation:
(First operand) ← (A) [Long word transfer]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the transferred data is "1", cleared otherwise.
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * – –
First operand ear eam
Second operand A A
Byte count 2 2+
Cycle count 2 2
Odd address correction 0 1
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CHAPTER 8 DETAILED INSTRUCTIONS8.72 MOVL (Move Long Word Data from Accumulator to
Destination)● Example:
MOVL RL1,A
In this example, the long word data (0197A024H) of the accumulator (A) is transferred to RL1.
Before execution After execution
0 1 9 7 A 0 2 4A 0 1 9 7 A 0 2 4A
× × × × × × × ×RL1 0 1 9 7 A 0 2 4RL1
CCR × × × × ×T N Z V C
CCR × 0 0 × ×T N Z V C
AH AL AH AL
F2MC-16FX Family
208 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.73 MOVN (Move Immediate Nibble Data to Accumulator)
8.73 MOVN (Move Immediate Nibble Data to Accumulator)
The value in AL is transferred to AH. And then 000H is transferred to the bit 4 to
bit 15 of AL; nibble data specified by the second operand is transferred to bit0 to bit3 of AL.
● Assembler format:
MOVN A,#imm4
● Operation:
(A) ← imm4 [Byte transfer]
● CCR:
I, S, and T: Unchanged
N: Cleared
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
MOVN A,#0FH
In this example, the word data (6207H) of AL is transferred to AH, and then the byte data
(0FH) with the 4-bit immediate data (FH) zero-extended is transferred to AL.
I S T N Z V C
– – – R * – –
× × × × 6 2 0 7 A
Before execution
6 2 0 7 0 0 0 F A
After execution
CCR × × × × ×T N Z V C
CCR × 0 0 × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.74 MOVS, MOVSI (Move String Byte with Increment)
8.74 MOVS, MOVSI (Move String Byte with Increment)
Transfer byte data from the address specified by AL in the space specified by <source bank> to the address specified by AH in the space specified by <destination bank>. The transfer is repeated the number of times specified by RW0, with the addresses being incremented each time.
The transfer is not performed if RW0 is equal to zero. Four types of registers PCB, DTB,
ADB, and SPB can be used as <destination bank> and <source bank>. By default, DTB is
assumed.
If an interrupt occurs during the transfer, the transfer is suspended to handle the interrupt. The
transfer is resumed after the interrupt has been handled.
● Assembler format:
MOVS [<destination bank>] [,<source bank>]
MOVSI [<destination bank>] [,<source bank>]
● Operation:
The following is repeated until RW0 becomes equal to zero:
((AH)) ← ((AL)) [Byte transfer]
(AH) ← (AH)+1, (AL) ← (AL)+1
(RW0) ← (RW0)–1
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 2
Cycle count: 1 cycle when RW0 is zero; RW0 cycles when RW0 is grayer
than 1 and the transfer area of source address and destination
address do not overlap; 2 × RW0 cycles in all other cases
Odd address correction: 1
I S T N Z V C
– – – – – – –
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CHAPTER 8 DETAILED INSTRUCTIONS8.74 MOVS, MOVSI (Move String Byte with Increment)
● Example:
MOVSI ADB,PCB
In this example, byte data is transferred from the address (FF0000H) specified by PCB and AL
to the address (018000H) specified by ADB and AH.
0 0 0 3RW0
Before execution
Memory
F C FF0003F D FF0002F E FF0001
F FPCB
× × 018002× × 018001
AH
8 0 0 0 0 0 0 0 AH AL
× × 018000
0 1ADB
F F FF0000AL
× × 018003
0 0 0 0RW0
After execution
Memory
F C FF0003F D FF0002F E FF0001
F FPCB
F D 018002F E 018001
AH
AH AL
F F 018000
0 1ADB
F F FF0000
AL
× × 018003
8 0 0 3 0 0 0 3
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.75 MOVSD (Move String Byte with Decrement)
8.75 MOVSD (Move String Byte with Decrement)
Transfer byte data from the address specified by AL in the space specified by <source bank> to the address specified by AH in the space specified by <destination bank>. The transfer is repeated the number of times specified by RW0, with the addresses being decremented each time.
The transfer is not performed if RW0 is equal to zero. Four types of registers PCB, DTB,
ADB, and SPB can be used as <destination bank> and <source bank>. By default, DTB is
assumed.
If an interrupt occurs during the transfer, the transfer is suspended to handle the interrupt. The
transfer is resumed after the interrupt has been handled.
● Assembler format:
MOVSD [<destination bank>] [,<source bank>]
● Operation:
The following is repeated until RW0 becomes equal to zero:
((AH)) ← ((AL)) [Byte transfer]
(AH) ← (AH)-1, (AL) ← (AL)-1
(RW0) ← (RW0)–1
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 2
Cycle count: 1 cycle when RW0 is zero; 2 × RW0 in all other cases
I S T N Z V C
– – – – – – –
F2MC-16FX Family
212 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.76 MOVSW, MOVSWI (Move String Word with Increment)
8.76 MOVSW, MOVSWI (Move String Word with Increment)
Transfer word data from the address specified by AL in the space specified by <source bank> to the address specified by AH in the space specified by <destination bank>. The transfer is repeated the number of times specified by RW0, with the addresses being incremented each time.
The transfer is not performed if RW0 is equal to zero. Four types of registers PCB, DTB,
ADB, and SPB can be used as <destination bank> and <source bank>. By default, DTB is
assumed.
If an interrupt occurs during the transfer, the transfer is suspended to handle the interrupt. The
transfer is resumed after the interrupt has been handled.
● Assembler format:
MOVSW [<destination bank>] [,<source bank>]
MOVSWI [<destination bank>] [,<source bank>]
● Operation:
The following is repeated until RW0 becomes equal to zero:
((AH)) ← ((AL)) [Word transfer]
(AH) ← (AH)+2, (AL) ← (AL)+2
(RW0) ← (RW0)–1
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 2
Cycle count: 1 cycle when RW0 is zero; 2 × RW0 in all other cases
I S T N Z V C
– – – – – – –
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CHAPTER 8 DETAILED INSTRUCTIONS8.76 MOVSW, MOVSWI (Move String Word with Increment)
● Example:
MOVSW,ADB
In this example, word data is transferred from the address (38A000H) specified by ADB and
AL to the address (CD0000H) specified by DTB and AH.
0 0 0 3RW0
Before execution
Memory
× × CD0005× × CD0004× × CD0003
C DDTB
3 1 38A0024 D 38A001
AL
AH AL
4 6 38A000
3 8ADB
× × CD0002
AH
3 6 38A003
0 0 0 0RW0
After execution
Memory
2 6 CD00054 2 CD00043 6 CD0003
C DDTB
3 1 38A0024 D 38A001
AL
AH AL
4 6 38A000
3 8ADB
3 1 CD0002
AH
3 6 38A0034 2 38A0042 6 38A005
4 2 38A0042 6 38A005
× × CD0001× × CD0000
4 D CD00014 6 CD0000
0 0 0 0 A 0 0 0 0 0 0 6 A 0 0 6
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
A A
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.77 MOVSWD (Move String Word with Decrement)
8.77 MOVSWD (Move String Word with Decrement)
Transfer word data from the address specified by AL in the space specified by <source bank> to the address specified by AH in the space specified by <destination bank>. The transfer is repeated the number of times specified by RW0, with the addresses being decremented each time.
The transfer is not performed if RW0 is equal to zero. Four types of registers PCB, DTB,
ADB, and SPB can be used as <destination bank> and <source bank>. By default, DTB is
assumed.
If an interrupt occurs during the transfer, the transfer is suspended to handle the interrupt. The
transfer is resumed after the interrupt has been handled.
● Assembler format:
MOVSWD [<destination bank>] [,<source bank>]
● Operation:
The following is repeated until RW0 becomes equal to zero:
((AH)) ← ((AL)) [Word transfer]
(AH) ← (AH)–2, (AL) ← (AL)–2
(RW0) ← (RW0)–1
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 2
Cycle count: 1 cycle when RW0 is zero; 2 × RW0 in all other cases
Odd address correction: RW0 cycle(s) when the transfer destination is an odd address;
RW0 cycle(s) when the transfer source is an odd address; and 2
× RW0 cycles when both the transfer destination and the
transfer source are odd addresses
I S T N Z V C
– – – – – – –
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CHAPTER 8 DETAILED INSTRUCTIONS8.78 MOVW (Move Word Data from Source to Accumulator)
8.78 MOVW (Move Word Data from Source to Accumulator)
The value in AL is transferred to AH. And then the word data in the second operand is transferred to AL.
If the second operand is @A, transfer to AH is not performed.
● Assembler format:
MOVW A,#imm16 MOVW A,@RWi+disp8
MOVW A,@A MOVW A,addr16
MOVW A,@RLi+disp8 MOVW A,RWi
MOVW A,SP MOVW A,dir
MOVW A,io
MOVW A,ear MOVW A,eam
● Operation:
(A) ← (Second operand) [Word transfer]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the transferred data is "1", cleared otherwise.
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * – –
First operand A A A A A A A A A A A
Second operand #imm16 @A @RLi+disp8 SP io @RWi+disp8 addr16 RWi dir ear eam
Byte count 3 2 3 1 2 2 3 1 2 2 2+
Cycle count 1 1 1 1 1 1 1 1 1 1 1
Odd address correction 0 1 1 0 1 1 1 0 1 0 1
F2MC-16FX Family
216 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.78 MOVW (Move Word Data from Source to Accumulator)
● Example:
MOVW A,0F9A0H
In this example, the word data (4901H) of AL is transferred to AH, and then the word data
(AE86H) at address F9A0H is transferred to AL.
× × × × 4 9 0 1 A
Before execution
4 9 0 1 A E 8 6 A
After execution
Memory Memory
A E F9A1 A E F9A18 6 F9A0 8 6 F9A0
CCR × × × × ×T N Z V C
CCR × 1 0 × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.79 MOVW (Move Word Data from Accumulator to Destination)
8.79 MOVW (Move Word Data from Accumulator to Destination)
Transfer the low-order word data of the accumulator (A) to the first operand.
● Assembler format:
MOVW @RLi+disp8,A MOVW addr16,A
MOVW SP,A MOVW RWi,A
MOVW io,A MOVW dir,A
MOVW @RWi+disp8,A
MOVW ear,A MOVW eam,A
● Operation:
(First operand) ← (A) [Word transfer]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the transferred data is "1", cleared otherwise.
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * – –
First operand dir @RLi+disp8 addr16 SP io @RWi+disp8 RWi ear eam
Second operand A A A A A A A A A
Byte count 2 3 3 1 2 2 1 2 2+
Cycle count 1 1 1 1 1 1 1 1 1
Odd address correction 1 1 1 0 1 1 0 0 1
F2MC-16FX Family
218 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.79 MOVW (Move Word Data from Accumulator to Destination)
● Example:
MOVW RW0,A
In this example, the word data (0000H) of AL is transferred to RW0.
× × × × 0 0 0 0A
Before execution
× × × ×RW0
× × × × 0 0 0 0A
After execution
0 0 0 0RW0
CCR × × × × ×T N Z V C
CCR × 0 1 × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.80 MOVW (Move Immediate Word Data to Destination)
8.80 MOVW (Move Immediate Word Data to Destination)
This instruction transfers the 16-bit immediate data to the first operand.
When the first operand is @PC + disp16, the transfer destination address is the address where
the machine instruction of the MOVW instruction is stored + 4 + disp16. Note that this is not
the address where the machine instruction of the instruction subsequent to the MOVW
instruction is stored+disp16.
● Assembler format:
MOVW ear,#imm16 MOVW eam,#imm16
● Operation:
(First operand) ← imm16
● CCR:
I, S, and T: Unchanged
N: Unchanged if the data is transferred to a register other than the general-purpose
registers. If the data is transferred to the general-purpose register, N is set when
the MSB of the transferred data is "1", cleared otherwise.
Z: Unchanged if the data is transferred to a register other than the general-purpose
registers. If the data is transferred to the general-purpose register, Z is set when the
transferred data is zero, cleared otherwise.
V and C: Unchanged and none of the flags is changed.
● Byte count and cycle count:
If the data is transferred to a general-
purpose register (RW0 to RW7)
If the data is transferred to a register other
than the general-purpose registers (RW0 to
RW7)
I S T N Z V C I S T N Z V C
– – – * * – – – – – – – – –
First operand ear eam
Second operand #imm16 #imm16
Byte count 4 4+
Cycle count 2 2
Odd address correction 0 1
F2MC-16FX Family
220 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.80 MOVW (Move Immediate Word Data to Destination)
● Example:
MOVW RW0,#2343H
In this example, the 16-bit immediate data (2343H) is transferred to RW0.
Before execution
× × × ×RW0
After execution
2 3 4 3RW0
CCR × × × × ×T N Z V C
CCR × 0 0 × ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.81 MOVW (Move Word Data from Source to Destination)
8.81 MOVW (Move Word Data from Source to Destination)
Transfer the word data specified by the second operand to the first operand.
● Assembler format:
MOVW RWi,#imm16
MOVW ear,RWi MOVW eam,RWi
MOVW RWi,ear MOVW RWi,eam
● Operation:
(First operand) ← (Second operand) [Word transfer]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the transferred data is "1", cleared otherwise.
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * – –
First operand RWi RWi RWi ear eam
Second operand #imm16 ear eam RWi RWi
Byte count 3 2 2+ 2 2+
Cycle count 1 1 1 1 1
Odd address correction 0 0 1 0 1
F2MC-16FX Family
222 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.81 MOVW (Move Word Data from Source to Destination)
● Example:
MOVW RW1,RW0
In this example, the word data (004AH) of RW0 is transferred to RW1.
Before execution
0 0 4 ARW0
After execution
0 0 4 ARW0
× × × × RW1 0 0 4 A RW1
× × × × × × × × A × × × × × × × × A
CCR × × × × ×T N Z V C
CCR × 0 0 × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.82 MOVW (Move Immediate Word Data to io)
8.82 MOVW (Move Immediate Word Data to io)
Transfer 16-bit immediate data to the I/O area specified by the first operand.
● Assembler format:
MOVW io,#imm16
● Operation:
(First operand) ← imm16 [Word transfer]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 4
Cycle count: 1
Odd address correction: 1
● Example:
MOVW 24H,#2343H
In this example, the 16-bit immediate data (2343H) is transferred to address 24H in the I/O area
as word data.
I S T N Z V C
– – – – – – –
Before execution After execution
Memory
× ×
Memory
× ×× × 000025 2 3 000025× × 000024 4 3 000024× × × ×
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.83 MOVW (Move Word Data from AH to Memory)
8.83 MOVW (Move Word Data from AH to Memory)
Transfer the word data of AH to the memory location specified by the contents of AL.
● Assembler format:
MOVW @AL,AH
● Operation:
((AL)) ← (AH) [Word transfer]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the transferred data is "1", cleared otherwise.
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
Byte count: 2
Cycle count: 1
Odd address correction: 1
● Example:
MOVW @AL,AH
In this example, the word data (00CBH) of AH is transferred to the address (FEFFH) specified
by AL.
I S T N Z V C
– – – * * – –
0 0 C B F E F F A
Before execution
0 0 C B F E F F A
After execution
Memory Memory
7 1 FEFF C B FEFF
CCR × × × × ×T N Z V C
CCR × 1 0 × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.84 MOVX (Move Byte Data with Sign Extension from Source
to Accumulator)
8.84 MOVX (Move Byte Data with Sign Extension from Source to Accumulator)
The value in AL is transferred to AH. And then the word data that is sign extended from a byte data in the second operand is transferred to AL.
If the second operand is @A, transfer to AH is not performed.
● Assembler format:
MOVX A,#imm8 MOVX A,@RWi+disp8
MOVX A,@A MOVX A,addr16
MOVX A,@RLi+disp8 MOVX A,Ri
MOVX A,dir MOVX A,io
MOVX A,ear MOVX A,eam
● Operation:
(A) ← (Second operand) [Byte transfer with sign extension]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the transferred data is "1", cleared otherwise.
Z: Set when the transferred data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * – –
First operand A A A A A A A A A A
Second operand #imm8 @A @RLi+disp8 dir io @RWi+disp8 addr16 Ri ear eam
Byte count 2 2 3 2 2 2 3 1 2 2+
Cycle count 1 1 1 1 1 1 1 1 1 1
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CHAPTER 8 DETAILED INSTRUCTIONS8.84 MOVX (Move Byte Data with Sign Extension from Source to Accumulator)
● Example:
MOVX A,0E001H
In this example, the word data (A046H) of AL is transferred to AH, and then the word data
(FF86H), for which the byte data (86H) at address E001H is sign-extended, is transferred to AL.
× × × × A 0 4 6 A
Before execution
A 0 4 6 F F 8 6 A
After execution
Memory Memory
8 6 E001 8 6 E001
CCR × × × × ×T N Z V C
CCR × 1 0 × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.85 MUL (Multiply Byte Data of Accumulator)
8.85 MUL (Multiply Byte Data of Accumulator)
This instruction multiplies the low-order byte data of AH by that of AL as signed binary numbers, then returns the result to AL of the accumulator (A).
● Assembler format:
MUL A
● Operation:
word (A) ← byte (AH)×byte (AL) [Byte multiplication]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 2
Cycle count: 4
● Example:
MUL A
In this example, the low-order byte data (FAH) of AH is multiplied by the low-order byte data
(11H) of AL with a sign. The word data (FF9AH) is set to AL as the multiplication result.
I S T N Z V C
– – – – – – –
Before execution After execution
AH AL AH AL
0 0 F A 0 0 1 1 A 0 0 F A F F 9 A A
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.86 MUL (Multiply Byte Data of Accumulator and Effective Address)
8.86 MUL (Multiply Byte Data of Accumulator and Effective Address)
Multiply the byte data of the accumulator (A) by the byte data specified by the second operand as signed binary numbers and restore the result in bits 0 to 15 of A.
● Assembler format:
MUL A,ear MUL A,eam
● Operation:
word (A) ← byte (A) × byte (ea) [Byte multiplication]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
● Example:
MUL A,R7
In this example, the low-order byte data (85H) of AL is multiplied by the byte data (A5H) in R7
with a sign. The word data (2B89H) is set to AL as the multiplication result.
I S T N Z V C
– – – – – – –
First operand A A
Second operand ear eam
Byte count 2 2+
Cycle count 4 5
× × × × 0 0 8 5A
Before execution
× × × × 2 B B 9 A
After execution
A 5R7 A 5R7
AH AL AH AL
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.87 MULW (Multiply Word Data of Accumulator)
8.87 MULW (Multiply Word Data of Accumulator)
Multiply the word data of AH by the word data specified by AL as signed binary numbers and restore the result in the accumulator (A) as long word data.
● Assembler format:
MULW A
● Operation:
long (A) ← word (AH)×word (AL) [Word multiplication]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 2
Cycle count: 6
● Example:
MULW A
In this example, the word data (AD01H) of AH is multiplied by the word data (05EDH) of AL
with a sign. The long word data is set to the accumulator (A) as the multiplication result.
I S T N Z V C
– – – – – – –
A D 0 1 0 5 E D A
Before execution After execution
AH AL AH AL
F E 1 4 2 E E D A
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.88 MULW (Multiply Word Data of Accumulator and Effective Address)
8.88 MULW (Multiply Word Data of Accumulator and Effective Address)
Multiply the word data of the accumulator (A) by the word data specified by the second operand as signed binary numbers and restore the result in A as long word data.
● Assembler format:
MULW A,ear MULW A,eam
● Operation:
long (A) ← word (A) × word (Second operand) [Word multiplication]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
● Example:
MULW A,RW5
In this example, the word data (8342H) of AL is multiplied by the word data (4314H) in RW5
with a sign. The long word data is set to the accumulator (A) as the multiplication result.
I S T N Z V C
– – – – – – –
First operand A A
Second operand ear eam
Byte count 2 2+
Cycle count 6 7
Odd address correction 0 1
Before execution After execution
AH AL AH AL
4 3 1 4 RW5 4 3 1 4RW5
× × × × 8 3 4 2 A D F 5 0 8 7 2 8 A
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.89 MULU (Multiply Unsigned Byte Data of Accumulator)
8.89 MULU (Multiply Unsigned Byte Data of Accumulator)
Multiply the low-order byte data of AH by the low-order byte data of AL as unsigned binary numbers and restore the result in the AL of the accumulator (A).
● Assembler format:
MULU A
● Operation:
word (A) ← byte (AH)×byte (AL) [Byte multiplication]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 1
Cycle count: 2
● Example:
MULU A
In this example, the low-order byte data (FAH) of AH is multiplied by the low-order byte data
(11H) of AL without a sign. The word data (109AH) is set to AL as the multiplication result.
I S T N Z V C
– – – – – – –
Before execution After execution
0 0 F A 0 0 1 1 A 0 0 F A 1 0 9 A A
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.90 MULU (Multiply Unsigned Byte Data of Accumulator and Effective Address)
8.90 MULU (Multiply Unsigned Byte Data of Accumulator and Effective Address)
Multiply the byte data of the accumulator (A) by the byte data specified by the second operand as unsigned binary numbers and restore the result in bits 0 to 15 of A.
● Assembler format:
MULU A, ear MULU A, eam
● Operation:
word (A) ← byte (A) × byte (Second operand) [Byte multiplication]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
● Example:
MULU A, R7
In this example, the low-order byte data (85H) of AL is multiplied by the byte data (A5H) in R7
without a sign. The word data (55B9H) is set to AL as the multiplication result.
I S T N Z V C
– – – – – – –
First operand A A
Second operand ear eam
Byte count 2 2 +
Cycle count 2 3
Before execution After execution
R7 R7A 5 A 5
× × × × 0 0 8 5 A × × × × 5 5 B 9 A
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.91 MULUW (Multiply Unsigned Word Data of Accumulator)
8.91 MULUW (Multiply Unsigned Word Data of Accumulator)
Multiply the word data of AH by the word data of AL as unsigned binary numbers and restore the result in the accumulator (A) as long word data.
● Assembler format:
MULUW A
● Operation:
long (A) ← word (AH) × word (AL) [Word multiplication]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 1
Cycle count: 4
● Example:
MULUW A
In this example, the word data (AD01H) of AH is multiplied by the word data (05EDH) of AL
without a sign. The long word data is set to the accumulator (A) as the multiplication result.
I S T N Z V C
– – – – – – –
Before execution After execution
A D 0 1 0 5 E D A 0 4 0 1 2 E E D A
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.92 MULUW (Multiply Unsigned Word Data of Accumulator and Effective Address)
8.92 MULUW (Multiply Unsigned Word Data of Accumulator and Effective Address)
Multiply the word data of the accumulator (A) by the word data specified by the second operand as unsigned binary numbers and restore the result in A as long word data.
● Assembler format:
MULUW A, ear MULUW A, eam
● Operation:
long (A) ← word (A) × word (Second operand) [Word multiplication]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
● Example:
MULUW A, RW5
In this example, the word data (8342H) of AL is multiplied by the word data (4314H) in RW5
without a sign. The long word data is set to the accumulator (A) as the multiplication result.
I S T N Z V C
– – – – – – –
First operand A A
Second operand ear eam
Byte count 2 2+
Cycle count 4 5
Odd address correction 0 1
4 3 1 4RW5
Before execution
× × × × 8 3 4 2 A
4 3 1 4RW5
After execution
A 2 2 6 4 8 7 2 8
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.93 NEG (Negate Byte Data of Destination)
8.93 NEG (Negate Byte Data of Destination)
Take the 2's complement of the byte data specified by the operand and restore the result in the operand. If the operand is the accumulator (A), the value resulting from sign-extending the operation result is transferred to upper byte of AL.
● Assembler format:
NEG A
NEG ear NEG eam
● Operation:
(Operand) ← 0–(Operand) [Byte operation]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
● Example:
NEG R0
In this example, the 2's complement of the byte data (59H) in R0 is obtained.
I S T N Z V C
– – – * * * *
Operand A ear eam
Byte count 1 2 2+
Cycle count 1 1 3
Before execution After execution
5 9R0 A 7R0
CCR × × × × ×T N Z V C
CCR × 1 0 0 1
T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.94 NEGW (Negate Word Data of Destination)
8.94 NEGW (Negate Word Data of Destination)
Take the 2's complement of the word data specified by the operand and restore the result in the operand.
● Assembler format:
NEGW A
NEGW ear NEGW eam
● Operation:
(Operand) ← 0–(Operand) [Word operation]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
● Example:
NEGW A
In this example, the 2's complement of the word data (AB98H) of AL is obtained.
I S T N Z V C
– – – * * * *
Operand A ear eam
Byte count 1 2 2+
Cycle count 1 1 3
Odd address correction 0 0 2
× × × × A B 9 8 A
Before execution
× × × × 5 4 6 8 A
After execution
CCR × × × × ×T N Z V C
CCR × 0 0 0 1
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.95 NOP (No Operation)
8.95 NOP (No Operation)
Perform no operation.
● Assembler format:
NOP
● Operation:
No operation is performed.
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
NOP
The NOP instruction performs no operations.
I S T N Z V C
– – – – – – –
× × × × × × × × A
F 0 0 0 PC
× × × × × × × × A
F 0 0 1 PC
Before execution After execution
Memory Memory
× × F001 × × F0010 0 F000 0 0 F000PC
PC
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.96 NOT (Not Byte Data of Destination)
8.96 NOT (Not Byte Data of Destination)
Take the logical NOT of the byte data specified by the operand and restore the result in the operand.
● Assembler format:
NOT A
NOT ear NOT eam
● Operation:
(Operand) ← not (Operand) [Byte logical NOT]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * R –
Operand A ear eam
Byte count 1 2 2+
Cycle count 1 1 3
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CHAPTER 8 DETAILED INSTRUCTIONS8.96 NOT (Not Byte Data of Destination)
● Example:
NOT 0071H
In this example, the byte data (FFH) at address 0071H is inverted for each bit.
× × × × × × × × A
Before execution
× × × × × × × × A
After execution
Memory Memory
F F 0071 0 0 0071
CCR × × × × ×T N Z V C
CCR × 0 1 0 ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.97 NOTW (Not Word Data of Destination)
8.97 NOTW (Not Word Data of Destination)
Take the logical NOT of the word data specified by the operand and restore the result in the operand.
● Assembler format:
NOTW A
NOTW ear NOTW eam
● Operation:
(Operand) ← not (Operand) [Word logical NOT]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
● Example:
NOTW RW3
In this example, the word data (258BH) of RW3 is inverted for each bit.
I S T N Z V C
– – – * * R –
Operand A ear eam
Byte count 1 2 2+
Cycle count 1 1 3
Odd address correction 0 0 2
Before execution
2 5 8 B RW3
After execution
D A 7 4 RW3
CCR × × × × ×T N Z V C
CCR × 1 0 0 ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.98 NRML (NORMALIZE Long Word)
8.98 NRML (NORMALIZE Long Word)
Shift the long word data of the accumulator (A) to the left until the most significant bit of the accumulator (A) becomes "1", if the long word data is not zero.
R0 is set to the number of shifts required and the zero flag (Z) is cleared.
If the long word data of the accumulator (A) is zero, R0 is set to zero and the zero flag (Z) is
set.
● Assembler format:
NRML A,R0
● Operation:
If A≠0: The long word data is shifted to the left until the most significant bit of A becomes 1.
(R0) ← Number of shifts required, Z ← 0
If A=0: (R0) ← 0, Z ← 1
● CCR:
I, S, T, and N: Unchanged
Z: Set when A is equal to zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
Byte count: 2
Cycle count: 1
● Example:
NRML A,R0
In this example, the long word data (00008361H) of the accumulator (A) is shifted to the left by
16 bits. The number of shifted bits (10H) is set to R0.
I S T N Z V C
– – – – * – –
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CHAPTER 8 DETAILED INSTRUCTIONS8.98 NRML (NORMALIZE Long Word)
0 0 0 0 8 3 6 1 A
Before execution
8 3 6 1 0 0 0 0A
After execution
3 4R0 1 0R0
CCR × × × × ×T N Z V C
CCR × × 0 × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.99 OR (Or Byte Data of Destination and Source to Destination)
8.99 OR (Or Byte Data of Destination and Source to Destination)
Take the logical OR of the byte data specified by the first operand and the byte data specified by the second operand and restore the result in the first operand.
● Assembler format:
OR A,#imm8
OR A,ear OR A,eam
OR ear,A OR eam,A
● Operation:
(First operand) ← (First operand) or (Second operand) [Byte logical OR]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * R –
First operand A A A ear eam
Second operand #imm8 ear eam A A
Byte count 2 2 2+ 2 2+
Cycle count 1 1 2 1 3
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CHAPTER 8 DETAILED INSTRUCTIONS8.99 OR (Or Byte Data of Destination and Source to Destination)
● Example:
OR 0052H,A
In this example, the logical OR is taken between the byte data at address 0052H and the low-
order byte data (37H) of AL.
× × × × 0 0 3 7 A
Before execution
× × × × 0 0 3 7 A
After execution
Memory Memory
F A 0052 F F 0052
CCR × × × × ×T N Z V C
CCR × 1 0 0 ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.100 OR (Or Byte Data of Immediate Data and Condition Code
Register to Condition Code Register)
8.100 OR (Or Byte Data of Immediate Data and Condition Code Register to Condition Code Register)
Take the logical OR of the byte data in the condition code register (CCR) and specified 8-bit immediate data and restore the result in the condition code register (CCR).
Bit 7 of the immediate data is ignored because the condition code register (CCR) is 7 bits long.
● Assembler format:
OR CCR,#imm8
● Operation:
(CCR) ← (CCR) or imm8 [Byte logical OR]
● CCR:
I: Stores bit 6 of the operation result.
S: Stores bit 5 of the operation result.
T: Stores bit 4 of the operation result.
N: Stores bit 3 of the operation result.
Z: Stores bit 2 of the operation result.
V: Stores bit 1 of the operation result.
C: Stores bit 0 of the operation result.
● Byte count and cycle count:
Byte count: 2
Cycle count: 1
I S T N Z V C
* * * * * * *
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CHAPTER 8 DETAILED INSTRUCTIONS8.100 OR (Or Byte Data of Immediate Data and Condition Code Register to Condition Code Register)
● Example:
OR CCR,#57H
In this example, the logical OR is taken between CCR and bits 6 to 0 of the 8-bit immediate
data (57H).
Before execution
0CCR 1 1 0 1 0 1I S T N Z V C
ILM × × ×ILM2 ILM1 ILM0
RP × × × × ×MSB LSB
After execution
1CCR 1 1 0 1 1 1I S T N Z V C
ILM × × ×ILM2 ILM1 ILM0
RP × × × × ×MSB LSB
× × × × × × × ×A × × × × × × × ×A
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.101 ORL (Or Long Word Data of Destination and Source to
Destination)
8.101 ORL (Or Long Word Data of Destination and Source to Destination)
Take the logical OR of the long word data for the accumulator (A) and that specified by the second operand and restore the result in A.
● Assembler format:
ORL A,ear ORL A,eam
● Operation:
(A) ← (A) or (Second operand) [Long word logical OR]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * R –
First operand A A
Second operand ear eam
Byte count 2 2+
Cycle count 2 3
Odd address correction 0 1
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CHAPTER 8 DETAILED INSTRUCTIONS8.101 ORL (Or Long Word Data of Destination and Source to Destination)
● Example:
ORL A,0FFF0H
In this example, the logical OR is taken between the long word data (725DF05CH) of the
accumulator (A) and the long word data (FF55AA00H) at address FFF0H.
7 2 5 D F 0 5 C A
Before execution
F F 5 D F A 5 C A
After execution
Memory Memory
F F FFF3 F F FFF35 5 FFF2 5 5 FFF2A A FFF1 A A FFF10 0 FFF0 0 0 FFF0
CCR × × × × ×T N Z V C
CCR × 1 0 0 ×T N Z V C
AH AL AH AL
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.102 ORW (Or Word Data of AH and AL to AL)
8.102 ORW (Or Word Data of AH and AL to AL)
Take the logical OR of the word data for AH and that for AL and restore the result in AL.
● Assembler format:
ORW A
● Operation:
(AL) ← (AH) or (AL) [Word logical OR]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
ORW A
In this example, the logical OR is taken between the word data (AB98H) of AL and the word
data (0426H) of AH.
I S T N Z V C
– – – * * R –
0 4 2 6 A B 9 8 A
Before execution
0 4 2 6 A F B E A
After execution
CCR × × × × ×T N Z V C
CCR × 1 0 0 ×T N Z V C
AH AL AH AL
F2MC-16FX Family
250 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.103 ORW (Or Word Data of Destination and Source to Destination)
8.103 ORW (Or Word Data of Destination and Source to Destination)
Take the logical OR of the word data specified by the first operand and the word data specified by the second operand and restore the result in the first operand.
● Assembler format:
ORW A,#imm16
ORW A,ear ORW A,eam
ORW ear,A ORW eam,A
● Operation:
(First operand) ← (First operand) or (Second operand) [Word logical OR]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * R –
First operand A A A ear eam
Second operand #imm16 ear eam A A
Byte count 3 2 2+ 2 2+
Cycle count 1 1 2 1 3
Odd address correction 0 0 1 0 2
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.103 ORW (Or Word Data of Destination and Source to
Destination)● Example:
ORW 0E001H,A
In this example, the logical OR is taken between the word data (4283H) at address E001H and
the word data (5963H) of AL.
Before execution After execution
Memory Memory
8 3 E002 D B E0024 2 E001 6 3 E001
× × × × 5 9 6 3 A × × × × 5 9 6 3 A
CCR × × × × ×T N Z V C
CCR × 1 0 0 ×T N Z V C
AH AL AH AL
F2MC-16FX Family
252 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.104 POPW (Pop Word Data of Accumulator from Stack Memory)
8.104 POPW (Pop Word Data of Accumulator from Stack Memory)
The AL value is transferred to AH. Then, the word data of the memory location pointed to by the stack pointer (SP) is transferred to AL. After the data is transferred, 0002H is word-added to the value of SP (word data).
● Assembler format:
POPW A
● Operation:
(A) ← ((SP)) [Word transfer]
(SP) ← (SP)+2 [Word addition]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
Odd address correction: 1
I S T N Z V C
– – – – – – –
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CHAPTER 8 DETAILED INSTRUCTIONS8.104 POPW (Pop Word Data of Accumulator from Stack
Memory)● Example:
POPW A
In this example, the word data (1635H) of AL is transferred to AH, and then the word data
(10ACH) at the address (0120H) specified by SP is transferred to AL. "2" is added to SP.
0 1 2 0SP 0 1 2 2 SP
Before execution After execution
Memory
0122
Memory
01221 0 0121 1 0 0121A C 0120 A C 0120SP
SP
0 4 2 2 1 6 3 5A 1 6 3 5 1 0 A C A
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
AH AL AH AL
F2MC-16FX Family
254 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.105 POPW (Pop Word Data of AH from Stack Memory)
8.105 POPW (Pop Word Data of AH from Stack Memory)
Transfer word data from the memory location pointed to by the stack pointer (SP) to AH. Then, 0002H is word-added to the value of SP (word data).
● Assembler format:
POPW AH
● Operation:
(AH) ← ((SP)) [Word transfer]
(SP) ← (SP)+2 [Word addition]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
Odd address correction: 1
● Example:
POPW AH
In this example, the word data (4314H) at the address (0120H) specified by SP is transferred to
AH. "2" is added to SP.
I S T N Z V C
– – – – – – –
0 4 2 2 1 6 3 5 A
0 1 2 0 SP
4 3 1 4 1 6 3 5 A
0 1 2 2 SP
Before execution After execution
Memory
0122
Memory
01224 3 0121 4 3 01211 4 0120 1 4 0120SP
SP
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.106 POPW (Pop Word Data of Program Status from Stack
Memory)
8.106 POPW (Pop Word Data of Program Status from Stack Memory)
Transfer word data from the memory location pointed to by the stack pointer (SP) to the processor status (PS). Bit 7 of the word data is ignored. Then, 0002H is word-added to the value of SP (word data).
● Assembler format:
POPW PS
● Operation:
(PS) ← ((SP)) [Word transfer]
(SP) ← (SP)+2 [Word addition]
● CCR:
The values of the corresponding bits for the stack memory are transferred.
● Byte count and cycle count:
Byte count: 1
Cycle count: 19 when the content of RP changes; 4 in all other cases
Odd address correction: 1
I S T N Z V C
* * * * * * *
F2MC-16FX Family
256 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.106 POPW (Pop Word Data of Program Status from Stack Memory)
● Example:
POPW PS
In this example, the word data (4314H) at the address (0120H) specified by SP is transferred to
PS. "2" is added to SP.
×CCR × × × × × ×I S T N Z V C
ILM × × ×ILM2 ILM1 ILM0
RP × × × × ×MSB LSB
0 1 2 0SP
Before execution
Memory
01224 3 01211 4 0120SP
0CCR 0 1 0 1 0 0I S T N Z V C
ILM 0 1 0ILM2 ILM1 ILM0
RP 0 0 0 1 1MSB LSB
0 1 2 2SP
After execution
Memory
01224 3 01211 4 0120
SP
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.107 POPW (Pop Registers from Stack Memory)
8.107 POPW (Pop Registers from Stack Memory)
Transfer the data pointed to by the stack pointer (SP) to the multiple general-purpose word registers specified by the register list (rlst).
In assembler representation, register names are enumerated as a register list. After assembly,
the register list turns into byte data.
● Assembler format:
POPW rlst
● Operation:
(RWx) ← ((SP)) [Word transfer]
(SP) ← (SP)+2 [Word addition]
The above operation is repeated for all the registers specified by rlst.
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 2
Cycle count: (Number of transfers)
Odd address correction: (Number of transfers)
I S T N Z V C
– – – – – – –
F2MC-16FX Family
258 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.107 POPW (Pop Registers from Stack Memory)
● Example:
POPW (RW0,RW4)
In this example, RW0 and RW4 are popped from the stack specified by SP.
3 4 F A SP
Before execution
34FE0 4 34FD0 3 34FC0 2 34FB
SP
× ×RW7 × ×
× ×RW0 × ×× ×RW1 × ×× ×RW2 × ×× ×RW3 × ×× ×RW4 × ×× ×RW5 × ×× ×RW6 × ×
0 1 34FA
Memory
3 4 F E SP
After execution
34FE0 4 34FD0 3 34FC0 2 34FB
SP
× ×RW7 × ×
0 2RW0 0 1× ×RW1 × ×× ×RW2 × ×× ×RW3 × ×0 4RW4 0 3× ×RW5 × ×× ×RW6 × ×
0 1 34FA
Memory
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.108 PUSHW (Push Word Data of Inherent Register to Stack
Memory)
8.108 PUSHW (Push Word Data of Inherent Register to Stack Memory)
Decrement the value of the stack pointer (SP) by two words and transfer the word data of the register to the memory location pointed to by the resulting SP value.
● Assembler format:
PUSHW A
PUSHW AH
PUSHW PS
● Operation:
(SP) ← (SP)–2 [Word subtraction]
((SP)) ← (Operand) [Word transfer]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
I S T N Z V C
– – – – – – –
Operand A AH PS
Byte count 1 1 1
Cycle count 1 1 1
Odd address correction 1 1 1
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260 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.108 PUSHW (Push Word Data of Inherent Register to Stack Memory)
● Example:
PUSHW A
In this example, "2" is subtracted from SP, and the word data of AL is transferred to the
address (0120H) specified by SP.
0 1 2 2 SP 0 1 2 0 SP
Before execution After execution
Memory
0122
Memory
0122× × 0121 4 5 0121× × 0120 A 4 0120
SP
SP
4 5 A 4 A 4 5 A 4 A
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
AH AL AH AL
× × × × × × × ×
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CHAPTER 8 DETAILED INSTRUCTIONS8.109 PUSHW (Push Registers to Stack Memory)
8.109 PUSHW (Push Registers to Stack Memory)
Transfer the contents of the multiple general-purpose word registers specified by the register list (rlst) to the memory location pointed to by the stack pointer (SP).
In assembler representation, register names are enumerated as a register list. After assembly,
the register list turns into byte data.
● Assembler format:
PUSHW rlst
● Operation:
(SP) ← (SP)–2 [Word subtraction]
((SP))← (RWx) [Word transfer]
The above operation is repeated for all the registers specified by rlst.
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 2
Cycle count: (Number of transfers)
Odd address correction: (Number of transfers)
I S T N Z V C
– – – – – – –
F2MC-16FX Family
262 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.109 PUSHW (Push Registers to Stack Memory)
● Example:
PUSHW (RW1,RW3)
In this example, RW3 and RW1 are pushed to the stack specified by SP.
3 4 F ESP
Before execution
34FE× × 34FD× × 34FC× × 34FB
SP
× ×RW7 × ×
× ×RW0 × ×3 5RW1 A 4× ×RW2 × ×6 DRW3 F 0× ×RW4 × ×× ×RW5 × ×× ×RW6 × ×
× × 34FA
Memory
3 4 F A SP
After execution
34FE6 D 34FDF 0 34FC3 5 34FB
SP
× ×RW7 × ×
× ×RW0 × ×3 5RW1 A 4× ×RW2 × ×6 DRW3 F 0× ×RW4 × ×× ×RW5 × ×× ×RW6 × ×
A 4 34FA
Memory
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.110 RET (Return from Subroutine)
8.110 RET (Return from Subroutine)
Cause a branch to the address pointed to by the stack pointer (SP).
If this instruction is used in combination with a subroutine call instruction (CALL, CALLV),
control returns to the instruction following the subroutine call instruction after the branch
operation is completed.
● Assembler format:
RET
● Operation:
(PC) ← ((SP)) [Word transfer]
(SP) ← (SP)+2 [Word addition]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 1
Cycle count: 4
Odd address correction: 1
● Example:
RET
In this example, the word data (FC22H) at the address (0062H) specified by SP is set to PC. "2"
is added to SP.
I S T N Z V C
– – – – – – –
Before execution
Memory
0064F C 00632 2 0062
0 0 6 2 SP
SP
F 0 0 2 PC
After execution
Memory
0064F C 00632 2 0062
0 0 6 4 SP
SP
F C 2 2 PC
F2MC-16FX Family
264 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.111 RETI (Return from Interrupt)
8.111 RETI (Return from Interrupt)
This instruction returns the data in the memory that is indicated by (SSP) to PS to detect interrupt requests performed using IF or ILM.
When the next interrupt request is received, the procedure branches to the detected interruption
vector. If no next interrupt is received, the procedure will return from the interruption process.
● Assembler format:
RETI
● Operation:
(1) If the next interrupt is accepted
(PS) ← ((SSP))
(S) ← 1, (PCB), (PC) ← Interrupt vector address
(ILM) ← Accepted interrupt level
DTB, PCB, DPR, ADB, AL, and AH are not restored.
(2) If control is returned from the next interrupt
(PS) ← ((SSP)), (SSP) ← (SSP)+2;
(PC) ← ((SSP)), (SSP) ← (SSP)+2;
(DTB),(PCB) ← ((SSP)), (SSP) ← (SSP)+2;
(DPR),(ADB) ← ((SSP)), (SSP) ← (SSP)+2;
(AL) ← ((SSP)), (SSP) ← (SSP)+2;
(AH) ← ((SSP)), (SSP) ← (SSP)+2
● CCR
I: Restored to the saved I value. I: Restored to the saved I value.
S: Set S: Restored to the saved S value.
T: Restored to the saved T value. T: Restored to the saved T value.
N: Restored to the saved N value. N: Restored to the saved N value.
Z: Restored to the saved Z value. Z: Restored to the saved Z value.
V: Restored to the saved V value. V: Restored to the saved V value.
C: Restored to the saved C value. C: Restored to the saved C value.
(1) If the next interrupt is accepted (2) If control is returned from the next
interrupt
I S T N Z V C I S T N Z V C
* S * * * * * * * * * * * *
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CHAPTER 8 DETAILED INSTRUCTIONS8.111 RETI (Return from Interrupt)
● Byte count and cycle count:
Byte count: 1
Cycle count: 23 when the content of RP changes; 6 in all other cases
Odd address correction: 1
● Example:
RETI (if control is returned from the interrupt)
In this example, the word data is transferred from the address (037FF4H) specified by SSB and
SP to each register. "2" is added to SP each time data is transferred to a register.
× × × ×PC
× ×DTB
× × × × × × × × A
Memory
038000 F F 037FFF E E 037FFE
SSP
× ×PCB
× ×DPR
× ×ADB
× ×ILM
× ×RP
0 3SSB
7 F F 4SSP
D D 037FFDC C 037FFCB B 037FFBA A 037FFA9 9 037FF98 8 037FF87 7 037FF76 6 037FF66 1 037FF58 0 037FF4
Before execution
7 7 6 6PC
9 9DTB
F F F E D D C C A
Memory
038000F F 037FFFE E 037FFE
SSP
8 8PCB
B BDPR
A AADB
0 3ILM
0 1RP
0 3SSB
8 0 0 0SSP
D D 037FFDC C 037FFCB B 037FFBA A 037FFA9 9 037FF98 8 037FF87 7 037FF76 6 037FF66 1 037FF58 0 037FF4
After execution
CCR
I S T N Z V C
× × × × × × ×I S T N Z V C0 0 0 0 0 0 0
CCR
AH AL AH AL
F2MC-16FX Family
266 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.112 RETP (Return from Physical Address)
8.112 RETP (Return from Physical Address)
Cause a branch to the physical address pointed to by the stack pointer (SP).
If this instruction is used in combination with the CALLP instruction, control returns to the
instruction following the CALLP instruction after the branch operation is completed.
● Assembler format:
RETP
● Operation:
(PC) ← ((SP)), (SP) ← (SP)+2 [Word addition]
(PCB) ← ((SP)) (Byte transfer), (SP) ← (SP)+2 [Word addition]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 1
Cycle count: 5
Odd address correction: 1
I S T N Z V C
– – – – – – –
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CHAPTER 8 DETAILED INSTRUCTIONS8.112 RETP (Return from Physical Address)
● Example:
RETP
In this example, PC and PCB are popped from the stack specified by USB and SP, and a
branch is caused to address AD4345H.
F 8 F CSP
Before execution
Memory
× × 15F9000 0 15F8FF
4 3 15F8FDA D 15F8FE
SP
2 2 F CPC
1 5USB0 8PCB
4 5 15F8FC
F 9 0 0SP
After execution
Memory
× × 15F9000 0 15F8FF
4 3 15F8FDA D 15F8FE
SP
4 3 4 5PC
1 5USBA DPCB
4 5 15F8FC
CCR × 0 × × × × ×I S T N Z V C
CCR × 0 × × × × ×I S T N Z V C
F2MC-16FX Family
268 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.113 ROLC (Rotate Byte Data of Accumulator with Carry to Left)
8.113 ROLC (Rotate Byte Data of Accumulator with Carry to Left)
Rotate or shift the byte data specified by the operand to the left by one bit, including the carry flag (C). The most significant bit of the operand is placed in the carry flag (C).
● Assembler format:
ROLC A
ROLC ear ROLC eam
● Operation:
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the shifting result is "1", cleared otherwise.
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit shifted out from the MSB of A.
● Byte count and cycle count:
I S T N Z V C
– – – * * – *
MSB LSB CA or operand
Operand A ear eam
Byte count 2 2 2+
Cycle count 1 1 3
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CHAPTER 8 DETAILED INSTRUCTIONS8.113 ROLC (Rotate Byte Data of Accumulator with Carry to
Left)● Example:
ROLC A
In this example, the low-order byte data (32H) of AL and the C flag ("0") are rotated to the left.
× × × × × × 3 2 A
Before execution
× × × × × × 6 4 A
After execution
CCR × × × × 0
T N Z V C
CCR × 0 0 × 0
T N Z V C
AH AL AH AL
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270 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.114 RORC (Rotate Byte Data of Accumulator with Carry to Right)
8.114 RORC (Rotate Byte Data of Accumulator with Carry to Right)
Rotate or shift the byte data specified by the operand to the right by one bit, including the carry flag (C). The least significant bit of the operand is placed in the carry flag (C).
● Assembler format:
RORC A
RORC ear RORC eam
● Operation:
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the shifting result is "1", cleared otherwise.
Z: Set when the shifting result is zero, cleared otherwise.
V: Unchanged
C: Stores the bit shifted out from the LSB of A.
● Byte count and cycle count:
I S T N Z V C
– – – * * – *
MSB LSB CA or operand
Operand A ear eam
Byte count 2 2 2+
Cycle count 1 1 3
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CHAPTER 8 DETAILED INSTRUCTIONS8.114 RORC (Rotate Byte Data of Accumulator with Carry to
Right)● Example:
RORC A
In this example, the low-order byte data (32H) of AL and the C flag ("0") are rotated to the
right.
× × × × × × 3 2
CCR
A
Before execution
× × × × × × 1 9
CCR
A
After execution
× × × × 0T N Z V C
× 0 0 × 0T N Z V C
AH AL AH AL
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272 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.115 SBBS (Set Bit and Branch if Bit Set)
8.115 SBBS (Set Bit and Branch if Bit Set)
Cause a branch if the bit data specified by the first operand is "1".
Control is transferred to the address resulting from word-adding the value resulting from sign-
extending the second operand to the address of the instruction following the SBBS instruction.
After the instruction has been executed, the bit specified by the first operand is set to "1".
● Assembler format:
SBBS addr16:bp,rel
● Operation:
If the condition is satisfied:
(PC) ← (PC)+<Byte count>+rel [Word addition], (addr16:bp) ← 1
If the condition is not satisfied:
(PC) ← (PC)+<Byte count> [Word addition], (addr16:bp) ← 1
● CCR:
I, S, T, and N: Unchanged
Z: Set when the bit data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
Byte count: 5
Cycle count: 5
● Example:
SBBS 1234H:5,20H
In this example, after bit 7 has been set to "1", a branch is caused (condition satisfied) because
bit 7 in the byte data (7FH) at address 1234H is equal to "1".
I S T N Z V C
– – – – * – –
Before execution
Memory
× ×7 F 1234× ×
E 1 0 0PC
After execution
Memory
× ×7 F 1234× ×
E 1 2 5PC
F2MC-16FX Family
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CHAPTER 8 DETAILED INSTRUCTIONS8.116 SCEQ, SCEQI (Scan String Byte until equal with
Increment)
8.116 SCEQ, SCEQI (Scan String Byte until equal with Increment)
Compare the byte data specified by AH in the space specified by <bank> with the data of AL. The address is incremented and RW0 is decremented until the byte data matches the data or RW0 becomes equal to zero.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. By default,
DTB is assumed.
If RW0 is equal to zero, comparison is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended to handle the
interrupt. After the interrupt has been handled, the execution of the instruction is resumed.
● Assembler format:
SCEQ [<bank>] SCEQI [<bank>]
● Operation:
The following operation is repeated until RW0 = 0 or ((AH)) = (AL) [Byte comparison]:
(AH) ← (AH)+1
(RW0) ← (RW0)–1
● CCR:
I, S, and T: Unchanged
N: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, N is set when the MSB of the last compare operation result is "1", cleared
otherwise.
Z: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, Z is set when a match with the contents of AL is found; cleared when the
instruction terminates with RW0 being set to "0".
V: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when an overflow has occurred as a result of the last compare
operation; cleared otherwise.
C: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when a borrow has occurred as a result of the last compare operation;
cleared otherwise.
I S T N Z V C
– – – * * * *
F2MC-16FX Family
274 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS8.116 SCEQ, SCEQI (Scan String Byte until equal with Increment)
● Byte count and cycle count:
Byte count: 2
Cycle count: 1 cycle when RW0 is zero; 3 cycles when RW0 is 1; and 2+2 × (Number
of times the comparison was performed) in all other cases
● Example:
SCEQ
In this example, the byte data (54H) at the address (031580H) specified by DTB and AH is
compared with the low-order byte data (46H) of AL. Both of them match with the byte data
(46H) at address 031585H.
0 1 0 0RW0
Before execution
0315864 6 0315854 8 031584
0 3DTB
1 5 8 0 0 0 4 6AH AL
4 9 031583
0 0 F ARW0 0 3DTB
1 5 8 6 0 0 4 6AH AL
4 D 0315824 E 0315815 4 031580AH
Memory
After execution
1315864 6 0315854 8 0315844 9 0315834 D 0315824 E 0315815 4 031580
AHMemory
CCR × × × × ×T N Z V C
CCR × 0 1 0 0
T N Z V C
A A
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CHAPTER 8 DETAILED INSTRUCTIONS8.117 SCEQD (Scan String Byte until equal with Decrement)
8.117 SCEQD (Scan String Byte until equal with Decrement)
Compare the byte data specified by AH in the space specified by <bank> with the data of AL. The address is decremented and RW0 is decremented until the byte data matches the data or RW0 becomes equal to zero.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. By default,
DTB is assumed.
If RW0 is equal to zero, comparison is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended to handle the
interrupt. After the interrupt has been handled, the execution of the instruction is resumed.
● Assembler format:
SCEQD [<bank>]
● Operation:
The following operation is repeated until RW0 = 0 or ((AH)) = (AL) [Byte comparison]:
(AH) ← (AH)–1
(RW0) ← (RW0)–1
● CCR:
I, S, and T: Unchanged
N: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, N is set when the MSB of the last compare operation result is "1", cleared
otherwise.
Z: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, Z is set when a match with the contents of AL is found; cleared when the
instruction terminates with RW0 being set to zero.
V: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when an overflow has occurred as a result of the last compare
operation; cleared otherwise.
C: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when a borrow has occurred as a result of the last compare operation;
cleared otherwise.
I S T N Z V C
– – – * * * *
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CHAPTER 8 DETAILED INSTRUCTIONS8.117 SCEQD (Scan String Byte until equal with Decrement)
● Byte count and cycle count:
Byte count: 2
Cycle count: 1 cycle when RW0 is zero; 3 cycles when RW0 is 1; and 2+2 ×
(Number of times the comparison was performed) in all other
cases
Odd address correction: Number of times the comparison was performed
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CHAPTER 8 DETAILED INSTRUCTIONS8.118 SCWEQ, SCWEQI (Scan String Word until equal with
Increment)
8.118 SCWEQ, SCWEQI (Scan String Word until equal with Increment)
Compare the word data specified by AH in the space specified by <bank> with the data of AL. The address is incremented and RW0 is decremented until the word data matches the data or RW0 becomes equal to zero.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. By default,
DTB is assumed.
If RW0 is equal to zero, comparison is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended to handle the
interrupt. After the interrupt has been handled, the execution of the instruction is resumed.
● Assembler format:
SCWEQ [<bank>] SCWEQI [<bank>]
● Operation:
The following operation is repeated until RW0 = 0 or ((AH)) = (AL) [Word comparison]:
(AH) ← (AH)+2
(RW0) ← (RW0)–1
● CCR:
I, S, and T: Unchanged
N: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, N is set when the MSB of the last compare operation result is "1", cleared
otherwise.
Z: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, Z is set when a match with the contents of AL is found; cleared when the
instruction terminates with RW0 being set to zero.
V: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when an overflow has occurred as a result of the last compare
operation; cleared otherwise.
C: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when a borrow has occurred as a result of the last compare operation;
cleared otherwise.
I S T N Z V C
– – – * * * *
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CHAPTER 8 DETAILED INSTRUCTIONS8.118 SCWEQ, SCWEQI (Scan String Word until equal with Increment)
● Byte count and cycle count:
Byte count: 2
Cycle count: 1 cycle when RW0 is zero; 3 cycles when RW0 is 1; and 2+2 ×
(Number of times the comparison was performed) in all other
cases
Odd address correction: Number of times the comparison was performed
● Example:
SCWEQ
In this example, the word data (E1E0H) at the address (DEC000H) specified by DTB and AH is
compared with the word data (00FFH) of AL. RW0 is set to "0", and processing is terminated.
0 0 0 3RW0
Before execution
E 6 DEC006E 5 DEC005E 4 DEC004
D EDTB
AH AL
E 3 DEC003
0 0 0 0RW0 D EDTB
AH AL
E 2 DEC002E 1 DEC001E 0 DEC000AH
Memory
After execution
E 6 DEC006E 5 DEC005E 4 DEC004E 3 DEC003E 2 DEC002E 1 DEC001E 0 DEC000
AH
Memory
C 0 0 0 0 0 F F C 0 0 6 0 0 F F
CCR × × × × ×T N Z V C
CCR × 1 0 0 1
T N Z V C
A A
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CHAPTER 8 DETAILED INSTRUCTIONS8.119 SCWEQD (Scan String Word until Equal with Decrement)
8.119 SCWEQD (Scan String Word until Equal with Decrement)
Compare the word data specified by AH in the space specified by <bank> with the data of AL. The address is decremented and RW0 is decremented until the word data matches the data or RW0 becomes equal to zero.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. By default,
DTB is assumed.
If RW0 is equal to zero, comparison is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended to handle the
interrupt. After the interrupt has been handled, the execution of the instruction is resumed.
● Assembler format:
SCWEQD [<bank>]
● Operation:
The following operation is repeated until RW0 = 0 or ((AH)) = (AL) [Word comparison]:
(AH) ← (AH)–2
(RW0) ← (RW0)–1
● CCR:
I, S, and T: Unchanged
N: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, N is set when the MSB of the last compare operation result is "1", cleared
otherwise.
Z: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, Z is set when a match with the contents of AL is found; cleared when the
instruction terminates with RW0 being set to zero.
V: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when an overflow has occurred as a result of the last compare
operation; cleared otherwise.
C: Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when a borrow has occurred as a result of the last compare operation;
cleared otherwise.
I S T N Z V C
– – – * * * *
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CHAPTER 8 DETAILED INSTRUCTIONS8.119 SCWEQD (Scan String Word until Equal with Decrement)
● Byte count and cycle count:
Byte count: 2
Cycle count: 1 cycle when RW0 is zero; 3 cycles when RW0 is 1; and 2+2 ×
(Number of times the comparison was performed) in all other
cases
Odd address correction: Number of times the comparison was performed
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CHAPTER 8 DETAILED INSTRUCTIONS8.120 SETB (Set Bit)
8.120 SETB (Set Bit)
Set the contents of the bit address specified by the operand to "1".
● Assembler format:
SETB addr16:bp
SETB dir:bp
SETB io:bp
● Operation:
(Operand) b ← 1 [Bit transfer]
● CCR:
None of the flags is changed.
Byte count and cycle count:
● Example:
SETB 0AA55H:4
In this example, bit 4 in data (FFH) at address AA55H is set to "1".
I S T N Z V C
– – – – – – –
Operand addr16:bp dir:bp io:bp
Byte count 4 3 3
Cycle count 3 3 3
Before execution
Memory
× ×6 F AA55× ×
After execution
Memory
× ×7 F AA55× ×
0 0 0 0 0CCRT N Z V C
0 0 0 0 0CCRT N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.121 SUB (Subtract Byte Data of Source from Destination to Destination)
8.121 SUB (Subtract Byte Data of Source from Destination to Destination)
Subtract the byte data specified by the second operand from the byte data specified by the first operand and restore the result in the first operand. If the first operand is A, 00H is transferred to upper byte of AL.
● Assembler format:
SUB A,#imm8 SUB A,dir
SUB A,ear SUB A,eam
SUB ear,A SUB eam,A
● Operation:
(First operand) ← (First operand)–(Second operand) [Byte subtraction]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – * * * *
First operand A A A A ear eam
Second operand #imm8 dir ear eam A A
Byte count 2 2 2 2+ 2 2+
Cycle count 1 2 1 2 1 3
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CHAPTER 8 DETAILED INSTRUCTIONS8.121 SUB (Subtract Byte Data of Source from Destination to
Destination)● Example:
SUB A,#22H
In this example, the 8-bit immediate data (22H) is subtracted from the low-order byte data
(01H) of AL.
Before execution After execution
CCR × × × × ×T N Z V C
CCR × 1 0 0 1
T N Z V C
× × × × 4 9 0 1 A × × × × 0 0 D F A
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.122 SUBC (Subtract Byte Data of AL from AH with Carry to AL)
8.122 SUBC (Subtract Byte Data of AL from AH with Carry to AL)
Subtract the low-order byte data of AL and the carry flag (C) from the low-order byte data of AH and restore the result in AL. 00H is transferred to upper byte of
AL.
● Assembler format:
SUBC A
● Operation:
(AL) ← (AH)–(AL)–(C) [Byte subtraction with a carry]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
SUBC A
In this example, the low-order byte data (D4H) of AL and the carry flag C ("1") are subtracted
from the low-order byte data (30H) of AL. The result is stored in the low-order byte of AL.
I S T N Z V C
– – – * * * *
0 5 0 5 0 0 D 4 A
Before execution
0 5 0 5 0 0 3 0 A
After execution
CCR × × × × ×T N Z V C
CCR × 1 0 0 1
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.123 SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
8.123 SUBC (Subtract Byte Data of Effective Address from Accumulator with Carry to Accumulator)
Subtract the byte data specified by the second operand and the carry flag (C) from the byte data of the accumulator (A) and restore the result in A. 00H is
transferred to upper byte of AL.
● Assembler format:
SUBC A,ear SUBC A,eam
● Operation:
(A) ← (A)–(Second operand)–(C) [Byte subtraction with a carry]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – * * * *
First operand A A
Second operand ear eam
Byte count 2 2+
Cycle count 1 2
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CHAPTER 8 DETAILED INSTRUCTIONS8.123 SUBC (Subtract Byte Data of Effective Address from Accumulator with Carry to Accumulator)
● Example:
SUBC A,R1
In this example, the byte data (54H) of R1 and the C flag ("0") are subtracted from the low-
order byte data (35H) of AL.
Before execution After execution
5 4R1 5 4R1
× × × × 0 0 3 5 A × × × × 0 0 E 1 A
CCR × × × × 0
T N Z V C
CCR × 1 0 0 1
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.124 SUBCW (Subtract Word Data of Effective Address from
Accumulator with Carry to Accumulator)
8.124 SUBCW (Subtract Word Data of Effective Address from Accumulator with Carry to Accumulator)
Subtract the word data specified by the second operand and the carry flag (C) from the low-order word data of the accumulator (A) and restore the result in A.
● Assembler format:
SUBCW A,ear SUBCW A,eam
● Operation:
(A) ← (A)–(Second operand)–(C) [Word subtraction with a carry]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – * * * *
First operand A A
Second operand ear eam
Byte count 2 2+
Cycle count 1 2
Odd address correction 0 1
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CHAPTER 8 DETAILED INSTRUCTIONS8.124 SUBCW (Subtract Word Data of Effective Address from Accumulator with Carry to Accumulator)
● Example:
SUBCW A,0E024H
In this example, the word data (A95BH) at address E024H and the C flag ("1") are subtracted
from the word data (7558H) of AL.
Before execution After execution
Memory Memory
A 9 E025 A 9 E0255 B E024 5 B E024
× × × × 7 5 5 8A × × × × C B F C A
CCR × × × × 1
T N Z V C
CCR × 1 0 0 1
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.125 SUBDC (Subtract Decimal Data of AL from AH with Carry
to AL)
8.125 SUBDC (Subtract Decimal Data of AL from AH with Carry to AL)
Subtract the low-order byte data of AL and the carry flag (C) from the low-order byte data of AH and restore the result in AL. 00H is transferred to upper byte of
AL.
● Assembler format:
SUBDC A
● Operation:
(AL) ← (AH)–(AL)–(C) [Decimal subtraction with a carry]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Undefined
C: Set when a borrow has occurred as a result of the decimal operation, cleared otherwise.
● Byte count and cycle count:
Byte count: 1
Cycle count: 2
● Example:
SUBDC A
In this example, the byte data (86H) of AL and the C flag ("0") are subtracted from the byte
data (86H) of AH in decimal operation.
I S T N Z V C
– – – * * * *
× × 8 6 × × 8 6 A
Before execution
× × 8 6 0 0 0 0 A
After execution
CCR × × × × 0
T N Z V C
CCR × 0 1 × 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.126 SUBL (Subtract Long Word Data of Source from Destination to Destination)
8.126 SUBL (Subtract Long Word Data of Source from Destination to Destination)
Subtract the long word data specified by the second operand from the long word data of the accumulator (A) and restore the result in A.
● Assembler format:
SUBL A,#imm32
SUBL A,ear SUBL A,eam
● Operation:
(First operand) ← (First operand)–(Second operand) [Long word subtraction]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – * * * *
First operand A A A
Second operand #imm32 ear eam
Byte count 5 2 2+
Cycle count 2 2 3
Odd address correction 0 0 1
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CHAPTER 8 DETAILED INSTRUCTIONS8.126 SUBL (Subtract Long Word Data of Source from
Destination to Destination)● Example:
SUBL A,0FD12H
In this example, the long word data (525F31BDH) at address FD12H is subtracted from the
long word data (34B3F201H) of the accumulator (A).
3 4 B 3 F 2 0 1 A
Before execution
E 2 5 4 C 0 4 4 A
After execution
Memory Memory
FD16 FD165 2 FD15 5 2 FD155 F FD14 5 F FD143 1 FD13 3 1 FD13B D FD12 B D FD12
CCR × × × × ×T N Z V C
CCR × 1 0 0 1
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.127 SUBW (Subtract Word Data of Source from Destination to Destination)
8.127 SUBW (Subtract Word Data of Source from Destination to Destination)
Subtract the word data specified by the second operand from the word data specified by the first operand and restore the result in the first operand.
● Assembler format:
SUBW A,#imm16
SUBW A,ear SUBW A,eam
SUBW ear,A SUBW eam,A
● Operation:
(First operand) ← (First operand)–(Second operand) [Word subtraction]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
I S T N Z V C
– – – * * * *
First operand A A A ear eam
Second operand #imm16 ear eam A A
Byte count 3 2 2+ 2 2+
Cycle count 1 1 2 1 3
Odd address correction 0 0 1 0 2
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CHAPTER 8 DETAILED INSTRUCTIONS8.127 SUBW (Subtract Word Data of Source from Destination to
Destination)● Example:
SUBW @RW0+,A
In this example, the word data (3104H) of AL is subtracted from the word data (5DABH) of the
address (E2A4H) specified by the first operand (@RW0+).
× × × × 3 1 0 4 A
E 2 A 4 RW0
× × × × 3 1 0 4 A
E 2 A 6 RW0
Before execution After execution
Memory Memory
5 D E2A5 2 C E2A5A B E2A4 A 7 E2A4
CCR × × × × ×T N Z V C
CCR × 0 0 0 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.128 SUBW (Subtract Word Data of AL from AH to AL)
8.128 SUBW (Subtract Word Data of AL from AH to AL)
Subtract the word data of AL from the word data of AH and restore the result to AL.
● Assembler format:
SUBW A
● Operation:
(AL) ← (AH)–(AL) [Word subtraction]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
SUBW A
In this example, the word data (1019H) of AL is subtracted from the word data (83A2H) of AH.
The subtraction result (7389H) is set to AL.
I S T N Z V C
– – – * * * *
8 3 A 2 1 0 1 9 A
Before execution
8 3 A 2 7 3 8 9 A
After execution
CCR × × × × ×T N Z V C
CCR × 0 0 1 0
T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.129 SWAP (Swap Byte Data of Accumulator)
8.129 SWAP (Swap Byte Data of Accumulator)
Swap the high- and low-order bytes of the word data for the accumulator (A) with each other.
● Assembler format:
SWAP
● Operation:
temp ← AL[7:0]
AL[7:0] ← AL[15:8]
AL[15:8] ← temp [Byte swapping]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
SWAP
In this example, the high-order byte data (06H) of AL is exchanged with the low-order byte
data (90H) of AL.
I S T N Z V C
– – – – – – –
× × × × 0 6 9 0 A
Before execution
× × × × 9 0 0 6 A
After execution
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.130 SWAPW (Swap Word Data of Accumulator)
8.130 SWAPW (Swap Word Data of Accumulator)
Swap the high- and low-order words of the long word data for the accumulator (A) with each other.
● Assembler format:
SWAPW
● Operation:
temp ← (AH)
(AH) ← (AL)
(AL) ← temp [Word swapping]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
SWAPW
In this example, the word data (1986H) of AH is exchanged with the word data (9861H) of AL.
I S T N Z V C
– – – – – – –
1 9 8 6 9 8 6 1 A
Before execution
9 8 6 1 1 9 8 6 A
After execution
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.131 UNLINK (Unlink and Create New Stack Frame)
8.131 UNLINK (Unlink and Create New Stack Frame)
Restore an old frame pointer from a stack.
● Assembler format:
UNLINK
● Operation:
(SP) ← (RW3), (RW3) ← ((SP)), (SP) ← (SP)+2
● CCR:
None of the flags is changed.
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
Odd address correction: 1
● Example:
UNLINK
In this example, the word data (E020H) of RW3 is transferred to SP, and RW3 is popped from
the stack specified by SP.
I S T N Z V C
– – – – – – –
Before execution
Memory
A 04 6 E020
E 0 0 0SP
SP × × E000
E 0 2 0RW3
E 0 2 2SP
A 0 4 6RW3
After execution
Memory
× × E022
4 6 E020
SPA 0 E021
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CHAPTER 8 DETAILED INSTRUCTIONS8.132 WBTc (Wait until Bit Condition Satisfied)
8.132 WBTc (Wait until Bit Condition Satisfied)
This instruction keeps reading data from the bit address specified by the operand until that data satisfies the conditions. Once the data at the specified bit address satisfies the conditions, control is transferred to the instruction subsequent to the WBTc instruction.
● Assembler format:
WBTC io:bp
WBTS io:bp
● Operation:
Data is read from the bit address specified by io:bp until the data satisfies the condition. If the
data from the bit address satisfies the condition, control is transferred to the next instruction.
Interrupts are acceptable while the read operation is repeated with the condition not satisfied.
If an interrupt is generated in this state, the RETI instruction causes control to return to the
WBTc instruction, not to the instruction following the WBTc instruction.
● CCR:
None of the flags is changed.
● Byte count and cycle count:
I S T N Z V C
– – – – – – –
Instruction WBTC WBTS
Condition Bit data=0 Bit data=1
Byte count 3 3
Cycle countUndefined
(Until the condition is satisfied) Undefined
(Until the condition is satisfied)
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CHAPTER 8 DETAILED INSTRUCTIONS8.132 WBTc (Wait until Bit Condition Satisfied)
● Example:
WBTS 34H:7
In this example, wait until bit 7 in the byte data at address 34H is set to "1".
Before execution
Memory
× ×7 F 0034H
× ×
E 1 0 0PC
After execution
Peripheralregister
Data is read from address 34H until bit 7 is set to "1" (because of resource operation, for example). When bit 7 becomes "1", execute the next instruction.
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CHAPTER 8 DETAILED INSTRUCTIONS8.133 XCH (Exchange Byte Data of Source to Destination)
8.133 XCH (Exchange Byte Data of Source to Destination)
Exchange the byte data specified by the first operand with that specified by the second operand.
If the first operand is A, the high-order byte of AL is set to 00H.
● Assembler format:
XCH A,ear XCH A,eam
XCH Ri,ear XCH Ri,eam
● Operation:
temp ← (First operand)
(First operand) ← (Second operand)
(Second operand) ← temp [Byte exchange]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
I S T N Z V C
– – – – – – –
First operand A A Ri Ri
Second operand ear eam ear eam
Byte count 2 2+ 2 2+
Cycle count 1 2 2 2
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CHAPTER 8 DETAILED INSTRUCTIONS8.133 XCH (Exchange Byte Data of Source to Destination)
● Example:
XCH R4,@RW0+
In this example, the byte data (F1H) of R4 is exchanged with the byte data (22H) at address
(0060H) specified by the second operand (@RW0+).
0 0 6 0RW0
F 1R4
Before execution After execution
Memory
0061
Memory
0061
2 2 0060 F 1 0060
0 0 6 1 RW0
2 2R4
RW0RW0
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
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CHAPTER 8 DETAILED INSTRUCTIONS8.134 XCHW (Exchange Word Data of Source to Destination)
8.134 XCHW (Exchange Word Data of Source to Destination)
Exchange the word data specified by the first operand with that specified by the second operand.
● Assembler format:
XCHW A,ear XCHW A,eam
XCHW RWi,ear XCHW RWi,eam
● Operation:
temp ← (First operand)
(First operand) ← (Second operand)
(Second operand) ← temp [Word exchange]
● CCR:
None of the flags is changed.
● Byte count and cycle count:
I S T N Z V C
– – – – – – –
First operand A A RWi RWi
Second operand ear eam ear eam
Byte count 2 2+ 2 2+
Cycle count 1 2 2 2
Odd address correction 0 2 0 2
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CHAPTER 8 DETAILED INSTRUCTIONS8.134 XCHW (Exchange Word Data of Source to Destination)
● Example:
XCHW A,@RW0
In this example, the word data (24B4H) of AL is exchanged with the word data (2D58H) at
address (E001H) specified by the second operand (@RW0).
× × × × 3 4 B 4 A
RW0
× × × × 2 D 5 8 A
RW0
Before execution After execution
Memory Memory
2 D E002 3 4 E0025 8 E001 B 4 E001RW0 RW0
E 0 0 1 E 0 0 1
CCR × × × × ×T N Z V C
CCR × × × × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.135 XOR (Exclusive Or Byte Data of Destination and Source to Destination)
8.135 XOR (Exclusive Or Byte Data of Destination and Source to Destination)
Take the logical exclusive OR of the byte data specified by the first operand and the byte data specified by the second operand and restore the result in the first operand.
● Assembler format:
XOR A,#imm8
XOR A,ear XOR A,eam
XOR ear,A XOR eam,A
● Operation:
(First operand) ← (First operand) xor (Second operand) [Byte logical exclusive OR]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * R –
First operand A A A ear eam
Second operand #imm8 ear eam A A
Byte count 2 2 2+ 2 2+
Cycle count 1 1 2 1 3
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CHAPTER 8 DETAILED INSTRUCTIONS8.135 XOR (Exclusive Or Byte Data of Destination and Source
to Destination)● Example:
XOR 0052H,A
In this example, the logical exclusive OR is taken between the byte data (FAH) at address
0052H and the low-order byte data (55H) of AL.
× × × × 0 0 5 5A
Before execution
× × × × 0 0 5 5A
After execution
Memory Memory
F A 000052 A F 000052
CCR × × × × ×T N Z V C
CCR × 1 0 0 ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.136 XORL (Exclusive Or Long Word Data of Destination and Source to Destination)
8.136 XORL (Exclusive Or Long Word Data of Destination and Source to Destination)
Take the logical exclusive OR of the long word data for the accumulator (A) and that specified by the second operand and restore the result in A.
● Assembler format:
XORL A,ear XORL A,eam
● Operation:
(A) ← (A) xor (Second operand) [Long word logical exclusive OR]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * R –
First operand A A
Second operand ear eam
Byte count 2 2+
Cycle count 2 3
Odd address correction 0 1
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CHAPTER 8 DETAILED INSTRUCTIONS8.136 XORL (Exclusive Or Long Word Data of Destination and
Source to Destination)● Example:
XORL A,0FFF0H
In this example, the logical exclusive OR is taken between the long word data (8252FEACH)
of the accumulator (A) and the long word data (FF55AA00H) at address FFF0H.
8 2 5 2 F E A C A
Before execution
7 D 0 7 5 4 A C A
After execution
Memory Memory
F F FFF35 5 FFF2A A FFF10 0 FFF0
F F FFF35 5 FFF2A A FFF10 0 FFF0
CCR × × × × ×T N Z V C
CCR × 0 0 0 ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.137 XORW (Exclusive Or Word Data of AH and AL to AL)
8.137 XORW (Exclusive Or Word Data of AH and AL to AL)
Take the logical exclusive OR for the word data of AH and that of AL and restore the result in AL.
● Assembler format:
XORW A
● Operation:
(AL) ← (AH) xor (AL) [Word logical exclusive OR]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
XORW A
In this example, the logical exclusive OR is taken between the word data (AB98H) of AL and
the word data (0426H) of AH.
I S T N Z V C
– – – * * R –
0 4 2 6 A B 9 8 A
Before execution
0 4 2 6 A F B E A
After execution
CCR × × × × ×T N Z V C
CCR × 1 0 0 ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.138 XORW (Exclusive Or Word Data of Destination and
Source to Destination)
8.138 XORW (Exclusive Or Word Data of Destination and Source to Destination)
Take the logical exclusive OR of the word data specified by the first operand and the word data specified by the second operand and restore the result in the first operand.
● Assembler format:
XORW A,#imm16
XORW A,ear XORW A,eam
XORW ear,A XORW eam,A
● Operation:
(First operand) ← (First operand) xor (Second operand) [Word logical exclusive OR]
● CCR:
I, S, and T: Unchanged
N: Set when the MSB of the operation result is "1", cleared otherwise.
Z: Set when the operation result is zero, cleared otherwise.
V: Cleared
C: Unchanged
● Byte count and cycle count:
I S T N Z V C
– – – * * R –
First operand A A A ear eam
Second operand #imm16 ear eam A A
Byte count 3 2 2+ 2 2+
Cycle count 1 1 2 1 3
Odd address correction 0 0 1 0 2
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CHAPTER 8 DETAILED INSTRUCTIONS8.138 XORW (Exclusive Or Word Data of Destination and Source to Destination)
● Example:
XORW 0E001H,A
In this example, the logical exclusive OR is taken between the word data (8342H) at address
E001H and the word data (5963H) of AL.
Before execution After execution
Memory Memory
8 3 E0024 2 E001
D A E0022 1 E001
× × × × 5 9 6 3 A × × × × 5 9 6 3 A
CCR × × × × ×T N Z V C
CCR × 1 0 0 ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.139 ZEXT (Zero Extend from Byte Data to Word Data)
8.139 ZEXT (Zero Extend from Byte Data to Word Data)
Transfer 00H to upper byte of AL.
● Assembler format:
ZEXT
● Operation:
AL[15:8] ← 00H
● CCR:
I, S, and T: Unchanged
N: Cleared
Z: Set when the zero-extended data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
ZEXT
In this example, the upper byte of AL is set to 00H.
I S T N Z V C
– – – R * – –
× × × × × × A
Before execution
× × × × 0 0 8 0 A
After execution
8 0
CCR × × × × ×T N Z V C
CCR × 0 0 × ×T N Z V C
AH AL AH AL
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CHAPTER 8 DETAILED INSTRUCTIONS8.140 ZEXTW (Zero Extend from Word Data to Long Word Data)
8.140 ZEXTW (Zero Extend from Word Data to Long Word Data)
Transfer 0000H to AH.
● Assembler format:
ZEXTW
● Operation:
AH ← 0000H
● CCR:
I, S, and T: Unchanged
N: Cleared
Z: Set when the zero-extended data is zero, cleared otherwise.
V and C: Unchanged
● Byte count and cycle count:
Byte count: 1
Cycle count: 1
● Example:
ZEXTW
In this example, AH is set to 0000H.
I S T N Z V C
– – – R * – –
× × × × F F 8 0 A
Before execution
0 0 0 0 F F 8 0A
After execution
CCR × × × × ×T N Z V C
CCR × 0 0 × ×T N Z V C
AH AL AH AL
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APPENDIX
This appendix includes lists and maps of
instructions for the F2MC-16FX CPU.
APPENDIX A Explanation of Instruction Lists
APPENDIX B Instruction Lists (351 Instructions)
APPENDIX C Instruction Maps
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APPENDIX APPENDIX A Explanation of Instruction Lists
APPENDIX A Explanation of Instruction Lists
This section explains items and symbols used in each instruction list included in Instruction Lists (351 Instructions).
A.1 Items Used in Instruction Lists
A.2 Symbols Used in Instruction Lists
A.3 Effective Address Field
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APPENDIXAPPENDIX A Explanation of Instruction Lists
A.1 Items Used in Instruction Lists
Table A.1-1 explains the items used in the instruction lists.
Table A.1-1 Explanation of the Items Used in the Instruction Lists
Item Description
MnemonicUpper-case letters and symbols: Described as they appear in assembler.Lower-case letters: Replaced when described in assembler.Numbers after lower-case letters: Indicate the bit width within the instruction.
# Indicates the byte count.
~ Indicates the cycle count.
BIndicates the cycle count required for correcting odd addresses.The actual cycle count during instruction execution is the correction value added to the value in the "~" column.
Operation Indicates operation of instruction.
LH
Indicates special operations involving bits 15 through 08 of the accumulator.Z: Transfers "0".X: Sign-extended transfer through sign extension.- : Transfers nothing.
AH
Indicates special operations involving the high-order 16 bits in the accumulator.*: Transfers from AL to AH.- : No transferZ: Transfers 00H to AH.X: Transfers 00H or FFH to AH using sign extension AL.
I Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry).
*: Changes due to execution of instruction.- : No changeS: Set by execution of instruction.R: Clear by execution of instruction.
S
T
N
Z
V
C
RMW
Indicates whether the instruction is a read-modify-write instruction (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.).*: Instruction is a read-modify-write instruction.-: Instruction is not a read-modify-write instruction.Note:
A read-modify-write instruction cannot be used on addresses of the I/O register, etc., that have different meanings depending on whether they are read or written.
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APPENDIX APPENDIX A Explanation of Instruction Lists
■ Execution cycle countThe cycle count required to execute instructions (execution cycle count) is the summation of
the cycle count of each instruction and the odd address correction value determined by access
conditions for data. At the actual instruction execution time, the execution cycle count may
become larger than the calculated value due to the instruction fetch delay, the data access
conflict, etc. Especially, when performing instruction fetch and data access from an external
bus by using the external bus interface, the execution cycle count becomes larger than the
calculated value.
■ Odd address correction For some instructions, the execution cycles increases when performing data access to odd
addresses. The execution cycles that increases at data access time to odd addresses is shown
under the title of "odd address correction" in item B in the instruction list.
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APPENDIXAPPENDIX A Explanation of Instruction Lists
A.2 Symbols Used in Instruction Lists
Table A.2-1 explains the symbols used in the instruction lists.
■ Explanation of the Symbols Used in the Instruction Lists
Table A.2-1 Explanation of the Symbols Used in the Instruction Lists (1 / 2)
Symbol Explanation
A
32 bit accumulator The bit length used is different for each instruction.
Byte: Lower 8 bits of ALWord: 16 bits of ALLong Word: 32 bits of AL and AH
AH Upper 16 bits of A
AL Lower 16 bits of A
SP Stack pointer (USP or SSP)
PC Program counter
PCB Program bank register
DTB Data bank register
ADB Additional data bank register
SSB System stack bank register
USB User stack bank register
DPR Direct page register
brg1 DTB, ADB, SSB, USB, DPR, PCB
brg2 DTB, ADB, SSB, USB, DPR
Ri R0, R1, R2, R3, R4, R5, R6, R7
Rj R0, R1, R2, R3
RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj RW0, RW1, RW2, RW3
RLi RL0, RL1, RL2, RL3
dir Abbreviated direct addressing
addr16 Direct addressing
addr24 Physical direct addressing
ad24 0-15 Bit0 to bit15 of address 24
ad24 16-23 Bit16 to bit23 of address 24
io I/O area (000000H to 0000FFH)
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APPENDIX APPENDIX A Explanation of Instruction Lists
imm4 4-bit immediate data
imm8 8-bit immediate data
imm16 16-bit immediate data
imm32 32-bit immediate data
ext (imm8) 16-bit data signed and extended from 8-bit immediate data
disp8 8-bit displacement
disp16 16-bit displacement
bp Bit offset value
vct4 Vector number (0 to 15)
vct8 Vector number (0 to 255)
( ) b Bit address
rel Branch specification relative to PC
ear Effective addressing (codes 00 to 07)
eam Effective addressing (codes 08 to 1F)
rlst Register list
Table A.2-1 Explanation of the Symbols Used in the Instruction Lists (2 / 2)
Symbol Explanation
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APPENDIXAPPENDIX A Explanation of Instruction Lists
A.3 Effective Address Field
Table A.3-1 lists address formats used in the effective address field.
Table A.3-1 Effective Address Field
Code Notation Address formatByte count of address
expansion part*
00 R0 RW0 RL0
Register direct Note: The general purpose register name
on the left notation corresponds to the byte, word and long-word types.
-
01 R1 RW1 (RL0)
02 R2 RW2 RL1
03 R3 RW3 (RL1)
04 R4 RW4 RL2
05 R5 RW5 (RL2)
06 R6 RW6 RL3
07 R7 RW7 (RL3)
08 @RW0
Register indirect 009 @RW1
0A @RW2
0B @RW3
0C @RW0+
Register indirect with post-incrementing 00D @RW1+
0E @RW2+
0F @RW3+
10 @RW0+disp8
Register indirect with 8-bit displacement 1
11 @RW1+disp8
12 @RW2+disp8
13 @RW3+disp8
14 @RW4+disp8
15 @RW5+disp8
16 @RW6+disp8
17 @RW7+disp8
18 @RW0+disp16
Register indirect with 16-bit displacement
219 @RW1+disp16
1A @RW2+disp16
1B @RW3+disp16
1C @RW0+RW7 Register indirect with index 0
1D @RW1+RW7 Register indirect with index 0
1E @PC+disp16 PC indirect with 16-bit displacement 2
1F addr16 Direct address 2*: The byte count of the address expansion part is shown in the "#" (byte count) column. "numeric value+", such as "2+",
written in the detailed instructions indicates the byte count of the address expansion part added to the value.
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APPENDIX APPENDIX B Instruction Lists (351 Instructions)
APPENDIX B Instruction Lists (351 Instructions)
Instruction lists used by the assembler is shown here. For each item and symbol in the instruction lists, see “APPENDIX A Explanation of Instruction Lists”.
Table B-1 Transfer Instructions (Byte) : 41 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
MOV A, dir 2 1 0 byte (A) ← (dir) Z * - - - * * - - -
MOV A, addr16 3 1 0 byte (A) ← (addr16) Z * - - - * * - - -
MOV A, Ri 1 1 0 byte (A) ← (Ri) Z * - - - * * - - -
MOV A, ear 2 1 0 byte (A) ← (ear) Z * - - - * * - - -
MOV A, eam 2+ 1 0 byte (A) ← (eam) Z * - - - * * - - -
MOV A, io 2 1 0 byte (A) ← (io) Z * - - - * * - - -
MOV A, #imm8 2 1 0 byte (A) ← imm8 Z * - - - * * - - -
MOV A, @A 2 1 0 byte (A) ← ((A)) Z - - - - * * - - -
MOV A, @RLi+disp8 3 1 0 byte (A) ← ((RLi)+disp8) Z * - - - * * - - -
MOVN A, #imm4 1 1 0 byte (A) ← imm4 Z * - - - R * - - -
MOVX A, dir 2 1 0 byte (A) ← (dir) X * - - - * * - - -
MOVX A, addr16 3 1 0 byte (A) ← (addr16) X * - - - * * - - -
MOVX A, Ri 1 1 0 byte (A) ← (Ri) X * - - - * * - - -
MOVX A, ear 2 1 0 byte (A) ← (ear) X * - - - * * - - -
MOVX A, eam 2+ 1 0 byte (A) ← (eam) X * - - - * * - - -
MOVX A, io 2 1 0 byte (A) ← (io) X * - - - * * - - -
MOVX A, #imm8 2 1 0 byte (A) ← imm8 X * - - - * * - - -
MOVX A, @A 2 1 0 byte (A) ← ((A)) X - - - - * * - - -
MOVX A, @RWi+disp8 2 1 0 byte (A) ← ((RWi)+disp8) X * - - - * * - - -
MOVX A, @RLi+disp8 3 1 0 byte (A) ← ((RLi)+disp8) X * - - - * * - - -
MOV dir, A 2 1 0 byte (dir) ← (A) - - - - - * * - - -
MOV addr16, A 3 1 0 byte (addr16) ← (A) - - - - - * * - - -
MOV Ri, A 1 1 0 byte (Ri) ← (A) - - - - - * * - - -
MOV ear, A 2 1 0 byte (ear) ← (A) - - - - - * * - - -
MOV eam, A 2+ 1 0 byte (eam) ← (A) - - - - - * * - - -
MOV io, A 2 1 0 byte (io) ← (A) - - - - - * * - - -
MOV @RLi+disp8, A 3 1 0 byte ((RLi)+disp8) ← (A) - - - - - * * - - -
MOV Ri, ear 2 1 0 byte (Ri) ← (ear) - - - - - * * - - -
MOV Ri, eam 2+ 1 0 byte (Ri) ← (eam) - - - - - * * - - -
MOV ear, Ri 2 1 0 byte (ear) ← (Ri) - - - - - * * - - -
MOV eam, Ri 2+ 1 0 byte (eam) ← (Ri) - - - - - * * - - -
MOV Ri, #imm8 2 1 0 byte (Ri) ← imm8 - - - - - * * - - -
MOV io, #imm8 3 1 0 byte (io) ← imm8 - - - - - - - - - -
MOV dir, #imm8 3 1 0 byte (dir) ← imm8 - - - - - - - - - -
MOV ear, #imm8 3 1 0 byte (ear) ← imm8 - - - - - * * - - -
MOV eam, #imm8 3+ 1 / 2*1 0 byte (eam) ← imm8 - - - - - - - - - -
MOV @AL, AH 2 1 0 byte ((A)) ← (AH) - - - - - * * - - -
XCH A, ear 2 1 0 byte (A) ←→ (ear) Z - - - - - - - - -
XCH A, eam 2+ 2 0 byte (A) ←→ (eam) Z - - - - - - - - -
XCH Ri, ear 2 2 0 byte (Ri) ←→ (ear) - - - - - - - - - -
XCH Ri, eam 2+ 2 0 byte (Ri) ←→ (eam) - - - - - - - - - -
*1 : 1 cycle in case of eam is Ri/@RWi/@RWi+/@RWi+RW7, 2 cycles in other case.
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APPENDIXAPPENDIX B Instruction Lists (351 Instructions)
Table B-2 Transfer Instructions (Word, Long Word) : 38 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
MOVW A, dir 2 1 1 word (A) ← (dir) - * - - - * * - - -
MOVW A, addr16 3 1 1 word (A) ← (addr16) - * - - - * * - - -
MOVW A, SP 1 1 0 word (A) ← (SP) - * - - - * * - - -
MOVW A, RWi 1 1 0 word (A) ← (RWi) - * - - - * * - - -
MOVW A, ear 2 1 0 word (A) ← (ear) - * - - - * * - - -
MOVW A, eam 2+ 1 1 word (A) ← (eam) - * - - - * * - - -
MOVW A, io 2 1 1 word (A) ← (io) - * - - - * * - - -
MOVW A, @A 2 1 1 word (A) ← ((A)) - - - - - * * - - -
MOVW A, #imm16 3 1 0 word (A) ← imm16 - * - - - * * - - -
MOVW A, @RWi+disp8 2 1 1 word (A) ← ((RWi)+disp8) - * - - - * * - - -
MOVW A, @RLi+disp8 3 1 1 word (A) ← ((RLi)+disp8) - * - - - * * - - -
MOVW dir, A 2 1 1 word (dir) ← (A) - - - - - * * - - -
MOVW addr16, A 3 1 1 word (addr16) ← (A) - - - - - * * - - -
MOVW SP, A 1 1 0 word (SP) ← (A) - - - - - * * - - -
MOVW RWi, A 1 1 0 word (RWi) ← (A) - - - - - * * - - -
MOVW ear, A 2 1 0 word (ear) ← (A) - - - - - * * - - -
MOVW eam, A 2+ 1 1 word (eam) ← (A) - - - - - * * - - -
MOVW io, A 2 1 1 word (io) ← (A) - - - - - * * - - -
MOVW @RWi+disp8, A 2 1 1 word ((RWi)+disp8) ← (A) - - - - - * * - - -
MOVW @RLi+disp8, A 3 1 1 word ((RLi)+disp8) ← (A) - - - - - * * - - -
MOVW RWi, ear 2 1 0 word (RWi) ← (ear) - - - - - * * - - -
MOVW RWi, eam 2+ 1 1 word (RWi) ← (eam) - - - - - * * - - -
MOVW ear, RWi 2 1 0 word (ear) ← (RWi) - - - - - * * - - -
MOVW eam, RWi 2+ 1 1 word (eam) ← (RWi) - - - - - * * - - -
MOVW RWi, #imm16 3 1 0 word (RWi) ← imm16 - - - - - * * - - -
MOVW io, #imm16 4 1 1 word (io) ← imm16 - - - - - - - - - -
MOVW ear, #imm16 4 2 0 word (ear) ← imm16 - - - - - * * - - -
MOVW eam, #imm16 4+ 2 1 word (eam) ← imm16 - - - - - - - - - -
MOVW @AL, AH 2 1 1 word ((A)) ← (AH) - - - - - * * - - -
XCHW A, ear 2 1 0 word (A) ←→ ear - - - - - - - - - -
XCHW A, eam 2+ 2 2 word (A) ←→ eam - - - - - - - - - -
XCHW RWi, ear 2 2 0 word (RWi) ←→ ear - - - - - - - - - -
XCHW RWi, eam 2+ 2 2 word (RWi) ←→ eam - - - - - - - - - -
MOVL A, ear 2 2 0 long (A) ← (ear) - - - - - * * - - -
MOVL A, eam 2+ 2 1 long (A) ← (eam) - - - - - * * - - -
MOVL A, #imm32 5 2 0 long (A) ← imm32 - - - - - * * - - -
MOVL ear, A 2 2 0 long (ear) ← (A) - - - - - * * - - -
MOVL eam, A 2+ 3 / 2*1 1 long (eam) ← (A) - - - - - * * - - -
*1 : 3 cycle in case of eam is @RWi+, 2 cycles in other case.
F2MC-16FX Family
322 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX B Instruction Lists (351 Instructions)
Table B-3 Addition/Subtraction Instructions (Byte, Word, Long Word) : 42 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
ADD A, #imm8 2 1 0 byte (A) ← (A) + imm8 Z - - - - * * * * -
ADD A, dir 2 2 0 byte (A) ← (A) + (dir) Z - - - - * * * * -
ADD A, ear 2 1 0 byte (A) ← (A) + (ear) Z - - - - * * * * -
ADD A, eam 2+ 2 0 byte (A) ← (A) + (eam) Z - - - - * * * * -
ADD ear, A 2 1 0 byte (ear) ← (ear) + (A) - - - - - * * * * -
ADD eam, A 2+ 3 0 byte (eam) ← (eam) + (A) Z - - - - * * * * *
ADDC A 1 1 0 byte (A) ← (AH) + (AL) + (C) Z - - - - * * * * -
ADDC A, ear 2 1 0 byte (A) ← (A) + (ear) + (C) Z - - - - * * * * -
ADDC A, eam 2+ 2 0 byte (A) ← (A) + (eam) + (C) Z - - - - * * * * -
ADDDC A 1 2 0 byte (A) ← (AH) + (AL) + (C) : decimal Z - - - - * * * * -
SUB A, #imm8 2 1 0 byte (A) ← (A) - imm8 Z - - - - * * * * -
SUB A, dir 2 2 0 byte (A) ← (A) - (dir) Z - - - - * * * * -
SUB A, ear 2 1 0 byte (A) ← (A) - (ear) Z - - - - * * * * -
SUB A, eam 2+ 2 0 byte (A) ← (A) - (eam) Z - - - - * * * * -
SUB ear, A 2 1 0 byte (ear) ← (ear) - (A) - - - - - * * * * -
SUB eam, A 2+ 3 0 byte (eam) ← (eam) - (A) - - - - - * * * * *
SUBC A 1 1 0 byte (A) ← (AH) - (AL) - (C) Z - - - - * * * * -
SUBC A, ear 2 1 0 byte (A) ← (A) - (ear) - (C) Z - - - - * * * * -
SUBC A, eam 2+ 2 0 byte (A) ← (A) - (eam) - (C) Z - - - - * * * * -
SUBDC A 1 2 0 byte (A) ← (AH) - (AL) - (C) : decimal Z - - - - * * * * -
ADDW A 1 1 0 word (A) ← (AH) + (AL) - - - - - * * * * -
ADDW A, ear 2 1 0 word (A) ← (A) + (ear) - - - - - * * * * -
ADDW A, eam 2+ 2 1 word (A) ← (A) + (eam) - - - - - * * * * -
ADDW A, #imm16 3 1 0 word (A) ← (A) + imm16 - - - - - * * * * -
ADDW ear, A 2 1 0 word (ear) ← (ear) + (A) - - - - - * * * * -
ADDW eam, A 2+ 3 2 word (eam) ← (eam) + (A) - - - - - * * * * *
ADDCW A, ear 2 1 0 word (A) ← (A) + (ear) + (C) - - - - - * * * * -
ADDCW A, eam 2+ 2 1 word (A) ← (A) + (eam) + (C) - - - - - * * * * -
SUBW A 1 1 0 word (A) ← (AH) - (AL) - - - - - * * * * -
SUBW A, ear 2 1 0 word (A) ← (A) - (ear) - - - - - * * * * -
SUBW A, eam 2+ 2 1 word (A) ← (A) - (eam) - - - - - * * * * -
SUBW A, #imm16 3 1 0 word (A) ← (A) - imm16 - - - - - * * * * -
SUBW ear, A 2 1 0 word (ear) ← (ear) - (A) - - - - - * * * * -
SUBW eam, A 2+ 3 2 word (eam) ← (eam) - (A) - - - - - * * * * *
SUBCW A, ear 2 1 0 word (A) ← (A) - (ear) - (C) - - - - - * * * * -
SUBCW A, eam 2+ 2 1 word (A) ← (A) - (eam) - (C) - - - - - * * * * -
ADDL A, ear 2 2 0 long (A) ← (A) + (ear) - - - - - * * * * -
ADDL A, eam 2+ 3 1 long (A) ← (A) + (eam) - - - - - * * * * -
ADDL A, #imm32 5 2 0 long (A) ← (A) + imm32 - - - - - * * * * -
SUBL A, ear 2 2 0 long (A) ← (A) - (ear) - - - - - * * * * -
SUBL A, eam 2+ 3 1 long (A) ← (A) - (eam) - - - - - * * * * -
SUBL A, #imm32 5 2 0 long (A) ← (A) - imm32 - - - - - * * * * -
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 323
APPENDIXAPPENDIX B Instruction Lists (351 Instructions)
Table B-4 Increment/Decrement Instructions (Byte, Word, Long Word) : 12 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
INC ear 2 1 0 byte (ear) ← (ear) + 1 - - - - - * * * - -
INC eam 2+ 3 0 byte (eam) ← (eam) + 1 - - - - - * * * - *
DEC ear 2 1 0 byte (ear) ← (ear) - 1 - - - - - * * * - -
DEC eam 2+ 3 0 byte (eam) ← (eam) - 1 - - - - - * * * - *
INCW ear 2 1 0 word (ear) ← (ear) + 1 - - - - - * * * - -
INCW eam 2+ 3 2 word (eam) ← (eam) + 1 - - - - - * * * - *
DECW ear 2 1 0 word (ear) ← (ear) - 1 - - - - - * * * - -
DECW eam 2+ 3 2 word (eam) ← (eam) - 1 - - - - - * * * - *
INCL ear 2 2 0 long (ear) ← (ear) + 1 - - - - - * * * - -
INCL eam 2+ 4 2 long (eam) ← (eam) + 1 - - - - - * * * - *
DECL ear 2 2 0 long (ear) ← (ear) - 1 - - - - - * * * - -
DECL eam 2+ 4 2 long (eam) ← (eam) - 1 - - - - - * * * - *
F2MC-16FX Family
324 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX B Instruction Lists (351 Instructions)
Table B-5 Compare Instructions (Byte, Word, Long Word) : 11 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
CMP A 1 1 0 byte (AH) - (AL) - - - - - * * * * -
CMP A, ear 2 1 0 byte (A) - (ear) - - - - - * * * * -
CMP A, eam 2+ 2 0 byte (A) - (eam) - - - - - * * * * -
CMP A, #imm8 2 1 0 byte (A) - imm8 - - - - - * * * * -
CMPW A 1 1 0 word (AH) - (AL) - - - - - * * * * -
CMPW A, ear 2 1 0 word (A) - (ear) - - - - - * * * * -
CMPW A, eam 2+ 2 1 word (A) - (eam) - - - - - * * * * -
CMPW A, #imm16 3 1 0 word (A) - imm16 - - - - - * * * * -
CMPL A, ear 2 2 0 long (A) - (ear) - - - - - * * * * -
CMPL A, eam 2+ 3 1 long (A) - (eam) - - - - - * * * * -
CMPL A, #imm32 5 2 0 long (A) - imm32 - - - - - * * * * -
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 325
APPENDIXAPPENDIX B Instruction Lists (351 Instructions)
Table B-6 Unsigned Multiplication/Division Instructions (Word, Long Word) : 11 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
DIVU A 1 4 / 9*1 0word (AH) / byte (AL)quotient → byte (AL), remainder → byte (AH)
- - - - - - - * * -
DIVU A, ear 2 4 / 9*1 0word (A) / byte (ear) quotient → byte (A), remainder → byte (ear)
- - - - - - - * * -
DIVU A, eam 2+ 5 / 11*2 0word (A) / byte (eam)quotient → byte (A), remainder → byte (eam)
- - - - - - - * * -
DIVUW A, ear 2 4 / 17*3 0long (A) / word (ear)quotient → word (A), remainder → word (ear)
- - - - - - - * * -
DIVUW A, eam 2+ 5 / 19*4 2long (A) / word (eam)quotient → word (A), remainder → word (eam)
- - - - - - - * * -
MULU A 1 2 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - -
MULU A, ear 2 2 0 byte (A) * byte (ear) → word (A) - - - - - - - - - -
MULU A, eam 2+ 3 0 byte (A) * byte (eam) → word (A) - - - - - - - - - -
MULUW A 1 4 0 word (AH) * word (AL) → long (A) - - - - - - - - - -
MULUW A, ear 2 4 0 word (A) * word (ear) → long (A) - - - - - - - - - -
MULUW A, eam 2+ 5 1 word (A) * word (eam) → long (A) - - - - - - - - - -
*1 : 4 cycles in case of overflow, 9 cycles in other case.
*2 : 5 cycles in case of overflow, 11 cycles in other case.
*3 : 4 cycles in case of overflow, 17 cycles in other case.
*4 : 5 cycles in case of overflow, 19 cycles in other case.
F2MC-16FX Family
326 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX B Instruction Lists (351 Instructions)
Table B-7 Signed Multiplication/Division Instructions (Word, Long Word) : 11 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
DIV A 2 5 / 11*1 0word (AH) / byte (AL)quotient → byte (AL), remainder → byte (AH)
Z - - - - - - * * -
DIV A, ear 2 5 / 11*1 0word (A) / byte (ear)quotient → byte (A), remainder → byte (ear)
Z - - - - - - * * -
DIV A, eam 2+ 6 / 13*2 0word (A) / byte (eam)quotient → byte (A), remainder → byte (eam)
Z - - - - - - * * -
DIVW A, ear 2 5 / 19*3 0long (A) / word (ear)quotient → word (A), remainder → word (ear)
- - - - - - - * * -
DIVW A, eam 2+ 6 / 21*4 2long (A) / word (eam)quotient → word (A), remainder → word (eam)
- - - - - - - * * -
MUL A 2 4 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - -
MUL A, ear 2 4 0 byte (A) * byte (ear) → word (A) - - - - - - - - - -
MUL A, eam 2+ 5 0 byte (A) * byte (eam) → word (A) - - - - - - - - - -
MULW A 2 6 0 word (AH) * word (AL) → long (A) - - - - - - - - - -
MULW A, ear 2 6 0 word (A) * word (ear) → long (A) - - - - - - - - - -
MULW A, eam 2+ 7 1 word (A) * word (eam) → long (A) - - - - - - - - - -
*1 : 5 cycles in case of overflow, 11 cycles in other case.
*2 : 6 cycles in case of overflow, 13 cycles in other case.
*3 : 5 cycles in case of overflow, 19 cycles in other case.
*4 : 6 cycles in case of overflow, 21 cycles in other case.
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 327
APPENDIXAPPENDIX B Instruction Lists (351 Instructions)
Table B-8 Logic Instructions (Byte, Word, Long Word) : 45 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
AND A, #imm8 2 1 0 byte (A) ← (A) and imm8 - - - - - * * R - -
AND A, ear 2 1 0 byte (A) ← (A) and (ear) - - - - - * * R - -
AND A, eam 2+ 2 0 byte (A) ← (A) and (eam) - - - - - * * R - -
AND ear, A 2 1 0 byte (ear) ← (ear) and (A) - - - - - * * R - -
AND eam, A 2+ 3 0 byte (eam) ← (eam) and (A) - - - - - * * R - *
OR A, #imm8 2 1 0 byte (A) ← (A) or imm8 - - - - - * * R - -
OR A, ear 2 1 0 byte (A) ← (A) or (ear) - - - - - * * R - -
OR A, eam 2+ 2 0 byte (A) ← (A) or (eam) - - - - - * * R - -
OR ear, A 2 1 0 byte (ear) ← (ear) or (A) - - - - - * * R - -
OR eam, A 2+ 3 0 byte (eam) ← (eam) or (A) - - - - - * * R - *
XOR A, #imm8 2 1 0 byte (A) ← (A) xor imm8 - - - - - * * R - -
XOR A, ear 2 1 0 byte (A) ← (A) xor (ear) - - - - - * * R - -
XOR A, eam 2+ 2 0 byte (A) ← (A) xor (eam) - - - - - * * R - -
XOR ear, A 2 1 0 byte (ear) ← (ear) xor (A) - - - - - * * R - -
XOR eam, A 2+ 3 0 byte (eam) ← (eam) xor (A) - - - - - * * R - *
NOT A 1 1 0 byte (A) ← not (A) - - - - - * * R - -
NOT ear 2 1 0 byte (ear) ← not (ear) - - - - - * * R - -
NOT eam 2+ 3 0 byte (eam) ← not (eam) - - - - - * * R - *
ANDW A 1 1 0 word (A) ← (AH) and (A) - - - - - * * R - -
ANDW A, #imm16 3 1 0 word (A) ← (A) and imm16 - - - - - * * R - -
ANDW A, ear 2 1 0 word (A) ← (A) and (ear) - - - - - * * R - -
ANDW A, eam 2+ 2 1 word (A) ← (A) and (eam) - - - - - * * R - -
ANDW ear, A 2 1 0 word (ear) ← (ear) and (A) - - - - - * * R - -
ANDW eam, A 2+ 3 2 word (eam) ← (eam) and (A) - - - - - * * R - *
ORW A 1 1 0 word (A) ← (AH) or (A) - - - - - * * R - -
ORW A, #imm16 3 1 0 word (A) ← (A) or imm16 - - - - - * * R - -
ORW A, ear 2 1 0 word (A) ← (A) or (ear) - - - - - * * R - -
ORW A, eam 2+ 2 1 word (A) ← (A) or (eam) - - - - - * * R - -
ORW ear, A 2 1 0 word (ear) ← (ear) or (A) - - - - - * * R - -
ORW eam, A 2+ 3 2 word (eam) ← (eam) or (A) - - - - - * * R - *
XORW A 1 1 0 word (A) ← (AH) xor (A) - - - - - * * R - -
XORW A, #imm16 3 1 0 word (A) ← (A) xor imm16 - - - - - * * R - -
XORW A, ear 2 1 0 word (A) ← (A) xor (ear) - - - - - * * R - -
XORW A, eam 2+ 2 1 word (A) ← (A) xor (eam) - - - - - * * R - -
XORW ear, A 2 1 0 word (ear) ← (ear) xor (A) - - - - - * * R - -
XORW eam, A 2+ 3 2 word (eam) ← (eam) xor (A) - - - - - * * R - *
NOTW A 1 1 0 word (A) ← not (A) - - - - - * * R - -
NOTW ear 2 1 0 word (ear) ← not (ear) - - - - - * * R - -
NOTW eam 2+ 3 2 word (eam) ← not (eam) - - - - - * * R - *
ANDL A, ear 2 2 0 long (A) ← (A) and (ear) - - - - - * * R - -
ANDL A, eam 2+ 3 1 long (A) ← (A) and (eam) - - - - - * * R - -
ORL A, ear 2 2 0 long (A) ← (A) or (ear) - - - - - * * R - -
ORL A, eam 2+ 3 1 long (A) ← (A) or (eam) - - - - - * * R - -
XORL A, ear 2 2 0 long (A) ← (A) xor (ear) - - - - - * * R - -
XORL A, eam 2+ 3 1 long (A) ← (A) xor (eam) - - - - - * * R - -
F2MC-16FX Family
328 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX B Instruction Lists (351 Instructions)
Table B-9 Sign Inversion Instructions (Byte, Word) : 6 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
NEG A 1 1 0 byte (A) ← 0 - (A) X - - - - * * * * -
NEG ear 2 1 0 byte (ear) ← 0 - (ear) - - - - - * * * * -
NEG eam 2+ 3 0 byte (eam) ← 0 - (eam) - - - - - * * * * *
NEGW A 1 1 0 word (A) ← 0 - (A) - - - - - * * * * -
NEGW ear 2 1 0 word (ear) ← 0 - (ear) - - - - - * * * * -
NEGW eam 2+ 3 2 word (eam) ← 0 - (eam) - - - - - * * * * *
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 329
APPENDIXAPPENDIX B Instruction Lists (351 Instructions)
Table B-10 Shift/Normalization Instructions (Byte, Word, Long Word) : 19 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
RORC A 2 1 0 byte (A) ← Right rotation of (A) with carry - - - - - * * - * -
RORC ear 2 1 0 byte (ear) ← Right rotation of (ear) with carry - - - - - * * - * -
RORC eam 2+ 3 0 byte (eam) ← Right rotation of (eam) with carry - - - - - * * - * *
ROLC A 2 1 0 byte (A) ← Left rotation of (A) with carry - - - - - * * - * -
ROLC ear 2 1 0 byte (ear) ← Right rotation of (ear) with carry - - - - - * * - * -
ROLC eam 2+ 3 0 byte (eam) ← Right rotation of (eam) with carry - - - - - * * - * *
ASR A, R0 2 1 0 byte (A) ← Arithmetic right barrel shift of (A) , (R0) bits - - - - * * * - * -
LSR A, R0 2 1 0 byte (A) ← Logical right barrel shift of (A) , (R0) bits - - - - * * * - * -
LSL A, R0 2 1 0 byte (A) ← Logical left barrel shift of (A) , (R0) bits - - - - - * * - * -
ASRW A 1 1 0 word (A) ← Arithmetic right shift of (A) , 1 bit - - - - * * * - * -
LSRW/SHRW A 1 1 0 word (A) ← Logical right shift of (A) , 1 bits - - - - * R * - * -
LSLW/SHLW A 1 1 0 word (A) ← Logical left shift of (A) , 1 bits - - - - - * * - * -
ASRW A, R0 2 1 0 word (A) ← Arithmetic right barrel shift of (A) , (R0) bits - - - - * * * - * -
LSRW A, R0 2 1 0 word (A) ← Logical right barrel shift of (A) , (R0) bits - - - - * * * - * -
LSLW A, R0 2 1 0 word (A) ← Logical left barrel shift of (A) , (R0) bits - - - - - * * - * -
ASRL A, R0 2 1 0 long (A) ← Arithmetic right barrel shift of (A) , (R0) bits - - - - * * * - * -
LSRL A, R0 2 1 0 long (A) ← Logical right barrel shift of (A) , (R0) bits - - - - * * * - * -
LSLL A, R0 2 1 0 long (A) ← Logical left barrel shift of (A) , (R0) bits - - - - - * * - * -
NRML A, R0 2 1 0long (A) ← Shift left (A) until the MSB is "1"byte (R0) ← Shift count (the first "1" bit position)
- - - - - - * - - -
F2MC-16FX Family
330 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX B Instruction Lists (351 Instructions)
Table B-11 Branch Instructions 1 : 31 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
BZ/BEQ rel 2 2 0 Branch on (Z) = 1 - - - - - - - - - -
BNZ/BNE rel 2 2 0 Branch on (Z) = 0 - - - - - - - - - -
BC/BLO rel 2 2 0 Branch on (C) = 1 - - - - - - - - - -
BNC/BHS rel 2 2 0 Branch on (C) = 0 - - - - - - - - - -
BN rel 2 2 0 Branch on (N) = 1 - - - - - - - - - -
BP rel 2 2 0 Branch on (N) = 0 - - - - - - - - - -
BV rel 2 2 0 Branch on (V) = 1 - - - - - - - - - -
BNV rel 2 2 0 Branch on (V) = 0 - - - - - - - - - -
BT rel 2 2 0 Branch on (T) = 1 - - - - - - - - - -
BNT rel 2 2 0 Branch on (T) = 0 - - - - - - - - - -
BLT rel 2 2 0 Branch on (V) xor (N) = 1 - - - - - - - - - -
BGE rel 2 2 0 Branch on (V) xor (N) = 0 - - - - - - - - - -
BLE rel 2 2 0 Branch on ((V) xor (N)) or (Z) = 1 - - - - - - - - - -
BGT rel 2 2 0 Branch on ((V) xor (N)) or (Z) = 0 - - - - - - - - - -
BLS rel 2 2 0 Branch on (C) or (Z) = 1 - - - - - - - - - -
BHI rel 2 2 0 Branch on (C) or (Z) = 0 - - - - - - - - - -
BRA rel 2 2 0 Branch always (Unconditional branch) - - - - - - - - - -
JMP @A 1 2 0 word (PC) ← (A) - - - - - - - - - -
JMP addr16 3 2 0 word (PC) ← addr16 - - - - - - - - - -
JMP @ear 2 2 0 word (PC) ← (ear) - - - - - - - - - -
JMP @eam 2+ 4 1 word (PC) ← (eam) - - - - - - - - - -
JMPP @ear 2 3 0 word (PC) ← (ear), (PCB) ← (ear+2) - - - - - - - - - -
JMPP @eam 2+ 5 1 word (PC) ← (eam), (PCB) ← (eam+2) - - - - - - - - - -
JMPP addr24 4 2 0 word (PC) ← ad24 0-15, (PCB) ← ad24 16-23 - - - - - - - - - -
CALL @ear 2 3 1word (SP) ← (SP)-2, ((SP)) ← (PC)+2word (PC) ← (ear)
- - - - - - - - - -
CALL @eam 2+ 5 1+1*a word (SP) ← (SP)-2, ((SP)) ← (PC)+ 2+word (PC) ← (eam)
- - - - - - - - - -
CALL addr16 3 3 1word (SP) ← (SP)-2, ((SP)) ← (PC)+3word (PC) ← addr16
- - - - - - - - - -
CALLV #vct4 1 5 1word (SP) ← (SP)-2, ((SP)) ← (PC)+1word (PC) ← (vecter_address)
- - - - - - - - - -
CALLP @ear 2 5 2word (SP) ← (SP)-2, ((SP)) ← (PCB)word (SP) ← (SP)-2, ((SP)) ← (PC)+2word (PC) ← (ear), (PCB) ← (ear+2)
- - - - - - - - - -
CALLP @eam 2+ 7 2+1*bword (SP) ← (SP)-2, ((SP)) ← (PCB)word (SP) ← (SP)-2, ((SP)) ← (PC)+ 2+word (PC) ← (eam), (PCB) ← (eam+2)
- - - - - - - - - -
CALLP addr24 4 4 2word (SP) ← (SP)-2, ((SP)) ← (PCB)word (SP) ← (SP)-2, ((SP)) ← (PC)+4word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
- - - - - - - - - -
*a : compensation value: +1 for odd stack, +1 for odd operand address
*b : compensation value +2 for odd stack, +1 for odd operand address.
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 331
APPENDIXAPPENDIX B Instruction Lists (351 Instructions)
Table B-12 Branch Instructions 2 : 19 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
CBNE A, #imm8, rel 3 5 0 Branch on byte (A) not equal to imm8 - - - - - * * * * -
CWBNE A, #imm16, rel 4 5 0 Branch on word (A) not equal to imm16 - - - - - * * * * -
CBNE ear, #imm8, rel 4 4 0 Branch on byte (ear) not equal to imm8 - - - - - * * * * -
CBNE eam, #imm8, rel 4+ 5 0 Branch on byte (eam) not equal to imm8 - - - - - * * * * -
CWBNE ear, #imm16, rel 5 5 0 Branch on word (ear) not equal to imm16 - - - - - * * * * -
CWBNE eam, #imm16, rel 5+ 6 1 Branch on word (eam) not equal to imm16 - - - - - * * * * -
DBNZ ear, rel 3 5 0 byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0 - - - - - * * * - -
DBNZ eam, rel 3+ 6 0 byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0 - - - - - * * * - *
DWBNZ ear, rel 3 5 0 word (ear) ← (ear) - 1, Branch on (ear) not equal to 0 - - - - - * * * - -
DWBNZ eam, rel 3+ 6 2 word (eam) ← (eam) - 1, Branch on (eam) not equal to 0 - - - - - * * * - *
INT #vct8 2 11 6 Software interrupt - - R S - - - - - -
INT addr16 3 8 6 Software interrupt - - R S - - - - - -
INTP addr24 4 8 6 Software interrupt - - R S - - - - - -
INT9 1 11 6 Software interrupt - - R S - - - - - -
INTE 1 12 6 Software interrupt for break point (reserved for emulator) - - R S - - - - - -
RETI 1 22 / 6*1 1 Return from interrupt - - * * * * * * * -
LINK #imm8 2 2 1word (SP) ← (SP) - 2, ((SP)) ← (RW3), word (RW3) ← (SP), (SP) ← (SP) - imm8
- - - - - - - - - -
UNLINK 1 1 1word (SP) ← (RW3), (RW3) ← ((SP)), word (SP) ← (SP) + 2
- - - - - - - - - -
RET 1 4 1 word (PC) ← ((SP)), (SP) ← (SP) + 2 - - - - - - - - - -
RETP 1 5 1word (PC) ← ((SP)), (SP) ← (SP) + 2, byte (PCB) ← ((SP)), (SP) ← (SP) + 2
- - - - - - - - - -
*1 : 6 cycles in case of RP stable, 22 cycles in other case.
F2MC-16FX Family
332 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX B Instruction Lists (351 Instructions)
Table B-13 Other Control Instructions (Byte, Word, Long Word) : 28 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
PUSHW A 1 1 1 word (SP) ← (SP) - 2, ((SP)) ← (A) - - - - - - - - - -
PUSHW AH 1 1 1 word (SP) ← (SP) - 2, ((SP)) ← (AH) - - - - - - - - - -
PUSHW PS 1 1 1 word (SP) ← (SP) - 2, ((SP)) ← (PS) - - - - - - - - - -
PUSHW rlst 2 N*1 N*a multi word (SP) ← (SP) - 2n, ((SP)) ← (rlst) - - - - - - - - - -
POPW A 1 1 1 word (A) ← ((SP)), (SP) ← (SP) + 2 - * - - - - - - - -
POPW AH 1 1 1 word (AH) ← ((SP)), (SP) ← (SP) + 2 - - - - - - - - - -
POPW PS 1 18 / 4*2 1 word (PS) ← ((SP)), (SP) ← (SP) + 2 - - * * * * * * * -
POPW rlst 2 N*1 N*a multi word (rlst) ← ((SP)), (SP) ← (SP) + 2n - - - - - - - - - -
JCTX @A 1 22 / 6*3 1 Context switch - - * * * * * * * -
AND CCR, #imm8 2 1 0 byte (CCR) ← (CCR) and imm8 - - * * * * * * * -
OR CCR, #imm8 2 1 0 byte (CCR) ← (CCR) or imm8 - - * * * * * * * -
MOV RP, #imm8 2 19 / 4*2 0 byte (RP) ← imm8 - - - - - - - - - -
MOV ILM, #imm8 2 1 0 byte (ILM) ← imm8 - - - - - - - - - -
MOVEA RWi, ear 2 1 0 word (RWi) ← ear - - - - - - - - - -
MOVEA RWi, eam 2+ 1 0 word (RWi) ← eam - - - - - - - - - -
MOVEA A, ear 2 1 0 word (A) ← ear - * - - - - - - - -
MOVEA A, eam 2+ 1 0 word (A) ← eam - * - - - - - - - -
ADDSP #imm8 2 1 0 word (SP) ← (SP) + ext(imm8) - - - - - - - - - -
ADDSP #imm16 3 1 0 word (SP) ← (SP) + imm16 - - - - - - - - - -
MOV A, brg1 2 1 0 byte (A) ← (brg1) Z * - - - * * - - -
MOV brg2, A 2 1 0 byte (brg2) ← (A) - - - - - * * - - -
NOP 1 1 0 No operation - - - - - - - - - -
ADB 1 1 0 Prefix code for AD space access - - - - - - - - - -
DTB 1 1 0 Prefix code for DT space access - - - - - - - - - -
PCB 1 1 0 Prefix code for PC space access - - - - - - - - - -
SPB 1 1 0 Prefix code for SP space access - - - - - - - - - -
NCC 1 1 0 Prefix code for flags no change - - - - - - - - - -
CMR 1 1 0 Prefix code for common register bank - - - - - - - - - -
*1 : N depends on number of registers to be saved/restored, minimum 1 cycle
*2 : 4 cycles in case of RP stable, 18 cycles in other case
*3 : 6 cycles in case of RP stable, 22 cycles in other case
*a : N depends on number of registers to be saved
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 333
APPENDIXAPPENDIX B Instruction Lists (351 Instructions)
Table B-14 Bit Operation Instructions : 21 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
MOVB A, dir:bp 3 1 0 byte (A) ← (dir:bp) b Z * - - - * * - - -
MOVB A, addr16:bp 4 1 0 byte (A) ← (addr16:bp) b Z * - - - * * - - -
MOVB A, io:bp 3 1 0 byte (A) ← (io:bp) b Z * - - - * * - - -
MOVB dir:bp, A 3 3 0 bit (dir:bp) b ← (A) - - - - - * * - - *
MOVB addr16:bp, A 4 3 0 bit (addr16:bp) b ← (A) - - - - - * * - - *
MOVB io:bp, A 3 3 0 bit (io:bp) b ← (A) - - - - - * * - - *
SETB dir:bp 3 3 0 bit (dir:bp) b ← 1 - - - - - - - - - *
SETB addr16:bp 4 3 0 bit (addr16:bp) b ← 1 - - - - - - - - - *
SETB io:bp 3 3 0 bit (io:bp) b ← 1 - - - - - - - - - *
CLRB dir:bp 3 3 0 bit (dir:bp) b ← 0 - - - - - - - - - *
CLRB addr16:bp 4 3 0 bit (addr16:bp) b ← 0 - - - - - - - - - *
CLRB io:bp 3 3 0 bit (io:bp) b ← 0 - - - - - - - - - *
BBC dir:bp, rel 4 5 0 Branch on (dir:bp) b = 0 - - - - - - * - - -
BBC addr16:bp, rel 5 5 0 Branch on (addr16:bp) b = 0 - - - - - - * - - -
BBC io:bp, rel 4 5 0 Branch on (io:bp) b = 0 - - - - - - * - - -
BBS dir:bp, rel 4 5 0 Branch on (dir:bp) b = 1 - - - - - - * - - -
BBS addr16:bp, rel 5 5 0 Branch on (addr16:bp) b = 1 - - - - - - * - - -
BBS io:bp, rel 4 5 0 Branch on (io:bp) b = 1 - - - - - - * - - -
SBBS addr16:bp, rel 5 5 0 Branch on (addr16:bp) b = 1, bit (addr16:bp) b ← 1 - - - - - - * - - *
WBTS io:bp 3 undefined*1 0 Wait until (io:bp) b = 1 - - - - - - - - - -
WBTC io:bp 3 undefined*2 0 Wait until (io:bp) b = 0 - - - - - - - - - -
*1 : 4 cycles if the bit is set already. In other case, the cycle is undefined.
*2 : 4 cycles if the bit is cleared already. In other case, the cycle is undefined.
F2MC-16FX Family
334 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX B Instruction Lists (351 Instructions)
Table B-15 Accumulator Instructions (Byte, Word) : 6 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
SWAP 1 1 0 byte (A) 0-7 ←→ (A) 8-15 - - - - - - - - - -
SWAPW 1 1 0 word (AH) ←→ (AL) - * - - - - - - - -
EXT 1 1 0 Byte sign extension X - - - - * * - - -
EXTW 1 1 0 Word sign extension - X - - - * * - - -
ZEXT 1 1 0 Byte zero extension Z - - - - R * - - -
ZEXTW 1 1 0 Word zero extension - Z - - - R * - - -
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 335
APPENDIXAPPENDIX B Instruction Lists (351 Instructions)
Table B-16 String Instructions : 10 instructions
Mnemonic # B Operation LH AH I S T N Z V C RMW
MOVS/MOVSI brg3, brg3 2 RW0*2 1 byte transfer @AH+ ← @AL+, (RW0) times - - - - - - - - - -
MOVSD brg3, brg3 2 2*RW0 0 byte transfer @AH- ← @AL-, (RW0) times - - - - - - - - - -
SCEQ/SCEQI brg3 2 2+2*N*3 0 byte search @AH+ = AL, (RW0) times or till match - - - - - * * * * -
SCEQD brg3 2 2+2*N*3 0 byte search @AH- = AL, (RW0) times or till match - - - - - * * * * -
FILS/FILSI brg3 2 RW0/2*4 1 byte fill @AH+ ← AL, (RW0) times - - - - - * * - - -
MOVSW/MOVSWI brg3, brg3 2 2*RW0 1 word transfer @AH+ ← @AL+, (RW0) times - - - - - - - - - -
MOVSWD brg3, brg3 2 2*RW0 (1+1)*RW0*a word transfer @AH- ← @AL-, (RW0) times - - - - - - - - - -
SCWEQ/SCWEQI brg3 2 2+2*N*3 N*b word search @AH+ = AL, (RW0) times or till match - - - - - * * * * -
SCWEQD brg3 2 2+2*N*3 N*b word search @AH- = AL, (RW0) times or till match - - - - - * * * * -
FILSW/FILSWI brg3 2 RW0 1 word fill @AH+ ← AL, (RW0) times - - - - - * * - - -
*1 : All String operations need 1 cycle if RW0=0.
*2 : 2*RW0 cycles if overlapping ranges, optimization can not be done.
*3 : 1 cycle if RW0=0, 3 cycles if RW0=1, N is number of items compared till match occurs.
*4 : The number of cycle is round up in case of odd number of bytes.
*a : Correction is 2*RW0 if both src and dest address is odd, 1*RW0 if only src or dest is odd.
*b : N is number of items compared till match occurs.
F2MC-16FX Family
336 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
APPENDIX C Instruction Maps
This appendix describes F2MC-16FX CPU instruction maps.
C.1 Structure of the Instruction Map
C.2 Basic Page Map
C.3 Bit Operation Instruction Map
C.4 Character String Operation Instruction Map
C.5 2-byte Instruction Map
C.6 ea-type Instruction Map
C.7 MOVEA RWi, ea Instruction Map
C.8 MOV Ri, ea Instruction Map
C.9 MOVW RWi, ea Instruction Map
C.10 MOV ea, Ri Instruction Map
C.11 MOVW ea, RWi Instruction Map
C.12 XCH Ri, ea Instruction Map
C.13 XCHW RWi, ea Instruction Map
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 337
APPENDIXAPPENDIX C Instruction Maps
C.1 Structure of the Instruction Map
The instruction code of the F2MC-16FX CPU consists of one- and two-byte instructions. The instruction map consists of more than one page that can be used for one- and two- byte instructions.
■ Structure of the Instruction MapFigure C.1-1 shows the structure of the instruction map.
Figure C.1-1 Structure of the F2MC-16FX CPU Instruction Map
The instruction code is described on the basic page map for one-byte instructions (such as the
NOP instruction). For two-byte instructions (such as the MOVS instruction), see the basic page
map to find the name of the map that describes the second byte of the instruction code to be
referenced next.
Figure C.1-2 shows the relationship between actual instruction codes and instruction maps.
Basic page map : First byte
Bit operation instruction
Character string operation instruction
2-byte instructions
ea-type instruction × 9 : Second byte
F2MC-16FX Family
338 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Figure C.1-2 Relationship Between Actual Instruction Codes and Instruction Maps
*: Extended page map is a generic name for bit operation instruction, character stringoperation instruction, 2-byte instruction, and ea-type instruction. More than one extendedpage map exists for each type of instruction.
May not exist for some instruction.
The length varies depending on instructions.
Instruction code First byte Second byte Operand Operand . . .
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 339
APPENDIXAPPENDIX C Instruction Maps
C.2 Basic Page Map
Table C.2-1 shows the basic page map.
F2MC-16FX Family
340 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.2-1 Basic Page Map00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
NO
PC
MR
AD
DA
, di
r
AD
DA
, #i
mm
8
MO
VA
, di
r
MO
VA
, io
BR
Are
lea in
stru
ctio
n 1
MO
VA
, R
0
MO
VR
0,A
MO
VR
0,#i
mm
8
MO
VX
A,
R0
MO
VX
A @R
W0+
disp
8
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
Z/B
EQ
rel
+1
INT
9N
CC
SU
BA
, di
r
SU
BA
, #i
mm
8
MO
Vdi
r,
A
MO
Vio
, A
JMP
@A
ea inst
ruct
ion
2M
OV
A,
R1
MO
VR
1,A
MO
VR
1,#i
mm
8
MO
VX
A,
R1
MO
VX
A @R
W1+
disp
8
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
NZ
/BN
Ere
l
+2
AD
DD
CA
SU
BD
CA
AD
DC
AS
UB
CA
MO
VA
, #i
mm
8
MO
VA
, ad
dr16
JMP
addr
16ea in
stru
ctio
n 3
MO
VA
, R
2
MO
VR
2,A
MO
VR
2,#i
mm
8
MO
VX
A,
R2
MO
VX
A @R
W2+
disp
8
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
C/B
LOre
l
+3
NE
GA
JCT
X@
AC
MP
AC
MP
A,
#im
m8
MO
VX
A,
#im
m8
MO
Vad
dr16
, A
JMP
Pad
dr24
ea inst
ruct
ion
4M
OV
A,
R3
MO
VR
3,A
MO
VR
3,#i
mm
8
MO
VX
A,
R3
MO
VX
A @R
W3+
disp
8
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
NC
/BH
Sre
l
+4
PC
BE
XT
AN
DC
CR
, #i
mm
8
AN
DA
, #i
mm
8
MO
Vdi
r,
#im
m8
MO
Vio
, #i
mm
8
CA
LLad
dr16
ea inst
ruct
ion
5M
OV
A,
R4
MO
VR
4,A
MO
VR
4,#i
mm
8
MO
VX
A,
R4
MO
VX
A @R
W4+
disp
8
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
Nre
l
+5
DT
BZ
EX
TO
RC
CR
, #i
mm
8
OR
A,
#im
m8
MO
VX
A,
dir
MO
VX
A,
io
CA
LLP
addr
24ea in
stru
ctio
n 6
MO
VA
, R
5
MO
VR
5,A
MO
VR
5,#i
mm
8
MO
VX
A,
R5
MO
VX
A @R
W5+
disp
8
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
Pre
l
+6
AD
BS
WA
PD
IVU
AX
OR
A,
#im
m8
MO
VW
A,
SP
MO
VW
io,
#im
m16
RE
TP
ea inst
ruct
ion
7M
OV
A,
R6
MO
VR
6,A
MO
VR
6,#i
mm
8
MO
VX
A,
R6
MO
VX
A @R
W6+
disp
8
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
Vre
l
+7
SP
BA
DD
SP
#im
m8
MU
LUA
NO
TA
MO
VW
SP
,A
MO
VX
A,
addr
16
RE
Tea in
stru
ctio
n 8
MO
VA
, R
7
MO
VR
7,A
MO
VR
7,#i
mm
8
MO
VX
A,
R7
MO
VX
A @R
W7+
disp
8
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
NV
rel
+8
LIN
K#i
mm
8A
DD
LA
, #i
mm
32
AD
DW
AA
DD
WA
, #i
mm
16
MO
VW
A,
dir
MO
VW
A,
io
INT
#vct
8ea in
stru
ctio
n 9
MO
VW
A,
RW
0
MO
VW
RW
0,
A
MO
VW
RW
0,
#im
m16
MO
VW
A,
@R
W0+
disp
8
MO
VW
@R
W0+
disp
8,A
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
Tre
l
+9
UN
LIN
KS
UB
LA
, #i
mm
32
SU
BW
AS
UB
WA
, #i
mm
16
MO
VW
dir,
A
MO
VW
io,
A
INT
addr
16M
OVE
A RW
i, ea
inst
ruct
ion
MO
VW
A,
RW
1
MO
VW
RW
1,
A
MO
VW
RW
1,
#im
m16
MO
VW
A,
@R
W1+
disp
8
MO
VW
@R
W1+
disp
8,A
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
NT
rel
+A
MO
VR
P,
#im
m8
MO
VIL
M,
#im
m8
CB
NE
A,
#im
m8,
rel
CW
BN
EA
, #i
mm
16, r
el
MO
VW
A,
#im
m16
MO
VW
A,
addr
16
INT
Pad
dr24
MO
V R
i, ea
inst
ruct
ion
MO
VW
A,
RW
2
MO
VW
RW
2,
A
MO
VW
RW
2,
#im
m16
MO
VW
A,
@R
W2+
disp
8
MO
VW
@R
W2+
disp
8,A
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
LTre
l
+B
NE
GW
AC
MP
LA
, #i
mm
32
CM
PW
AC
MP
WA
, #i
mm
16
MO
VL
A,
#im
m32
MO
VW
addr
16,
A
RE
TI
MO
VW R
Wi,
eain
stru
ctio
nM
OV
WA
, R
W3
MO
VW
RW
3,
A
MO
VW
RW
3,
#im
m16
MO
VW
A,
@R
W3+
disp
8
MO
VW
@R
W3+
disp
8,A
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
GE
rel
+C
LSLW
AE
XT
WA
ND
WA
AN
DW
A,
#im
m16
PU
SH
WA
PO
PW
AB
it op
erat
ion
inst
ruct
ion
MO
V ea
, Ri
inst
ruct
ion
MO
VW
A,
RW
4
MO
VW
RW
4,
A
MO
VW
RW
4,
#im
m16
MO
VW
A,
@R
W4+
disp
8
MO
VW
@R
W4+
disp
8,A
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
LEre
l
+D
INT
EZ
EX
TW
OR
WA
OR
WA
, #i
mm
16
PU
SH
WA
HP
OP
WA
HM
OVW
ea,
RW
iin
stru
ctio
nM
OV
WA
, R
W5
MO
VW
RW
5,
A
MO
VW
RW
5,
#im
m16
MO
VW
A,
@R
W5+
disp
8
MO
VW
@R
W5+
disp
8,A
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
GT
rel
+E
AS
RW
AS
WA
PW
XO
RW
AX
OR
WA
, #i
mm
16
PU
SH
WP
SP
OP
WP
SSt
ring
oper
atio
nin
stru
ctio
nX
CH
Ri,
eain
stru
ctio
nM
OV
WA
, R
W6
MO
VW
RW
6,
A
MO
VW
RW
6,
#im
m16
MO
VW
A,
@R
W6+
disp
8
MO
VW
@R
W6+
disp
8,A
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
LSre
l
+F
LSR
WA
AD
DS
P#i
mm
16M
ULU
WA
NO
TW
AP
US
HW
rlst
PO
PW
rlst
2-by
tein
stru
ctio
nXC
HW
RW
i, ea
inst
ruct
ion
MO
VW
A,
RW
7
MO
VW
RW
7,
A
MO
VW
RW
7,
#im
m16
MO
VW
A,
@R
W7+
disp
8
MO
VW
@R
W7+
disp
8,A
MO
VN
A,
#im
m4
CA
LLV
#vct
4B
HI
rel
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 341
APPENDIXAPPENDIX C Instruction Maps
C.3 Bit Operation Instruction Map
Table C.3-1 shows the bit operation instruction map.
F2MC-16FX Family
342 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.3-1 Bit Operation Instruction Map (First Byte = 6CH)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
MO
VB
A,
io:b
p
MO
VB
ip:b
p,A
CLR
Bio
:bp
SE
TB
io:b
pB
BC
ip:b
p,re
l
BB
Sio
:bp,
rel
WB
TS
io:b
pW
BT
Cio
:bp
+1
MO
VB
A,
io:b
p
MO
VB
ip:b
p,A
CLR
Bio
:bp
SE
TB
io:b
pB
BC
ip:b
p,re
l
BB
Sio
:bp,
rel
WB
TS
io:b
pW
BT
Cio
:bp
+2
MO
VB
A,
io:b
p
MO
VB
ip:b
p,A
CLR
Bio
:bp
SE
TB
io:b
pB
BC
ip:b
p,re
l
BB
Sio
:bp,
rel
WB
TS
io:b
pW
BT
Cio
:bp
+3
MO
VB
A,
io:b
p
MO
VB
ip:b
p,A
CLR
Bio
:bp
SE
TB
io:b
pB
BC
ip:b
p,re
l
BB
Sio
:bp,
rel
WB
TS
io:b
pW
BT
Cio
:bp
+4
MO
VB
A,
io:b
p
MO
VB
ip:b
p,A
CLR
Bio
:bp
SE
TB
io:b
pB
BC
ip:b
p,re
l
BB
Sio
:bp,
rel
WB
TS
io:b
pW
BT
Cio
:bp
+5
MO
VB
A,
io:b
p
MO
VB
ip:b
p,A
CLR
Bio
:bp
SE
TB
io:b
pB
BC
ip:b
p,re
l
BB
Sio
:bp,
rel
WB
TS
io:b
pW
BT
Cio
:bp
+6
MO
VB
A,
io:b
p
MO
VB
ip:b
p,A
CLR
Bio
:bp
SE
TB
io:b
pB
BC
ip:b
p,re
l
BB
Sio
:bp,
rel
WB
TS
io:b
pW
BT
Cio
:bp
+7
MO
VB
A,
io:b
p
MO
VB
ip:b
p,A
CLR
Bio
:bp
SE
TB
io:b
pB
BC
ip:b
p,re
l
BB
Sio
:bp,
rel
WB
TS
io:b
pW
BT
Cio
:bp
+8
MO
VB
A,
dir:
bp
MO
VB
A,
addr
16:b
p
MO
VB
dir:
bp,
A
MO
VB
addr
16:b
pC
LRB
dir:
bpC
LRB
addr
16:b
pS
ET
Bdi
r:bp
SE
TB
addr
16:b
pB
BC
dir:
bp,
rel
BB
Cad
dr16
:bp,
rel
BB
Sdi
r:bp
,re
l
BB
Sad
dr16
:bp,
rel
SB
BS
addr
16:b
p,re
l
+9
MO
VB
A,
dir:
bp
MO
VB
A,
addr
16:b
p
MO
VB
dir:
bp,
A
MO
VB
addr
16:b
pC
LRB
dir:
bpC
LRB
addr
16:b
pS
ET
Bdi
r:bp
SE
TB
addr
16:b
pB
BC
dir:
bp,
rel
BB
Cad
dr16
:bp,
rel
BB
Sdi
r:bp
,re
l
BB
Sad
dr16
:bp,
rel
SB
BS
addr
16:b
p,re
l
+A
MO
VB
A,
dir:
bp
MO
VB
A,
addr
16:b
p
MO
VB
dir:
bp,
A
MO
VB
addr
16:b
pC
LRB
dir:
bpC
LRB
addr
16:b
pS
ET
Bdi
r:bp
SE
TB
addr
16:b
pB
BC
dir:
bp,
rel
BB
Cad
dr16
:bp,
rel
BB
Sdi
r:bp
,re
l
BB
Sad
dr16
:bp,
rel
SB
BS
addr
16:b
p,re
l
+B
MO
VB
A,
dir:
bp
MO
VB
A,
addr
16:b
p
MO
VB
dir:
bp,
A
MO
VB
addr
16:b
pC
LRB
dir:
bpC
LRB
addr
16:b
pS
ET
Bdi
r:bp
SE
TB
addr
16:b
pB
BC
dir:
bp,
rel
BB
Cad
dr16
:bp,
rel
BB
Sdi
r:bp
,re
l
BB
Sad
dr16
:bp,
rel
SB
BS
addr
16:b
p,re
l
+C
MO
VB
A,
dir:
bp
MO
VB
A,
addr
16:b
p
MO
VB
dir:
bp,
A
MO
VB
addr
16:b
pC
LRB
dir:
bpC
LRB
addr
16:b
pS
ET
Bdi
r:bp
SE
TB
addr
16:b
pB
BC
dir:
bp,
rel
BB
Cad
dr16
:bp,
rel
BB
Sdi
r:bp
,re
l
BB
Sad
dr16
:bp,
rel
SB
BS
addr
16:b
p,re
l
+D
MO
VB
A,
dir:
bp
MO
VB
A,
addr
16:b
p
MO
VB
dir:
bp,
A
MO
VB
addr
16:b
pC
LRB
dir:
bpC
LRB
addr
16:b
pS
ET
Bdi
r:bp
SE
TB
addr
16:b
pB
BC
dir:
bp,
rel
BB
Cad
dr16
:bp,
rel
BB
Sdi
r:bp
,re
l
BB
Sad
dr16
:bp,
rel
SB
BS
addr
16:b
p,re
l
+E
MO
VB
A,
dir:
bp
MO
VB
A,
addr
16:b
p
MO
VB
dir:
bp,
A
MO
VB
addr
16:b
pC
LRB
dir:
bpC
LRB
addr
16:b
pS
ET
Bdi
r:bp
SE
TB
addr
16:b
pB
BC
dir:
bp,
rel
BB
Cad
dr16
:bp,
rel
BB
Sdi
r:bp
,re
l
BB
Sad
dr16
:bp,
rel
SB
BS
addr
16:b
p,re
l
+F
MO
VB
A,
dir:
bp
MO
VB
A,
addr
16:b
p
MO
VB
dir:
bp,
A
MO
VB
addr
16:b
pC
LRB
dir:
bpC
LRB
addr
16:b
pS
ET
Bdi
r:bp
SE
TB
addr
16:b
pB
BC
dir:
bp,
rel
BB
Cad
dr16
:bp,
rel
BB
Sdi
r:bp
,re
l
BB
Sad
dr16
:bp,
rel
SB
BS
addr
16:b
p,re
l
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 343
APPENDIXAPPENDIX C Instruction Maps
C.4 Character String Operation Instruction Map
Table C.4-1 shows the character string operation instruction map.
F2MC-16FX Family
344 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.4-1 Character String Operation Instruction Map (First Byte = 6EH)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
MO
VS
IP
CB
,P
CB
MO
VS
DP
CB
,P
CB
MO
VS
WI
PC
B,
PC
B
MO
VS
WD
PC
B,
PC
B
SC
EQ
IP
CB
SC
EQ
DP
CB
SC
WE
QI
PC
BS
CW
EQ
DP
CB
FIL
SI
PC
BF
ILS
WI
PC
B
+1
MO
VS
IP
CB
,D
TB
MO
VS
DP
CB
,D
TB
MO
VS
WI
PC
B,
DT
B
MO
VS
WD
PC
B,
DT
B
SC
EQ
ID
TB
SC
EQ
DD
TB
SC
WE
QI
DT
BS
CW
EQ
DD
TB
FIL
SI
DT
BF
ILS
WI
DT
B
+2
MO
VS
IP
CB
,A
DB
MO
VS
DP
CB
,A
DB
MO
VS
WI
PC
B,
AD
B
MO
VS
WD
PC
B,
AD
B
SC
EQ
IA
DB
SC
EQ
DA
DB
SC
WE
QI
AD
BS
CW
EQ
DA
DB
FIL
SI
AD
BF
ILS
WI
AD
B
+3
MO
VS
IP
CB
,S
PB
MO
VS
DP
CB
,S
PB
MO
VS
WI
PC
B,
SP
B
MO
VS
WD
PC
B,
SP
B
SC
EQ
IS
PB
SC
EQ
DS
PB
SC
WE
QI
SP
BS
CW
EQ
DS
PB
FIL
SI
SP
BF
ILS
WI
SP
B
+4
MO
VS
ID
TB
,P
CB
MO
VS
DD
TB
,P
CB
MO
VS
WI
DT
B,
PC
B
MO
VS
WD
DT
B,
PC
B
+5
MO
VS
ID
TB
,D
TB
MO
VS
DD
TB
,D
TB
MO
VS
WI
DT
B,
DT
B
MO
VS
WD
DT
B,
DT
B
+6
MO
VS
ID
TB
,A
DB
MO
VS
DD
TB
,A
DB
MO
VS
WI
DT
B,
AD
B
MO
VS
WD
DT
B,
AD
B
+7
MO
VS
ID
TB
,S
PB
MO
VS
DD
TB
,S
PB
MO
VS
WI
DT
B,
SP
B
MO
VS
WD
DT
B,
SP
B
+8
MO
VS
IA
DB
,P
CB
MO
VS
DA
DB
,P
CB
MO
VS
WI
AD
B,
PC
B
MO
VS
WD
AD
B,
PC
B
+9
MO
VS
IA
DB
,D
TB
MO
VS
DA
DB
,D
TB
MO
VS
WI
AD
B,
DT
B
MO
VS
WD
AD
B,
DT
B
+A
MO
VS
IA
DB
,A
DB
MO
VS
DA
DB
,A
DB
MO
VS
WI
AD
B,
AD
B
MO
VS
WD
AD
B,
AD
B
+B
MO
VS
IA
DB
,S
PB
MO
VS
DA
DB
,S
PB
MO
VS
WI
AD
B,
SP
B
MO
VS
WD
AD
B,
SP
B
+C
MO
VS
IS
PB
,P
CB
MO
VS
DS
PB
,P
CB
MO
VS
WI
SP
B,
PC
B
MO
VS
WD
SP
B,
PC
B
+D
MO
VS
IS
PB
,D
TB
MO
VS
DS
PB
,D
TB
MO
VS
WI
SP
B,
DT
B
MO
VS
WD
SP
B,
DT
B
+E
MO
VS
IS
PB
,A
DB
MO
VS
DS
PB
,A
DB
MO
VS
WI
SP
B,
AD
B
MO
VS
WD
SP
B,
AD
B
+F
MO
VS
IS
PB
,S
PB
MO
VS
DS
PB
,S
PB
MO
VS
WI
SP
B,
SP
B
MO
VS
WD
SP
B,
SP
B
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 345
APPENDIXAPPENDIX C Instruction Maps
C.5 2-byte Instruction Map
Table C.5-1 shows the 2-byte instruction map.
F2MC-16FX Family
346 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.5-1 2-byte Instruction Map (First Byte = 6FH)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
MO
VA
,D
TB
MO
VD
TB
,A
MO
VX
A,
@R
L0+
disp
8
MO
V@
RL0
+dis
p8,
A
MO
VA
,@
RL0
+di
sp8
+1
MO
VA
,A
DB
MO
VA
DB
,A
+2
MO
VA
,S
SB
MO
VS
SB
,A
MO
VX
A,
@R
L1+
disp
8
MO
V@
RL1
+dis
p8,
A
MO
VA
,@
RL1
+di
sp8
+3
MO
VA
,U
SB
MO
VU
SB
,A
+4
MO
VA
,D
PR
MO
VD
PR
,A
MO
VX
A,
@R
L2+
disp
8
MO
V@
RL2
+dis
p8,
A
MO
VA
,@
RL2
+dis
p8
+5
MO
VA
,@
A
MO
V@
AL,
AH
+6
MO
VA
,P
CB
MO
VX
A,
@A
MO
VX
A,
@R
L3+
disp
8
MO
V@
RL3
+dis
p8,
A
MO
VA
,@
RL3
+di
sp8
+7
RO
LCA
RO
RC
A
+8
MO
VW
@R
L0+d
isp8
,
A
MO
VW
A,
@R
L0+
disp
8
MU
LA
+9
MU
LWA
+A
MO
VW
@R
L1+d
isp8
,
A
MO
VW
A,
@R
L1+
disp
8
DIV
A
+B
+C
LSLW
A,
R0
LSLL
A,
R0
LSL
A,
R0
MO
VW
@R
L2+d
isp8
,
A
MO
VW
A,
@R
L2+
disp
8
+D
MO
VW
A,
@A
MO
VW
@A
L,A
H
NR
ML
A,
R0
+E
AS
RW
A,
R0
AS
RL
A,
R0
AS
RA
,R
0
MO
VW
@R
L3+d
isp8
,
A
MO
VW
A,
@R
L3+
disp
8
+F
LSR
WA
,R
0
LSR
LA
,R
0
LSR
A,
R0
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 347
APPENDIXAPPENDIX C Instruction Maps
C.6 ea-type Instruction Map
ea-type instruction maps (first byte = 70H to first byte = 78H) are shown in the
following nine tables:• Table C.6-1 for ea-type instruction (1) (first byte = 70H)
• Table C.6-2 for ea-type instruction (2) (first byte = 71H)
• Table C.6-3 for ea-type instruction (3) (first byte = 72H)
• Table C.6-4 for ea-type instruction (4) (first byte = 73H)
• Table C.6-5 for ea-type instruction (5) (first byte = 74H)
• Table C.6-6 for ea-type instruction (6) (first byte = 75H)
• Table C.6-7 for ea-type instruction (7) (first byte = 76H)
• Table C.6-8 for ea-type instruction (8) (first byte = 77H)
• Table C.6-9 for ea-type instruction (9) (first byte = 78H)
F2MC-16FX Family
348 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.6-1 ea-byte Instruction (1) (First Byte = 70H)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
AD
DL
A,
RL0
AD
DL
A,
@R
W0+
disp
8
SU
BL
A,
RL0
SU
BL
A,
@R
W0+
disp
8
CW
BN
ER
W0,
#im
m16
, rel
CW
BN
E@
RW
0+di
sp8,
#im
m16
, rel
CM
PL
A,
RL0
CM
PL
A,
@R
W0+
disp
8
AN
DL
A,
RL0
AN
DL
A,
@R
W0+
disp
8
OR
LA
,R
L0
OR
LA
,@
RW
0+di
sp8
XO
RL
A,
RL0
XO
RL
A,
@R
W0+
disp
8
CB
NE
R0,
#im
m8,
rel
CB
NE
@R
W0+
disp
8,
#im
m8,
rel
+1
AD
DL
A,
RL0
AD
DL
A,
@R
W1+
disp
8
SU
BL
A,
RL0
SU
BL
A,
@R
W1+
disp
8
CW
BN
ER
W1,
#im
m16
, rel
CW
BN
E@
RW
1+di
sp8,
#im
m16
, rel
CM
PL
A,
RL0
CM
PL
A,
@R
W1+
disp
8
AN
DL
A,
RL0
AN
DL
A,
@R
W1+
disp
8
OR
LA
,R
L0
OR
LA
,@
RW
1+di
sp8
XO
RL
A,
RL0
XO
RL
A,
@R
W1+
disp
8
CB
NE
R1,
#im
m8,
rel
CB
NE
@R
W1+
disp
8,
#im
m8,
rel
+2
AD
DL
A,
RL1
AD
DL
A,
@R
W2+
disp
8
SU
BL
A,
RL1
SU
BL
A,
@R
W2+
disp
8
CW
BN
ER
W2,
#im
m16
, rel
CW
BN
E@
RW
2+di
sp8,
#im
m16
, rel
CM
PL
A,
RL1
CM
PL
A,
@R
W2+
disp
8
AN
DL
A,
RL1
AN
DL
A,
@R
W2+
disp
8
OR
LA
,R
L1
OR
LA
,@
RW
2+di
sp8
XO
RL
A,
RL1
XO
RL
A,
@R
W2+
disp
8
CB
NE
R2,
#im
m8,
rel
CB
NE
@R
W2+
disp
8,
#im
m8,
rel
+3
AD
DL
A,
RL1
AD
DL
A,
@R
W3+
disp
8
SU
BL
A,
RL1
SU
BL
A,
@R
W3+
disp
8
CW
BN
ER
W3,
#im
m16
, rel
CW
BN
E@
RW
3+di
sp8,
#im
m16
, rel
CM
PL
A,
RL1
CM
PL
A,
@R
W3+
disp
8
AN
DL
A,
RL1
AN
DL
A,
@R
W3+
disp
8
OR
LA
,R
L1
OR
LA
,@
RW
3+di
sp8
XO
RL
A,
RL1
XO
RL
A,
@R
W3+
disp
8
CB
NE
R3,
#im
m8,
rel
CB
NE
@R
W3+
disp
8,
#im
m8,
rel
+4
AD
DL
A,
RL2
AD
DL
A,
@R
W4+
disp
8
SU
BL
A,
RL2
SU
BL
A,
@R
W4+
disp
8
CW
BN
ER
W4,
#im
m16
, rel
CW
BN
E@
RW
4+di
sp8,
#im
m16
, rel
CM
PL
A,
RL2
CM
PL
A,
@R
W4+
disp
8
AN
DL
A,
RL2
AN
DL
A,
@R
W4+
disp
8
OR
LA
,R
L2
OR
LA
,@
RW
4+di
sp8
XO
RL
A,
RL2
XO
RL
A,
@R
W4+
disp
8
CB
NE
R4,
#im
m8,
rel
CB
NE
@R
W4+
disp
8,
#im
m8,
rel
+5
AD
DL
A,
RL2
AD
DL
A,
@R
W5+
disp
8
SU
BL
A,
RL2
SU
BL
A,
@R
W5+
disp
8
CW
BN
ER
W5,
#im
m16
, rel
CW
BN
E@
RW
5+di
sp8,
#im
m16
, rel
CM
PL
A,
RL2
CM
PL
A,
@R
W5+
disp
8
AN
DL
A,
RL2
AN
DL
A,
@R
W5+
disp
8
OR
LA
,R
L2
OR
LA
,@
RW
5+di
sp8
XO
RL
A,
RL2
XO
RL
A,
@R
W5+
disp
8
CB
NE
R5,
#im
m8,
rel
CB
NE
@R
W5+
disp
8,
#im
m8,
rel
+6
AD
DL
A,
RL3
AD
DL
A,
@R
W6+
disp
8
SU
BL
A,
RL3
SU
BL
A,
@R
W6+
disp
8
CW
BN
ER
W6,
#im
m16
, rel
CW
BN
E@
RW
6+di
sp8,
#im
m16
, rel
CM
PL
A,
RL3
CM
PL
A,
@R
W6+
disp
8
AN
DL
A,
RL3
AN
DL
A,
@R
W6+
disp
8
OR
LA
,R
L3
OR
LA
,@
RW
6+di
sp8
XO
RL
A,
RL3
XO
RL
A,
@R
W6+
disp
8
CB
NE
R6,
#im
m8,
rel
CB
NE
@R
W6+
disp
8,
#im
m8,
rel
+7
AD
DL
A,
RL3
AD
DL
A,
@R
W7+
disp
8
SU
BL
A,
RL3
SU
BL
A,
@R
W7+
disp
8
CW
BN
ER
W7,
#im
m16
, rel
CW
BN
E@
RW
7+di
sp8,
#im
m16
, rel
CM
PL
A,
RL3
CM
PL
A,
@R
W7+
disp
8
AN
DL
A,
RL3
AN
DL
A,
@R
W7+
disp
8
OR
LA
,R
L3
OR
LA
,@
RW
7+di
sp8
XO
RL
A,
RL3
XO
RL
A,
@R
W7+
disp
8
CB
NE
R7,
#im
m8,
rel
CB
NE
@R
W7+
disp
8,
#im
m8,
rel
+8
AD
DL
A,
@R
W0
AD
DL
A,
@R
W0+
disp
16
SU
BL
A,
@R
W0
SU
BL
A,
@R
W0+
disp
16
CW
BN
E@
RW
0,#i
mm
16, r
el
CW
BN
E@
RW
0+di
sp16
,#i
mm
16, r
el
CM
PL
A,
@R
W0
CM
PL
A,
@R
W0+
disp
16
AN
DL
A,
@R
W0
AN
DL
A,
@R
W0+
disp
16
OR
LA
,@
RW
0
OR
LA
,@
RW
0+di
sp16
XO
RL
A,
@R
W0
XO
RL
A,
@R
W0+
disp
16
CB
NE
@R
W0,
#im
m8,
rel
CB
NE
@R
W0+
disp
16,
#im
m8,
rel
+9
AD
DL
A,
@R
W1
AD
DL
A,
@R
W1+
disp
16
SU
BL
A,
@R
W1
SU
BL
A,
@R
W1+
disp
16
CW
BN
E@
RW
1,#i
mm
16, r
el
CW
BN
E@
RW
1+di
sp16
,#i
mm
16, r
el
CM
PL
A,
@R
W1
CM
PL
A,
@R
W1+
disp
16
AN
DL
A,
@R
W1
AN
DL
A,
@R
W1+
disp
16
OR
LA
,@
RW
1
OR
LA
,@
RW
1+di
sp16
XO
RL
A,
@R
W1
XO
RL
A,
@R
W1+
disp
16
CB
NE
@R
W1,
#im
m8,
rel
CB
NE
@R
W1+
disp
16,
#im
m8,
rel
+A
AD
DL
A,
@R
W2
AD
DL
A,
@R
W2+
disp
16
SU
BL
A,
@R
W2
SU
BL
A,
@R
W2+
disp
16
CW
BN
E@
RW
2,#i
mm
16, r
el
CW
BN
E@
RW
2+di
sp16
,#i
mm
16, r
el
CM
PL
A,
@R
W2
CM
PL
A,
@R
W2+
disp
16
AN
DL
A,
@R
W2
AN
DL
A,
@R
W2+
disp
16
OR
LA
,@
RW
2
OR
LA
,@
RW
2+di
sp16
XO
RL
A,
@R
W2
XO
RL
A,
@R
W2+
disp
16
CB
NE
@R
W2,
#im
m8,
rel
CB
NE
@R
W2+
disp
16,
#im
m8,
rel
+B
AD
DL
A,
@R
W3
AD
DL
A,
@R
W3+
disp
16
SU
BL
A,
@R
W3
SU
BL
A,
@R
W3+
disp
16
CW
BN
E@
RW
3,#i
mm
16, r
el
CW
BN
E@
RW
3+di
sp16
,#i
mm
16, r
el
CM
PL
A,
@R
W3
CM
PL
A,
@R
W3+
disp
16
AN
DL
A,
@R
W3
AN
DL
A,
@R
W3+
disp
16
OR
LA
,@
RW
3
OR
LA
,@
RW
3+di
sp16
XO
RL
A,
@R
W3
XO
RL
A,
@R
W3+
disp
16
CB
NE
@R
W3,
#im
m8,
rel
CB
NE
@R
W3+
disp
16,
#im
m8,
rel
+C
AD
DL
A,
@R
W0+
AD
DL
A,
@R
W0+
RW
7
SU
BL
A,
@R
W0+
SU
BL
A,
@R
W0+
RW
7
CW
BN
E@
RW
0+,
#im
m16
, rel
CW
BN
E@
RW
0+R
W7,
#im
m16
, rel
CM
PL
A,
@R
W0+
CM
PL
A,
@R
W0+
RW
7
AN
DL
A,
@R
W0+
AN
DL
A,
@R
W0+
RW
7
OR
LA
,@
RW
0+
OR
LA
,@
RW
0+R
W7
XO
RL
A,
@R
W0+
XO
RL
A,
@R
W0+
RW
7
CB
NE
@R
W0+
,#i
mm
8, r
el
CB
NE
@R
W0+
RW
7,
#im
m8,
rel
+D
AD
DL
A,
@R
W1+
AD
DL
A,
@R
W1+
RW
7
SU
BL
A,
@R
W1+
SU
BL
A,
@R
W1+
RW
7
CW
BN
E@
RW
1+,
#im
m16
, rel
CW
BN
E@
RW
1+R
W7,
#im
m16
, rel
CM
PL
A,
@R
W1+
CM
PL
A,
@R
W1+
RW
7
AN
DL
A,
@R
W1+
AN
DL
A,
@R
W1+
RW
7
OR
LA
,@
RW
1+
OR
LA
,@
RW
1+R
W7
XO
RL
A,
@R
W1+
XO
RL
A,
@R
W1+
RW
7
CB
NE
@R
W1+
,#i
mm
8, r
el
CB
NE
@R
W1+
RW
7,
#im
m8,
rel
+E
AD
DL
A,
@R
W2+
AD
DL
A,
@P
C+
disp
16
SU
BL
A,
@R
W2+
SU
BL
A,
@P
C+
disp
16
CW
BN
E@
RW
2+,
#im
m16
, rel
CW
BN
E@
PC
+dis
p16,
#im
m16
, rel
CM
PL
A,
@R
W2+
CM
PL
A,
@P
C+
disp
16
AN
DL
A,
@R
W2+
AN
DL
A,
@P
C+
disp
16
OR
LA
,@
RW
2+
OR
LA
,@
PC
+di
sp16
XO
RL
A,
@R
W2+
XO
RL
A,
@P
C+
disp
16
CB
NE
@R
W2+
,#i
mm
8, r
el
CB
NE
@P
C+d
isp1
6,
#im
m8,
rel
+F
AD
DL
A,
@R
W3+
AD
DL
A,
addr
16
SU
BL
A,
@R
W3+
SU
BL
A,
addr
16
CW
BN
E@
RW
3+,
#im
m16
, rel
CW
BN
Ead
dr16
,#i
mm
16, r
el
CM
PL
A,
@R
W3+
CM
PL
A,
addr
16
AN
DL
A,
@R
W3+
AN
DL
A,
addr
16
OR
LA
,@
RW
3+
OR
LA
,ad
dr16
XO
RL
A,
@R
W3+
XO
RL
A,
addr
16
CB
NE
@R
W3+
,#i
mm
8, r
el
CB
NE
addr
16,
#im
m8,
rel
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 349
APPENDIXAPPENDIX C Instruction Maps
Table C.6-2 ea-type Instruction (2) (First Byte = 71H)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
JMP
P@
RL0
JMP
P@
@R
W0+
disp
8C
ALL
P@
RL0
CA
LLP
@@
RW0+
disp
8IN
CL
RL0
INC
L@
RW
0+di
sp8
DE
CL
RL0
DE
CL
@R
W0+
disp
8M
OV
LA
,R
L0
MO
VL
A,
@R
W0+
disp
8
MO
VL
RL0
,A
MO
VL
@R
W0+
disp
8,
A
MO
VR
0,#i
mm
8
MO
V@
RW
0+di
sp8,
#im
m8
MO
VE
AA
,R
W0
MO
VE
AA
,@
RW
0+di
sp8
+1
JMP
P@
RL0
JMP
P@
@R
W1+
disp
8C
ALL
P@
RL0
CA
LLP
@@
RW1+
disp
8IN
CL
RL0
INC
L@
RW
1+di
sp8
DE
CL
RL0
DE
CL
@R
W1+
disp
8M
OV
LA
,R
L0
MO
VL
A,
@R
W1+
disp
8
MO
VL
RL0
,A
MO
VL
@R
W1+
disp
8,
A
MO
VR
1,#i
mm
8
MO
V@
RW
1+di
sp8,
#im
m8
MO
VE
AA
,R
W1
MO
VE
AA
,@
RW
1+di
sp8
+2
JMP
P@
RL1
JMP
P@
@R
W2+
disp
8C
ALL
P@
RL1
CA
LLP
@@
RW2+
disp
8IN
CL
RL1
INC
L@
RW
2+di
sp8
DE
CL
RL1
DE
CL
@R
W2+
disp
8M
OV
LA
,R
L1
MO
VL
A,
@R
W2+
disp
8
MO
VL
RL1
,A
MO
VL
@R
W2+
disp
8,
A
MO
VR
2,#i
mm
8
MO
V@
RW
2+di
sp8,
#im
m8
MO
VE
AA
,R
W2
MO
VE
AA
,@
RW
2+di
sp8
+3
JMP
P@
RL1
JMP
P@
@R
W3+
disp
8C
ALL
P@
RL1
CA
LLP
@@
RW3+
disp
8IN
CL
RL1
INC
L@
RW
3+di
sp8
DE
CL
RL1
DE
CL
@R
W3+
disp
8M
OV
LA
,R
L1
MO
VL
A,
@R
W3+
disp
8
MO
VL
RL1
,A
MO
VL
@R
W3+
disp
8,
A
MO
VR
3,#i
mm
8
MO
V@
RW
3+di
sp8,
#im
m8
MO
VE
AA
,R
W3
MO
VE
AA
,@
RW
3+di
sp8
+4
JMP
P@
RL2
JMP
P@
@R
W4+
disp
8C
ALL
P@
RL2
CA
LLP
@@
RW4+
disp
8IN
CL
RL2
INC
L@
RW
4+di
sp8
DE
CL
RL2
DE
CL
@R
W4+
disp
8M
OV
LA
,R
L2
MO
VL
A,
@R
W4+
disp
8
MO
VL
RL2
,A
MO
VL
@R
W4+
disp
8,
A
MO
VR
4,#i
mm
8
MO
V@
RW
4+di
sp8,
#im
m8
MO
VE
AA
,R
W4
MO
VE
AA
,@
RW
4+di
sp8
+5
JMP
P@
RL2
JMP
P@
@R
W5+
disp
8C
ALL
P@
RL2
CA
LLP
@@
RW5+
disp
8IN
CL
RL2
INC
L@
RW
5+di
sp8
DE
CL
RL2
DE
CL
@R
W5+
disp
8M
OV
LA
,R
L2
MO
VL
A,
@R
W5+
disp
8
MO
VL
RL2
,A
MO
VL
@R
W5+
disp
8,
A
MO
VR
5,#i
mm
8
MO
V@
RW
5+di
sp8,
#im
m8
MO
VE
AA
,R
W5
MO
VE
AA
,@
RW
5+di
sp8
+6
JMP
P@
RL3
JMP
P@
@R
W6+
disp
8C
ALL
P@
RL3
CA
LLP
@@
RW6+
disp
8IN
CL
RL3
INC
L@
RW
6+di
sp8
DE
CL
RL3
DE
CL
@R
W6+
disp
8M
OV
LA
,R
L3
MO
VL
A,
@R
W6+
disp
8
MO
VL
RL3
,A
MO
VL
@R
W6+
disp
8,
A
MO
VR
6,#i
mm
8
MO
V@
RW
6+di
sp8,
#im
m8
MO
VE
AA
,R
W6
MO
VE
AA
,@
RW
6+di
sp8
+7
JMP
P@
RL3
JMP
P@
@R
W7+
disp
8C
ALL
P@
RL3
CA
LLP
@@
RW7+
disp
8IN
CL
RL3
INC
L@
RW
7+di
sp8
DE
CL
RL3
DE
CL
@R
W7+
disp
8M
OV
LA
,R
L3
MO
VL
A,
@R
W7+
disp
8
MO
VL
RL3
,A
MO
VL
@R
W7+
disp
8,
A
MO
VR
7,#i
mm
8
MO
V@
RW
7+di
sp8,
#im
m8
MO
VE
AA
,R
W7
MO
VE
AA
,@
RW
7+di
sp8
+8
JMP
P@
@R
W0
JMP
P@
@RW
0+di
sp16
CA
LLP
@@
RW
0C
ALL
P@
@RW
0+di
sp16
INC
L@
RW
0IN
CL
@R
W0+
disp
16D
EC
L@
RW
0D
EC
L@
RW
0+di
sp16
MO
VL
A,
@R
W0
MO
VL
A,
@R
W0+
disp
16
MO
VL
@R
W0,
A
MO
VL
@R
W0+
disp
16,
A
MO
V@
RW
0,#i
mm
8
MO
V@
RW
0+di
sp16
,
#im
m8
MO
VE
AA
,@
RW
0
MO
VE
AA
,@
RW
0+di
sp16
+9
JMP
P@
@R
W1
JMP
P@
@RW
1+di
sp16
CA
LLP
@@
RW
1C
ALL
P@
@RW
1+di
sp16
INC
L@
RW
1IN
CL
@R
W1+
disp
16D
EC
L@
RW
1D
EC
L@
RW
1+di
sp16
MO
VL
A,
@R
W1
MO
VL
A,
@R
W1+
disp
16
MO
VL
@R
W1,
A
MO
VL
@R
W1+
disp
16,
A
MO
V@
RW
1,#i
mm
8
MO
V@
RW
1+di
sp16
,
#im
m8
MO
VE
AA
,@
RW
1
MO
VE
AA
,@
RW
1+di
sp16
+A
JMP
P@
@R
W2
JMP
P@
@RW
2+di
sp16
CA
LLP
@@
RW
2C
ALL
P@
@RW
2+di
sp16
INC
L@
RW
2IN
CL
@R
W2+
disp
16D
EC
L@
RW
2D
EC
L@
RW
2+di
sp16
MO
VL
A,
@R
W2
MO
VL
A,
@R
W2+
disp
16
MO
VL
@R
W2,
A
MO
VL
@R
W2+
disp
16,
A
MO
V@
RW
2,#i
mm
8
MO
V@
RW
2+di
sp16
,
#im
m8
MO
VE
AA
,@
RW
2
MO
VE
AA
,@
RW
2+di
sp16
+B
JMP
P@
@R
W3
JMP
P@
@RW
3+di
sp16
CA
LLP
@@
RW
3C
ALL
P@
@RW
3+di
sp16
INC
L@
RW
3IN
CL
@R
W3+
disp
16D
EC
L@
RW
3D
EC
L@
RW
3+di
sp16
MO
VL
A,
@R
W3
MO
VL
A,
@R
W3+
disp
16
MO
VL
@R
W3,
A
MO
VL
@R
W3+
disp
16,
A
MO
V@
RW
3,#i
mm
8
MO
V@
RW
3+di
sp16
,
#im
m8
MO
VE
AA
,@
RW
3
MO
VE
AA
,@
RW
3+di
sp16
+C
JMP
P@
@R
W0+
JMP
P@
@R
W0+
RW
7C
ALL
P@
@R
W0+
CA
LLP
@@
RW
0+R
W7
INC
L@
RW
0+IN
CL
@R
W0+
RW
7D
EC
L@
RW
0+D
EC
L@
RW
0+R
W7
MO
VL
A,
@R
W0+
MO
VL
A,
@R
W0+
RW
7
MO
VL
@R
W0+
,A
MO
VL
@R
W0+
RW
7,
A
MO
V@
RW
0+,
#im
m8
MO
V@
RW
0+R
W7,
#im
m8
MO
VE
AA
,@
RW
0+
MO
VE
AA
,@
RW
0+R
W7
+D
JMP
P@
@R
W1+
JMP
P@
@R
W1+
RW
7C
ALL
P@
@R
W1+
CA
LLP
@@
RW
1+R
W7
INC
L@
RW
1+IN
CL
@R
W1+
RW
7D
EC
L@
RW
1+D
EC
L@
RW
1+R
W7
MO
VL
A,
@R
W1+
MO
VL
A,
@R
W1+
RW
7
MO
VL
@R
W1+
,A
MO
VL
@R
W1+
RW
7,
A
MO
V@
RW
1+,
#im
m8
MO
V@
RW
1+R
W7,
#im
m8
MO
VE
AA
,@
RW
1+
MO
VE
AA
,@
RW
1+R
W7
+E
JMP
P@
@R
W2+
JMP
P@
@PC
+dis
p16
CA
LLP
@@
RW
2+C
ALL
P@
@PC
+dis
p16
INC
L@
RW
2+IN
CL
@P
C+
disp
16D
EC
L@
RW
2+D
EC
L@
PC
+di
sp16
MO
VL
A,
@R
W2+
MO
VL
A,
@P
C+
disp
16
MO
VL
@R
W2+
,A
MO
VL
@P
C+d
isp1
6,
A
MO
V@
RW
2+,
#im
m8
MO
V@
PC
+dis
p16,
#im
m8
MO
VE
AA
,@
RW
2+
MO
VE
AA
,@
PC
+di
sp16
+F
JMP
P@
@R
W3+
JMP
P@
addr
16C
ALL
P@
@R
W3+
CA
LLP
@ad
dr16
INC
L@
RW
3+IN
CL
addr
16D
EC
L@
RW
3+D
EC
Lad
dr16
MO
VL
A,
@R
W3+
MO
VL
A,
addr
16
MO
VL
@R
W3+
,A
MO
VL
addr
16,
A
MO
V@
RW
3+,
#im
m8
MO
Vad
dr16
,#i
mm
8
MO
VE
AA
,@
RW
3+
MO
VE
AA
,ad
dr16
F2MC-16FX Family
350 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.6-3 ea-type Instruction (3) (First Byte = 72H)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
RO
LCR
0R
OLC
@R
W0+
disp
8R
OR
CR
0R
OR
C@
RW
0+di
sp8
INC
R0
INC
@R
W0+
disp
8D
EC
R0
DE
C@
RW
0+di
sp8
MO
VA
,R
0
MO
VA
,@
RW
0+di
sp8
MO
VR
0,A
MO
V@
RW
0+di
sp8,
A
MO
VX
A,
R0
MO
VX
A,
@R
W0+
disp
8
XC
HA
,R
0
XC
HA
,@
RW
0+di
sp8
+1
RO
LCR
1R
OLC
@R
W1+
disp
8R
OR
CR
1R
OR
C@
RW
1+di
sp8
INC
R1
INC
@R
W1+
disp
8D
EC
R1
DE
C@
RW
1+di
sp8
MO
VA
,R
1
MO
VA
,@
RW
1+di
sp8
MO
VR
1,A
MO
V@
RW
1+di
sp8,
A
MO
VX
A,
R1
MO
VX
A,
@R
W1+
disp
8
XC
HA
,R
1
XC
HA
,@
RW
1+di
sp8
+2
RO
LCR
2R
OLC
@R
W2+
disp
8R
OR
CR
2R
OR
C@
RW
2+di
sp8
INC
R2
INC
@R
W2+
disp
8D
EC
R2
DE
C@
RW
2+di
sp8
MO
VA
,R
2
MO
VA
,@
RW
2+di
sp8
MO
VR
2,A
MO
V@
RW
2+di
sp8,
A
MO
VX
A,
R2
MO
VX
A,
@R
W2+
disp
8
XC
HA
,R
2
XC
HA
,@
RW
2+di
sp8
+3
RO
LCR
3R
OLC
@R
W3+
disp
8R
OR
CR
3R
OR
C@
RW
3+di
sp8
INC
R3
INC
@R
W3+
disp
8D
EC
R3
DE
C@
RW
3+di
sp8
MO
VA
,R
3
MO
VA
,@
RW
3+di
sp8
MO
VR
3,A
MO
V@
RW
3+di
sp8,
A
MO
VX
A,
R3
MO
VX
A,
@R
W3+
disp
8
XC
HA
,R
3
XC
HA
,@
RW
3+di
sp8
+4
RO
LCR
4R
OLC
@R
W4+
disp
8R
OR
CR
4R
OR
C@
RW
4+di
sp8
INC
R4
INC
@R
W4+
disp
8D
EC
R4
DE
C@
RW
4+di
sp8
MO
VA
,R
4
MO
VA
,@
RW
4+di
sp8
MO
VR
4,A
MO
V@
RW
4+di
sp8,
A
MO
VX
A,
R4
MO
VX
A,
@R
W4+
disp
8
XC
HA
,R
4
XC
HA
,@
RW
4+di
sp8
+5
RO
LCR
5R
OLC
@R
W5+
disp
8R
OR
CR
5R
OR
C@
RW
5+di
sp8
INC
R5
INC
@R
W5+
disp
8D
EC
R5
DE
C@
RW
5+di
sp8
MO
VA
,R
5
MO
VA
,@
RW
5+di
sp8
MO
VR
5,A
MO
V@
RW
5+di
sp8,
A
MO
VX
A,
R5
MO
VX
A,
@R
W5+
disp
8
XC
HA
,R
5
XC
HA
,@
RW
5+di
sp8
+6
RO
LCR
6R
OLC
@R
W6+
disp
8R
OR
CR
6R
OR
C@
RW
6+di
sp8
INC
R6
INC
@R
W6+
disp
8D
EC
R6
DE
C@
RW
6+di
sp8
MO
VA
,R
6
MO
VA
,@
RW
6+di
sp8
MO
VR
6,A
MO
V@
RW
6+di
sp8,
A
MO
VX
A,
R6
MO
VX
A,
@R
W6+
disp
8
XC
HA
,R
6
XC
HA
,@
RW
6+di
sp8
+7
RO
LCR
7R
OLC
@R
W7+
disp
8R
OR
CR
7R
OR
C@
RW
7+di
sp8
INC
R7
INC
@R
W7+
disp
8D
EC
R7
DE
C@
RW
7+di
sp8
MO
VA
,R
7
MO
VA
,@
RW
7+di
sp8
MO
VR
7,A
MO
V@
RW
7+di
sp8,
A
MO
VX
A,
R7
MO
VX
A,
@R
W7+
disp
8
XC
HA
,R
7
XC
HA
,@
RW
7+di
sp8
+8
RO
LC@
RW
0R
OLC
@R
W0+
disp
16R
OR
C@
RW
0R
OR
C@
RW
0+di
sp16
INC
@R
W0
INC
@R
W0+
disp
16D
EC
@R
W0
DE
C@
RW
0+di
sp16
MO
VA
,@
RW
0
MO
VA
,@
RW
0+di
sp16
MO
V@
RW
0,A
MO
V@
RW
0+di
sp16
,
A
MO
VX
A,
@R
W0
MO
VX
A,
@R
W0+
disp
16
XC
HA
,@
RW
0
XC
HA
,@
RW
0+di
sp16
+9
RO
LC@
RW
1R
OLC
@R
W1+
disp
16R
OR
C@
RW
1R
OR
C@
RW
1+di
sp16
INC
@R
W1
INC
@R
W1+
disp
16D
EC
@R
W1
DE
C@
RW
1+di
sp16
MO
VA
,@
RW
1
MO
VA
,@
RW
1+di
sp16
MO
V@
RW
1,A
MO
V@
RW
1+di
sp16
,
A
MO
VX
A,
@R
W1
MO
VX
A,
@R
W1+
disp
16
XC
HA
,@
RW
1
XC
HA
,@
RW
1+di
sp16
+A
RO
LC@
RW
2R
OLC
@R
W2+
disp
16R
OR
C@
RW
2R
OR
C@
RW
2+di
sp16
INC
@R
W2
INC
@R
W2+
disp
16D
EC
@R
W2
DE
C@
RW
2+di
sp16
MO
VA
,@
RW
2
MO
VA
,@
RW
2+di
sp16
MO
V@
RW
2,A
MO
V@
RW
2+di
sp16
,
A
MO
VX
A,
@R
W2
MO
VX
A,
@R
W2+
disp
16
XC
HA
,@
RW
2
XC
HA
,@
RW
2+di
sp16
+B
RO
LC@
RW
3R
OLC
@R
W3+
disp
16R
OR
C@
RW
3R
OR
C@
RW
3+di
sp16
INC
@R
W3
INC
@R
W3+
disp
16D
EC
@R
W3
DE
C@
RW
3+di
sp16
MO
VA
,@
RW
3
MO
VA
,@
RW
3+di
sp16
MO
V@
RW
3,A
MO
V@
RW
3+di
sp16
,
A
MO
VX
A,
@R
W3
MO
VX
A,
@R
W3+
disp
16
XC
HA
,@
RW
3
XC
HA
,@
RW
3+di
sp16
+C
RO
LC@
RW
0+R
OLC
@R
W0+
RW
7R
OR
C@
RW
0+R
OR
C@
RW
0+R
W7
INC
@R
W0+
INC
@R
W0+
RW
7D
EC
@R
W0+
DE
C@
RW
0+R
W7
MO
VA
,@
RW
0+
MO
VA
,@
RW
0+R
W7
MO
V@
RW
0+,
A
MO
V@
RW
0+R
W7,
A
MO
VX
A,
@R
W0+
MO
VX
A,
@R
W0+
RW
7
XC
HA
,@
RW
0+
XC
HA
,@
RW
0+R
W7
+D
RO
LC@
RW
1+R
OLC
@R
W1+
RW
7R
OR
C@
RW
1+R
OR
C@
RW
1+R
W7
INC
@R
W1+
INC
@R
W1+
RW
7D
EC
@R
W1+
DE
C@
RW
1+R
W7
MO
VA
,@
RW
1+
MO
VA
,@
RW
1+R
W7
MO
V@
RW
1+,
A
MO
V@
RW
1+R
W7,
A
MO
VX
A,
@R
W1+
MO
VX
A,
@R
W1+
RW
7
XC
HA
,@
RW
1+
XC
HA
,@
RW
1+R
W7
+E
RO
LC@
RW
2+R
OLC
@P
C+
disp
16R
OR
C@
RW
2+R
OR
C@
PC
+di
sp16
INC
@R
W2+
INC
@P
C+
disp
16D
EC
@R
W2+
DE
C@
PC
+di
sp16
MO
VA
,@
RW
2+
MO
VA
,@
PC
+di
sp16
MO
V@
RW
2+,
A
MO
V@
PC
+dis
p16,
A
MO
VX
A,
@R
W2+
MO
VX
A,
@P
C+
disp
16
XC
HA
,@
RW
2+
XC
HA
,@
PC
+di
sp16
+F
RO
LC@
RW
3+R
OLC
addr
16R
OR
C@
RW
3+R
OR
Cad
dr16
INC
@R
W3+
INC
addr
16D
EC
@R
W3+
DE
Cad
dr16
MO
VA
,@
RW
3+
MO
VA
,ad
dr16
MO
V@
RW
3+,
A
MO
Vad
dr16
,A
MO
VX
A,
@R
W3+
MO
VX
A,
addr
16
XC
HA
,@
RW
3+
XC
HA
,ad
dr16
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 351
APPENDIXAPPENDIX C Instruction Maps
Table C.6-4 ea-type Instruction (4) (First Byte = 73H)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
JMP
@R
W0
JMP
@@
RW
0+di
sp8
CA
LL@
RW
0C
ALL
@@
RW0+
disp
8IN
CW
RW
0IN
CW
@R
W0+
disp
8D
EC
WR
W0
DE
CW
@R
W0+
disp
8M
OV
WA
,R
W0
MO
VW
A,
@R
W0+
disp
8
MO
VW
RW
0,A
MO
VW
@R
W0+
disp
8,
A
MO
VW
RW
0,#i
mm
16
MO
VW
@R
W0+
disp
8,
#im
m16
XC
HW
A,
RW
0
XC
HW
A,
@R
W0+
disp
8
+1
JMP
@R
W1
JMP
@@
RW
1+di
sp8
CA
LL@
RW
1C
ALL
@@
RW1+
disp
8IN
CW
RW
1IN
CW
@R
W1+
disp
8D
EC
WR
W1
DE
CW
@R
W1+
disp
8M
OV
WA
,R
W1
MO
VW
A,
@R
W1+
disp
8
MO
VW
RW
1,A
MO
VW
@R
W1+
disp
8,
A
MO
VW
RW
1,#i
mm
16
MO
VW
@R
W1+
disp
8,
#im
m16
XC
HW
A,
RW
1
XC
HW
A,
@R
W1+
disp
8
+2
JMP
@R
W2
JMP
@@
RW
2+di
sp8
CA
LL@
RW
2C
ALL
@@
RW2+
disp
8IN
CW
RW
2IN
CW
@R
W2+
disp
8D
EC
WR
W2
DE
CW
@R
W2+
disp
8M
OV
WA
,R
W2
MO
VW
A,
@R
W2+
disp
8
MO
VW
RW
2,A
MO
VW
@R
W2+
disp
8,
A
MO
VW
RW
2,#i
mm
16
MO
VW
@R
W2+
disp
8,
#im
m16
XC
HW
A,
RW
2
XC
HW
A,
@R
W2+
disp
8
+3
JMP
@R
W3
JMP
@@
RW
3+di
sp8
CA
LL@
RW
3C
ALL
@@
RW3+
disp
8IN
CW
RW
3IN
CW
@R
W3+
disp
8D
EC
WR
W3
DE
CW
@R
W3+
disp
8M
OV
WA
,R
W3
MO
VW
A,
@R
W3+
disp
8
MO
VW
RW
3,A
MO
VW
@R
W3+
disp
8,
A
MO
VW
RW
3,#i
mm
16
MO
VW
@R
W3+
disp
8,
#im
m16
XC
HW
A,
RW
3
XC
HW
A,
@R
W3+
disp
8
+4
JMP
@R
W4
JMP
@@
RW
4+di
sp8
CA
LL@
RW
4C
ALL
@@
RW4+
disp
8IN
CW
RW
4IN
CW
@R
W4+
disp
8D
EC
WR
W4
DE
CW
@R
W4+
disp
8M
OV
WA
,R
W4
MO
VW
A,
@R
W4+
disp
8
MO
VW
RW
4,A
MO
VW
@R
W4+
disp
8,
A
MO
VW
RW
4,#i
mm
16
MO
VW
@R
W4+
disp
8,
#im
m16
XC
HW
A,
RW
4
XC
HW
A,
@R
W4+
disp
8
+5
JMP
@R
W5
JMP
@@
RW
5+di
sp8
CA
LL@
RW
5C
ALL
@@
RW5+
disp
8IN
CW
RW
5IN
CW
@R
W5+
disp
8D
EC
WR
W5
DE
CW
@R
W5+
disp
8M
OV
WA
,R
W5
MO
VW
A,
@R
W5+
disp
8
MO
VW
RW
5,A
MO
VW
@R
W5+
disp
8,
A
MO
VW
RW
5,#i
mm
16
MO
VW
@R
W5+
disp
8,
#im
m16
XC
HW
A,
RW
5
XC
HW
A,
@R
W5+
disp
8
+6
JMP
@R
W6
JMP
@@
RW
6+di
sp8
CA
LL@
RW
6C
ALL
@@
RW6+
disp
8IN
CW
RW
6IN
CW
@R
W6+
disp
8D
EC
WR
W6
DE
CW
@R
W6+
disp
8M
OV
WA
,R
W6
MO
VW
A,
@R
W6+
disp
8
MO
VW
RW
6,A
MO
VW
@R
W6+
disp
8,
A
MO
VW
RW
6,#i
mm
16
MO
VW
@R
W6+
disp
8,
#im
m16
XC
HW
A,
RW
6
XC
HW
A,
@R
W6+
disp
8
+7
JMP
@R
W7
JMP
@@
RW
7+di
sp8
CA
LL@
RW
7C
ALL
@@
RW7+
disp
8IN
CW
RW
7IN
CW
@R
W7+
disp
8D
EC
WR
W7
DE
CW
@R
W7+
disp
8M
OV
WA
,R
W7
MO
VW
A,
@R
W7+
disp
8
MO
VW
RW
7,A
MO
VW
@R
W7+
disp
8,
A
MO
VW
RW
7,#i
mm
16
MO
VW
@R
W7+
disp
8,
#im
m16
XC
HW
A,
RW
7
XC
HW
A,
@R
W7+
disp
8
+8
JMP
@@
RW
0JM
P@
@RW
0+di
sp16
CA
LL@
@R
W0
CA
LL@
@RW
0+di
sp16
INC
W@
RW
0IN
CW
@R
W0+
disp
16D
EC
W@
RW
0D
EC
W@
RW
0+di
sp16
MO
VW
A,
@R
W0
MO
VW
A,
@R
W0+
disp
16
MO
VW
@R
W0,
A
MO
VW
@R
W0+
disp
16,
A
MO
VW
@R
W0,
#im
m16
MO
VW
@R
W0+
disp
16,
#im
m16
XC
HW
A,
@R
W0
XC
HW
A,
@R
W0+
disp
16
+9
JMP
@@
RW
1JM
P@
@RW
1+di
sp16
CA
LL@
@R
W1
CA
LL@
@RW
1+di
sp16
INC
W@
RW
1IN
CW
@R
W1+
disp
16D
EC
W@
RW
1D
EC
W@
RW
1+di
sp16
MO
VW
A,
@R
W1
MO
VW
A,
@R
W1+
disp
16
MO
VW
@R
W1,
A
MO
VW
@R
W1+
disp
16,
A
MO
VW
@R
W1,
#im
m16
MO
VW
@R
W1+
disp
16,
#im
m16
XC
HW
A,
@R
W1
XC
HW
A,
@R
W1+
disp
16
+A
JMP
@@
RW
2JM
P@
@RW
2+di
sp16
CA
LL@
@R
W2
CA
LL@
@RW
2+di
sp16
INC
W@
RW
2IN
CW
@R
W2+
disp
16D
EC
W@
RW
2D
EC
W@
RW
2+di
sp16
MO
VW
A,
@R
W2
MO
VW
A,
@R
W2+
disp
16
MO
VW
@R
W2,
A
MO
VW
@R
W2+
disp
16,
A
MO
VW
@R
W2,
#im
m16
MO
VW
@R
W2+
disp
16,
#im
m16
XC
HW
A,
@R
W2
XC
HW
A,
@R
W2+
disp
16
+B
JMP
@@
RW
3JM
P@
@RW
3+di
sp16
CA
LL@
@R
W3
CA
LL@
@RW
3+di
sp16
INC
W@
RW
3IN
CW
@R
W3+
disp
16D
EC
W@
RW
3D
EC
W@
RW
3+di
sp16
MO
VW
A,
@R
W3
MO
VW
A,
@R
W3+
disp
16
MO
VW
@R
W3,
A
MO
VW
@R
W3+
disp
16,
A
MO
VW
@R
W3,
#im
m16
MO
VW
@R
W3+
disp
16,
#im
m16
XC
HW
A,
@R
W3
XC
HW
A,
@R
W3+
disp
16
+C
JMP
@@
RW
0+JM
P@
@R
W0+
RW
7C
ALL
@@
RW
0+C
ALL
@@
RW
0+R
W7
INC
W@
RW
0+IN
CW
@R
W0+
RW
7D
EC
W@
RW
0+D
EC
W@
RW
0+R
W7
MO
VW
A,
@R
W0+
MO
VW
A,
@R
W0+
RW
7
MO
VW
@R
W0+
,A
MO
VW
@R
W0+
RW
7,
A
MO
VW
@R
W0+
,#i
mm
16
MO
VW
@R
W0+
RW
7,
#im
m16
XC
HW
A,
@R
W0+
XC
HW
A,
@R
W0+
RW
7
+D
JMP
@@
RW
1+JM
P@
@R
W1+
RW
7C
ALL
@@
RW
1+C
ALL
@@
RW
1+R
W7
INC
W@
RW
1+IN
CW
@R
W1+
RW
7D
EC
W@
RW
1+D
EC
W@
RW
1+R
W7
MO
VW
A,
@R
W1+
MO
VW
A,
@R
W1+
RW
7
MO
VW
@R
W1+
,A
MO
VW
@R
W1+
RW
7,
A
MO
VW
@R
W1+
,#i
mm
16
MO
VW
@R
W1+
RW
7,
#im
m16
XC
HW
A,
@R
W1+
XC
HW
A,
@R
W1+
RW
7
+E
JMP
@@
RW
2+JM
P@
@PC
+dis
p16
CA
LL@
@R
W2+
CA
LL@
@PC
+dis
p16
INC
W@
RW
2+IN
CW
@P
C+
disp
16D
EC
W@
RW
2+D
EC
W@
PC
+di
sp16
MO
VW
A,
@R
W2+
MO
VW
A,
@P
C+
disp
16
MO
VW
@R
W2+
,A
MO
VW
@P
C+d
isp1
6,
A
MO
VW
@R
W2+
,#i
mm
16
MO
VW
@P
C+d
isp1
6,
#im
m16
XC
HW
A,
@R
W2+
XC
HW
A,
@P
C+
disp
16
+F
JMP
@@
RW
3+JM
P@
addr
16C
ALL
@@
RW
3+C
ALL
@ad
dr16
INC
W@
RW
3+IN
CW
addr
16D
EC
W@
RW
3+D
EC
Wad
dr16
MO
VW
A,
@R
W3+
MO
VW
A,
addr
16
MO
VW
@R
W3+
,A
MO
VW
addr
16,
A
MO
VW
@R
W3+
,#i
mm
16
MO
VW
addr
16,
#im
m16
XC
HW
A,
@R
W3+
XC
HW
A,
addr
16
F2MC-16FX Family
352 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.6-5 ea-type Instruction (5) (First Byte = 74H)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
AD
DA
,R
0
AD
DA
,@
RW
0+di
sp8
SU
BA
,R
0
SU
BA
,@
RW
0+di
sp8
AD
DC
A,
R0
AD
DC
A,
@R
W0+
disp
8
CM
PA
,R
0
CM
PA
,@
RW
0+di
sp8
AN
DA
,R
0
AN
DA
,@
RW
0+di
sp8
OR
A,
R0
OR
A,
@R
W0+
disp
8
XO
RA
,R
0
XO
RA
,@
RW
0+di
sp8
DB
NZ
R0,
rel
DB
NZ
@R
W0+
disp
8,
rel
+1
AD
DA
,R
1
AD
DA
,@
RW
1+di
sp8
SU
BA
,R
1
SU
BA
,@
RW
1+di
sp8
AD
DC
A,
R1
AD
DC
A,
@R
W1+
disp
8
CM
PA
,R
1
CM
PA
,@
RW
1+di
sp8
AN
DA
,R
1
AN
DA
,@
RW
1+di
sp8
OR
A,
R1
OR
A,
@R
W1+
disp
8
XO
RA
,R
1
XO
RA
,@
RW
1+di
sp8
DB
NZ
R1,
rel
DB
NZ
@R
W1+
disp
8,
rel
+2
AD
DA
,R
2
AD
DA
,@
RW
2+di
sp8
SU
BA
,R
2
SU
BA
,@
RW
2+di
sp8
AD
DC
A,
R2
AD
DC
A,
@R
W2+
disp
8
CM
PA
,R
2
CM
PA
,@
RW
2+di
sp8
AN
DA
,R
2
AN
DA
,@
RW
2+di
sp8
OR
A,
R2
OR
A,
@R
W2+
disp
8
XO
RA
,R
2
XO
RA
,@
RW
2+di
sp8
DB
NZ
R2,
rel
DB
NZ
@R
W2+
disp
8,
rel
+3
AD
DA
,R
3
AD
DA
,@
RW
3+di
sp8
SU
BA
,R
3
SU
BA
,@
RW
3+di
sp8
AD
DC
A,
R3
AD
DC
A,
@R
W3+
disp
8
CM
PA
,R
3
CM
PA
,@
RW
3+di
sp8
AN
DA
,R
3
AN
DA
,@
RW
3+di
sp8
OR
A,
R3
OR
A,
@R
W3+
disp
8
XO
RA
,R
3
XO
RA
,@
RW
3+di
sp8
DB
NZ
R3,
rel
DB
NZ
@R
W3+
disp
8,
rel
+4
AD
DA
,R
4
AD
DA
,@
RW
4+di
sp8
SU
BA
,R
4
SU
BA
,@
RW
4+di
sp8
AD
DC
A,
R4
AD
DC
A,
@R
W4+
disp
8
CM
PA
,R
4
CM
PA
,@
RW
4+di
sp8
AN
DA
,R
4
AN
DA
,@
RW
4+di
sp8
OR
A,
R4
OR
A,
@R
W4+
disp
8
XO
RA
,R
4
XO
RA
,@
RW
4+di
sp8
DB
NZ
R4,
rel
DB
NZ
@R
W4+
disp
8,
rel
+5
AD
DA
,R
5
AD
DA
,@
RW
5+di
sp8
SU
BA
,R
5
SU
BA
,@
RW
5+di
sp8
AD
DC
A,
R5
AD
DC
A,
@R
W5+
disp
8
CM
PA
,R
5
CM
PA
,@
RW
5+di
sp8
AN
DA
,R
5
AN
DA
,@
RW
5+di
sp8
OR
A,
R5
OR
A,
@R
W5+
disp
8
XO
RA
,R
5
XO
RA
,@
RW
5+di
sp8
DB
NZ
R5,
rel
DB
NZ
@R
W5+
disp
8,
rel
+6
AD
DA
,R
6
AD
DA
,@
RW
6+di
sp8
SU
BA
,R
6
SU
BA
,@
RW
6+di
sp8
AD
DC
A,
R6
AD
DC
A,
@R
W6+
disp
8
CM
PA
,R
6
CM
PA
,@
RW
6+di
sp8
AN
DA
,R
6
AN
DA
,@
RW
6+di
sp8
OR
A,
R6
OR
A,
@R
W6+
disp
8
XO
RA
,R
6
XO
RA
,@
RW
6+di
sp8
DB
NZ
R6,
rel
DB
NZ
@R
W6+
disp
8,
rel
+7
AD
DA
,R
7
AD
DA
,@
RW
7+di
sp8
SU
BA
,R
7
SU
BA
,@
RW
7+di
sp8
AD
DC
A,
R7
AD
DC
A,
@R
W7+
disp
8
CM
PA
,R
7
CM
PA
,@
RW
7+di
sp8
AN
DA
,R
7
AN
DA
,@
RW
7+di
sp8
OR
A,
R7
OR
A,
@R
W7+
disp
8
XO
RA
,R
7
XO
RA
,@
RW
7+di
sp8
DB
NZ
R7,
rel
DB
NZ
@R
W7+
disp
8,
rel
+8
AD
DA
,@
RW
0
AD
DA
,@
RW
0+di
sp16
SU
BA
,@
RW
0
SU
BA
,@
RW
0+di
sp16
AD
DC
A,
@R
W0
AD
DC
A,
@R
W0+
disp
16
CM
PA
,@
RW
0
CM
PA
,@
RW
0+di
sp16
AN
DA
,@
RW
0
AN
DA
,@
RW
0+di
sp16
OR
A,
@R
W0
OR
A,
@R
W0+
disp
16
XO
RA
,@
RW
0
XO
RA
,@
RW
0+di
sp16
DB
NZ
@R
W0,
rel
DB
NZ
@R
W0+
disp
16,
rel
+9
AD
DA
,@
RW
1
AD
DA
,@
RW
1+di
sp16
SU
BA
,@
RW
1
SU
BA
,@
RW
1+di
sp16
AD
DC
A,
@R
W1
AD
DC
A,
@R
W1+
disp
16
CM
PA
,@
RW
1
CM
PA
,@
RW
1+di
sp16
AN
DA
,@
RW
1
AN
DA
,@
RW
1+di
sp16
OR
A,
@R
W1
OR
A,
@R
W1+
disp
16
XO
RA
,@
RW
1
XO
RA
,@
RW
1+di
sp16
DB
NZ
@R
W1,
rel
DB
NZ
@R
W1+
disp
16,
rel
+A
AD
DA
,@
RW
2
AD
DA
,@
RW
2+di
sp16
SU
BA
,@
RW
2
SU
BA
,@
RW
2+di
sp16
AD
DC
A,
@R
W2
AD
DC
A,
@R
W2+
disp
16
CM
PA
,@
RW
2
CM
PA
,@
RW
2+di
sp16
AN
DA
,@
RW
2
AN
DA
,@
RW
2+di
sp16
OR
A,
@R
W2
OR
A,
@R
W2+
disp
16
XO
RA
,@
RW
2
XO
RA
,@
RW
2+di
sp16
DB
NZ
@R
W2,
rel
DB
NZ
@R
W2+
disp
16,
rel
+B
AD
DA
,@
RW
3
AD
DA
,@
RW
3+di
sp16
SU
BA
,@
RW
3
SU
BA
,@
RW
3+di
sp16
AD
DC
A,
@R
W3
AD
DC
A,
@R
W3+
disp
16
CM
PA
,@
RW
3
CM
PA
,@
RW
3+di
sp16
AN
DA
,@
RW
3
AN
DA
,@
RW
3+di
sp16
OR
A,
@R
W3
OR
A,
@R
W3+
disp
16
XO
RA
,@
RW
3
XO
RA
,@
RW
3+di
sp16
DB
NZ
@R
W3,
rel
DB
NZ
@R
W3+
disp
16,
rel
+C
AD
DA
,@
RW
0+
AD
DA
,@
RW
0+R
W7
SU
BA
,@
RW
0+
SU
BA
,@
RW
0+R
W7
AD
DC
A,
@R
W0+
AD
DC
A,
@R
W0+
RW
7
CM
PA
,@
RW
0+
CM
PA
,@
RW
0+R
W7
AN
DA
,@
RW
0+
AN
DA
,@
RW
0+R
W7
OR
A,
@R
W0+
OR
A,
@R
W0+
RW
7
XO
RA
,@
RW
0+
XO
RA
,@
RW
0+R
W7
DB
NZ
@R
W0+
,re
l
DB
NZ
@R
W0+
RW
7,
rel
+D
AD
DA
,@
RW
1+
AD
DA
,@
RW
1+R
W7
SU
BA
,@
RW
1+
SU
BA
,@
RW
1+R
W7
AD
DC
A,
@R
W1+
AD
DC
A,
@R
W1+
RW
7
CM
PA
,@
RW
1+
CM
PA
,@
RW
1+R
W7
AN
DA
,@
RW
1+
AN
DA
,@
RW
1+R
W7
OR
A,
@R
W1+
OR
A,
@R
W1+
RW
7
XO
RA
,@
RW
1+
XO
RA
,@
RW
1+R
W7
DB
NZ
@R
W1+
,re
l
DB
NZ
@R
W1+
RW
7,
rel
+E
AD
DA
,@
RW
2+
AD
DA
,@
PC
+di
sp16
SU
BA
,@
RW
2+
SU
BA
,@
PC
+di
sp16
AD
DC
A,
@R
W2+
AD
DC
A,
@P
C+
disp
16
CM
PA
,@
RW
2+
CM
PA
,@
PC
+di
sp16
AN
DA
,@
RW
2+
AN
DA
,@
PC
+di
sp16
OR
A,
@R
W2+
OR
A,
@P
C+
disp
16
XO
RA
,@
RW
2+
XO
RA
,@
PC
+di
sp16
DB
NZ
@R
W2+
,re
l
DB
NZ
@P
C+d
isp1
6,
rel
+F
AD
DA
,@
RW
3+
AD
DA
,ad
dr16
SU
BA
,@
RW
3+
SU
BA
,ad
dr16
AD
DC
A,
@R
W3+
AD
DC
A,
addr
16
CM
PA
,@
RW
3+
CM
PA
,ad
dr16
AN
DA
,@
RW
3+
AN
DA
,ad
dr16
OR
A,
@R
W3+
OR
A,
addr
16
XO
RA
,@
RW
3+
XO
RA
,ad
dr16
DB
NZ
@R
W3+
,re
l
DB
NZ
addr
16,
rel
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 353
APPENDIXAPPENDIX C Instruction Maps
Table C.6-6 ea-type Instruction (6) (First Byte = 75H)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
AD
DR
0,A
AD
D@
RW
0+di
sp8,
A
SU
BR
0,A
SU
B@
RW
0+di
sp8,
A
SU
BC
A,
R0
SU
BC
A,
@R
W0+
disp
8
NE
GR
0N
EG
@R
W0+
disp
8A
ND
R0,
A
AN
D@
RW
0+di
sp8,
A
OR
R0,
A
OR
@R
W0+
disp
8,A
XO
RR
0,A
XO
R@
RW
0+di
sp8,
A
NO
TR
0N
OT
@R
W0+
disp
8
+1
AD
DR
1,A
AD
D@
RW
1+di
sp8,
A
SU
BR
1,A
SU
B@
RW
1+di
sp8,
A
SU
BC
A,
R1
SU
BC
A,
@R
W1+
disp
8
NE
GR
1N
EG
@R
W1+
disp
8A
ND
R1,
A
AN
D@
RW
1+di
sp8,
A
OR
R1,
A
OR
@R
W1+
disp
8,A
XO
RR
1,A
XO
R@
RW
1+di
sp8,
A
NO
TR
1N
OT
@R
W1+
disp
8
+2
AD
DR
2,A
AD
D@
RW
2+di
sp8,
A
SU
BR
2,A
SU
B@
RW
2+di
sp8,
A
SU
BC
A,
R2
SU
BC
A,
@R
W2+
disp
8
NE
GR
2N
EG
@R
W2+
disp
8A
ND
R2,
A
AN
D@
RW
2+di
sp8,
A
OR
R2,
A
OR
@R
W2+
disp
8,A
XO
RR
2,A
XO
R@
RW
2+di
sp8,
A
NO
TR
2N
OT
@R
W2+
disp
8
+3
AD
DR
3,A
AD
D@
RW
3+di
sp8,
A
SU
BR
3,A
SU
B@
RW
3+di
sp8,
A
SU
BC
A,
R3
SU
BC
A,
@R
W3+
disp
8
NE
GR
3N
EG
@R
W3+
disp
8A
ND
R3,
A
AN
D@
RW
3+di
sp8,
A
OR
R3,
A
OR
@R
W3+
disp
8,A
XO
RR
3,A
XO
R@
RW
3+di
sp8,
A
NO
TR
3N
OT
@R
W3+
disp
8
+4
AD
DR
4,A
AD
D@
RW
4+di
sp8,
A
SU
BR
4,A
SU
B@
RW
4+di
sp8,
A
SU
BC
A,
R4
SU
BC
A,
@R
W4+
disp
8
NE
GR
4N
EG
@R
W4+
disp
8A
ND
R4,
A
AN
D@
RW
4+di
sp8,
A
OR
R4,
A
OR
@R
W4+
disp
8,A
XO
RR
4,A
XO
R@
RW
4+di
sp8,
A
NO
TR
4N
OT
@R
W4+
disp
8
+5
AD
DR
5,A
AD
D@
RW
5+di
sp8,
A
SU
BR
5,A
SU
B@
RW
5+di
sp8,
A
SU
BC
A,
R5
SU
BC
A,
@R
W5+
disp
8
NE
GR
5N
EG
@R
W5+
disp
8A
ND
R5,
A
AN
D@
RW
5+di
sp8,
A
OR
R5,
A
OR
@R
W5+
disp
8,A
XO
RR
5,A
XO
R@
RW
5+di
sp8,
A
NO
TR
5N
OT
@R
W5+
disp
8
+6
AD
DR
6,A
AD
D@
RW
6+di
sp8,
A
SU
BR
6,A
SU
B@
RW
6+di
sp8,
A
SU
BC
A,
R6
SU
BC
A,
@R
W6+
disp
8
NE
GR
6N
EG
@R
W6+
disp
8A
ND
R6,
A
AN
D@
RW
6+di
sp8,
A
OR
R6,
A
OR
@R
W6+
disp
8,A
XO
RR
6,A
XO
R@
RW
6+di
sp8,
A
NO
TR
6N
OT
@R
W6+
disp
8
+7
AD
DR
7,A
AD
D@
RW
7+di
sp8,
A
SU
BR
7,A
SU
B@
RW
7+di
sp8,
A
SU
BC
A,
R7
SU
BC
A,
@R
W7+
disp
8
NE
GR
7N
EG
@R
W7+
disp
8A
ND
R7,
A
AN
D@
RW
7+di
sp8,
A
OR
R7,
A
OR
@R
W7+
disp
8,A
XO
RR
7,A
XO
R@
RW
7+di
sp8,
A
NO
TR
7N
OT
@R
W7+
disp
8
+8
AD
D@
RW
0,A
AD
D@
RW
0+di
sp16
,A
SU
B@
RW
0,A
SU
B@
RW
0+di
sp16
,A
SU
BC
A,
@R
W0
SU
BC
A,
@R
W0+
disp
16
NE
G@
RW
0N
EG
@R
W0+
disp
16A
ND
@R
W0,
A
AN
D@
RW
0+di
sp16
,A
OR
@R
W0,
A
OR
@R
W0+
disp
16,
A
XO
R@
RW
0,A
XO
R@
RW
0+di
sp16
,A
NO
T@
RW
0N
OT
@R
W0+
disp
16
+9
AD
D@
RW
1,A
AD
D@
RW
1+di
sp16
,A
SU
B@
RW
1,A
SU
B@
RW
1+di
sp16
,A
SU
BC
A,
@R
W1
SU
BC
A,
@R
W1+
disp
16
NE
G@
RW
1N
EG
@R
W1+
disp
16A
ND
@R
W1,
A
AN
D@
RW
1+di
sp16
,A
OR
@R
W1,
A
OR
@R
W1+
disp
16,
A
XO
R@
RW
1,A
XO
R@
RW
1+di
sp16
,A
NO
T@
RW
1N
OT
@R
W1+
disp
16
+A
AD
D@
RW
2,A
AD
D@
RW
2+di
sp16
,A
SU
B@
RW
2,A
SU
B@
RW
2+di
sp16
,A
SU
BC
A,
@R
W2
SU
BC
A,
@R
W2+
disp
16
NE
G@
RW
2N
EG
@R
W2+
disp
16A
ND
@R
W2,
A
AN
D@
RW
2+di
sp16
,A
OR
@R
W2,
A
OR
@R
W2+
disp
16,
A
XO
R@
RW
2,A
XO
R@
RW
2+di
sp16
,A
NO
T@
RW
2N
OT
@R
W2+
disp
16
+B
AD
D@
RW
3,A
AD
D@
RW
3+di
sp16
,A
SU
B@
RW
3,A
SU
B@
RW
3+di
sp16
,A
SU
BC
A,
@R
W3
SU
BC
A,
@R
W3+
disp
16
NE
G@
RW
3N
EG
@R
W3+
disp
16A
ND
@R
W3,
A
AN
D@
RW
3+di
sp16
,A
OR
@R
W3,
A
OR
@R
W3+
disp
16,
A
XO
R@
RW
3,A
XO
R@
RW
3+di
sp16
,A
NO
T@
RW
3N
OT
@R
W3+
disp
16
+C
AD
D@
RW
0+,
A
AD
D@
RW
0+R
W7,
A
SU
B@
RW
0+,
A
SU
B@
RW
0+R
W7,
A
SU
BC
A,
@R
W0+
SU
BC
A,
@R
W0+
RW
7
NE
G@
RW
0+N
EG
@R
W0+
RW
7A
ND
@R
W0+
,A
AN
D@
RW
0+R
W7,
A
OR
@R
W0+
,A
OR
@R
W0+
RW
7,A
XO
R@
RW
0+,
A
XO
R@
RW
0+R
W7,
A
NO
T@
RW
0+N
OT
@R
W0+
RW
7
+D
AD
D@
RW
1+,
A
AD
D@
RW
1+R
W7,
A
SU
B@
RW
1+,
A
SU
B@
RW
1+R
W7,
A
SU
BC
A,
@R
W1+
SU
BC
A,
@R
W1+
RW
7
NE
G@
RW
1+N
EG
@R
W1+
RW
7A
ND
@R
W1+
,A
AN
D@
RW
1+R
W7,
A
OR
@R
W1+
,A
OR
@R
W1+
RW
7,A
XO
R@
RW
1+,
A
XO
R@
RW
1+R
W7,
A
NO
T@
RW
1+N
OT
@R
W1+
RW
7
+E
AD
D@
RW
2+,
A
AD
D@
PC
+dis
p16,
A
SU
B@
RW
2+,
A
SU
B@
PC
+dis
p16,
A
SU
BC
A,
@R
W2+
SU
BC
A,
@P
C+
disp
16
NE
G@
RW
2+N
EG
@P
C+
disp
16A
ND
@R
W2+
,A
AN
D@
PC
+dis
p16,
A
OR
@R
W2+
,A
OR
@P
C+d
isp1
6,A
XO
R@
RW
2+,
A
XO
R@
PC
+dis
p16,
A
NO
T@
RW
2+N
OT
@P
C+
disp
16
+F
AD
D@
RW
3+,
A
AD
Dad
dr16
,A
SU
B@
RW
3+,
A
SU
Bad
dr16
,A
SU
BC
A,
@R
W3+
SU
BC
A,
addr
16
NE
G@
RW
3+N
EG
addr
16A
ND
@R
W3+
,A
AN
Dad
dr16
,A
OR
@R
W3+
,A
OR
addr
16,
A
XO
R@
RW
3+,
A
XO
Rad
dr16
,A
NO
T@
RW
3+N
OT
addr
16
F2MC-16FX Family
354 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.6-7 ea-type Instruction (7) (First Byte = 76H)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
AD
DW
A,
RW
0
AD
DW
A,
@R
W0+
disp
8
SU
BW
A,
RW
0
SU
BW
A,
@R
W0+
disp
8
AD
DC
WA
,R
W0
AD
DC
WA
,@
RW
0+di
sp8
CM
PW
A,
RW
0
CM
PW
A,
@R
W0+
disp
8
AN
DW
A,
RW
0
AN
DW
A,
@R
W0+
disp
8
OR
WA
,R
W0
OR
WA
,@
RW
0+di
sp8
XO
RW
A,
RW
0
XO
RW
A,
@R
W0+
disp
8
DW
BN
ZR
W0,
rel
DW
BN
Z@
RW
0+di
sp8,
rel
+1
AD
DW
A,
RW
1
AD
DW
A,
@R
W1+
disp
8
SU
BW
A,
RW
1
SU
BW
A,
@R
W1+
disp
8
AD
DC
WA
,R
W1
AD
DC
WA
,@
RW
1+di
sp8
CM
PW
A,
RW
1
CM
PW
A,
@R
W1+
disp
8
AN
DW
A,
RW
1
AN
DW
A,
@R
W1+
disp
8
OR
WA
,R
W1
OR
WA
,@
RW
1+di
sp8
XO
RW
A,
RW
1
XO
RW
A,
@R
W1+
disp
8
DW
BN
ZR
W1,
rel
DW
BN
Z@
RW
1+di
sp8,
rel
+2
AD
DW
A,
RW
2
AD
DW
A,
@R
W2+
disp
8
SU
BW
A,
RW
2
SU
BW
A,
@R
W2+
disp
8
AD
DC
WA
,R
W2
AD
DC
WA
,@
RW
2+di
sp8
CM
PW
A,
RW
2
CM
PW
A,
@R
W2+
disp
8
AN
DW
A,
RW
2
AN
DW
A,
@R
W2+
disp
8
OR
WA
,R
W2
OR
WA
,@
RW
2+di
sp8
XO
RW
A,
RW
2
XO
RW
A,
@R
W2+
disp
8
DW
BN
ZR
W2,
rel
DW
BN
Z@
RW
2+di
sp8,
rel
+3
AD
DW
A,
RW
3
AD
DW
A,
@R
W3+
disp
8
SU
BW
A,
RW
3
SU
BW
A,
@R
W3+
disp
8
AD
DC
WA
,R
W3
AD
DC
WA
,@
RW
3+di
sp8
CM
PW
A,
RW
3
CM
PW
A,
@R
W3+
disp
8
AN
DW
A,
RW
3
AN
DW
A,
@R
W3+
disp
8
OR
WA
,R
W3
OR
WA
,@
RW
3+di
sp8
XO
RW
A,
RW
3
XO
RW
A,
@R
W3+
disp
8
DW
BN
ZR
W3,
rel
DW
BN
Z@
RW
3+di
sp8,
rel
+4
AD
DW
A,
RW
4
AD
DW
A,
@R
W4+
disp
8
SU
BW
A,
RW
4
SU
BW
A,
@R
W4+
disp
8
AD
DC
WA
,R
W4
AD
DC
WA
,@
RW
4+di
sp8
CM
PW
A,
RW
4
CM
PW
A,
@R
W4+
disp
8
AN
DW
A,
RW
4
AN
DW
A,
@R
W4+
disp
8
OR
WA
,R
W4
OR
WA
,@
RW
4+di
sp8
XO
RW
A,
RW
4
XO
RW
A,
@R
W4+
disp
8
DW
BN
ZR
W4,
rel
DW
BN
Z@
RW
4+di
sp8,
rel
+5
AD
DW
A,
RW
5
AD
DW
A,
@R
W5+
disp
8
SU
BW
A,
RW
5
SU
BW
A,
@R
W5+
disp
8
AD
DC
WA
,R
W5
AD
DC
WA
,@
RW
5+di
sp8
CM
PW
A,
RW
5
CM
PW
A,
@R
W5+
disp
8
AN
DW
A,
RW
5
AN
DW
A,
@R
W5+
disp
8
OR
WA
,R
W5
OR
WA
,@
RW
5+di
sp8
XO
RW
A,
RW
5
XO
RW
A,
@R
W5+
disp
8
DW
BN
ZR
W5,
rel
DW
BN
Z@
RW
5+di
sp8,
rel
+6
AD
DW
A,
RW
6
AD
DW
A,
@R
W6+
disp
8
SU
BW
A,
RW
6
SU
BW
A,
@R
W6+
disp
8
AD
DC
WA
,R
W6
AD
DC
WA
,@
RW
6+di
sp8
CM
PW
A,
RW
6
CM
PW
A,
@R
W6+
disp
8
AN
DW
A,
RW
6
AN
DW
A,
@R
W6+
disp
8
OR
WA
,R
W6
OR
WA
,@
RW
6+di
sp8
XO
RW
A,
RW
6
XO
RW
A,
@R
W6+
disp
8
DW
BN
ZR
W6,
rel
DW
BN
Z@
RW
6+di
sp8,
rel
+7
AD
DW
A,
RW
7
AD
DW
A,
@R
W7+
disp
8
SU
BW
A,
RW
7
SU
BW
A,
@R
W7+
disp
8
AD
DC
WA
,R
W7
AD
DC
WA
,@
RW
7+di
sp8
CM
PW
A,
RW
7
CM
PW
A,
@R
W7+
disp
8
AN
DW
A,
RW
7
AN
DW
A,
@R
W7+
disp
8
OR
WA
,R
W7
OR
WA
,@
RW
7+di
sp8
XO
RW
A,
RW
7
XO
RW
A,
@R
W7+
disp
8
DW
BN
ZR
W7,
rel
DW
BN
Z@
RW
7+di
sp8,
rel
+8
AD
DW
A,
@R
W0
AD
DW
A,
@R
W0+
disp
16
SU
BW
A,
@R
W0
SU
BW
A,
@R
W0+
disp
16
AD
DC
WA
,@
RW
0
AD
DC
WA
,@
RW
0+di
sp16
CM
PW
A,
@R
W0
CM
PW
A,
@R
W0+
disp
16
AN
DW
A,
@R
W0
AN
DW
A,
@R
W0+
disp
16
OR
WA
,@
RW
0
OR
WA
,@
RW
0+di
sp16
XO
RW
A,
@R
W0
XO
RW
A,
@R
W0+
disp
16
DW
BN
Z@
RW
0,re
l
DW
BN
Z@
RW
0+di
sp16
,re
l
+9
AD
DW
A,
@R
W1
AD
DW
A,
@R
W1+
disp
16
SU
BW
A,
@R
W1
SU
BW
A,
@R
W1+
disp
16
AD
DC
WA
,@
RW
1
AD
DC
WA
,@
RW
1+di
sp16
CM
PW
A,
@R
W1
CM
PW
A,
@R
W1+
disp
16
AN
DW
A,
@R
W1
AN
DW
A,
@R
W1+
disp
16
OR
WA
,@
RW
1
OR
WA
,@
RW
1+di
sp16
XO
RW
A,
@R
W1
XO
RW
A,
@R
W1+
disp
16
DW
BN
Z@
RW
1,re
l
DW
BN
Z@
RW
1+di
sp16
,
rel
+A
AD
DW
A,
@R
W2
AD
DW
A,
@R
W2+
disp
16
SU
BW
A,
@R
W2
SU
BW
A,
@R
W2+
disp
16
AD
DC
WA
,@
RW
2
AD
DC
WA
,@
RW
2+di
sp16
CM
PW
A,
@R
W2
CM
PW
A,
@R
W2+
disp
16
AN
DW
A,
@R
W2
AN
DW
A,
@R
W2+
disp
16
OR
WA
,@
RW
2
OR
WA
,@
RW
2+di
sp16
XO
RW
A,
@R
W2
XO
RW
A,
@R
W2+
disp
16
DW
BN
Z@
RW
2,re
l
DW
BN
Z@
RW
2+di
sp16
,
rel
+B
AD
DW
A,
@R
W3
AD
DW
A,
@R
W3+
disp
16
SU
BW
A,
@R
W3
SU
BW
A,
@R
W3+
disp
16
AD
DC
WA
,@
RW
3
AD
DC
WA
,@
RW
3+di
sp16
CM
PW
A,
@R
W3
CM
PW
A,
@R
W3+
disp
16
AN
DW
A,
@R
W3
AN
DW
A,
@R
W3+
disp
16
OR
WA
,@
RW
3
OR
WA
,@
RW
3+di
sp16
XO
RW
A,
@R
W3
XO
RW
A,
@R
W3+
disp
16
DW
BN
Z@
RW
3,re
l
DW
BN
Z@
RW
3+di
sp16
,
rel
+C
AD
DW
A,
@R
W0+
AD
DW
A,
@R
W0+
RW
7
SU
BW
A,
@R
W0+
SU
BW
A,
@R
W0+
RW
7
AD
DC
WA
,@
RW
0+
AD
DC
WA
,@
RW
0+R
W7
CM
PW
A,
@R
W0+
CM
PW
A,
@R
W0+
RW
7
AN
DW
A,
@R
W0+
AN
DW
A,
@R
W0+
RW
7
OR
WA
,@
RW
0+
OR
WA
,@
RW
0+R
W7
XO
RW
A,
@R
W0+
XO
RW
A,
@R
W0+
RW
7
DW
BN
Z@
RW
0+,
rel
DW
BN
Z@
RW
0+R
W7,
rel
+D
AD
DW
A,
@R
W1+
AD
DW
A,
@R
W1+
RW
7
SU
BW
A,
@R
W1+
SU
BW
A,
@R
W1+
RW
7
AD
DC
WA
,@
RW
1+
AD
DC
WA
,@
RW
1+R
W7
CM
PW
A,
@R
W1+
CM
PW
A,
@R
W1+
RW
7
AN
DW
A,
@R
W1+
AN
DW
A,
@R
W1+
RW
7
OR
WA
,@
RW
1+
OR
WA
,@
RW
1+R
W7
XO
RW
A,
@R
W1+
XO
RW
A,
@R
W1+
RW
7
DW
BN
Z@
RW
1+,
rel
DW
BN
Z@
RW
1+R
W7,
rel
+E
AD
DW
A,
@R
W2+
AD
DW
A,
@P
C+
disp
16
SU
BW
A,
@R
W2+
SU
BW
A,
@P
C+
disp
16
AD
DC
WA
,@
RW
2+
AD
DC
WA
,@
PC
+di
sp16
CM
PW
A,
@R
W2+
CM
PW
A,
@P
C+
disp
16
AN
DW
A,
@R
W2+
AN
DW
A,
@P
C+
disp
16
OR
WA
,@
RW
2+
OR
WA
,@
PC
+di
sp16
XO
RW
A,
@R
W2+
XO
RW
A,
@P
C+
disp
16
DW
BN
Z@
RW
2+,
rel
DW
BN
Z@
PC
+dis
p16,
rel
+F
AD
DW
A,
@R
W3+
AD
DW
A,
addr
16
SU
BW
A,
@R
W3+
SU
BW
A,
addr
16
AD
DC
WA
,@
RW
3+
AD
DC
WA
,ad
dr16
CM
PW
A,
@R
W3+
CM
PW
A,
addr
16
AN
DW
A,
@R
W3+
AN
DW
A,
addr
16
OR
WA
,@
RW
3+
OR
WA
,ad
dr16
XO
RW
A,
@R
W3+
XO
RW
A,
addr
16
DW
BN
Z@
RW
3+,
rel
DW
BN
Zad
dr16
,re
l
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 355
APPENDIXAPPENDIX C Instruction Maps
Table C.6-8 ea-type Instruction (8) (First Byte = 77H)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
AD
DW
RW
0,A
AD
DW
@R
W0+
disp
8,A
SU
BW
RW
0,A
SU
BW
@R
W0+
disp
8,A
SU
BC
WA
,R
W0
SU
BC
WA
,@
RW
0+di
sp8
NE
GW
RW
0N
EG
W@
RW
0+di
sp8
AN
DW
RW
0,A
AN
DW
@R
W0+
disp
8,A
OR
WR
W0,
A
OR
W@
RW
0+di
sp8,
A
XO
RW
RW
0,A
XO
RW
@R
W0+
disp
8,A
NO
TW
RW
0N
OT
W@
RW
0+di
sp8
+1
AD
DW
RW
1,A
AD
DW
@R
W1+
disp
8,A
SU
BW
RW
1,A
SU
BW
@R
W1+
disp
8,A
SU
BC
WA
,R
W1
SU
BC
WA
,@
RW
1+di
sp8
NE
GW
RW
1N
EG
W@
RW
1+di
sp8
AN
DW
RW
1,A
AN
DW
@R
W1+
disp
8,A
OR
WR
W1,
A
OR
W@
RW
1+di
sp8,
A
XO
RW
RW
1,A
XO
RW
@R
W1+
disp
8,A
NO
TW
RW
1N
OT
W@
RW
1+di
sp8
+2
AD
DW
RW
2,A
AD
DW
@R
W2+
disp
8,A
SU
BW
RW
2,A
SU
BW
@R
W2+
disp
8,A
SU
BC
WA
,R
W2
SU
BC
WA
,@
RW
2+di
sp8
NE
GW
RW
2N
EG
W@
RW
2+di
sp8
AN
DW
RW
2,A
AN
DW
@R
W2+
disp
8,A
OR
WR
W2,
A
OR
W@
RW
2+di
sp8,
A
XO
RW
RW
2,A
XO
RW
@R
W2+
disp
8,A
NO
TW
RW
2N
OT
W@
RW
2+di
sp8
+3
AD
DW
RW
3,A
AD
DW
@R
W3+
disp
8,A
SU
BW
RW
3,A
SU
BW
@R
W3+
disp
8,A
SU
BC
WA
,R
W3
SU
BC
WA
,@
RW
3+di
sp8
NE
GW
RW
3N
EG
W@
RW
3+di
sp8
AN
DW
RW
3,A
AN
DW
@R
W3+
disp
8,A
OR
WR
W3,
A
OR
W@
RW
3+di
sp8,
A
XO
RW
RW
3,A
XO
RW
@R
W3+
disp
8,A
NO
TW
RW
3N
OT
W@
RW
3+di
sp8
+4
AD
DW
RW
4,A
AD
DW
@R
W4+
disp
8,A
SU
BW
RW
4,A
SU
BW
@R
W4+
disp
8,A
SU
BC
WA
,R
W4
SU
BC
WA
,@
RW
4+di
sp8
NE
GW
RW
4N
EG
W@
RW
4+di
sp8
AN
DW
RW
4,A
AN
DW
@R
W4+
disp
8,A
OR
WR
W4,
A
OR
W@
RW
4+di
sp8,
A
XO
RW
RW
4,A
XO
RW
@R
W4+
disp
8,A
NO
TW
RW
4N
OT
W@
RW
4+di
sp8
+5
AD
DW
RW
5,A
AD
DW
@R
W5+
disp
8,A
SU
BW
RW
5,A
SU
BW
@R
W5+
disp
8,A
SU
BC
WA
,R
W5
SU
BC
WA
,@
RW
5+di
sp8
NE
GW
RW
5N
EG
W@
RW
5+di
sp8
AN
DW
RW
5,A
AN
DW
@R
W5+
disp
8,A
OR
WR
W5,
A
OR
W@
RW
5+di
sp8,
A
XO
RW
RW
5,A
XO
RW
@R
W5+
disp
8,A
NO
TW
RW
5N
OT
W@
RW
5+di
sp8
+6
AD
DW
RW
6,A
AD
DW
@R
W6+
disp
8,A
SU
BW
RW
6,A
SU
BW
@R
W6+
disp
8,A
SU
BC
WA
,R
W6
SU
BC
WA
,@
RW
6+di
sp8
NE
GW
RW
6N
EG
W@
RW
6+di
sp8
AN
DW
RW
6,A
AN
DW
@R
W6+
disp
8,A
OR
WR
W6,
A
OR
W@
RW
6+di
sp8,
A
XO
RW
RW
6,A
XO
RW
@R
W6+
disp
8,A
NO
TW
RW
6N
OT
W@
RW
6+di
sp8
+7
AD
DW
RW
7,A
AD
DW
@R
W7+
disp
8,A
SU
BW
RW
7,A
SU
BW
@R
W7+
disp
8,A
SU
BC
WA
,R
W7
SU
BC
WA
,@
RW
7+di
sp8
NE
GW
RW
7N
EG
W@
RW
7+di
sp8
AN
DW
RW
7,A
AN
DW
@R
W7+
disp
8,A
OR
WR
W7,
A
OR
W@
RW
7+di
sp8,
A
XO
RW
RW
7,A
XO
RW
@R
W7+
disp
8,A
NO
TW
RW
7N
OT
W@
RW
7+di
sp8
+8
AD
DW
@R
W0,
A
AD
DW
@R
W0+
disp
16,
A
SU
BW
@R
W0,
A
SU
BW
@R
W0+
disp
16,
A
SU
BC
WA
,@
RW
0
SU
BC
WA
,@
RW
0+di
sp16
NE
GW
@R
W0
NE
GW
@R
W0+
disp
16A
ND
W@
RW
0,A
AN
DW
@R
W0+
disp
16,
A
OR
W@
RW
0,A
OR
W@
RW
0+di
sp16
,A
XO
RW
@R
W0,
A
XO
RW
@R
W0+
disp
16,
A
NO
TW
@R
W0
NO
TW
@R
W0+
disp
16
+9
AD
DW
@R
W1,
A
AD
DW
@R
W1+
disp
16,
A
SU
BW
@R
W1,
A
SU
BW
@R
W1+
disp
16,
A
SU
BC
WA
,@
RW
1
SU
BC
WA
,@
RW
1+di
sp16
NE
GW
@R
W1
NE
GW
@R
W1+
disp
16A
ND
W@
RW
1,A
AN
DW
@R
W1+
disp
16,
A
OR
W@
RW
1,A
OR
W@
RW
1+di
sp16
,A
XO
RW
@R
W1,
A
XO
RW
@R
W1+
disp
16,
A
NO
TW
@R
W1
NO
TW
@R
W1+
disp
16
+A
AD
DW
@R
W2,
A
AD
DW
@R
W2+
disp
16,
A
SU
BW
@R
W2,
A
SU
BW
@R
W2+
disp
16,
A
SU
BC
WA
,@
RW
2
SU
BC
WA
,@
RW
2+di
sp16
NE
GW
@R
W2
NE
GW
@R
W2+
disp
16A
ND
W@
RW
2,A
AN
DW
@R
W2+
disp
16,
A
OR
W@
RW
2,A
OR
W@
RW
2+di
sp16
,A
XO
RW
@R
W2,
A
XO
RW
@R
W2+
disp
16,
A
NO
TW
@R
W2
NO
TW
@R
W2+
disp
16
+B
AD
DW
@R
W3,
A
AD
DW
@R
W3+
disp
16,
A
SU
BW
@R
W3,
A
SU
BW
@R
W3+
disp
16,
A
SU
BC
WA
,@
RW
3
SU
BC
WA
,@
RW
3+di
sp16
NE
GW
@R
W3
NE
GW
@R
W3+
disp
16A
ND
W@
RW
3,A
AN
DW
@R
W3+
disp
16,
A
OR
W@
RW
3,A
OR
W@
RW
3+di
sp16
,A
XO
RW
@R
W3,
A
XO
RW
@R
W3+
disp
16,
A
NO
TW
@R
W3
NO
TW
@R
W3+
disp
16
+C
AD
DW
@R
W0+
,A
AD
DW
@R
W0+
RW
7,A
SU
BW
@R
W0+
,A
SU
BW
@R
W0+
RW
7,A
SU
BC
WA
,@
RW
0+
SU
BC
WA
,@
RW
0+R
W7
NE
GW
@R
W0+
NE
GW
@R
W0+
RW
7A
ND
W@
RW
0+,
A
AN
DW
@R
W0+
RW
7,A
OR
W@
RW
0+,
A
OR
W@
RW
0+R
W7,
A
XO
RW
@R
W0+
,A
XO
RW
@R
W0+
RW
7,A
NO
TW
@R
W0+
NO
TW
@R
W0+
RW
7
+D
AD
DW
@R
W1+
,A
AD
DW
@R
W1+
RW
7,A
SU
BW
@R
W1+
,A
SU
BW
@R
W1+
RW
7,A
SU
BC
WA
,@
RW
1+
SU
BC
WA
,@
RW
1+R
W7
NE
GW
@R
W1+
NE
GW
@R
W1+
RW
7A
ND
W@
RW
1+,
A
AN
DW
@R
W1+
RW
7,A
OR
W@
RW
1+,
A
OR
W@
RW
1+R
W7,
A
XO
RW
@R
W1+
,A
XO
RW
@R
W1+
RW
7,A
NO
TW
@R
W1+
NO
TW
@R
W1+
RW
7
+E
AD
DW
@R
W2+
,A
AD
DW
@P
C+d
isp1
6,A
SU
BW
@R
W2+
,A
SU
BW
@P
C+d
isp1
6,A
SU
BC
WA
,@
RW
2+
SU
BC
WA
,@
PC
+dis
p16
NE
GW
@R
W2+
NE
GW
@P
C+d
isp1
6A
ND
W@
RW
2+,
A
AN
DW
@P
C+d
isp1
6,A
OR
W@
RW
2+,
A
OR
W@
PC
+dis
p16,
A
XO
RW
@R
W2+
,A
XO
RW
@P
C+d
isp1
6,A
NO
TW
@R
W2+
NO
TW
@P
C+d
isp1
6
+F
AD
DW
@R
W3+
,A
AD
DW
addr
16,
A
SU
BW
@R
W3+
,A
SU
BW
addr
16,
A
SU
BC
WA
,@
RW
3+
SU
BC
WA
,ad
dr16
NE
GW
@R
W3+
NE
GW
addr
16A
ND
W@
RW
3+,
A
AN
DW
addr
16,
A
OR
W@
RW
3+,
A
OR
Wad
dr16
,A
XO
RW
@R
W3+
,A
XO
RW
addr
16,
A
NO
TW
@R
W3+
NO
TW
addr
16
F2MC-16FX Family
356 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.6-9 ea-type Instruction (9) (First Byte = 78H)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
MU
LUA
,R
0
MU
LUA
,@
RW
0+di
sp8
MU
LUW
A,
RW
0
MU
LUW
A,
@R
W0+
disp
8
MU
LA
,R
0
MU
LA
,@
RW
0+di
sp8
MU
LWA
,R
W0
MU
LWA
,@
RW
0+di
sp8
DIV
UA
,R
0
DIV
UA
,@
RW
0+di
sp8
DIV
UW
A,
RW
0
DIV
UW
A,
@R
W0+
disp
8
DIV
A,
R0
DIV
A,
@R
W0+
disp
8
DIV
WA
,R
W0
DIV
WA
,@
RW
0+di
sp8
+1
MU
LUA
,R
1
MU
LUA
,@
RW
1+di
sp8
MU
LUW
A,
RW
1
MU
LUW
A,
@R
W1+
disp
8
MU
LA
,R
1
MU
LA
,@
RW
1+di
sp8
MU
LWA
,R
W1
MU
LWA
,@
RW
1+di
sp8
DIV
UA
,R
1
DIV
UA
,@
RW
1+di
sp8
DIV
UW
A,
RW
1
DIV
UW
A,
@R
W1+
disp
8
DIV
A,
R1
DIV
A,
@R
W1+
disp
8
DIV
WA
,R
W1
DIV
WA
,@
RW
1+di
sp8
+2
MU
LUA
,R
2
MU
LUA
,@
RW
2+di
sp8
MU
LUW
A,
RW
2
MU
LUW
A,
@R
W2+
disp
8
MU
LA
,R
2
MU
LA
,@
RW
2+di
sp8
MU
LWA
,R
W2
MU
LWA
,@
RW
2+di
sp8
DIV
UA
,R
2
DIV
UA
,@
RW
2+di
sp8
DIV
UW
A,
RW
2
DIV
UW
A,
@R
W2+
disp
8
DIV
A,
R2
DIV
A,
@R
W2+
disp
8
DIV
WA
,R
W2
DIV
WA
,@
RW
2+di
sp8
+3
MU
LUA
,R
3
MU
LUA
,@
RW
3+di
sp8
MU
LUW
A,
RW
3
MU
LUW
A,
@R
W3+
disp
8
MU
LA
,R
3
MU
LA
,@
RW
3+di
sp8
MU
LWA
,R
W3
MU
LWA
,@
RW
3+di
sp8
DIV
UA
,R
3
DIV
UA
,@
RW
3+di
sp8
DIV
UW
A,
RW
3
DIV
UW
A,
@R
W3+
disp
8
DIV
A,
R3
DIV
A,
@R
W3+
disp
8
DIV
WA
,R
W3
DIV
WA
,@
RW
3+di
sp8
+4
MU
LUA
,R
4
MU
LUA
,@
RW
4+di
sp8
MU
LUW
A,
RW
4
MU
LUW
A,
@R
W4+
disp
8
MU
LA
,R
4
MU
LA
,@
RW
4+di
sp8
MU
LWA
,R
W4
MU
LWA
,@
RW
4+di
sp8
DIV
UA
,R
4
DIV
UA
,@
RW
4+di
sp8
DIV
UW
A,
RW
4
DIV
UW
A,
@R
W4+
disp
8
DIV
A,
R4
DIV
A,
@R
W4+
disp
8
DIV
WA
,R
W4
DIV
WA
,@
RW
4+di
sp8
+5
MU
LUA
,R
5
MU
LUA
,@
RW
5+di
sp8
MU
LUW
A,
RW
5
MU
LUW
A,
@R
W5+
disp
8
MU
LA
,R
5
MU
LA
,@
RW
5+di
sp8
MU
LWA
,R
W5
MU
LWA
,@
RW
5+di
sp8
DIV
UA
,R
5
DIV
UA
,@
RW
5+di
sp8
DIV
UW
A,
RW
5
DIV
UW
A,
@R
W5+
disp
8
DIV
A,
R5
DIV
A,
@R
W5+
disp
8
DIV
WA
,R
W5
DIV
WA
,@
RW
5+di
sp8
+6
MU
LUA
,R
6
MU
LUA
,@
RW
6+di
sp8
MU
LUW
A,
RW
6
MU
LUW
A,
@R
W6+
disp
8
MU
LA
,R
6
MU
LA
,@
RW
6+di
sp8
MU
LWA
,R
W6
MU
LWA
,@
RW
6+di
sp8
DIV
UA
,R
6
DIV
UA
,@
RW
6+di
sp8
DIV
UW
A,
RW
6
DIV
UW
A,
@R
W6+
disp
8
DIV
A,
R6
DIV
A,
@R
W6+
disp
8
DIV
WA
,R
W6
DIV
WA
,@
RW
6+di
sp8
+7
MU
LUA
,R
7
MU
LUA
,@
RW
7+di
sp8
MU
LUW
A,
RW
7
MU
LUW
A,
@R
W7+
disp
8
MU
LA
,R
7
MU
LA
,@
RW
7+di
sp8
MU
LWA
,R
W7
MU
LWA
,@
RW
7+di
sp8
DIV
UA
,R
7
DIV
UA
,@
RW
7+di
sp8
DIV
UW
A,
RW
7
DIV
UW
A,
@R
W7+
disp
8
DIV
A,
R7
DIV
A,
@R
W7+
disp
8
DIV
WA
,R
W7
DIV
WA
,@
RW
7+di
sp8
+8
MU
LUA
,@
RW
0
MU
LUA
,@
RW
0+di
sp16
MU
LUW
A,
@R
W0
MU
LUW
A,
@R
W0+
disp
16
MU
LA
,@
RW
0
MU
LA
,@
RW
0+di
sp16
MU
LWA
,@
RW
0
MU
LWA
,@
RW
0+di
sp16
DIV
UA
,@
RW
0
DIV
UA
,@
RW
0+di
sp16
DIV
UW
A,
@R
W0
DIV
UW
A,
@R
W0+
disp
16
DIV
A,
@R
W0
DIV
A,
@R
W0+
disp
16
DIV
WA
,@
RW
0
DIV
WA
,@
RW
0+di
sp16
+9
MU
LUA
,@
RW
1
MU
LUA
,@
RW
1+di
sp16
MU
LUW
A,
@R
W1
MU
LUW
A,
@R
W1+
disp
16
MU
LA
,@
RW
1
MU
LA
,@
RW
1+di
sp16
MU
LWA
,@
RW
1
MU
LWA
,@
RW
1+di
sp16
DIV
UA
,@
RW
1
DIV
UA
,@
RW
1+di
sp16
DIV
UW
A,
@R
W1
DIV
UW
A,
@R
W1+
disp
16
DIV
A,
@R
W1
DIV
A,
@R
W1+
disp
16
DIV
WA
,@
RW
1
DIV
WA
,@
RW
1+di
sp16
+A
MU
LUA
,@
RW
2
MU
LUA
,@
RW
2+di
sp16
MU
LUW
A,
@R
W2
MU
LUW
A,
@R
W2+
disp
16
MU
LA
,@
RW
2
MU
LA
,@
RW
2+di
sp16
MU
LWA
,@
RW
2
MU
LWA
,@
RW
2+di
sp16
DIV
UA
,@
RW
2
DIV
UA
,@
RW
2+di
sp16
DIV
UW
A,
@R
W2
DIV
UW
A,
@R
W2+
disp
16
DIV
A,
@R
W2
DIV
A,
@R
W2+
disp
16
DIV
WA
,@
RW
2
DIV
WA
,@
RW
2+di
sp16
+B
MU
LUA
,@
RW
3
MU
LUA
,@
RW
3+di
sp16
MU
LUW
A,
@R
W3
MU
LUW
A,
@R
W3+
disp
16
MU
LA
,@
RW
3
MU
LA
,@
RW
3+di
sp16
MU
LWA
,@
RW
3
MU
LWA
,@
RW
3+di
sp16
DIV
UA
,@
RW
3
DIV
UA
,@
RW
3+di
sp16
DIV
UW
A,
@R
W3
DIV
UW
A,
@R
W3+
disp
16
DIV
A,
@R
W3
DIV
A,
@R
W3+
disp
16
DIV
WA
,@
RW
3
DIV
WA
,@
RW
3+di
sp16
+C
MU
LUA
,@
RW
0+
MU
LUA
,@
RW
0+R
W7
MU
LUW
A,
@R
W0+
MU
LUW
A,
@R
W0+
RW
7
MU
LA
,@
RW
0+
MU
LA
,@
RW
0+R
W7
MU
LWA
,@
RW
0+
MU
LWA
,@
RW
0+R
W7
DIV
UA
,@
RW
0+
DIV
UA
,@
RW
0+R
W7
DIV
UW
A,
@R
W0+
DIV
UW
A,
@R
W0+
RW
7
DIV
A,
@R
W0+
DIV
A,
@R
W0+
RW
7
DIV
WA
,@
RW
0+
DIV
WA
,@
RW
0+R
W7
+D
MU
LUA
,@
RW
1+
MU
LUA
,@
RW
1+R
W7
MU
LUW
A,
@R
W1+
MU
LUW
A,
@R
W1+
RW
7
MU
LA
,@
RW
1+
MU
LA
,@
RW
1+R
W7
MU
LWA
,@
RW
1+
MU
LWA
,@
RW
1+R
W7
DIV
UA
,@
RW
1+
DIV
UA
,@
RW
1+R
W7
DIV
UW
A,
@R
W1+
DIV
UW
A,
@R
W1+
RW
7
DIV
A,
@R
W1+
DIV
A,
@R
W1+
RW
7
DIV
WA
,@
RW
1+
DIV
WA
,@
RW
1+R
W7
+E
MU
LUA
,@
RW
2+
MU
LUA
,@
PC
+dis
p16
MU
LUW
A,
@R
W2+
MU
LUW
A,
@P
C+d
isp1
6
MU
LA
,@
RW
2+
MU
LA
,@
PC
+dis
p16
MU
LWA
,@
RW
2+
MU
LWA
,@
PC
+dis
p16
DIV
UA
,@
RW
2+
DIV
UA
,@
PC
+dis
p16
DIV
UW
A,
@R
W2+
DIV
UW
A,
@P
C+d
isp1
6
DIV
A,
@R
W2+
DIV
A,
@P
C+d
isp1
6
DIV
WA
,@
RW
2+
DIV
WA
,@
PC
+dis
p16
+F
MU
LUA
,@
RW
3+
MU
LUA
,ad
dr16
MU
LUW
A,
@R
W3+
MU
LUW
A,
addr
16
MU
LA
,@
RW
3+
MU
LA
,ad
dr16
MU
LWA
,@
RW
3+
MU
LWA
,ad
dr16
DIV
UA
,@
RW
3+
DIV
UA
,ad
dr16
DIV
UW
A,
@R
W3+
DIV
UW
A,
addr
16
DIV
A,
@R
W3+
DIV
A,
addr
16
DIV
WA
,@
RW
3+
DIV
WA
,ad
dr16
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 357
APPENDIXAPPENDIX C Instruction Maps
C.7 MOVEA RWi, ea Instruction Map
Table C.7-1 lists MOVEA RWi, ea instruction map.
F2MC-16FX Family
358 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.7-1 MOVEA RWi, ea Instruction (First Byte = 79H)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
MO
VE
AR
W0,
RW
0
MO
VE
AR
W0,
@R
W0+
disp
8
MO
VE
AR
W1,
RW
0
MO
VE
AR
W1,
@R
W0+
disp
8
MO
VE
AR
W2,
RW
0
MO
VE
AR
W2,
@R
W0+
disp
8
MO
VE
AR
W3,
RW
0
MO
VE
AR
W3,
@R
W0+
disp
8
MO
VE
AR
W4,
RW
0
MO
VE
AR
W4,
@R
W0+
disp
8
MO
VE
AR
W5,
RW
0
MO
VE
AR
W5,
@R
W0+
disp
8
MO
VE
AR
W6,
RW
0
MO
VE
AR
W6,
@R
W0+
disp
8
MO
VE
AR
W7,
RW
0
MO
VE
AR
W7,
@R
W0+
disp
8
+1
MO
VE
AR
W0,
RW
1
MO
VE
AR
W0,
@R
W1+
disp
8
MO
VE
AR
W1,
RW
1
MO
VE
AR
W1,
@R
W1+
disp
8
MO
VE
AR
W2,
RW
1
MO
VE
AR
W2,
@R
W1+
disp
8
MO
VE
AR
W3,
RW
1
MO
VE
AR
W3,
@R
W1+
disp
8
MO
VE
AR
W4,
RW
1
MO
VE
AR
W4,
@R
W1+
disp
8
MO
VE
AR
W5,
RW
1
MO
VE
AR
W5,
@R
W1+
disp
8
MO
VE
AR
W6,
RW
1
MO
VE
AR
W6,
@R
W1+
disp
8
MO
VE
AR
W7,
RW
1
MO
VE
AR
W7,
@R
W1+
disp
8
+2
MO
VE
AR
W0,
RW
2
MO
VE
AR
W0,
@R
W2+
disp
8
MO
VE
AR
W1,
RW
2
MO
VE
AR
W1,
@R
W2+
disp
8
MO
VE
AR
W2,
RW
2
MO
VE
AR
W2,
@R
W2+
disp
8
MO
VE
AR
W3,
RW
2
MO
VE
AR
W3,
@R
W2+
disp
8
MO
VE
AR
W4,
RW
2
MO
VE
AR
W4,
@R
W2+
disp
8
MO
VE
AR
W5,
RW
2
MO
VE
AR
W5,
@R
W2+
disp
8
MO
VE
AR
W6,
RW
2
MO
VE
AR
W6,
@R
W2+
disp
8
MO
VE
AR
W7,
RW
2
MO
VE
AR
W7,
@R
W2+
disp
8
+3
MO
VE
AR
W0,
RW
3
MO
VE
AR
W0,
@R
W3+
disp
8
MO
VE
AR
W1,
RW
3
MO
VE
AR
W1,
@R
W3+
disp
8
MO
VE
AR
W2,
RW
3
MO
VE
AR
W2,
@R
W3+
disp
8
MO
VE
AR
W3,
RW
3
MO
VE
AR
W3,
@R
W3+
disp
8
MO
VE
AR
W4,
RW
3
MO
VE
AR
W4,
@R
W3+
disp
8
MO
VE
AR
W5,
RW
3
MO
VE
AR
W5,
@R
W3+
disp
8
MO
VE
AR
W6,
RW
3
MO
VE
AR
W6,
@R
W3+
disp
8
MO
VE
AR
W7,
RW
3
MO
VE
AR
W7,
@R
W3+
disp
8
+4
MO
VE
AR
W0,
RW
4
MO
VE
AR
W0,
@R
W4+
disp
8
MO
VE
AR
W1,
RW
4
MO
VE
AR
W1,
@R
W4+
disp
8
MO
VE
AR
W2,
RW
4
MO
VE
AR
W2,
@R
W4+
disp
8
MO
VE
AR
W3,
RW
4
MO
VE
AR
W3,
@R
W4+
disp
8
MO
VE
AR
W4,
RW
4
MO
VE
AR
W4,
@R
W4+
disp
8
MO
VE
AR
W5,
RW
4
MO
VE
AR
W5,
@R
W4+
disp
8
MO
VE
AR
W6,
RW
4
MO
VE
AR
W6,
@R
W4+
disp
8
MO
VE
AR
W7,
RW
4
MO
VE
AR
W7,
@R
W4+
disp
8
+5
MO
VE
AR
W0,
RW
5
MO
VE
AR
W0,
@R
W5+
disp
8
MO
VE
AR
W1,
RW
5
MO
VE
AR
W1,
@R
W5+
disp
8
MO
VE
AR
W2,
RW
5
MO
VE
AR
W2,
@R
W5+
disp
8
MO
VE
AR
W3,
RW
5
MO
VE
AR
W3,
@R
W5+
disp
8
MO
VE
AR
W4,
RW
5
MO
VE
AR
W4,
@R
W5+
disp
8
MO
VE
AR
W5,
RW
5
MO
VE
AR
W5,
@R
W5+
disp
8
MO
VE
AR
W6,
RW
5
MO
VE
AR
W6,
@R
W5+
disp
8
MO
VE
AR
W7,
RW
5
MO
VE
AR
W7,
@R
W5+
disp
8
+6
MO
VE
AR
W0,
RW
6
MO
VE
AR
W0,
@R
W6+
disp
8
MO
VE
AR
W1,
RW
6
MO
VE
AR
W1,
@R
W6+
disp
8
MO
VE
AR
W2,
RW
6
MO
VE
AR
W2,
@R
W6+
disp
8
MO
VE
AR
W3,
RW
6
MO
VE
AR
W3,
@R
W6+
disp
8
MO
VE
AR
W4,
RW
6
MO
VE
AR
W4,
@R
W6+
disp
8
MO
VE
AR
W5,
RW
6
MO
VE
AR
W5,
@R
W6+
disp
8
MO
VE
AR
W6,
RW
6
MO
VE
AR
W6,
@R
W6+
disp
8
MO
VE
AR
W7,
RW
6
MO
VE
AR
W7,
@R
W6+
disp
8
+7
MO
VE
AR
W0,
RW
7
MO
VE
AR
W0,
@R
W7+
disp
8
MO
VE
AR
W1,
RW
7
MO
VE
AR
W1,
@R
W7+
disp
8
MO
VE
AR
W2,
RW
7
MO
VE
AR
W2,
@R
W7+
disp
8
MO
VE
AR
W3,
RW
7
MO
VE
AR
W3,
@R
W7+
disp
8
MO
VE
AR
W4,
RW
7
MO
VE
AR
W4,
@R
W7+
disp
8
MO
VE
AR
W5,
RW
7
MO
VE
AR
W5,
@R
W7+
disp
8
MO
VE
AR
W6,
RW
7
MO
VE
AR
W6,
@R
W7+
disp
8
MO
VE
AR
W7,
RW
7
MO
VE
AR
W7,
@R
W7+
disp
8
+8
MO
VE
AR
W0,
@R
W0
MO
VE
AR
W0,
@R
W0+
disp
16
MO
VE
AR
W1,
@R
W0
MO
VE
AR
W1,
@R
W0+
disp
16
MO
VE
AR
W2,
@R
W0
MO
VE
AR
W2,
@R
W0+
disp
16
MO
VE
AR
W3,
@R
W0
MO
VE
AR
W3,
@R
W0+
disp
16
MO
VE
AR
W4,
@R
W0
MO
VE
AR
W4,
@R
W0+
disp
16
MO
VE
AR
W5,
@R
W0
MO
VE
AR
W5,
@R
W0+
disp
16
MO
VE
AR
W6,
@R
W0
MO
VE
AR
W6,
@R
W0+
disp
16
MO
VE
AR
W7,
@R
W0
MO
VE
AR
W7,
@R
W0+
disp
16
+9
MO
VE
AR
W0,
@R
W1
MO
VE
AR
W0,
@R
W1+
disp
16
MO
VE
AR
W1,
@R
W1
MO
VE
AR
W1,
@R
W1+
disp
16
MO
VE
AR
W2,
@R
W1
MO
VE
AR
W2,
@R
W1+
disp
16
MO
VE
AR
W3,
@R
W1
MO
VE
AR
W3,
@R
W1+
disp
16
MO
VE
AR
W4,
@R
W1
MO
VE
AR
W4,
@R
W1+
disp
16
MO
VE
AR
W5,
@R
W1
MO
VE
AR
W5,
@R
W1+
disp
16
MO
VE
AR
W6,
@R
W1
MO
VE
AR
W6,
@R
W1+
disp
16
MO
VE
AR
W7,
@R
W1
MO
VE
AR
W7,
@R
W1+
disp
16
+A
MO
VE
AR
W0,
@R
W2
MO
VE
AR
W0,
@R
W2+
disp
16
MO
VE
AR
W1,
@R
W2
MO
VE
AR
W1,
@R
W2+
disp
16
MO
VE
AR
W2,
@R
W2
MO
VE
AR
W2,
@R
W2+
disp
16
MO
VE
AR
W3,
@R
W2
MO
VE
AR
W3,
@R
W2+
disp
16
MO
VE
AR
W4,
@R
W2
MO
VE
AR
W4,
@R
W2+
disp
16
MO
VE
AR
W5,
@R
W2
MO
VE
AR
W5,
@R
W2+
disp
16
MO
VE
AR
W6,
@R
W2
MO
VE
AR
W6,
@R
W2+
disp
16
MO
VE
AR
W7,
@R
W2
MO
VE
AR
W7,
@R
W2+
disp
16
+B
MO
VE
AR
W0,
@R
W3
MO
VE
AR
W0,
@R
W3+
disp
16
MO
VE
AR
W1,
@R
W3
MO
VE
AR
W1,
@R
W3+
disp
16
MO
VE
AR
W2,
@R
W3
MO
VE
AR
W2,
@R
W3+
disp
16
MO
VE
AR
W3,
@R
W3
MO
VE
AR
W3,
@R
W3+
disp
16
MO
VE
AR
W4,
@R
W3
MO
VE
AR
W4,
@R
W3+
disp
16
MO
VE
AR
W5,
@R
W3
MO
VE
AR
W5,
@R
W3+
disp
16
MO
VE
AR
W6,
@R
W3
MO
VE
AR
W6,
@R
W3+
disp
16
MO
VE
AR
W7,
@R
W3
MO
VE
AR
W7,
@R
W3+
disp
16
+C
MO
VE
AR
W0,
@R
W0+
MO
VE
AR
W0,
@R
W0+
RW
7
MO
VE
AR
W1,
@R
W0+
MO
VE
AR
W1,
@R
W0+
RW
7
MO
VE
AR
W2,
@R
W0+
MO
VE
AR
W2,
@R
W0+
RW
7
MO
VE
AR
W3,
@R
W0+
MO
VE
AR
W3,
@R
W0+
RW
7
MO
VE
AR
W4,
@R
W0+
MO
VE
AR
W4,
@R
W0+
RW
7
MO
VE
AR
W5,
@R
W0+
MO
VE
AR
W5,
@R
W0+
RW
7
MO
VE
AR
W6,
@R
W0+
MO
VE
AR
W6,
@R
W0+
RW
7
MO
VE
AR
W7,
@R
W0+
MO
VE
AR
W7,
@R
W0+
RW
7
+D
MO
VE
AR
W0,
@R
W1+
MO
VE
AR
W0,
@R
W1+
RW
7
MO
VE
AR
W1,
@R
W1+
MO
VE
AR
W1,
@R
W1+
RW
7
MO
VE
AR
W2,
@R
W1+
MO
VE
AR
W2,
@R
W1+
RW
7
MO
VE
AR
W3,
@R
W1+
MO
VE
AR
W3,
@R
W1+
RW
7
MO
VE
AR
W4,
@R
W1+
MO
VE
AR
W4,
@R
W1+
RW
7
MO
VE
AR
W5,
@R
W1+
MO
VE
AR
W5,
@R
W1+
RW
7
MO
VE
AR
W6,
@R
W1+
MO
VE
AR
W6,
@R
W1+
RW
7
MO
VE
AR
W7,
@R
W1+
MO
VE
AR
W7,
@R
W1+
RW
7
+E
MO
VE
AR
W0,
@R
W2+
MO
VE
AR
W0,
@P
C+d
isp1
6
MO
VE
AR
W1,
@R
W2+
MO
VE
AR
W1,
@P
C+d
isp1
6
MO
VE
AR
W2,
@R
W2+
MO
VE
AR
W2,
@P
C+d
isp1
6
MO
VE
AR
W3,
@R
W2+
MO
VE
AR
W3,
@P
C+d
isp1
6
MO
VE
AR
W4,
@R
W2+
MO
VE
AR
W4,
@P
C+d
isp1
6
MO
VE
AR
W5,
@R
W2+
MO
VE
AR
W5,
@P
C+d
isp1
6
MO
VE
AR
W6,
@R
W2+
MO
VE
AR
W6,
@P
C+d
isp1
6
MO
VE
AR
W7,
@R
W2+
MO
VE
AR
W7,
@P
C+d
isp1
6
+F
MO
VE
AR
W0,
@R
W3+
MO
VE
AR
W0,
addr
16
MO
VE
AR
W1,
@R
W3+
MO
VE
AR
W1,
addr
16
MO
VE
AR
W2,
@R
W3+
MO
VE
AR
W2,
addr
16
MO
VE
AR
W3,
@R
W3+
MO
VE
AR
W3,
addr
16
MO
VE
AR
W4,
@R
W3+
MO
VE
AR
W4,
addr
16
MO
VE
AR
W5,
@R
W3+
MO
VE
AR
W5,
addr
16
MO
VE
AR
W6,
@R
W3+
MO
VE
AR
W6,
addr
16
MO
VE
AR
W7,
@R
W3+
MO
VE
AR
W7,
addr
16
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 359
APPENDIXAPPENDIX C Instruction Maps
C.8 MOV Ri, ea Instruction Map
Table C.8-1 lists MOV Ri, ea instruction map.
F2MC-16FX Family
360 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.8-1 MOV Ri, ea Instruction (First Byte = 7AH)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
MO
VR
0,R
0
MO
VR
0,@
RW
0+di
sp8
MO
VR
1,R
0
MO
VR
1,@
RW
0+di
sp8
MO
VR
2,R
0
MO
VR
2,@
RW
0+di
sp8
MO
VR
3,R
0
MO
VR
3,@
RW
0+di
sp8
MO
VR
4,R
0
MO
VR
4,@
RW
0+di
sp8
MO
VR
5,R
0
MO
VR
5,@
RW
0+di
sp8
MO
VR
6,R
0
MO
VR
6,@
RW
0+di
sp8
MO
VR
7,R
0
MO
VR
7,@
RW
0+di
sp8
+1
MO
VR
0,R
1
MO
VR
0,@
RW
1+di
sp8
MO
VR
1,R
1
MO
VR
1,@
RW
1+di
sp8
MO
VR
2,R
1
MO
VR
2,@
RW
1+di
sp8
MO
VR
3,R
1
MO
VR
3,@
RW
1+di
sp8
MO
VR
4,R
1
MO
VR
4,@
RW
1+di
sp8
MO
VR
5,R
1
MO
VR
5,@
RW
1+di
sp8
MO
VR
6,R
1
MO
VR
6,@
RW
1+di
sp8
MO
VR
7,R
1
MO
VR
7,@
RW
1+di
sp8
+2
MO
VR
0,R
2
MO
VR
0,@
RW
2+di
sp8
MO
VR
1,R
2
MO
VR
1,@
RW
2+di
sp8
MO
VR
2,R
2
MO
VR
2,@
RW
2+di
sp8
MO
VR
3,R
2
MO
VR
3,@
RW
2+di
sp8
MO
VR
4,R
2
MO
VR
4,@
RW
2+di
sp8
MO
VR
5,R
2
MO
VR
5,@
RW
2+di
sp8
MO
VR
6,R
2
MO
VR
6,@
RW
2+di
sp8
MO
VR
7,R
2
MO
VR
7,@
RW
2+di
sp8
+3
MO
VR
0,R
3
MO
VR
0,@
RW
3+di
sp8
MO
VR
1,R
3
MO
VR
1,@
RW
3+di
sp8
MO
VR
2,R
3
MO
VR
2,@
RW
3+di
sp8
MO
VR
3,R
3
MO
VR
3,@
RW
3+di
sp8
MO
VR
4,R
3
MO
VR
4,@
RW
3+di
sp8
MO
VR
5,R
3
MO
VR
5,@
RW
3+di
sp8
MO
VR
6,R
3
MO
VR
6,@
RW
3+di
sp8
MO
VR
7,R
3
MO
VR
7,@
RW
3+di
sp8
+4
MO
VR
0,R
4
MO
VR
0,@
RW
4+di
sp8
MO
VR
1,R
4
MO
VR
1,@
RW
4+di
sp8
MO
VR
2,R
4
MO
VR
2,@
RW
4+di
sp8
MO
VR
3,R
4
MO
VR
3,@
RW
4+di
sp8
MO
VR
4,R
4
MO
VR
4,@
RW
4+di
sp8
MO
VR
5,R
4
MO
VR
5,@
RW
4+di
sp8
MO
VR
6,R
4
MO
VR
6,@
RW
4+di
sp8
MO
VR
7,R
4
MO
VR
7,@
RW
4+di
sp8
+5
MO
VR
0,R
5
MO
VR
0,@
RW
5+di
sp8
MO
VR
1,R
5
MO
VR
1,@
RW
5+di
sp8
MO
VR
2,R
5
MO
VR
2,@
RW
5+di
sp8
MO
VR
3,R
5
MO
VR
3,@
RW
5+di
sp8
MO
VR
4,R
5
MO
VR
4,@
RW
5+di
sp8
MO
VR
5,R
5
MO
VR
5,@
RW
5+di
sp8
MO
VR
6,R
5
MO
VR
6,@
RW
5+di
sp8
MO
VR
7,R
5
MO
VR
7,@
RW
5+di
sp8
+6
MO
VR
0,R
6
MO
VR
0,@
RW
6+di
sp8
MO
VR
1,R
6
MO
VR
1,@
RW
6+di
sp8
MO
VR
2,R
6
MO
VR
2,@
RW
6+di
sp8
MO
VR
3,R
6
MO
VR
3,@
RW
6+di
sp8
MO
VR
4,R
6
MO
VR
4,@
RW
6+di
sp8
MO
VR
5,R
6
MO
VR
5,@
RW
6+di
sp8
MO
VR
6,R
6
MO
VR
6,@
RW
6+di
sp8
MO
VR
7,R
6
MO
VR
7,@
RW
6+di
sp8
+7
MO
VR
0,R
7
MO
VR
0,@
RW
7+di
sp8
MO
VR
1,R
7
MO
VR
1,@
RW
7+di
sp8
MO
VR
2,R
7
MO
VR
2,@
RW
7+di
sp8
MO
VR
3,R
7
MO
VR
3,@
RW
7+di
sp8
MO
VR
4,R
7
MO
VR
4,@
RW
7+di
sp8
MO
VR
5,R
7
MO
VR
5,@
RW
7+di
sp8
MO
VR
6,R
7
MO
VR
6,@
RW
7+di
sp8
MO
VR
7,R
7
MO
VR
7,@
RW
7+di
sp8
+8
MO
VR
0,@
RW
0
MO
VR
0,@
RW
0+di
sp16
MO
VR
1,@
RW
0
MO
VR
1,@
RW
0+di
sp16
MO
VR
2,@
RW
0
MO
VR
2,@
RW
0+di
sp16
MO
VR
3,@
RW
0
MO
VR
3,@
RW
0+di
sp16
MO
VR
4,@
RW
0
MO
VR
4,@
RW
0+di
sp16
MO
VR
5,@
RW
0
MO
VR
5,@
RW
0+di
sp16
MO
VR
6,@
RW
0
MO
VR
6,@
RW
0+di
sp16
MO
VR
7,@
RW
0
MO
VR
7,@
RW
0+di
sp16
+9
MO
VR
0,@
RW
1
MO
VR
0,@
RW
1+di
sp16
MO
VR
1,@
RW
1
MO
VR
1,@
RW
1+di
sp16
MO
VR
2,@
RW
1
MO
VR
2,@
RW
1+di
sp16
MO
VR
3,@
RW
1
MO
VR
3,@
RW
1+di
sp16
MO
VR
4,@
RW
1
MO
VR
4,@
RW
1+di
sp16
MO
VR
5,@
RW
1
MO
VR
5,@
RW
1+di
sp16
MO
VR
6,@
RW
1
MO
VR
6,@
RW
1+di
sp16
MO
VR
7,@
RW
1
MO
VR
7,@
RW
1+di
sp16
+A
MO
VR
0,@
RW
2
MO
VR
0,@
RW
2+di
sp16
MO
VR
1,@
RW
2
MO
VR
1,@
RW
2+di
sp16
MO
VR
2,@
RW
2
MO
VR
2,@
RW
2+di
sp16
MO
VR
3,@
RW
2
MO
VR
3,@
RW
2+di
sp16
MO
VR
4,@
RW
2
MO
VR
4,@
RW
2+di
sp16
MO
VR
5,@
RW
2
MO
VR
5,@
RW
2+di
sp16
MO
VR
6,@
RW
2
MO
VR
6,@
RW
2+di
sp16
MO
VR
7,@
RW
2
MO
VR
7,@
RW
2+di
sp16
+B
MO
VR
0,@
RW
3
MO
VR
0,@
RW
3+di
sp16
MO
VR
1,@
RW
3
MO
VR
1,@
RW
3+di
sp16
MO
VR
2,@
RW
3
MO
VR
2,@
RW
3+di
sp16
MO
VR
3,@
RW
3
MO
VR
3,@
RW
3+di
sp16
MO
VR
4,@
RW
3
MO
VR
4,@
RW
3+di
sp16
MO
VR
5,@
RW
3
MO
VR
5,@
RW
3+di
sp16
MO
VR
6,@
RW
3
MO
VR
6,@
RW
3+di
sp16
MO
VR
7,@
RW
3
MO
VR
7,@
RW
3+di
sp16
+C
MO
VR
0,@
RW
0+
MO
VR
0,@
RW
0+R
W7
MO
VR
1,@
RW
0+
MO
VR
1,@
RW
0+R
W7
MO
VR
2,@
RW
0+
MO
VR
2,@
RW
0+R
W7
MO
VR
3,@
RW
0+
MO
VR
3,@
RW
0+R
W7
MO
VR
4,@
RW
0+
MO
VR
4,@
RW
0+R
W7
MO
VR
5,@
RW
0+
MO
VR
5,@
RW
0+R
W7
MO
VR
6,@
RW
0+
MO
VR
6,@
RW
0+R
W7
MO
VR
7,@
RW
0+
MO
VR
7,@
RW
0+R
W7
+D
MO
VR
0,@
RW
1+
MO
VR
0,@
RW
1+R
W7
MO
VR
1,@
RW
1+
MO
VR
1,@
RW
1+R
W7
MO
VR
2,@
RW
1+
MO
VR
2,@
RW
1+R
W7
MO
VR
3,@
RW
1+
MO
VR
3,@
RW
1+R
W7
MO
VR
4,@
RW
1+
MO
VR
4,@
RW
1+R
W7
MO
VR
5,@
RW
1+
MO
VR
5,@
RW
1+R
W7
MO
VR
6,@
RW
1+
MO
VR
6,@
RW
1+R
W7
MO
VR
7,@
RW
1+
MO
VR
7,@
RW
1+R
W7
+E
MO
VR
0,@
RW
2+
MO
VR
0,@
PC
+dis
p16
MO
VR
1,@
RW
2+
MO
VR
1,@
PC
+dis
p16
MO
VR
2,@
RW
2+
MO
VR
2,@
PC
+dis
p16
MO
VR
3,@
RW
2+
MO
VR
3,@
PC
+dis
p16
MO
VR
4,@
RW
2+
MO
VR
4,@
PC
+dis
p16
MO
VR
5,@
RW
2+
MO
VR
5,@
PC
+dis
p16
MO
VR
6,@
RW
2+
MO
VR
6,@
PC
+dis
p16
MO
VR
7,@
RW
2+
MO
VR
7,@
PC
+dis
p16
+F
MO
VR
0,@
RW
3+
MO
VR
0,ad
dr16
MO
VR
1,@
RW
3+
MO
VR
1,ad
dr16
MO
VR
2,@
RW
3+
MO
VR
2,ad
dr16
MO
VR
3,@
RW
3+
MO
VR
3,ad
dr16
MO
VR
4,@
RW
3+
MO
VR
4,ad
dr16
MO
VR
5,@
RW
3+
MO
VR
5,ad
dr16
MO
VR
6,@
RW
3+
MO
VR
6,ad
dr16
MO
VR
7,@
RW
3+
MO
VR
7,ad
dr16
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 361
APPENDIXAPPENDIX C Instruction Maps
C.9 MOVW RWi, ea Instruction Map
Table C.9-1 lists MOVW RWi, ea instruction map.
F2MC-16FX Family
362 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.9-1 MOVW RWi, ea Instruction (First Byte = 7BH)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
MO
VW
RW
0,R
W0
MO
VW
RW
0,@
RW
0+di
sp8
MO
VW
RW
1,R
W0
MO
VW
RW
1,@
RW
0+di
sp8
MO
VW
RW
2,R
W0
MO
VW
RW
2,@
RW
0+di
sp8
MO
VW
RW
3,R
W0
MO
VW
RW
3,@
RW
0+di
sp8
MO
VW
RW
4,R
W0
MO
VW
RW
4,@
RW
0+di
sp8
MO
VW
RW
5,R
W0
MO
VW
RW
5,@
RW
0+di
sp8
MO
VW
RW
6,R
W0
MO
VW
RW
6,@
RW
0+di
sp8
MO
VW
RW
7,R
W0
MO
VW
RW
7,@
RW
0+di
sp8
+1
MO
VW
RW
0,R
W1
MO
VW
RW
0,@
RW
1+di
sp8
MO
VW
RW
1,R
W1
MO
VW
RW
1,@
RW
1+di
sp8
MO
VW
RW
2,R
W1
MO
VW
RW
2,@
RW
1+di
sp8
MO
VW
RW
3,R
W1
MO
VW
RW
3,@
RW
1+di
sp8
MO
VW
RW
4,R
W1
MO
VW
RW
4,@
RW
1+di
sp8
MO
VW
RW
5,R
W1
MO
VW
RW
5,@
RW
1+di
sp8
MO
VW
RW
6,R
W1
MO
VW
RW
6,@
RW
1+di
sp8
MO
VW
RW
7,R
W1
MO
VW
RW
7,@
RW
1+di
sp8
+2
MO
VW
RW
0,R
W2
MO
VW
RW
0,@
RW
2+di
sp8
MO
VW
RW
1,R
W2
MO
VW
RW
1,@
RW
2+di
sp8
MO
VW
RW
2,R
W2
MO
VW
RW
2,@
RW
2+di
sp8
MO
VW
RW
3,R
W2
MO
VW
RW
3,@
RW
2+di
sp8
MO
VW
RW
4,R
W2
MO
VW
RW
4,@
RW
2+di
sp8
MO
VW
RW
5,R
W2
MO
VW
RW
5,@
RW
2+di
sp8
MO
VW
RW
6,R
W2
MO
VW
RW
6,@
RW
2+di
sp8
MO
VW
RW
7,R
W2
MO
VW
RW
7,@
RW
2+di
sp8
+3
MO
VW
RW
0,R
W3
MO
VW
RW
0,@
RW
3+di
sp8
MO
VW
RW
1,R
W3
MO
VW
RW
1,@
RW
3+di
sp8
MO
VW
RW
2,R
W3
MO
VW
RW
2,@
RW
3+di
sp8
MO
VW
RW
3,R
W3
MO
VW
RW
3,@
RW
3+di
sp8
MO
VW
RW
4,R
W3
MO
VW
RW
4,@
RW
3+di
sp8
MO
VW
RW
5,R
W3
MO
VW
RW
5,@
RW
3+di
sp8
MO
VW
RW
6,R
W3
MO
VW
RW
6,@
RW
3+di
sp8
MO
VW
RW
7,R
W3
MO
VW
RW
7,@
RW
3+di
sp8
+4
MO
VW
RW
0,R
W4
MO
VW
RW
0,@
RW
4+di
sp8
MO
VW
RW
1,R
W4
MO
VW
RW
1,@
RW
4+di
sp8
MO
VW
RW
2,R
W4
MO
VW
RW
2,@
RW
4+di
sp8
MO
VW
RW
3,R
W4
MO
VW
RW
3,@
RW
4+di
sp8
MO
VW
RW
4,R
W4
MO
VW
RW
4,@
RW
4+di
sp8
MO
VW
RW
5,R
W4
MO
VW
RW
5,@
RW
4+di
sp8
MO
VW
RW
6,R
W4
MO
VW
RW
6,@
RW
4+di
sp8
MO
VW
RW
7,R
W4
MO
VW
RW
7,@
RW
4+di
sp8
+5
MO
VW
RW
0,R
W5
MO
VW
RW
0,@
RW
5+di
sp8
MO
VW
RW
1,R
W5
MO
VW
RW
1,@
RW
5+di
sp8
MO
VW
RW
2,R
W5
MO
VW
RW
2,@
RW
5+di
sp8
MO
VW
RW
3,R
W5
MO
VW
RW
3,@
RW
5+di
sp8
MO
VW
RW
4,R
W5
MO
VW
RW
4,@
RW
5+di
sp8
MO
VW
RW
5,R
W5
MO
VW
RW
5,@
RW
5+di
sp8
MO
VW
RW
6,R
W5
MO
VW
RW
6,@
RW
5+di
sp8
MO
VW
RW
7,R
W5
MO
VW
RW
7,@
RW
5+di
sp8
+6
MO
VW
RW
0,R
W6
MO
VW
RW
0,@
RW
6+di
sp8
MO
VW
RW
1,R
W6
MO
VW
RW
1,@
RW
6+di
sp8
MO
VW
RW
2,R
W6
MO
VW
RW
2,@
RW
6+di
sp8
MO
VW
RW
3,R
W6
MO
VW
RW
3,@
RW
6+di
sp8
MO
VW
RW
4,R
W6
MO
VW
RW
4,@
RW
6+di
sp8
MO
VW
RW
5,R
W6
MO
VW
RW
5,@
RW
6+di
sp8
MO
VW
RW
6,R
W6
MO
VW
RW
6,@
RW
6+di
sp8
MO
VW
RW
7,R
W6
MO
VW
RW
7,@
RW
6+di
sp8
+7
MO
VW
RW
0,R
W7
MO
VW
RW
0,@
RW
7+di
sp8
MO
VW
RW
1,R
W7
MO
VW
RW
1,@
RW
7+di
sp8
MO
VW
RW
2,R
W7
MO
VW
RW
2,@
RW
7+di
sp8
MO
VW
RW
3,R
W7
MO
VW
RW
3,@
RW
7+di
sp8
MO
VW
RW
4,R
W7
MO
VW
RW
4,@
RW
7+di
sp8
MO
VW
RW
5,R
W7
MO
VW
RW
5,@
RW
7+di
sp8
MO
VW
RW
6,R
W7
MO
VW
RW
6,@
RW
7+di
sp8
MO
VW
RW
7,R
W7
MO
VW
RW
7,@
RW
7+di
sp8
+8
MO
VW
RW
0,@
RW
0
MO
VW
RW
0,@
RW
0+di
sp16
MO
VW
RW
1,@
RW
0
MO
VW
RW
1,@
RW
0+di
sp16
MO
VW
RW
2,@
RW
0
MO
VW
RW
2,@
RW
0+di
sp16
MO
VW
RW
3,@
RW
0
MO
VW
RW
3,@
RW
0+di
sp16
MO
VW
RW
4,@
RW
0
MO
VW
RW
4,@
RW
0+di
sp16
MO
VW
RW
5,@
RW
0
MO
VW
RW
5,@
RW
0+di
sp16
MO
VW
RW
6,@
RW
0
MO
VW
RW
6,@
RW
0+di
sp16
MO
VW
RW
7,@
RW
0
MO
VW
RW
7,@
RW
0+di
sp16
+9
MO
VW
RW
0,@
RW
1
MO
VW
RW
0,@
RW
1+di
sp16
MO
VW
RW
1,@
RW
1
MO
VW
RW
1,@
RW
1+di
sp16
MO
VW
RW
2,@
RW
1
MO
VW
RW
2,@
RW
1+di
sp16
MO
VW
RW
3,@
RW
1
MO
VW
RW
3,@
RW
1+di
sp16
MO
VW
RW
4,@
RW
1
MO
VW
RW
4,@
RW
1+di
sp16
MO
VW
RW
5,@
RW
1
MO
VW
RW
5,@
RW
1+di
sp16
MO
VW
RW
6,@
RW
1
MO
VW
RW
6,@
RW
1+di
sp16
MO
VW
RW
7,@
RW
1
MO
VW
RW
7,@
RW
1+di
sp16
+A
MO
VW
RW
0,@
RW
2
MO
VW
RW
0,@
RW
2+di
sp16
MO
VW
RW
1,@
RW
2
MO
VW
RW
1,@
RW
2+di
sp16
MO
VW
RW
2,@
RW
2
MO
VW
RW
2,@
RW
2+di
sp16
MO
VW
RW
3,@
RW
2
MO
VW
RW
3,@
RW
2+di
sp16
MO
VW
RW
4,@
RW
2
MO
VW
RW
4,@
RW
2+di
sp16
MO
VW
RW
5,@
RW
2
MO
VW
RW
5,@
RW
2+di
sp16
MO
VW
RW
6,@
RW
2
MO
VW
RW
6,@
RW
2+di
sp16
MO
VW
RW
7,@
RW
2
MO
VW
RW
7,@
RW
2+di
sp16
+B
MO
VW
RW
0,@
RW
3
MO
VW
RW
0,@
RW
3+di
sp16
MO
VW
RW
1,@
RW
3
MO
VW
RW
1,@
RW
3+di
sp16
MO
VW
RW
2,@
RW
3
MO
VW
RW
2,@
RW
3+di
sp16
MO
VW
RW
3,@
RW
3
MO
VW
RW
3,@
RW
3+di
sp16
MO
VW
RW
4,@
RW
3
MO
VW
RW
4,@
RW
3+di
sp16
MO
VW
RW
5,@
RW
3
MO
VW
RW
5,@
RW
3+di
sp16
MO
VW
RW
6,@
RW
3
MO
VW
RW
6,@
RW
3+di
sp16
MO
VW
RW
7,@
RW
3
MO
VW
RW
7,@
RW
3+di
sp16
+C
MO
VW
RW
0,@
RW
0+
MO
VW
RW
0,@
RW
0+R
W7
MO
VW
RW
1,@
RW
0+
MO
VW
RW
1,@
RW
0+R
W7
MO
VW
RW
2,@
RW
0+
MO
VW
RW
2,@
RW
0+R
W7
MO
VW
RW
3,@
RW
0+
MO
VW
RW
3,@
RW
0+R
W7
MO
VW
RW
4,@
RW
0+
MO
VW
RW
4,@
RW
0+R
W7
MO
VW
RW
5,@
RW
0+
MO
VW
RW
5,@
RW
0+R
W7
MO
VW
RW
6,@
RW
0+
MO
VW
RW
6,@
RW
0+R
W7
MO
VW
RW
7,@
RW
0+
MO
VW
RW
7,@
RW
0+R
W7
+D
MO
VW
RW
0,@
RW
1+
MO
VW
RW
0,@
RW
1+R
W7
MO
VW
RW
1,@
RW
1+
MO
VW
RW
1,@
RW
1+R
W7
MO
VW
RW
2,@
RW
1+
MO
VW
RW
2,@
RW
1+R
W7
MO
VW
RW
3,@
RW
1+
MO
VW
RW
3,@
RW
1+R
W7
MO
VW
RW
4,@
RW
1+
MO
VW
RW
4,@
RW
1+R
W7
MO
VW
RW
5,@
RW
1+
MO
VW
RW
5,@
RW
1+R
W7
MO
VW
RW
6,@
RW
1+
MO
VW
RW
6,@
RW
1+R
W7
MO
VW
RW
7,@
RW
1+
MO
VW
RW
7,@
RW
1+R
W7
+E
MO
VW
RW
0,@
RW
2+
MO
VW
RW
0,@
PC
+dis
p16
MO
VW
RW
1,@
RW
2+
MO
VW
RW
1,@
PC
+dis
p16
MO
VW
RW
2,@
RW
2+
MO
VW
RW
2,@
PC
+dis
p16
MO
VW
RW
3,@
RW
2+
MO
VW
RW
3,@
PC
+dis
p16
MO
VW
RW
4,@
RW
2+
MO
VW
RW
4,@
PC
+dis
p16
MO
VW
RW
5,@
RW
2+
MO
VW
RW
5,@
PC
+dis
p16
MO
VW
RW
6,@
RW
2+
MO
VW
RW
6,@
PC
+dis
p16
MO
VW
RW
7,@
RW
2+
MO
VW
RW
7,@
PC
+dis
p16
+F
MO
VW
RW
0,@
RW
3+
MO
VW
RW
0,ad
dr16
MO
VW
RW
1,@
RW
3+
MO
VW
RW
1,ad
dr16
MO
VW
RW
2,@
RW
3+
MO
VW
RW
2,ad
dr16
MO
VW
RW
3,@
RW
3+
MO
VW
RW
3,ad
dr16
MO
VW
RW
4,@
RW
3+
MO
VW
RW
4,ad
dr16
MO
VW
RW
5,@
RW
3+
MO
VW
RW
5,ad
dr16
MO
VW
RW
6,@
RW
3+
MO
VW
RW
6,ad
dr16
MO
VW
RW
7,@
RW
3+
MO
VW
RW
7,ad
dr16
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 363
APPENDIXAPPENDIX C Instruction Maps
C.10 MOV ea, Ri Instruction Map
Table C.10-1 lists MOV ea, Ri instruction map.
F2MC-16FX Family
364 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.10-1 MOV ea, Ri Instruction (First Byte = 7CH)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
MO
VR
0,R
0
MO
V@
RW
0+di
sp8,
R0
MO
VR
0,R
1
MO
V@
RW
0+di
sp8,
R1
MO
VR
0,R
2
MO
V@
RW
0+di
sp8,
R2
MO
VR
0,R
3
MO
V@
RW
0+di
sp8,
R3
MO
VR
0,R
4
MO
V@
RW
0+di
sp8,
R4
MO
VR
0,R
5
MO
V@
RW
0+di
sp8,
R5
MO
VR
0,R
6
MO
V@
RW
0+di
sp8,
R6
MO
VR
0,R
7
MO
V@
RW
0+di
sp8,
R7
+1
MO
VR
1,R
0
MO
V@
RW
1+di
sp8,
R0
MO
VR
1,R
1
MO
V@
RW
1+di
sp8,
R1
MO
VR
1,R
2
MO
V@
RW
1+di
sp8,
R2
MO
VR
1,R
3
MO
V@
RW
1+di
sp8,
R3
MO
VR
1,R
4
MO
V@
RW
1+di
sp8,
R4
MO
VR
1,R
5
MO
V@
RW
1+di
sp8,
R5
MO
VR
1,R
6
MO
V@
RW
1+di
sp8,
R6
MO
VR
1,R
7
MO
V@
RW
1+di
sp8,
R7
+2
MO
VR
2,R
0
MO
V@
RW
2+di
sp8,
R0
MO
VR
2,R
1
MO
V@
RW
2+di
sp8,
R1
MO
VR
2,R
2
MO
V@
RW
2+di
sp8,
R2
MO
VR
2,R
3
MO
V@
RW
2+di
sp8,
R3
MO
VR
2,R
4
MO
V@
RW
2+di
sp8,
R4
MO
VR
2,R
5
MO
V@
RW
2+di
sp8,
R5
MO
VR
2,R
6
MO
V@
RW
2+di
sp8,
R6
MO
VR
2,R
7
MO
V@
RW
2+di
sp8,
R7
+3
MO
VR
3,R
0
MO
V@
RW
3+di
sp8,
R0
MO
VR
3,R
1
MO
V@
RW
3+di
sp8,
R1
MO
VR
3,R
2
MO
V@
RW
3+di
sp8,
R2
MO
VR
3,R
3
MO
V@
RW
3+di
sp8,
R3
MO
VR
3,R
4
MO
V@
RW
3+di
sp8,
R4
MO
VR
3,R
5
MO
V@
RW
3+di
sp8,
R5
MO
VR
3,R
6
MO
V@
RW
3+di
sp8,
R6
MO
VR
3,R
7
MO
V@
RW
3+di
sp8,
R7
+4
MO
VR
4,R
0
MO
V@
RW
4+di
sp8,
R0
MO
VR
4,R
1
MO
V@
RW
4+di
sp8,
R1
MO
VR
4,R
2
MO
V@
RW
4+di
sp8,
R2
MO
VR
4,R
3
MO
V@
RW
4+di
sp8,
R3
MO
VR
4,R
4
MO
V@
RW
4+di
sp8,
R4
MO
VR
4,R
5
MO
V@
RW
4+di
sp8,
R5
MO
VR
4,R
6
MO
V@
RW
4+di
sp8,
R6
MO
VR
4,R
7
MO
V@
RW
4+di
sp8,
R7
+5
MO
VR
5,R
0
MO
V@
RW
5+di
sp8,
R0
MO
VR
5,R
1
MO
V@
RW
5+di
sp8,
R1
MO
VR
5,R
2
MO
V@
RW
5+di
sp8,
R2
MO
VR
5,R
3
MO
V@
RW
5+di
sp8,
R3
MO
VR
5,R
4
MO
V@
RW
5+di
sp8,
R4
MO
VR
5,R
5
MO
V@
RW
5+di
sp8,
R5
MO
VR
5,R
6
MO
V@
RW
5+di
sp8,
R6
MO
VR
5,R
7
MO
V@
RW
5+di
sp8,
R7
+6
MO
VR
6,R
0
MO
V@
RW
6+di
sp8,
R0
MO
VR
6,R
1
MO
V@
RW
6+di
sp8,
R1
MO
VR
6,R
2
MO
V@
RW
6+di
sp8,
R2
MO
VR
6,R
3
MO
V@
RW
6+di
sp8,
R3
MO
VR
6,R
4
MO
V@
RW
6+di
sp8,
R4
MO
VR
6,R
5
MO
V@
RW
6+di
sp8,
R5
MO
VR
6,R
6
MO
V@
RW
6+di
sp8,
R6
MO
VR
6,R
7
MO
V@
RW
6+di
sp8,
R7
+7
MO
VR
7,R
0
MO
V@
RW
7+di
sp8,
R0
MO
VR
7,R
1
MO
V@
RW
7+di
sp8,
R1
MO
VR
7,R
2
MO
V@
RW
7+di
sp8,
R2
MO
VR
7,R
3
MO
V@
RW
7+di
sp8,
R3
MO
VR
7,R
4
MO
V@
RW
7+di
sp8,
R4
MO
VR
7,R
5
MO
V@
RW
7+di
sp8,
R5
MO
VR
7,R
6
MO
V@
RW
7+di
sp8,
R6
MO
VR
7,R
7
MO
V@
RW
7+di
sp8,
R7
+8
MO
V@
RW
0,R
0
MO
V@
RW
0+di
sp16
,R
0
MO
V@
RW
0,R
1
MO
V@
RW
0+di
sp16
,R
1
MO
V@
RW
0,R
2
MO
V@
RW
0+di
sp16
,R
2
MO
V@
RW
0,R
3
MO
V@
RW
0+di
sp16
,R
3
MO
V@
RW
0,R
4
MO
V@
RW
0+di
sp16
,R
4
MO
V@
RW
0,R
5
MO
V@
RW
0+di
sp16
,R
5
MO
V@
RW
0,R
6
MO
V@
RW
0+di
sp16
,R
6
MO
V@
RW
0,R
7
MO
V@
RW
0+di
sp16
,R
7
+9
MO
V@
RW
1,R
0
MO
V@
RW
1+di
sp16
,R
0
MO
V@
RW
1,R
1
MO
V@
RW
1+di
sp16
,R
1
MO
V@
RW
1,R
2
MO
V@
RW
1+di
sp16
,R
2
MO
V@
RW
1,R
3
MO
V@
RW
1+di
sp16
,R
3
MO
V@
RW
1,R
4
MO
V@
RW
1+di
sp16
,R
4
MO
V@
RW
1,R
5
MO
V@
RW
1+di
sp16
,R
5
MO
V@
RW
1,R
6
MO
V@
RW
1+di
sp16
,R
6
MO
V@
RW
1,R
7
MO
V@
RW
1+di
sp16
,R
7
+A
MO
V@
RW
2,R
0
MO
V@
RW
2+di
sp16
,R
0
MO
V@
RW
2,R
1
MO
V@
RW
2+di
sp16
,R
1
MO
V@
RW
2,R
2
MO
V@
RW
2+di
sp16
,R
2
MO
V@
RW
2,R
3
MO
V@
RW
2+di
sp16
,R
3
MO
V@
RW
2,R
4
MO
V@
RW
2+di
sp16
,R
4
MO
V@
RW
2,R
5
MO
V@
RW
2+di
sp16
,R
5
MO
V@
RW
2,R
6
MO
V@
RW
2+di
sp16
,R
6
MO
V@
RW
2,R
7
MO
V@
RW
2+di
sp16
,R
7
+B
MO
V@
RW
3,R
0
MO
V@
RW
3+di
sp16
,R
0
MO
V@
RW
3,R
1
MO
V@
RW
3+di
sp16
,R
1
MO
V@
RW
3,R
2
MO
V@
RW
3+di
sp16
,R
2
MO
V@
RW
3,R
3
MO
V@
RW
3+di
sp16
,R
3
MO
V@
RW
3,R
4
MO
V@
RW
3+di
sp16
,R
4
MO
V@
RW
3,R
5
MO
V@
RW
3+di
sp16
,R
5
MO
V@
RW
3,R
6
MO
V@
RW
3+di
sp16
,R
6
MO
V@
RW
3,R
7
MO
V@
RW
3+di
sp16
,R
7
+C
MO
V@
RW
0+,
R0
MO
V@
RW
0+R
W7,
R0
MO
V@
RW
0+,
R1
MO
V@
RW
0+R
W7,
R1
MO
V@
RW
0+,
R2
MO
V@
RW
0+R
W7,
R2
MO
V@
RW
0+,
R3
MO
V@
RW
0+R
W7,
R3
MO
V@
RW
0+,
R4
MO
V@
RW
0+R
W7,
R4
MO
V@
RW
0+,
R5
MO
V@
RW
0+R
W7,
R5
MO
V@
RW
0+,
R6
MO
V@
RW
0+R
W7,
R6
MO
V@
RW
0+,
R7
MO
V@
RW
0+R
W7,
R7
+D
MO
V@
RW
1+,
R0
MO
V@
RW
1+R
W7,
R0
MO
V@
RW
1+,
R1
MO
V@
RW
1+R
W7,
R1
MO
V@
RW
1+,
R2
MO
V@
RW
1+R
W7,
R2
MO
V@
RW
1+,
R3
MO
V@
RW
1+R
W7,
R3
MO
V@
RW
1+,
R4
MO
V@
RW
1+R
W7,
R4
MO
V@
RW
1+,
R5
MO
V@
RW
1+R
W7,
R5
MO
V@
RW
1+,
R6
MO
V@
RW
1+R
W7,
R6
MO
V@
RW
1+,
R7
MO
V@
RW
1+R
W7,
R7
+E
MO
V@
RW
2+,
R0
MO
V@
PC
+dis
p16,
R0
MO
V@
RW
2+,
R1
MO
V@
PC
+dis
p16,
R1
MO
V@
RW
2+,
R2
MO
V@
PC
+dis
p16,
R2
MO
V@
RW
2+,
R3
MO
V@
PC
+dis
p16,
R3
MO
V@
RW
2+,
R4
MO
V@
PC
+dis
p16,
R4
MO
V@
RW
2+,
R5
MO
V@
PC
+dis
p16,
R5
MO
V@
RW
2+,
R6
MO
V@
PC
+dis
p16,
R6
MO
V@
RW
2+,
R7
MO
V@
PC
+dis
p16,
R7
+F
MO
V@
RW
3+,
R0
MO
Vad
dr16
,R
0
MO
V@
RW
3+,
R1
MO
Vad
dr16
,R
1
MO
V@
RW
3+,
R2
MO
Vad
dr16
,R
2
MO
V@
RW
3+,
R3
MO
Vad
dr16
,R
3
MO
V@
RW
3+,
R4
MO
Vad
dr16
,R
4
MO
V@
RW
3+,
R5
MO
Vad
dr16
,R
5
MO
V@
RW
3+,
R6
MO
Vad
dr16
,R
6
MO
V@
RW
3+,
R7
MO
Vad
dr16
,R
7
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 365
APPENDIXAPPENDIX C Instruction Maps
C.11 MOVW ea, RWi Instruction Map
Table C.11-1 lists MOVW ea, RWi instruction map.
F2MC-16FX Family
366 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.11-1 MOVW ea, RWi Instruction (First Byte = 7DH)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
MO
VW
RW
0,R
W0
MO
VW
@R
W0+
disp
8,R
W0
MO
VW
RW
0,R
W1
MO
VW
@R
W0+
disp
8,R
W1
MO
VW
RW
0,R
W2
MO
VW
@R
W0+
disp
8,R
W2
MO
VW
RW
0,R
W3
MO
VW
@R
W0+
disp
8,R
W3
MO
VW
RW
0,R
W4
MO
VW
@R
W0+
disp
8,R
W4
MO
VW
RW
0,R
W5
MO
VW
@R
W0+
disp
8,R
W5
MO
VW
RW
0,R
W6
MO
VW
@R
W0+
disp
8,R
W6
MO
VW
RW
0,R
W7
MO
VW
@R
W0+
disp
8,R
W7
+1
MO
VW
RW
1,R
W0
MO
VW
@R
W1+
disp
8,R
W0
MO
VW
RW
1,R
W1
MO
VW
@R
W1+
disp
8,R
W1
MO
VW
RW
1,R
W2
MO
VW
@R
W1+
disp
8,R
W2
MO
VW
RW
1,R
W3
MO
VW
@R
W1+
disp
8,R
W3
MO
VW
RW
1,R
W4
MO
VW
@R
W1+
disp
8,R
W4
MO
VW
RW
1,R
W5
MO
VW
@R
W1+
disp
8,R
W5
MO
VW
RW
1,R
W6
MO
VW
@R
W1+
disp
8,R
W6
MO
VW
RW
1,R
W7
MO
VW
@R
W1+
disp
8,R
W7
+2
MO
VW
RW
2,R
W0
MO
VW
@R
W2+
disp
8,R
W0
MO
VW
RW
2,R
W1
MO
VW
@R
W2+
disp
8,R
W1
MO
VW
RW
2,R
W2
MO
VW
@R
W2+
disp
8,R
W2
MO
VW
RW
2,R
W3
MO
VW
@R
W2+
disp
8,R
W3
MO
VW
RW
2,R
W4
MO
VW
@R
W2+
disp
8,R
W4
MO
VW
RW
2,R
W5
MO
VW
@R
W2+
disp
8,R
W5
MO
VW
RW
2,R
W6
MO
VW
@R
W2+
disp
8,R
W6
MO
VW
RW
2,R
W7
MO
VW
@R
W2+
disp
8,R
W7
+3
MO
VW
RW
3,R
W0
MO
VW
@R
W3+
disp
8,R
W0
MO
VW
RW
3,R
W1
MO
VW
@R
W3+
disp
8,R
W1
MO
VW
RW
3,R
W2
MO
VW
@R
W3+
disp
8,R
W2
MO
VW
RW
3,R
W3
MO
VW
@R
W3+
disp
8,R
W3
MO
VW
RW
3,R
W4
MO
VW
@R
W3+
disp
8,R
W4
MO
VW
RW
3,R
W5
MO
VW
@R
W3+
disp
8,R
W5
MO
VW
RW
3,R
W6
MO
VW
@R
W3+
disp
8,R
W6
MO
VW
RW
3,R
W7
MO
VW
@R
W3+
disp
8,R
W7
+4
MO
VW
RW
4,R
W0
MO
VW
@R
W4+
disp
8,R
W0
MO
VW
RW
4,R
W1
MO
VW
@R
W4+
disp
8,R
W1
MO
VW
RW
4,R
W2
MO
VW
@R
W4+
disp
8,R
W2
MO
VW
RW
4,R
W3
MO
VW
@R
W4+
disp
8,R
W3
MO
VW
RW
4,R
W4
MO
VW
@R
W4+
disp
8,R
W4
MO
VW
RW
4,R
W5
MO
VW
@R
W4+
disp
8,R
W5
MO
VW
RW
4,R
W6
MO
VW
@R
W4+
disp
8,R
W6
MO
VW
RW
4,R
W7
MO
VW
@R
W4+
disp
8,R
W7
+5
MO
VW
RW
5,R
W0
MO
VW
@R
W5+
disp
8,R
W0
MO
VW
RW
5,R
W1
MO
VW
@R
W5+
disp
8,R
W1
MO
VW
RW
5,R
W2
MO
VW
@R
W5+
disp
8,R
W2
MO
VW
RW
5,R
W3
MO
VW
@R
W5+
disp
8,R
W3
MO
VW
RW
5,R
W4
MO
VW
@R
W5+
disp
8,R
W4
MO
VW
RW
5,R
W5
MO
VW
@R
W5+
disp
8,R
W5
MO
VW
RW
5,R
W6
MO
VW
@R
W5+
disp
8,R
W6
MO
VW
RW
5,R
W7
MO
VW
@R
W5+
disp
8,R
W7
+6
MO
VW
RW
6,R
W0
MO
VW
@R
W6+
disp
8,R
W0
MO
VW
RW
6,R
W1
MO
VW
@R
W6+
disp
8,R
W1
MO
VW
RW
6,R
W2
MO
VW
@R
W6+
disp
8,R
W2
MO
VW
RW
6,R
W3
MO
VW
@R
W6+
disp
8,R
W3
MO
VW
RW
6,R
W4
MO
VW
@R
W6+
disp
8,R
W4
MO
VW
RW
6,R
W5
MO
VW
@R
W6+
disp
8,R
W5
MO
VW
RW
6,R
W6
MO
VW
@R
W6+
disp
8,R
W6
MO
VW
RW
6,R
W7
MO
VW
@R
W6+
disp
8,R
W7
+7
MO
VW
RW
7,R
W0
MO
VW
@R
W7+
disp
8,R
W0
MO
VW
RW
7,R
W1
MO
VW
@R
W7+
disp
8,R
W1
MO
VW
RW
7,R
W2
MO
VW
@R
W7+
disp
8,R
W2
MO
VW
RW
7,R
W3
MO
VW
@R
W7+
disp
8,R
W3
MO
VW
RW
7,R
W4
MO
VW
@R
W7+
disp
8,R
W4
MO
VW
RW
7,R
W5
MO
VW
@R
W7+
disp
8,R
W5
MO
VW
RW
7,R
W6
MO
VW
@R
W7+
disp
8,R
W6
MO
VW
RW
7,R
W7
MO
VW
@R
W7+
disp
8,R
W7
+8
MO
VW
@R
W0,
RW
0
MO
VW
@R
W0+
disp
16,
RW
0
MO
VW
@R
W0,
RW
1
MO
VW
@R
W0+
disp
16,
RW
1
MO
VW
@R
W0,
RW
2
MO
VW
@R
W0+
disp
16,
RW
2
MO
VW
@R
W0,
RW
3
MO
VW
@R
W0+
disp
16,
RW
3
MO
VW
@R
W0,
RW
4
MO
VW
@R
W0+
disp
16,
RW
4
MO
VW
@R
W0,
RW
5
MO
VW
@R
W0+
disp
16,
RW
5
MO
VW
@R
W0,
RW
6
MO
VW
@R
W0+
disp
16,
RW
6
MO
VW
@R
W0,
RW
7
MO
VW
@R
W0+
disp
16,
RW
7
+9
MO
VW
@R
W1,
RW
0
MO
VW
@R
W1+
disp
16,
RW
0
MO
VW
@R
W1,
RW
1
MO
VW
@R
W1+
disp
16,
RW
1
MO
VW
@R
W1,
RW
2
MO
VW
@R
W1+
disp
16,
RW
2
MO
VW
@R
W1,
RW
3
MO
VW
@R
W1+
disp
16,
RW
3
MO
VW
@R
W1,
RW
4
MO
VW
@R
W1+
disp
16,
RW
4
MO
VW
@R
W1,
RW
5
MO
VW
@R
W1+
disp
16,
RW
5
MO
VW
@R
W1,
RW
6
MO
VW
@R
W1+
disp
16,
RW
6
MO
VW
@R
W1,
RW
7
MO
VW
@R
W1+
disp
16,
RW
7
+A
MO
VW
@R
W2,
RW
0
MO
VW
@R
W2+
disp
16,
RW
0
MO
VW
@R
W2,
RW
1
MO
VW
@R
W2+
disp
16,
RW
1
MO
VW
@R
W2,
RW
2
MO
VW
@R
W2+
disp
16,
RW
2
MO
VW
@R
W2,
RW
3
MO
VW
@R
W2+
disp
16,
RW
3
MO
VW
@R
W2,
RW
4
MO
VW
@R
W2+
disp
16,
RW
4
MO
VW
@R
W2,
RW
5
MO
VW
@R
W2+
disp
16,
RW
5
MO
VW
@R
W2,
RW
6
MO
VW
@R
W2+
disp
16,
RW
6
MO
VW
@R
W2,
RW
7
MO
VW
@R
W2+
disp
16,
RW
7
+B
MO
VW
@R
W3,
RW
0
MO
VW
@R
W3+
disp
16,
RW
0
MO
VW
@R
W3,
RW
1
MO
VW
@R
W3+
disp
16,
RW
1
MO
VW
@R
W3,
RW
2
MO
VW
@R
W3+
disp
16,
RW
2
MO
VW
@R
W3,
RW
3
MO
VW
@R
W3+
disp
16,
RW
3
MO
VW
@R
W3,
RW
4
MO
VW
@R
W3+
disp
16,
RW
4
MO
VW
@R
W3,
RW
5
MO
VW
@R
W3+
disp
16,
RW
5
MO
VW
@R
W3,
RW
6
MO
VW
@R
W3+
disp
16,
RW
6
MO
VW
@R
W3,
RW
7
MO
VW
@R
W3+
disp
16,
RW
7
+C
MO
VW
@R
W0+
,R
W0
MO
VW
@R
W0+
RW
7,R
W0
MO
VW
@R
W0+
,R
W1
MO
VW
@R
W0+
RW
7,R
W1
MO
VW
@R
W0+
,R
W2
MO
VW
@R
W0+
RW
7,R
W2
MO
VW
@R
W0+
,R
W3
MO
VW
@R
W0+
RW
7,R
W3
MO
VW
@R
W0+
,R
W4
MO
VW
@R
W0+
RW
7,R
W4
MO
VW
@R
W0+
,R
W5
MO
VW
@R
W0+
RW
7,R
W5
MO
VW
@R
W0+
,R
W6
MO
VW
@R
W0+
RW
7,R
W6
MO
VW
@R
W0+
,R
W7
MO
VW
@R
W0+
RW
7,R
W7
+D
MO
VW
@R
W1+
,R
W0
MO
VW
@R
W1+
RW
7,R
W0
MO
VW
@R
W1+
,R
W1
MO
VW
@R
W1+
RW
7,R
W1
MO
VW
@R
W1+
,R
W2
MO
VW
@R
W1+
RW
7,R
W2
MO
VW
@R
W1+
,R
W3
MO
VW
@R
W1+
RW
7,R
W3
MO
VW
@R
W1+
,R
W4
MO
VW
@R
W1+
RW
7,R
W4
MO
VW
@R
W1+
,R
W5
MO
VW
@R
W1+
RW
7,R
W5
MO
VW
@R
W1+
,R
W6
MO
VW
@R
W1+
RW
7,R
W6
MO
VW
@R
W1+
,R
W7
MO
VW
@R
W1+
RW
7,R
W7
+E
MO
VW
@R
W2+
,R
W0
MO
VW
@P
C+d
isp1
6,R
W0
MO
VW
@R
W2+
,R
W1
MO
VW
@P
C+d
isp1
6,R
W1
MO
VW
@R
W2+
,R
W2
MO
VW
@P
C+d
isp1
6,R
W2
MO
VW
@R
W2+
,R
W3
MO
VW
@P
C+d
isp1
6,R
W3
MO
VW
@R
W2+
,R
W4
MO
VW
@P
C+d
isp1
6,R
W4
MO
VW
@R
W2+
,R
W5
MO
VW
@P
C+d
isp1
6,R
W5
MO
VW
@R
W2+
,R
W6
MO
VW
@P
C+d
isp1
6,R
W6
MO
VW
@R
W2+
,R
W7
MO
VW
@P
C+d
isp1
6,R
W7
+F
MO
VW
@R
W3+
,R
W0
MO
VW
addr
16,
RW
0
MO
VW
@R
W3+
,R
W1
MO
VW
addr
16,
RW
1
MO
VW
@R
W3+
,R
W2
MO
VW
addr
16,
RW
2
MO
VW
@R
W3+
,R
W3
MO
VW
addr
16,
RW
3
MO
VW
@R
W3+
,R
W4
MO
VW
addr
16,
RW
4
MO
VW
@R
W3+
,R
W5
MO
VW
addr
16,
RW
5
MO
VW
@R
W3+
,R
W6
MO
VW
addr
16,
RW
6
MO
VW
@R
W3+
,R
W7
MO
VW
addr
16,
RW
7
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 367
APPENDIXAPPENDIX C Instruction Maps
C.12 XCH Ri, ea Instruction Map
Table C.12-1 lists XCH Ri, ea instruction map.
F2MC-16FX Family
368 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.12-1 XCH Ri, ea Instruction (First Byte = 7EH)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
XC
HR
0,R
0
XC
HR
0,@
RW
0+di
sp8
XC
HR
1,R
0
XC
HR
1,@
RW
0+di
sp8
XC
HR
2,R
0
XC
HR
2,@
RW
0+di
sp8
XC
HR
3,R
0
XC
HR
3,@
RW
0+di
sp8
XC
HR
4,R
0
XC
HR
4,@
RW
0+di
sp8
XC
HR
5,R
0
XC
HR
5,@
RW
0+di
sp8
XC
HR
6,R
0
XC
HR
6,@
RW
0+di
sp8
XC
HR
7,R
0
XC
HR
7,@
RW
0+di
sp8
+1
XC
HR
0,R
1
XC
HR
0,@
RW
1+di
sp8
XC
HR
1,R
1
XC
HR
1,@
RW
1+di
sp8
XC
HR
2,R
1
XC
HR
2,@
RW
1+di
sp8
XC
HR
3,R
1
XC
HR
3,@
RW
1+di
sp8
XC
HR
4,R
1
XC
HR
4,@
RW
1+di
sp8
XC
HR
5,R
1
XC
HR
5,@
RW
1+di
sp8
XC
HR
6,R
1
XC
HR
6,@
RW
1+di
sp8
XC
HR
7,R
1
XC
HR
7,@
RW
1+di
sp8
+2
XC
HR
0,R
2
XC
HR
0,@
RW
2+di
sp8
XC
HR
1,R
2
XC
HR
1,@
RW
2+di
sp8
XC
HR
2,R
2
XC
HR
2,@
RW
2+di
sp8
XC
HR
3,R
2
XC
HR
3,@
RW
2+di
sp8
XC
HR
4,R
2
XC
HR
4,@
RW
2+di
sp8
XC
HR
5,R
2
XC
HR
5,@
RW
2+di
sp8
XC
HR
6,R
2
XC
HR
6,@
RW
2+di
sp8
XC
HR
7,R
2
XC
HR
7,@
RW
2+di
sp8
+3
XC
HR
0,R
3
XC
HR
0,@
RW
3+di
sp8
XC
HR
1,R
3
XC
HR
1,@
RW
3+di
sp8
XC
HR
2,R
3
XC
HR
2,@
RW
3+di
sp8
XC
HR
3,R
3
XC
HR
3,@
RW
3+di
sp8
XC
HR
4,R
3
XC
HR
4,@
RW
3+di
sp8
XC
HR
5,R
3
XC
HR
5,@
RW
3+di
sp8
XC
HR
6,R
3
XC
HR
6,@
RW
3+di
sp8
XC
HR
7,R
3
XC
HR
7,@
RW
3+di
sp8
+4
XC
HR
0,R
4
XC
HR
0,@
RW
4+di
sp8
XC
HR
1,R
4
XC
HR
1,@
RW
4+di
sp8
XC
HR
2,R
4
XC
HR
2,@
RW
4+di
sp8
XC
HR
3,R
4
XC
HR
3,@
RW
4+di
sp8
XC
HR
4,R
4
XC
HR
4,@
RW
4+di
sp8
XC
HR
5,R
4
XC
HR
5,@
RW
4+di
sp8
XC
HR
6,R
4
XC
HR
6,@
RW
4+di
sp8
XC
HR
7,R
4
XC
HR
7,@
RW
4+di
sp8
+5
XC
HR
0,R
5
XC
HR
0,@
RW
5+di
sp8
XC
HR
1,R
5
XC
HR
1,@
RW
5+di
sp8
XC
HR
2,R
5
XC
HR
2,@
RW
5+di
sp8
XC
HR
3,R
5
XC
HR
3,@
RW
5+di
sp8
XC
HR
4,R
5
XC
HR
4,@
RW
5+di
sp8
XC
HR
5,R
5
XC
HR
5,@
RW
5+di
sp8
XC
HR
6,R
5
XC
HR
6,@
RW
5+di
sp8
XC
HR
7,R
5
XC
HR
7,@
RW
5+di
sp8
+6
XC
HR
0,R
6
XC
HR
0,@
RW
6+di
sp8
XC
HR
1,R
6
XC
HR
1,@
RW
6+di
sp8
XC
HR
2,R
6
XC
HR
2,@
RW
6+di
sp8
XC
HR
3,R
6
XC
HR
3,@
RW
6+di
sp8
XC
HR
4,R
6
XC
HR
4,@
RW
6+di
sp8
XC
HR
5,R
6
XC
HR
5,@
RW
6+di
sp8
XC
HR
6,R
6
XC
HR
6,@
RW
6+di
sp8
XC
HR
7,R
6
XC
HR
7,@
RW
6+di
sp8
+7
XC
HR
0,R
7
XC
HR
0,@
RW
7+di
sp8
XC
HR
1,R
7
XC
HR
1,@
RW
7+di
sp8
XC
HR
2,R
7
XC
HR
2,@
RW
7+di
sp8
XC
HR
3,R
7
XC
HR
3,@
RW
7+di
sp8
XC
HR
4,R
7
XC
HR
4,@
RW
7+di
sp8
XC
HR
5,R
7
XC
HR
5,@
RW
7+di
sp8
XC
HR
6,R
7
XC
HR
6,@
RW
7+di
sp8
XC
HR
7,R
7
XC
HR
7,@
RW
7+di
sp8
+8
XC
HR
0,@
RW
0
XC
HR
0,@
RW
0+di
sp16
XC
HR
1,@
RW
0
XC
HR
1,@
RW
0+di
sp16
XC
HR
2,@
RW
0
XC
HR
2,@
RW
0+di
sp16
XC
HR
3,@
RW
0
XC
HR
3,@
RW
0+di
sp16
XC
HR
4,@
RW
0
XC
HR
4,@
RW
0+di
sp16
XC
HR
5,@
RW
0
XC
HR
5,@
RW
0+di
sp16
XC
HR
6,@
RW
0
XC
HR
6,@
RW
0+di
sp16
XC
HR
7,@
RW
0
XC
HR
7,@
RW
0+di
sp16
+9
XC
HR
0,@
RW
1
XC
HR
0,@
RW
1+di
sp16
XC
HR
1,@
RW
1
XC
HR
1,@
RW
1+di
sp16
XC
HR
2,@
RW
1
XC
HR
2,@
RW
1+di
sp16
XC
HR
3,@
RW
1
XC
HR
3,@
RW
1+di
sp16
XC
HR
4,@
RW
1
XC
HR
4,@
RW
1+di
sp16
XC
HR
5,@
RW
1
XC
HR
5,@
RW
1+di
sp16
XC
HR
6,@
RW
1
XC
HR
6,@
RW
1+di
sp16
XC
HR
7,@
RW
1
XC
HR
7,@
RW
1+di
sp16
+A
XC
HR
0,@
RW
2
XC
HR
0,@
RW
2+di
sp16
XC
HR
1,@
RW
2
XC
HR
1,@
RW
2+di
sp16
XC
HR
2,@
RW
2
XC
HR
2,@
RW
2+di
sp16
XC
HR
3,@
RW
2
XC
HR
3,@
RW
2+di
sp16
XC
HR
4,@
RW
2
XC
HR
4,@
RW
2+di
sp16
XC
HR
5,@
RW
2
XC
HR
5,@
RW
2+di
sp16
XC
HR
6,@
RW
2
XC
HR
6,@
RW
2+di
sp16
XC
HR
7,@
RW
2
XC
HR
7,@
RW
2+di
sp16
+B
XC
HR
0,@
RW
3
XC
HR
0,@
RW
3+di
sp16
XC
HR
1,@
RW
3
XC
HR
1,@
RW
3+di
sp16
XC
HR
2,@
RW
3
XC
HR
2,@
RW
3+di
sp16
XC
HR
3,@
RW
3
XC
HR
3,@
RW
3+di
sp16
XC
HR
4,@
RW
3
XC
HR
4,@
RW
3+di
sp16
XC
HR
5,@
RW
3
XC
HR
5,@
RW
3+di
sp16
XC
HR
6,@
RW
3
XC
HR
6,@
RW
3+di
sp16
XC
HR
7,@
RW
3
XC
HR
7,@
RW
3+di
sp16
+C
XC
HR
0,@
RW
0+
XC
HR
0,@
RW
0+R
W7
XC
HR
1,@
RW
0+
XC
HR
1,@
RW
0+R
W7
XC
HR
2,@
RW
0+
XC
HR
2,@
RW
0+R
W7
XC
HR
3,@
RW
0+
XC
HR
3,@
RW
0+R
W7
XC
HR
4,@
RW
0+
XC
HR
4,@
RW
0+R
W7
XC
HR
5,@
RW
0+
XC
HR
5,@
RW
0+R
W7
XC
HR
6,@
RW
0+
XC
HR
6,@
RW
0+R
W7
XC
HR
7,@
RW
0+
XC
HR
7,@
RW
0+R
W7
+D
XC
HR
0,@
RW
1+
XC
HR
0,@
RW
1+R
W7
XC
HR
1,@
RW
1+
XC
HR
1,@
RW
1+R
W7
XC
HR
2,@
RW
1+
XC
HR
2,@
RW
1+R
W7
XC
HR
3,@
RW
1+
XC
HR
3,@
RW
1+R
W7
XC
HR
4,@
RW
1+
XC
HR
4,@
RW
1+R
W7
XC
HR
5,@
RW
1+
XC
HR
5,@
RW
1+R
W7
XC
HR
6,@
RW
1+
XC
HR
6,@
RW
1+R
W7
XC
HR
7,@
RW
1+
XC
HR
7,@
RW
1+R
W7
+E
XC
HR
0,@
RW
2+
XC
HR
0,@
PC
+di
sp16
XC
HR
1,@
RW
2+
XC
HR
1,@
PC
+di
sp16
XC
HR
2,@
RW
2+
XC
HR
2,@
PC
+di
sp16
XC
HR
3,@
RW
2+
XC
HR
3,@
PC
+di
sp16
XC
HR
4,@
RW
2+
XC
HR
4,@
PC
+di
sp16
XC
HR
5,@
RW
2+
XC
HR
5,@
PC
+di
sp16
XC
HR
6,@
RW
2+
XC
HR
6,@
PC
+di
sp16
XC
HR
7,@
RW
2+
XC
HR
7,@
PC
+di
sp16
+F
XC
HR
0,@
RW
3+
XC
HR
0,ad
dr16
XC
HR
1,@
RW
3+
XC
HR
1,ad
dr16
XC
HR
2,@
RW
3+
XC
HR
2,ad
dr16
XC
HR
3,@
RW
3+
XC
HR
3,ad
dr16
XC
HR
4,@
RW
3+
XC
HR
4,ad
dr16
XC
HR
5,@
RW
3+
XC
HR
5,ad
dr16
XC
HR
6,@
RW
3+
XC
HR
6,ad
dr16
XC
HR
7,@
RW
3+
XC
HR
7,ad
dr16
F2MC-16FX Family
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 369
APPENDIXAPPENDIX C Instruction Maps
C.13 XCHW RWi, ea Instruction Map
Table C.13-1 lists XCHW RWi, ea instruction map.
F2MC-16FX Family
370 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
APPENDIX APPENDIX C Instruction Maps
Table C.13-1 XCHW RWi, ea Instruction (First Byte = 7FH)00
1020
3040
5060
7080
90A
0B
0C
0D
0E
0F
0
+0
XC
HW
RW
0,R
W0
XC
HW
RW
0,@
RW
0+di
sp8
XC
HW
RW
1,R
W0
XC
HW
RW
1,@
RW
0+di
sp8
XC
HW
RW
2,R
W0
XC
HW
RW
2,@
RW
0+di
sp8
XC
HW
RW
3,R
W0
XC
HW
RW
3,@
RW
0+di
sp8
XC
HW
RW
4,R
W0
XC
HW
RW
4,@
RW
0+di
sp8
XC
HW
RW
5,R
W0
XC
HW
RW
5,@
RW
0+di
sp8
XC
HW
RW
6,R
W0
XC
HW
RW
6,@
RW
0+di
sp8
XC
HW
RW
7,R
W0
XC
HW
RW
7,@
RW
0+di
sp8
+1
XC
HW
RW
0,R
W1
XC
HW
RW
0,@
RW
1+di
sp8
XC
HW
RW
1,R
W1
XC
HW
RW
1,@
RW
1+di
sp8
XC
HW
RW
2,R
W1
XC
HW
RW
2,@
RW
1+di
sp8
XC
HW
RW
3,R
W1
XC
HW
RW
3,@
RW
1+di
sp8
XC
HW
RW
4,R
W1
XC
HW
RW
4,@
RW
1+di
sp8
XC
HW
RW
5,R
W1
XC
HW
RW
5,@
RW
1+di
sp8
XC
HW
RW
6,R
W1
XC
HW
RW
6,@
RW
1+di
sp8
XC
HW
RW
7,R
W1
XC
HW
RW
7,@
RW
1+di
sp8
+2
XC
HW
RW
0,R
W2
XC
HW
RW
0,@
RW
2+di
sp8
XC
HW
RW
1,R
W2
XC
HW
RW
1,@
RW
2+di
sp8
XC
HW
RW
2,R
W2
XC
HW
RW
2,@
RW
2+di
sp8
XC
HW
RW
3,R
W2
XC
HW
RW
3,@
RW
2+di
sp8
XC
HW
RW
4,R
W2
XC
HW
RW
4,@
RW
2+di
sp8
XC
HW
RW
5,R
W2
XC
HW
RW
5,@
RW
2+di
sp8
XC
HW
RW
6,R
W2
XC
HW
RW
6,@
RW
2+di
sp8
XC
HW
RW
7,R
W2
XC
HW
RW
7,@
RW
2+di
sp8
+3
XC
HW
RW
0,R
W3
XC
HW
RW
0,@
RW
3+di
sp8
XC
HW
RW
1,R
W3
XC
HW
RW
1,@
RW
3+di
sp8
XC
HW
RW
2,R
W3
XC
HW
RW
2,@
RW
3+di
sp8
XC
HW
RW
3,R
W3
XC
HW
RW
3,@
RW
3+di
sp8
XC
HW
RW
4,R
W3
XC
HW
RW
4,@
RW
3+di
sp8
XC
HW
RW
5,R
W3
XC
HW
RW
5,@
RW
3+di
sp8
XC
HW
RW
6,R
W3
XC
HW
RW
6,@
RW
3+di
sp8
XC
HW
RW
7,R
W3
XC
HW
RW
7,@
RW
3+di
sp8
+4
XC
HW
RW
0,R
W4
XC
HW
RW
0,@
RW
4+di
sp8
XC
HW
RW
1,R
W4
XC
HW
RW
1,@
RW
4+di
sp8
XC
HW
RW
2,R
W4
XC
HW
RW
2,@
RW
4+di
sp8
XC
HW
RW
3,R
W4
XC
HW
RW
3,@
RW
4+di
sp8
XC
HW
RW
4,R
W4
XC
HW
RW
4,@
RW
4+di
sp8
XC
HW
RW
5,R
W4
XC
HW
RW
5,@
RW
4+di
sp8
XC
HW
RW
6,R
W4
XC
HW
RW
6,@
RW
4+di
sp8
XC
HW
RW
7,R
W4
XC
HW
RW
7,@
RW
4+di
sp8
+5
XC
HW
RW
0,R
W5
XC
HW
RW
0,@
RW
5+di
sp8
XC
HW
RW
1,R
W5
XC
HW
RW
1,@
RW
5+di
sp8
XC
HW
RW
2,R
W5
XC
HW
RW
2,@
RW
5+di
sp8
XC
HW
RW
3,R
W5
XC
HW
RW
3,@
RW
5+di
sp8
XC
HW
RW
4,R
W5
XC
HW
RW
4,@
RW
5+di
sp8
XC
HW
RW
5,R
W5
XC
HW
RW
5,@
RW
5+di
sp8
XC
HW
RW
6,R
W5
XC
HW
RW
6,@
RW
5+di
sp8
XC
HW
RW
7,R
W5
XC
HW
RW
7,@
RW
5+di
sp8
+6
XC
HW
RW
0,R
W6
XC
HW
RW
0,@
RW
6+di
sp8
XC
HW
RW
1,R
W6
XC
HW
RW
1,@
RW
6+di
sp8
XC
HW
RW
2,R
W6
XC
HW
RW
2,@
RW
6+di
sp8
XC
HW
RW
3,R
W6
XC
HW
RW
3,@
RW
6+di
sp8
XC
HW
RW
4,R
W6
XC
HW
RW
4,@
RW
6+di
sp8
XC
HW
RW
5,R
W6
XC
HW
RW
5,@
RW
6+di
sp8
XC
HW
RW
6,R
W6
XC
HW
RW
6,@
RW
6+di
sp8
XC
HW
RW
7,R
W6
XC
HW
RW
7,@
RW
6+di
sp8
+7
XC
HW
RW
0,R
W7
XC
HW
RW
0,@
RW
7+di
sp8
XC
HW
RW
1,R
W7
XC
HW
RW
1,@
RW
7+di
sp8
XC
HW
RW
2,R
W7
XC
HW
RW
2,@
RW
7+di
sp8
XC
HW
RW
3,R
W7
XC
HW
RW
3,@
RW
7+di
sp8
XC
HW
RW
4,R
W7
XC
HW
RW
4,@
RW
7+di
sp8
XC
HW
RW
5,R
W7
XC
HW
RW
5,@
RW
7+di
sp8
XC
HW
RW
6,R
W7
XC
HW
RW
6,@
RW
7+di
sp8
XC
HW
RW
7,R
W7
XC
HW
RW
7,@
RW
7+di
sp8
+8
XC
HW
RW
0,@
RW
0
XC
HW
RW
0,@
RW
0+di
sp16
XC
HW
RW
1,@
RW
0
XC
HW
RW
1,@
RW
0+di
sp16
XC
HW
RW
2,@
RW
0
XC
HW
RW
2,@
RW
0+di
sp16
XC
HW
RW
3,@
RW
0
XC
HW
RW
3,@
RW
0+di
sp16
XC
HW
RW
4,@
RW
0
XC
HW
RW
4,@
RW
0+di
sp16
XC
HW
RW
5,@
RW
0
XC
HW
RW
5,@
RW
0+di
sp16
XC
HW
RW
6,@
RW
0
XC
HW
RW
6,@
RW
0+di
sp16
XC
HW
RW
7,@
RW
0
XC
HW
RW
7,@
RW
0+di
sp16
+9
XC
HW
RW
0,@
RW
1
XC
HW
RW
0,@
RW
1+di
sp16
XC
HW
RW
1,@
RW
1
XC
HW
RW
1,@
RW
1+di
sp16
XC
HW
RW
2,@
RW
1
XC
HW
RW
2,@
RW
1+di
sp16
XC
HW
RW
3,@
RW
1
XC
HW
RW
3,@
RW
1+di
sp16
XC
HW
RW
4,@
RW
1
XC
HW
RW
4,@
RW
1+di
sp16
XC
HW
RW
5,@
RW
1
XC
HW
RW
5,@
RW
1+di
sp16
XC
HW
RW
6,@
RW
1
XC
HW
RW
6,@
RW
1+di
sp16
XC
HW
RW
7,@
RW
1
XC
HW
RW
7,@
RW
1+di
sp16
+A
XC
HW
RW
0,@
RW
2
XC
HW
RW
0,@
RW
2+di
sp16
XC
HW
RW
1,@
RW
2
XC
HW
RW
1,@
RW
2+di
sp16
XC
HW
RW
2,@
RW
2
XC
HW
RW
2,@
RW
2+di
sp16
XC
HW
RW
3,@
RW
2
XC
HW
RW
3,@
RW
2+di
sp16
XC
HW
RW
4,@
RW
2
XC
HW
RW
4,@
RW
2+di
sp16
XC
HW
RW
5,@
RW
2
XC
HW
RW
5,@
RW
2+di
sp16
XC
HW
RW
6,@
RW
2
XC
HW
RW
6,@
RW
2+di
sp16
XC
HW
RW
7,@
RW
2
XC
HW
RW
7,@
RW
2+di
sp16
+B
XC
HW
RW
0,@
RW
3
XC
HW
RW
0,@
RW
3+di
sp16
XC
HW
RW
1,@
RW
3
XC
HW
RW
1,@
RW
3+di
sp16
XC
HW
RW
2,@
RW
3
XC
HW
RW
2,@
RW
3+di
sp16
XC
HW
RW
3,@
RW
3
XC
HW
RW
3,@
RW
3+di
sp16
XC
HW
RW
4,@
RW
3
XC
HW
RW
4,@
RW
3+di
sp16
XC
HW
RW
5,@
RW
3
XC
HW
RW
5,@
RW
3+di
sp16
XC
HW
RW
6,@
RW
3
XC
HW
RW
6,@
RW
3+di
sp16
XC
HW
RW
7,@
RW
3
XC
HW
RW
7,@
RW
3+di
sp16
+C
XC
HW
RW
0,@
RW
0+
XC
HW
RW
0,@
RW
0+R
W7
XC
HW
RW
1,@
RW
0+
XC
HW
RW
1,@
RW
0+R
W7
XC
HW
RW
2,@
RW
0+
XC
HW
RW
2,@
RW
0+R
W7
XC
HW
RW
3,@
RW
0+
XC
HW
RW
3,@
RW
0+R
W7
XC
HW
RW
4,@
RW
0+
XC
HW
RW
4,@
RW
0+R
W7
XC
HW
RW
5,@
RW
0+
XC
HW
RW
5,@
RW
0+R
W7
XC
HW
RW
6,@
RW
0+
XC
HW
RW
6,@
RW
0+R
W7
XC
HW
RW
7,@
RW
0+
XC
HW
RW
7,@
RW
0+R
W7
+D
XC
HW
RW
0,@
RW
1+
XC
HW
RW
0,@
RW
1+R
W7
XC
HW
RW
1,@
RW
1+
XC
HW
RW
1,@
RW
1+R
W7
XC
HW
RW
2,@
RW
1+
XC
HW
RW
2,@
RW
1+R
W7
XC
HW
RW
3,@
RW
1+
XC
HW
RW
3,@
RW
1+R
W7
XC
HW
RW
4,@
RW
1+
XC
HW
RW
4,@
RW
1+R
W7
XC
HW
RW
5,@
RW
1+
XC
HW
RW
5,@
RW
1+R
W7
XC
HW
RW
6,@
RW
1+
XC
HW
RW
6,@
RW
1+R
W7
XC
HW
RW
7,@
RW
1+
XC
HW
RW
7,@
RW
1+R
W7
+E
XC
HW
RW
0,@
RW
2+
XC
HW
RW
0,@
PC
+dis
p16
XC
HW
RW
1,@
RW
2+
XC
HW
RW
1,@
PC
+dis
p16
XC
HW
RW
2,@
RW
2+
XC
HW
RW
2,@
PC
+dis
p16
XC
HW
RW
3,@
RW
2+
XC
HW
RW
3,@
PC
+dis
p16
XC
HW
RW
4,@
RW
2+
XC
HW
RW
4,@
PC
+dis
p16
XC
HW
RW
5,@
RW
2+
XC
HW
RW
5,@
PC
+dis
p16
XC
HW
RW
6,@
RW
2+
XC
HW
RW
6,@
PC
+dis
p16
XC
HW
RW
7,@
RW
2+
XC
HW
RW
7,@
PC
+dis
p16
+F
XC
HW
RW
0,@
RW
3+
XC
HW
RW
0,ad
dr16
XC
HW
RW
1,@
RW
3+
XC
HW
RW
1,ad
dr16
XC
HW
RW
2,@
RW
3+
XC
HW
RW
2,ad
dr16
XC
HW
RW
3,@
RW
3+
XC
HW
RW
3,ad
dr16
XC
HW
RW
4,@
RW
3+
XC
HW
RW
4,ad
dr16
XC
HW
RW
5,@
RW
3+
XC
HW
RW
5,ad
dr16
XC
HW
RW
6,@
RW
3+
XC
HW
RW
6,ad
dr16
XC
HW
RW
7,@
RW
3+
XC
HW
RW
7,ad
dr16
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 371
INDEX
INDEX
The index follows on the next page.This is listed in alphabetic order.
INDEX
372 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
Index
A
AAccumulator (A) .........................................20ADD (Add Byte Data of Destination and Source
to Destination) ...............................83ADDC (Add Byte Data of Accumulator and
Effective Address with Carry to Accumulator).................................86
ADDC (Add Byte Data of AL and AH with Carryto AL) ...........................................85
ADDCW (Add Word Data of Accumulator andEffective Address with Carry to Accumulator).................................88
ADDDC (Add Decimal Data of AL and AH withCarry to AL) ..................................90
ADDL (Add Long Word Data of Destination andSource to Destination) ....................91
ADDSP (Add Word Data of Stack Pointer andImmediate Data to Stack Pointer) .........................................93
ADDW (Add Word Data of AL and AH to AL) .....................................94
ADDW (Add Word Data of Destination andSource to Destination) ....................95
AND (And Byte Data of Destination and Sourceto Destination) ...............................97
AND (And Byte Data of Immediate Data andCondition Code Register)................99
ANDL (And Long Word Data of Destination andSource to Destination) ..................101
ANDW (And Word Data of AH and AL to AL) ...................................103
ANDW (And Word Data of Destination andSource to Destination) ..................104
ASR (Arithmetic Shift Byte Data of Accumulator to Right) ..................106
ASRL (Arithmetic Shift Long Word Data of Ac-cumulator to Right) ......................108
ASRW (Arithmetic Shift Word Data of Accumulator to Right) ..........110, 112
AccumulatorAccumulator (A) .........................................20
AddressingBank Addressing Mode ...............................12Direct Addressing .......................................73Indirect Addressing .....................................75Linear Addressing Mode..............................11
B
BBBcc (Branch if Bit Condition
satisfied)..................................... 114Bcc (Branch relative if Condition
satisfied)..................................... 116Bank Addressing
Bank Addressing Mode............................... 12Bank Select Prefix
Bank Select Prefix ...................................... 38Banks
Memory Space Divided into Banks and Values inEach Register Bank ....................... 14
C
CCALL (Call Subroutine) ........................... 118CALLP (Call Physical Address) ................ 120CALLV (Call Vectored Subroutine)........... 122CBNE (Compare Byte Data and Branch if not
Equal) ........................................ 124CLRB (Clear Bit) ..................................... 126CMP (Compare Byte Data of Destination and
Source)....................................... 127CMPL (Compare Long Word Data of
Destination and Source) ............... 129CMPW (Compare Word Data of Destination and
Source)....................................... 131CWBNE (Compare Word Data and Branch if not
Equal) ........................................ 133CCR
Condition Code Register (CCR)................... 25CMR
Common Register Bank Prefix (CMR) ......... 40Common Register Bank Prefix
Common Register Bank Prefix (CMR) ......... 40Condition Code Register
Condition Code Register (CCR)................... 25Correction Address
Odd Address Correction.............................. 82CPU
CPU Memory Space ................................... 10Hardware Configuration of the F2MC-16FX
CPU ............................................... 4Overview of CPU ......................................... 2
CycleExecution Cycles........................................ 82
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 373
INDEX
D
DDBNZ (Decrement Byte Data and Branch if not
Zero)...........................................135DEC (Decrement Byte Data) ......................137DECL (Decrement Long Word Data)..........138DECW (Decrement Word Data) .................139DIV (Divide Word Data by Byte Data) .......141DIVU (Divide unsigned Word Data by unsigned
Byte Data) ...................................145DIVUW (Divide unsigned Long Word Data by
unsigned Word Data)....................147DIVW (Divide Long Word Data by Word
Data)...........................................143DWBNZ (Decrement Word Data and Branch if
not Zero) .....................................149Direct Addressing
Direct Addressing .......................................73Direct Memory Access
Direct Memory Access (DMA) ....................47Direct Page Register
Direct Page Register (DPR) .........................30DMA
Direct Memory Access (DMA) ....................47DPR
Direct Page Register (DPR) .........................30
E
EEXT (Sign Extend from Byte Data to
Word Data) .................................151EXTW (Sign Extend from Word Data to Long
Word Data) .................................152Effective Address
Effective Address Field ...............................72Exception
Exceptions..................................................47Hardware Exceptions (Non Maskable
Interrupts) .....................................67Software Exceptions (Op-Code) ...................66
Execution cycleExecution cycle count................................316
F
FFILS, FILSI (Fill String Byte) ....................153FILSW, FILSWI (Fill String Word) ............155
F2MC-16FXHardware Configuration of the F2MC-16FX
CPU................................................4Sample Hardware configuration of F2MC-16FX
Family MCU ...................................6Flag Change Inhibit Prefix Code
Flag Change Inhibit Prefix Code (NCC) ........41
G
General-purpose RegistersCalling General-purpose Registers in
RAM............................................ 36
H
HardwareHardware Configuration of the F2MC-16FX
CPU ............................................... 4Hardware Exceptions (Non Maskable
Interrupts)..................................... 67Hardware Interrupt Operation ...................... 59Hardware Interrupt Processing Time ............ 60Hardware Interrupts.............................. 46, 57Multiple Hardware Interrupts ...................... 63Sample Hardware configuration of F2MC-16FX
Family MCU................................... 6Structure of the Hardware Interrupt
System ......................................... 57
I
IINC (Increment Byte Data (Address
Specification)) ............................ 157INCL (Increment Long Word Data) ........... 158INCW (Increment Word Data)................... 159INT (Software Interrupt (Vector
Specification)) ............................ 163INT (Software Interrupt) ........................... 161INT9 (Software Interrupt) ......................... 165INTP (Software Interrupt) ......................... 167
ICRInterrupt Control Register (ICR) .................. 51
ILMInterrupt Level Mask (ILM) ........................ 27
Indirect AddressingIndirect Addressing .................................... 75
InstructionExplanation of the Symbols Used in the
Instruction Lists .......................... 317Instruction Overview .................................. 80MOV Ri, ea Instruction Map
(First Byte = 7AH) ....................... 360Relationships between Instructions Rejecting
Interrupt Requests and Prefix Codes ........................................... 42
Structure of the Instruction Map ................ 337Symbols (Abbreviations) Used in Detailed
Instructions ................................... 81Instruction Map
Structure of the Instruction Map ................ 337Interrupt
Hardware Interrupt Operation ...................... 59Hardware Interrupt Processing Time ............ 60Hardware Interrupts.............................. 46, 57
INDEX
374 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
Interrupt Acceptance Priority .......................64Interrupt Flow.............................................55Interrupt Vector ..........................................48Multiple Hardware Interrupts .......................63Multiple Software Interrupts ........................63Relationships between Instructions Rejecting
Interrupt Requests and Prefix Codes............................................42
Software Interrupt Operation ........................62Software Interrupts................................47, 61Structure of the Hardware Interrupt
System ..........................................57Structure of the Software Interrupt
System ..........................................61Interrupt Control Register
Interrupt Control Register (ICR) ...................51Interrupt Level Mask
Interrupt Level Mask (ILM) .........................27
J
JJCTX (Jump Context)................................169JMP (Jump Destination Address)................171JMPP (Jump Destination Physical
Address)......................................172
L
LLINK (Link and Create New Stack
Frame) ........................................173LSL (Logical Shift Byte Data of Accumulator to
Left) ...........................................174LSLL (Logical Shift Long Word Data of
Accumulator to Left) ....................176LSLW (Logical Shift Word Data of Accumulator
to Left)................................178, 179LSR (Logical Shift Byte Data of Accumulator to
Right) .........................................181LSRL (Logical Shift Long Word Data of
Accumulator to Right) ..................183LSRW (Logical Shift Word Data of Accumulator
to Right)..............................185, 187Linear Addressing
Linear Addressing Mode..............................11Linear Addressing Mode
Linear Addressing Mode..............................11
M
MMOV (Move Byte Data from Accumulator to
Destination) .................................191MOV (Move Byte Data from AH to
Memory) .....................................197MOV (Move Byte Data from Source to
Accumulator)...............................189
MOV (Move Byte Data from Source to Destination) ................................ 195
MOV (Move Byte Immediate Data to Destination) ................................ 193
MOVB (Move Bit Data from Accumulator to BitAddress) ..................................... 200
MOVB (Move Bit Data from Bit Address to Accumulator) .............................. 198
MOVEA (Move Effective Address to Destination) ................................ 202
MOVL (Move Long Word Data from Accumulator to Destination)......... 206
MOVL (Move Long Word Data from Source toAccumulator) .............................. 204
MOVN (Move Immediate Nibble Data to Accumulator) .............................. 208
MOVS, MOVSI (Move String Byte with Increment) .................................. 209
MOVSD (Move String Byte with Decrement) ................................. 211
MOVSW, MOVSWI (Move String Word withIncrement) .................................. 212
MOVSWI (Move String Word with Decrement) ................................. 214
MOVW (Move Immediate Word Data to Destination) ................................ 219
MOVW (Move Immediate Word Data to io) .............................................. 223
MOVW (Move Word Data from Accumulator toDestination) ................................ 217
MOVW (Move Word Data from AH to Memory) .................................... 224
MOVW (Move Word Data from Source to Accumulator) .............................. 215
MOVW (Move Word Data from Source to Destination) ................................ 221
MOVX (Move Byte Data with Sign Extensionfrom Source to Accumulator) ....... 225
MUL (Multiply Byte Data of Accumulator andEffective Address)....................... 228
MUL (Multiply Byte Data of Accumulator) 227MULU (Multiply Unsigned Byte Data of
Accumulator and Effective Address) ..................................... 232
MULU (Multiply Unsigned Byte Data of Accumulator) .............................. 231
MULUW (Multiply Unsigned Word Data of Accumulator and Effective Address) ..................................... 234
MULUW (Multiply Unsigned Word Data of Accumulator) .............................. 233
MULW (Multiply Word Data of Accumulatorand Effective Address)................. 230
MULW (Multiply Word Data of Accumulator) .............................. 229
CM44-00203-3E FUJITSU MICROELECTRONICS LIMITED 375
INDEX
MCUSample Hardware configuration of F2MC-16FX
Family MCU ...................................6Memory Access
Direct Memory Access (DMA) ....................47Memory Space
CPU Memory Space....................................10Memory Space Divided into Banks and Values in
Each Register Bank ........................14Multi-byte Data Layout in a Memory
Space ............................................15Mode
Bank Addressing Mode ...............................12Linear Addressing Mode..............................11
MOVMOV Ri, ea Instruction Map
(First Byte = 7AH)........................360Multi-byte Data
Access to Multi-byte Data............................16Multi-byte Data Layout in a Memory
Space ............................................15Multiple
Multiple Hardware Interrupts .......................63Multiple Software Interrupts ........................63
N
NNEG (Negate Byte Data of Destination) ......235NEGW (Negate Word Data of
Destination).................................236NOP (No Operation) .................................237NOT (Not Byte Data of Destination)...........238NOTW (Not Word Data of Destination) ......240NRML (NORMALIZE Long Word) ...........241
NCCFlag Change Inhibit Prefix Code (NCC) ........41
NMINMI Control Status Register (NMI)..............53
Non Maskable InterruptHardware Exceptions (Non Maskable
Interrupts) .....................................67
O
OOR (Or Byte Data of Destination and Source to
Destination).................................242OR (Or Byte Data of Immediate Data and
Condition Code Register to ConditionCode Register) .............................244
ORL (Or Long Word Data of Destination andSource to Destination) ..................246
ORW (Or Word Data of AH and AL to AL) ...................................248
ORW (Or Word Data of Destination and Sourceto Destination) .............................249
Odd AddressOdd Address Correction.............................. 82
Op-CodeSoftware Exceptions (Op-Code) .................. 66
P
PPOPW (Pop Registers from Stack
Memory) .................................... 256POPW (Pop Word Data of Accumulator from
Stack Memory) ........................... 251POPW (Pop Word Data of AH from Stack
Memory) .................................... 253POPW (Pop Word Data of Program Status from
Stack Memory) ........................... 254PUSHW (Push Registers to Stack
Memory) .................................... 260PUSHW (Push Word Data of Inherent Register
to Stack Memory)........................ 258PC
Program Counter (PC) ................................ 29Prefix
Bank Select Prefix ...................................... 38Common Register Bank Prefix (CMR) ......... 40Flag Change Inhibit Prefix Code (NCC) ....... 41If Two or More Prefix Codes Appear in
Succession .................................... 43Relationships between Instructions Rejecting
Interrupt Requests and Prefix Codes ........................................... 42
PriorityInterrupt Acceptance Priority....................... 64
Processor StatusProcessor Status (PS) .................................. 24
Program CounterProgram Counter (PC) ................................ 29
PSProcessor Status (PS) .................................. 24
R
RRET (Return from Subroutine) .................. 262RETI (Return from Interrupt) .................... 263RETP (Return from Physical Address) ....... 265ROLC (Rotate Byte Data of Accumulator with
Carry to Left) .............................. 267RORC (Rotate Byte Data of Accumulator with
Carry to Right) ............................ 269RAM
Calling General-purpose Registers in RAM............................................ 36
Register Banks in RAM .............................. 34Register
Bank Register ............................................ 31Register Bank
INDEX
376 FUJITSU MICROELECTRONICS LIMITED CM44-00203-3E
Memory Space Divided into Banks and Values inEach Register Bank ........................14
Register Bank PointerRegister Bank Pointer (RP) ..........................26
Register BanksRegister Banks in RAM ...............................34
RPRegister Bank Pointer (RP) ..........................26
S
SSBBS (Set Bit and Branch if Bit Set) ..........271SCEQ, SCEQI (Scan String Byte until equal with
Increment) ...................................272SCEQD (Scan String Byte until equal with
Decrement)..................................274SCWEQ, SCWEQI (Scan String Word until
equal with Increment)...................276SCWEQD (Scan String Word until Equal with
Decrement)..................................278SETB (Set Bit)..........................................280SUB (Subtract Byte Data of Source from
Destination to Destination)............281SUBC (Subtract Byte Data of AL from AH with
Carry to AL) ................................283SUBC (Subtract Byte Data of Effective Address
from Accumulator with Carry to Accumulator)...............................284
SUBCW (Subtract Word Data of Effective Address from Accumulator with Carryto Accumulator) ...........................286
SUBDC (Subtract Decimal Data of AL from AHwith Carry to AL) ........................288
SUBL (Subtract Long Word Data of Source fromDestination to Destination)............289
SUBW (Subtract Word Data of AL from AH toAL).............................................293
SUBW (Subtract Word Data of Source fromDestination to Destination)............291
SWAP (Swap Byte Data of Accumulator)...............................294
SWAPW (Swap Word Data of Accumulator)...............................295
SoftwareMultiple Software Interrupts ........................63Software Exceptions (Op-Code) ...................66Software Interrupt Operation ........................62Software Interrupts................................47, 61Structure of the Software Interrupt
System ..........................................61SSP
User Stack Pointer (USP) and System StackPointer (SSP) .................................22
SymbolExplanation of the Symbols Used in the
Instruction Lists ...........................317
Symbols (Abbreviations) Used in Detailed Instructions ................................... 81
System Stack PointerUser Stack Pointer (USP) and System Stack
Pointer (SSP) ................................ 22
U
UUNLINK (Unlink and Create New Stack
Frame) ....................................... 296User Stack Pointer
User Stack Pointer (USP) and System StackPointer (SSP) ................................ 22
USPUser Stack Pointer (USP) and System Stack
Pointer (SSP) ................................ 22
V
VectorInterrupt Vector.......................................... 48
W
WWBTc (Wait until Bit Condition
Satisfied) .................................... 297
X
XXCH (Exchange Byte Data of Source to
Destination) ................................ 299XCHW (Exchange Word Data of Source to
Destination) ................................ 301XOR (Exclusive Or Byte Data of Destination and
Source to Destination) ................. 303XORL (Exclusive Or Long Word Data of
Destination and Source to Destination) ................................ 305
XORW (Exclusive Or Word Data of AH and ALto AL) ........................................ 307
XORW (Exclusive Or Word Data of Destinationand Source to Destination) ........... 308
Z
ZZEXT (Zero Extend from Byte Data to Word
Data) .......................................... 310ZEXTW (Zero Extend from Word Data to Long
Word Data)................................. 311
CM44-00203-3E
FUJITSU MICROELECTRONICS • CONTROLLER MANUAL
F2MC-16FX
16-BIT MICROCONTROLLER
PROGRAMMING MANUAL
March 2010 the third edition
Published FUJITSU MICROELECTRONICS LIMITEDEdited Sales Promotion Dept.