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MN704-00006-2v0-EFUJITSU SEMICONDUCTOR CONTROLLER MANUAL

FUJITSU SEMICONDUCTOR CONFIDENTIAL

F2MC-16FX 16-BIT MICROCONTROLLER

MB96610/620 series HARDWARE MANUAL

FUJITSU SEMICONDUCTOR LIMITED


F2MC-16FX 16-BIT MICROCONTROLLER

MB96610/620 series HARDWARE MANUAL

For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development.

http://edevice.fujitsu.com/micom/en-support/



FUJITSU SEMICONDUCTOR CONFIDENTIAL i

Preface

Objectives and intended reader Thank you very much for your continued patronage of Fujitsu semiconductor products.

The MB96600 Super series has been developed as a general-purpose version of the F2MC-16FX series, which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC (ASIC).

This manual explains the functions and operation of the MB96600 Super series for designers who actually use the MB96600 Super series to design products. Please read this manual first and refer to the respective "Data Sheet" of devices for device-specific details..

Trademark F2MC is the abbreviation of FUJITSU Flexible Microcontroller. Other system and product names in this manual are trademarks of respective companies or organizations. The symbols ™ and ® are sometimes omitted in this manual.

MN704-00006-2v0-E (1)

MB96610/620 Series



The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented

solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Copyright ©2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved.

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MB96610/620 Series


FUJITSU SEMICONDUCTOR CONFIDENTIAL iii

Related Manuals The manuals related to this series are listed below. See the manual appropriate to the applicable conditions. The contents of these manuals are subject to change without notice. Contact us to check the latest versions available.

Hardware Manual F2MC-16FX FAMILY MB96610/620 SERIES HARDWARE MANUAL (this manual)

Data sheet For details about device-specific, Pin Assignments, electrical characteristics, package dimensions, ordering information etc., see the following document.

16-bit PROPRIETARY MICROCONTROLLER F2MC-16FX FAMILY DATA SHEET * The data sheets for each series are provided.

Please see the appropriate data sheet for the series that you are using.

CPU Programming manual For details about the functions and operations of 16FX-CPU, see the following document.

F2MC-16FX 16-BIT MICROCONTROLLER PROGRAMMING MANUAL

MN704-00006-2v0-E (3)

MB96610/620 Series



How to Use This Manual

Finding a Function The following methods can be used to search for the explanation of a desired function in this manual:

Search from the table of the contents The table of the contents lists the manual contents in the order of description.

Search from the register The address where each register is located is not described in the text. To verify the address of a

register, see "I/O Map" in Appendixes.

Terminology This manual uses the following terminology.

Term Explanation

Word Indicates access in units of 32 bits.

Half word Indicates access in units of 16 bits.

Byte Indicates access in units of 8 bits.

Notations The notations in bit configuration of the register explanation of this manual are written as follows. bit : bit number Attribute : Attributes for read and write of each bit R : Read only W : Write only R/W : Readable/Writable - : Undefined

Initial value : Initial value of the register after reset 0 : Initial value is "0" 1 : Initial value is "1" X : Initial value is undefined

The multiple bits are written as follows in this manual.

Example : bit7:0 indicates the bits from bit7 to bit0 The values such as for addresses are written as follows in this manual. Hexadecimal number : "0x" is attached in the beginning of a value as a prefix (example : 0xFFFF) Binary number : "0b" is attached in the beginning of a value as a prefix (example: 0b1111) Decimal number : Written using numbers only (example : 1000)

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FUJITSU SEMICONDUCTOR CONFIDENTIAL 1

CONTENTS

CHAPTER 1: OVERVIEW......................................................................................................1 1. Features ............................................................................................................................2 2. Super Series Lineup..........................................................................................................4 3. Block Diagram of MB96F610/F620 ...................................................................................5 4. General Note on Using This Document .............................................................................7 5. 16-bit I/O-Timer Configuration ...........................................................................................8 6. Input Capture Unit Source Select for LIN-USART .............................................................9 7. Peripheral Resource Pin Relocation................................................................................15

CHAPTER 2: CPU................................................................................................................25 1. Overview .........................................................................................................................26 2. Hardware Structure .........................................................................................................27 3. Memory Space ................................................................................................................31

3.1. Memory Areas ...............................................................................................................32 3.2. Linear Addressing Method ............................................................................................35 3.3. Bank Addressing Method ..............................................................................................36 3.4. Multi-byte Data in Memory Space .................................................................................39

4. Special Registers.............................................................................................................40 4.1. Accumulator (A).............................................................................................................42 4.2. User Stack Pointer (USP) and System Stack Pointer (SSP) ........................................44 4.3. Processor Status (PS)...................................................................................................45 4.4. Program Counter (PC) ..................................................................................................49 4.5. Direct Page Register (DPR)..........................................................................................50 4.6. Bank Register (PCB, DTB, ADB, USB, SSB) ...............................................................51

5. General-Purpose Registers .............................................................................................52 5.1. Register Bank................................................................................................................53 5.2. Addressing General-Purpose Registers .......................................................................54

6. Prefix Codes....................................................................................................................55 6.1. Bank Selection Prefix ....................................................................................................56 6.2. Common Register Bank Prefix (CMR)..........................................................................58 6.3. Flag Change Inhibit Prefix (NCC) .................................................................................59 6.4. Prefix Code Restrictions ...............................................................................................60

CHAPTER 3: INTERRUPTS ................................................................................................63 1. Overview .........................................................................................................................64 2. Interrupt Flow ..................................................................................................................66 3. Hardware Interrupts.........................................................................................................68 4. Software Interrupts ..........................................................................................................71 5. Multiple Interrupts ............................................................................................................73 6. Exceptions.......................................................................................................................76 7. Interrupt Vector................................................................................................................83 8. Interrupt Control Registers (ICR).....................................................................................86 9. Non Maskable Interrupt (NMI) .........................................................................................88

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CHAPTER 4: DMA ...............................................................................................................91 1. Overview .........................................................................................................................92 2. Operation.........................................................................................................................94 3. Descriptor ........................................................................................................................96

3.1. DMA Register List .........................................................................................................98 3.2. DMA I/O Address Pointer Bank Select (IOABK) ...........................................................99 3.3. Data Count Register (DCT).........................................................................................100 3.4. I/O Register Address Pointer (IOA).............................................................................101 3.5. DMA Control Register (DMACS).................................................................................102 3.6. Buffer Address Pointer (BAP) .....................................................................................104

4. Registers .......................................................................................................................105 4.1. DMA Interrupt Request Select Register (DISEL) ........................................................106 4.2. DMA Status Register (DSR)........................................................................................107 4.3. DMA Stop Status Register (DSSR) .............................................................................108 4.4. DMA Enable Register (DER).......................................................................................109

5. Examples of DMA Transfers ..........................................................................................110

CHAPTER 5: DELAYED INTERRUPT ...............................................................................113 1. Overview .......................................................................................................................114 2. Operation.......................................................................................................................115 3. Register .........................................................................................................................116

3.1. Delayed Interrupt Cause Issuance/ Cancellation Register (DIRR: Delayed Interrupt Request Register)........................ 117

CHAPTER 6: CLOCKS ......................................................................................................119 1. Overview .......................................................................................................................120 2. Clock Modes..................................................................................................................122 3. Configuration of the PLL................................................................................................124 4. Oscillation Stabilization Wait Time .................................................................................126 5. Connection of an Oscillator or an External Clock to the Microcontroller ........................128 6. Registers .......................................................................................................................130

6.1. Clock Selection Register (CKSR) ...............................................................................131 6.2. Clock Monitor Register (CKMR)..................................................................................135 6.3. Clock Stabilization Select Register (CKSSR) .............................................................138 6.4. Clock Frequency Control Register (CKFCR) ..............................................................141 6.5. PLL Control Register (PLLCR)....................................................................................144

CHAPTER 7: RESETS AND STARTUP.............................................................................147 1. Overview .......................................................................................................................148 2. Reset, System Clock and Stabilization Wait Times........................................................150 3. Startup after Power and External Reset ........................................................................152 4. Boot ROM Program Execution and Operation Mode and ROM Configuration Block ....155 5. Operation of the Clock Stop Detection Function and Reset ..........................................161 6. Operation of the Low Voltage Reset and Interrupt Function ..........................................164 7. Registers .......................................................................................................................166

7.1. Reset Configuration Register (RCR)...........................................................................167 7.2. Reset Cause and Clock Status Register (RCCSR/RCCSRC)....................................169 7.3. Clock Input and LVD Control Register (CILCR)..........................................................173

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CHAPTER 8: STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT......177 1. Overview .......................................................................................................................178 2. Usage Notes on Standby Mode.....................................................................................182 3. Using the Extended Standby Mode Control Register ....................................................184 4. Voltage Regulator Operation .........................................................................................187

4.1. Changing the Voltage Regulator operation mode.......................................................188 4.2. Setting the Voltage Regulator Output Voltage ............................................................190

5. Standby Modes..............................................................................................................191 5.1. Sleep mode (RC Sleep, Main Sleep, PLL Sleep, Sub Sleep Mode)...........................193 5.2. Timer Mode (RC Timer, Main Timer, PLL Timer, Sub Timer mode) ............................196 5.3. Stop Mode ...................................................................................................................199

6. Mode Change Table and Operation Status....................................................................202 7. Registers .......................................................................................................................204

7.1. Standby Mode Control Register (SMCR)....................................................................205 7.2. Extended Standby Mode Control Register (ESMCR) .................................................207 7.3. Voltage Regulator Control Register (VRCR)...............................................................209

CHAPTER 9: SOURCE CLOCK TIMERS..........................................................................211 1. Overview .......................................................................................................................212 2. RC Clock Timer .............................................................................................................213

2.1. Operations...................................................................................................................214 2.2. RC Clock Timer Control Register (RCTCR)................................................................215

3. Main Clock Timer...........................................................................................................217 3.1. Operations...................................................................................................................218 3.2. Main Clock Timer Control Register (MCTCR).............................................................219

4. Sub Clock Timer ............................................................................................................221 4.1. Operations...................................................................................................................222 4.2. Sub Clock Timer Control Register (SCTCR)...............................................................223

CHAPTER 10: WATCHDOG TIMER AND WATCHDOG RESET.......................................225 1. Overview .......................................................................................................................226 2. Operation.......................................................................................................................227 3. Registers .......................................................................................................................233

3.1. Watchdog Timer Configuration Register (WDTC).......................................................234 3.2. Watchdog Timer Extended Configuration Register (WDTEC) ....................................238 3.3. Watchdog Timer Clear Pattern Register (WDTCP).....................................................241

CHAPTER 11: I/O PORTS .................................................................................................243 1. Overview .......................................................................................................................244 2. Registers .......................................................................................................................245

2.1. Port Data Register (PDRnn) .......................................................................................246 2.2. External Pin State Register (EPSRnn)........................................................................248 2.3. Data Direction Register (DDRnn)................................................................................249 2.4. Port Input Enable Register (PIERnn) ..........................................................................250 2.5. Port High Drive Register (PHDRnn)............................................................................251 2.6. Pull-Up Control Register (PUCRnn)............................................................................252 2.7. Pull-Down Control Register (PDCRnn).......................................................................253

3. Register Usage..............................................................................................................254

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CHAPTER 12: 16-BIT I/O TIMER.......................................................................................255 1. Overview .......................................................................................................................256 2. 16-bit I/O Timer Registers..............................................................................................258 3. 16-bit Free-Running Timer.............................................................................................260

3.1. Operation ....................................................................................................................261 3.2. Data Register (TCDTn) ...............................................................................................263 3.3. Control Status Register (TCCSLn)..............................................................................264

4. Output Compare Unit.....................................................................................................267 4.1. Operation ....................................................................................................................268 4.2. Output Compare Register (OCCP(2n) / OCCP(2n+1))...............................................273 4.3. Control Status Registers of Output Compare (OCS(2n) / OCS(2n+1)) ......................274

5. Input Capture Unit .........................................................................................................280 5.1. Operation ....................................................................................................................281 5.2. Input Capture Data Register (IPCPn) .........................................................................282

CHAPTER 13: 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)..................287 1. Overview .......................................................................................................................288 2. Internal Clock and External Event Counter Operations .................................................290 3. Underflow Operation .....................................................................................................292 4. Output Pin Functions.....................................................................................................293 5. Counter Operation State................................................................................................294 6. TIN Latch Function ........................................................................................................295 7. 16-Bit Reload Timer (With Event Count Function).........................................................296

7.1. Timer Control Status Register (TMCSRn)...................................................................297 7.2. Register Layout of 16-bit Timer Register (TMRn)/

16-bit Reload Register (TMRLRn) ...........................................................................300 8. Cascading .....................................................................................................................301

8.1. Reload Timer Input Select Register (TMISR) .............................................................302

CHAPTER 14: PROGRAMMABLE PULSE GENERATOR ................................................305 1. Overview .......................................................................................................................306 2. Operation.......................................................................................................................310 3. Registers .......................................................................................................................317

3.1. PPG Control Status Register (PCNn) .........................................................................318 3.2. Extended PPG Control Status Register 1 (EPCN1n)..................................................322 3.3. Extended PPG Control Status Register 2 (EPCN2n)..................................................327 3.4. General Control Register 1 (GCN1g)..........................................................................330 3.5. General Control Register 2 (GCN2g)..........................................................................331 3.6. General Control Register 3 (GCN3g)..........................................................................332 3.7. General Control Register 4 (GCN4g)..........................................................................333 3.8. General Control Register 5 (GCN5g)..........................................................................334 3.9. PPG Cycle Setting Register (PCSRn) ........................................................................335 3.10. PPG Duty Setting Register (PDUTn) ........................................................................336 3.11. PPG Timer Register (PTMRn)...................................................................................337 3.12. PPG Start Delay Register (PSDRn) ..........................................................................338 3.13. PPG Timing Point Capture Register (PTPCn) ..........................................................339 3.14. PPG End Duty Register (PEDRn).............................................................................340 3.15. General Control Register (GCNR) ............................................................................341

4. Cautions ........................................................................................................................342 MN704-00006-2v0-E (8)

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CHAPTER 15: Quadrature Position/Revolution Counter ...................................................343 1. Overview .......................................................................................................................344 2. Configuration .................................................................................................................345 3. Operations.....................................................................................................................346 4. Registers .......................................................................................................................359

4.1. Quadrature Position/Revolution Counter Position Count Register (QPCR) ...............360 4.2. QPRC Revolution Count Register (QRCR) ................................................................362 4.3. QPRC Position Counter Compare Register (QPCCR) ...............................................363 4.4. QPRC Position and Revolution Counter Compare Register (QPRCR) ......................364 4.5. QPRC Control Register (QCR) ...................................................................................365 4.6. QPRC Extension Control Register (QECR)................................................................370 4.7. Low-Order Bytes of QPRC Interrupt Control Register (QICRL) .................................372 4.8. High-Order Bytes of QPRC Interrupt Control Register (QICRH) ................................376 4.9. QPRC Maximum Position Register(QMPR) ...............................................................380

CHAPTER 16: EXTERNAL INTERRUPTS ........................................................................381 1. Overview .......................................................................................................................382 2. Registers .......................................................................................................................383

2.1. Interrupt Enable Register (ENIRn: External Interrupt Request Enable Register) .......384 2.2. Interrupt Flags (EIRRn: External Interrupt Request Register) ....................................385 2.3. Request Level Setting Register (ELVRn: External Interrupt Level Register)..............386

3. Notes on Using the External Interrupt Functions ...........................................................387

CHAPTER 17: A/D Converter.............................................................................................389 1. Overview .......................................................................................................................390 2. Operation.......................................................................................................................392 3. Conversion Data Protection Function ............................................................................393 4. Data Buffer Function......................................................................................................396 5. Range Comparator Function .........................................................................................405 6. Scan Disable Function...................................................................................................407 7. ADC Pulse Detection Function ......................................................................................409 8. Registers .......................................................................................................................412

8.1. A/D Control Status Register (ADCS)...........................................................................413 8.2. A/D Data Register (ADCR)..........................................................................................419 8.3. A/D Setting Register (ADSR) ......................................................................................421 8.4. A/D Data Buffer Control Register (ADDBCR) .............................................................424 8.5. A/D Data Buffer Registers (ADCBR0-7)......................................................................428 8.6. Upper Threshold Registers for Range Comparator (ADRCOH0-3)............................430 8.7. Lower Threshold Registers for Range Comparator (ADRCOL0-3) ............................431 8.8. Channel Control Registers for Range Comparator (ADCC0-15)................................432 8.9. Inverted Range Selection Registers for Range Comparator (ADRCOIRS0-3)...........434 8.10. Range Comparator Over Threshold Flag Registers (ADRCOOF0-3).......................436 8.11. Range Comparator Flag Registers (ADRCOINTF0-3)..............................................438 8.12. Disable Channel for Scan Register (ADDSCR0-3)...................................................440 8.13. ADC Pulse Counter Reload Registers (ADPCTNRD0-31/ADPCTPRD0-31) ...........442 8.14. ADC Pulse Counter Registers (ADPCTNCT0-31/ADPCTPCT0-31) ........................444 8.15. ADC Pulse Counter Interrupt Enable Registers (ADPCIE0-3)..................................446 8.16. ADC Pulse Counter Zero Flag Registers (ADPCZF0-3) ...........................................448 8.17. Analog Input Enable Register (ADERx) ....................................................................450

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CHAPTER 18: A/D CONVERTER TRIGGER.....................................................................451 1. Overview .......................................................................................................................452 2. Operation.......................................................................................................................454 3. Registers .......................................................................................................................455

3.1. ADC Trigger Control Register (ADTGCRn).................................................................456 3.2. ADC Trigger Input Select (ADTGISELn) .....................................................................457

CHAPTER 19: USART .......................................................................................................459 1. Overview .......................................................................................................................460 2. Configuration .................................................................................................................463 3. Pins ...............................................................................................................................469 4. Operation.......................................................................................................................470

4.1. Operation in Asynchronous Mode (Op. Modes 0 and 1).............................................472 4.2. Operation in Synchronous Mode (Operation Mode 2) ................................................474 4.3. Features of USART in LIN Mode ................................................................................477 4.4. Operation with LIN Function (Operation Mode 3) .......................................................481 4.5. Direct Access to Serial Pins ........................................................................................486 4.6. Bidirectional Communication Function (Normal Mode) ..............................................487 4.7. Master-Slave Communication Function (Multiprocessor Mode).................................490 4.8. LIN Communication Function......................................................................................494 4.9. Sample Flowcharts for USART in LIN Communication (Operation Mode 3) ..............496

5. Interrupts .......................................................................................................................502 5.1. Reception Interrupt Generation and Flag Set Timing .................................................507 5.2. Transmission Interrupt Generation and Flag Set Timing ............................................510

6. Baud Rates....................................................................................................................512 6.1. Setting the Baud Rate.................................................................................................514 6.2. Restarting the Reload Counter ...................................................................................517 6.3. Automatic Baud Rate Detection and Adjustment ........................................................518

7. Registers .......................................................................................................................519 7.1. Serial Control Register (SCRn)...................................................................................520 7.2. Serial Mode Register (SMRn) ...................................................................................523 7.3. Serial Status Register (SSRn).....................................................................................526 7.4. Reception and Transmission Data Register (RDRn/TDRn)........................................529 7.5. Extended Status/Control Register (ESCRn) ...............................................................532 7.6. Extended Communication Control Register (ECCRn) ................................................535 7.7. Baud Rate Generation / Reload Counter Register (BGRn) ........................................538 7.8. Extended Serial Interrupt Register (ESIRn)................................................................539 7.9. Transmission FIFO Control Register (TFCRn) ...........................................................541 7.10. Reception FIFO Control Register (RFCRn) ..............................................................543 7.11. Transmission FIFO Status Register (TFSRn)............................................................545 7.12. Reception FIFO Status Register (RFSRn)................................................................547 7.13. Sync Field Time-out Register (SFTRn).....................................................................549 7.14. Checksum Status and Control Register (CSCRn) ....................................................550 7.15. Frame-ID Data Register (FIDRn) ..............................................................................553 7.16. Extended Feature Enable Register (EFERLn)..........................................................554 7.17. Extended Feature Enable Register (EFERHn) .........................................................556 7.18. Extended Interrupt Enable Register (EIERn)............................................................559 7.19. Extended Status Register (ESRn).............................................................................561

8. Notes on Using..............................................................................................................564

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CHAPTER 20: 400 kHz I2C INTERFACE...........................................................................571 1. Overview .......................................................................................................................572 2. Operation.......................................................................................................................574 3. Programming Flow Charts.............................................................................................576 4. Registers .......................................................................................................................578

4.1. Bus Status Register (IBSRn).......................................................................................579 4.2. Bus Control Register (IBCRn).....................................................................................582 4.3. Ten Bit Slave Address Register (ITBAn) .....................................................................588 4.4. Ten Bit Slave Address Mask Register (ITMKn)...........................................................589 4.5. Seven Bit Slave Address Register (ISBAn) ................................................................591 4.6. Seven Bit Slave Address Mask Register (ISMKn) ......................................................592 4.7. Data Register (IDARn) ................................................................................................593 4.8. Clock Control Register (ICCRn)..................................................................................594

CHAPTER 21: CAN CONTROLLER ..................................................................................597 1. Overview .......................................................................................................................598 2. Functional Description...................................................................................................599 3. CAN Application ............................................................................................................603 4. Register Description ......................................................................................................611 5. CAN Device Related Registers .....................................................................................615

5.1. CAN Output Enable Register (COERn) ......................................................................616 6. CAN Protocol Related Registers ...................................................................................617

6.1. CAN Control Register (CTRLRn) ................................................................................618 6.2. Status Register (STATRn) ...........................................................................................621 6.3. Error Counter (ERRCNTn)..........................................................................................624 6.4. Bit Timing Register (BTRn) .........................................................................................625 6.5. Test Register (TESTRn) ..............................................................................................627 6.6. BRP Extension Register (BRPERn)............................................................................629

7. Message Interface Register Sets ..................................................................................630 7.1. IFx Command Request Registers (IFxCREQn)..........................................................632 7.2. IFx Command Mask Register (IFxCMSKn) ................................................................634 7.3. IFx Mask Registers (IFxMSK1n, IFxMSK2n) ..............................................................637 7.4. IFx Arbitration Registers (IFxARB1n, IFxARB2n) .......................................................638 7.5. IFx Message Control Register (IFxMCTRn) ...............................................................639 7.6. IFx Data A and Data B Registers (IFxDTA1n, IFxDTA2n, IFxDTB1n, IFxDTB2n) ......640

8. Message Object in the Message Memory .....................................................................641 9. Message Handler Registers ..........................................................................................646

9.1. Interrupt Register (INTRn) ..........................................................................................647 9.2. Transmission Request Registers (TREQR1n, TREQR2n) .........................................649 9.3. New Data Registers (NEWDT1n, NEWDT2n) ............................................................651 9.4. Interrupt Pending Registers (INTPND1n, INTPND2n)................................................653 9.5. Message Valid Registers (MSGVAL1n, MSGVAL2n) .................................................655

CHAPTER 22: CLOCK OUTPUT FUNCTION....................................................................657 1. Overview .......................................................................................................................658 2. Operation.......................................................................................................................659 3. Configuration and Activation Registers..........................................................................660

3.1. Clock Output Configuration Register (COCR) ............................................................661 3.2. Clock Output Activation Register (COAR) ..................................................................663

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CHAPTER 23: REAL TIME CLOCK ...................................................................................667 1. Overview .......................................................................................................................668 2. Operation.......................................................................................................................670 3. Registers .......................................................................................................................672

3.1. Timer Control Register (WTCR)..................................................................................673 3.2. Timer Control Extended Register (WTCER) ...............................................................677 3.3. Clock Select Register (WTCKSR)...............................................................................678 3.4. Sub-Second Register (WTBR)....................................................................................679 3.5. Second/Minute/Hour Registers (WTSR, WTMR, WTHR)...........................................680

4. Cautions ........................................................................................................................682

CHAPTER 24: CLOCK CALIBRATION UNIT.....................................................................683 1. Overview .......................................................................................................................684 2. Registers Description ....................................................................................................687

2.1. Clock Calibration Unit Control Register (CUCR) ........................................................688 2.2. Clock Calibration Unit Duration Timer Data Register (CUTD) ....................................690 2.3. Clock Calibration Unit Calibration Timer Data Register (24-bit) (CUTR) ....................692

3. Application Notes...........................................................................................................693

CHAPTER 25: ROM/RAM MIRRORING MODULE ...........................................................695 1. Overview .......................................................................................................................696 2. Registers .......................................................................................................................697

2.1. ROM Mirroring Register (ROMM) ...............................................................................698

CHAPTER 26: DUAL OPERATION FLASH MEMORY ......................................................701 1. Overview .......................................................................................................................702 2. Block Diagram and Sector Configuration.......................................................................704 3. Modes............................................................................................................................706 4. Starting the Flash Memory Automatic Algorithm ............................................................707 5. Confirming the Automatic Algorithm Execution State.....................................................709

5.1. Data Polling Flag (DQ[15,7]) .......................................................................................712 5.2. Toggle Bit Flag (DQ[14,6])...........................................................................................713 5.3. Timing Limit Exceeded Flag (DQ[13,5]) ......................................................................714 5.4. Sector Erase Timer Flag (DQ[11,3])............................................................................715 5.5. Toggle Bit-2 Flag (DQ[10,2]) .......................................................................................716

6. Detailed Explanation of Writing to and Erasing Flash Memory......................................717 6.1. Setting The Read/Reset State ....................................................................................718 6.2. Writing Data by Submitting the Write Command Sequence .......................................719 6.3. Writing the Data by using the Write Command Sequencer ........................................721 6.4. Erasing All Data (Chip Erase) .....................................................................................723 6.5. Erasing Optional Data (Sector erase) .........................................................................724 6.6. Suspending Sector Erase ...........................................................................................726 6.7. Restarting Sector Erase..............................................................................................727 6.8. Protecting Sectors from being Erased/Written to........................................................728

7. Registers .......................................................................................................................730 7.1. Dual operation Flash Configuration Register (DFCA, DFCB).....................................731 7.2. Dual Operation Flash Interrupt Control Register (DFICA, DFICB) .............................733 7.3. Dual Operation Flash Status Register (DFSA, DFSB)................................................736 7.4. Dual Operation Flash Interrupt Status Register (DFISA, DFISB) ...............................739

MN704-00006-2v0-E (12)

MB96610/620 Series



7.5. Dual Operation Flash Write Access Control Register 0-1 (DFWC0A, DFWC0B, DFWC1A, DFWC1B) ...........................................................742

8. Notes on using ..............................................................................................................744 9. Programming example ..................................................................................................745

CHAPTER 27: FLASH SECURITY ....................................................................................755 1. Overview .......................................................................................................................756 2. Usage............................................................................................................................757

CHAPTER 28: EXAMPLES OF SERIAL PROGRAMMING CONNECTION ......................761 1. Basic Configuration of Serial Programming Connection................................................762 2. Example of connecting a PC for programming the Flash Microcontroller ......................765 3. Example of connecting a programming tool

for programming the Flash Microcontroller.................................................................766

CHAPTER 29: ON CHIP DEBUGGER (OCD) ...................................................................767 1. Features ........................................................................................................................768 2. Configuration .................................................................................................................769 3. Guideline to Design DEBUG I/F on Target Board..........................................................771

APPENDIX ..................................................................................................................773 A. I/O Map of MB96610.....................................................................................................774 B. I/O Map of MB96620.....................................................................................................793

MN704-00006-2v0-E (13)

MB96610/620 Series



MN704-00006-2v0-E (14)

MB96610/620 Series

MAIN CHANGES IN THIS EDITION This history table is for MB96610/620 Series Hardware Manual Rev. 2 (MN704-00006-2v0-E) from MB96620 Series Hardware Manual Preliminary Rev. 1 (MN704-00006-0v01-E). MB96610 Series of MB96610/620 Series Hardware Manual Rev. 2 (MN704-00006-2v0-E) is the first edition.

A change on a page is indicated by a vertical line drawn on the left of that page. Page Section Change Results

13 CHAPTER 1: OVERVIEW ■Input Capture Unit Source Select ・Input Capture Edge Register ICE89

Changed description of IEI9; ｢USART1 is input source｣→｢Rising edge detected｣

793

APPENDIX B. I/O Map of MB96620

Changed ADECR to Reserved register; ｢00001E H ADECR｣｢00001F H Reserved｣ →｢00001E H - 00001F H Reserved｣ Added Reserved; 「00002E H - 000033 H Reserved｣

797

Changed Reserved register; ｢000396 H - 000399 H Reserved｣ →｢000396 H - 00039F H Reserved｣ Changed EDSU to Reserved register; ｢0003A6 H - 0003ABH Reserved｣｢0003AC H EDSU2L｣｢0003AD H EDSU2H｣ →｢0003A6 H - 0003AD H Reserved｣ Changed EDSU to Reserved register; ｢0003AF H EDSU｣｢0003B0 H - 0003E7 H Reserved｣ →｢0003AF H -0003E7 H Reserved｣

799

Changed ADER2 to Reserved register; ｢0004D2 H ADER2｣ →｢0004D2 H Reserved｣ Changed PRRR2-4 to Reserved register; ｢0004D8 H PRRR2｣｢0004D9 H PRRR3｣｢0004DA H PRRR4｣ →｢0004D8 H -0004DA H Reserved｣

800

Changed range of Reserved register; ｢0004FB H -0005DF H Reserved｣ →｢000508 H -000513 H Reserved｣ Changed IPCPL8,IPCPH8 to Reserved register; ｢000516 H IPCPL8｣｢000517 H IPCPH8｣ →｢000516 H - 000517 H Reserved｣ Changed IPCPL11,IPCPH11 to Reserved register; ｢00051E H IPCPL11｣｢00051F H IPCPH11｣｢000520 H -00053D H Reserved｣ →｢00051E H - 00053D H Reserved｣

(15)

Page Section Change Results

802

APPENDIX B. I/O Map of MB96620

Changed range of Reserved register; ｢0005A4 H -0006AB H Reserved｣ →｢0005A4 H -0005AB H Reserved｣ Changed PRRR10-13 to Reserved register; ｢0005B4 H - 00065F H Reserved｣｢000660 H PRRR10｣｢000661 H PRRR11｣｢000662 H PRRR12｣｢000663 H PRRR13｣｢000664 H - 0008FF H Reserved｣ →｢0005B4 H - 0008FF H Reserved｣

806

Changed ADRCOOF20 to Reserved register; ｢000B56 H ADRCOOF20｣ →｢000B56 H Reserved｣ Changed ADRCOINTF20 to Reserved register; ｢000B5E H ADRCOINTF20｣ →｢000B5E H Reserved｣

809

Changed ADRCOIRS20 to Reserved register; ｢0E9542 H ADRCOIRS20｣ →｢0E9542 H Reserved｣ Changed ADCC080-110 to Reserved register; ｢0E9558 H ADCC080｣｢0E9559 H ADCC090｣｢0E955A H ADCC100｣｢0E955B H ADCC110｣ →｢0E9558 H -0E955B H Reserved」 Changed ADCC130 to Reserved register; ｢0E955D H ADCC130｣ →｢0E955D H Reserved｣

(16)

1. Features


CHAPTER: OVERVIEW FUJITSU SEMICONDUCTOR CONFIDENTIAL 1

CHAPTER: OVERVIEW The MB96600 Super series is a family member of the F2MC-16FX micro controllers. It consists of many different series of microcontrollers, which are targeting different applications. Programming between all members of the Super series is common.

1. Features 2. Super Series Lineup 3. Block Diagram of MB96F610/F620 4. General Note on Using This Document 5. 16-bit I/O-Timer Configuration 6. Input Capture Unit Source Select for LIN-USART 7. Peripheral Resource Pin Relocation

Management Code: 96F61F62OVERVIEW-E01.0

CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 1

MB96610/620 Series

1. Features



1. Features

The feature set of F2MC-16FX family’s MB96610/620 series makes it especially well suited for automotive applications.

Features of MB96610 16-bit core CPU, up to 32 MHz CPU clock, 31.2 ns instruction cycle time 0.18m CMOS Process Technology Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23

different addressing modes; barrel shift; variety of pointers) 8-byte instruction execution queue Signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) instructions available Internal voltage regulator supports reduced internal MCU voltage, offering low EMI and low power

consumption figures Code Security Feature Up to 1 FULL-CAN interfaces; conforming to Version 2.0 Part A and Part B, ISO16845 certified Powerful interrupt functions (8 progr. priority levels; up to 11 external interrupts) Fast Interrupt processing Up to 2 channels DMA - Automatic transfer function independent of CPU, can be assigned freely to

resources Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) Hardware Watchdog Timer Up to 3 channels full duplex USARTs (SCI/LIN) Up to 16 channels analog inputs for A/D Converter (Resolution 10-bit or 8-bit) Up to 2 channels16-bit reload timer, and 1 channel for PPG Up to 7 channels ICU (Input capture unit) 16-bit Up to 5 channels OCU (Output Compare unit) 16-bit Up to 4 channels 16-bit free running timer Up to 8 channels 16-bit (Up to 16 channels 8-bit) Programmable Pulse Generator Up to 2 channels QPRC (Quadrature position/revolution counter) Low Power Consumption - 13 operating modes (different Run, Sleep, Timer modes, Stop mode) 4 MHz to 8 MHz external clock (up to 16 MHz when using Fast Clock Input mode), on-chip PLL with

programmable multiplication factor 1 ... 8 32-100 kHz Subsystem Clock 100kHz/2MHz internal RC clock Programmable Pull-up resistors for all ports Package: 48-pin plastic LQFP Controller Area Network (CAN) - License of Robert Bosch GmbH On-Chip debug system

CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 2

MB96610/620 Series

1. Features



Features of MB96620 16-bit core CPU, up to 32 MHz CPU clock, 31.2 ns instruction cycle time 0.18m CMOS Process Technology Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23

different addressing modes; barrel shift; variety of pointers) 8-byte instruction execution queue Signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) instructions available Internal voltage regulator supports reduced internal MCU voltage, offering low EMI and low power

consumption figures Code Security Feature Up to 1 FULL-CAN interfaces; conforming to Version 2.0 Part A and Part B, ISO16845 certified Powerful interrupt functions (8 progr. priority levels; up to 13 external interrupts) Fast Interrupt processing Up to 2 channels DMA - Automatic transfer function independent of CPU, can be assigned freely to

resources Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) Hardware Watchdog Timer Up to 3 channels full duplex USARTs (SCI/LIN) Up to 1 channels I2C with 400 kbit/s Up to 21 channels analog inputs for A/D Converter (Resolution 10-bit or 8-bit) Up to 2 channels16-bit reload timer, and 1 channel for PPG Up to 8 channels ICU (Input capture unit) 16-bit Up to 6 channels OCU (Output Compare unit) 16-bit Up to 4 channels 16-bit free running timer Up to 8 channels 16-bit (Up to 16 channels 8-bit) Programmable Pulse Generator Up to 2 channels QPRC (Quadrature position/revolution counter) Low Power Consumption - 13 operating modes (different Run, Sleep, Timer modes, Stop mode) 4 MHz to 8 MHz external clock (up to 16 MHz when using Fast Clock Input mode), on-chip PLL with

programmable multiplication factor 1 ... 8 32-100 kHz Subsystem Clock 100kHz/2MHz internal RC clock Programmable Pull-up resistors for all ports Package: 64-pin plastic LQFP Controller Area Network (CAN) - License of Robert Bosch GmbH On-Chip debug system

CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 3

MB96610/620 Series

2. Super Series Lineup



2. Super Series Lineup

Table 2-1 provides an overview of the MB96600 Super series.

Super Series Lineup The F2MC-16FX MB96600 Super series covers the F2MC-16FX series as shown in Table 2-1.

Table 2-1 MB96600 Super Series Lineup

Series Flash Products

MB96610 MB96F61x

MB96620 MB96F62x

MB96630 MB96F63x

MB96640 MB96F64x

MB96650 MB96F65x

MB96660 MB96F66x

MB96670 MB96F67x

MB96680 MB96F68x

MB96690 MB96F69x

MB966A0 MB96F6Ax

MB966B0 MB96F6Bx

MB966C0 MB96F6Cx

CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 4

MB96610/620 Series

3. Block Diagram of MB96F610/F620




Figure 3-1 shows a principle block diagram of MB96F610/F620 series.

Block Diagram of MB96F610/F620 Figure 3-1 Block Diagram of MB96F610/F620

MB96F610

MD

InterruptController

DMA Controller

Per

iphe

ral B

us 1

(CLK

P1)

Per

iphe

ral B

us 2

(CLK

P2)

I/O Timer 3 FRT 3 ICU 10


I/O Timer 1 FRT 1

ICU 4/5/6 OCU 4/6/7

I/O Timer 0 FRT 0

ICU 0/1 OCU 0/1

16-bit Reload Timer

2 ch.

10-bit ADC

16 ch.

CAN Interface1 ch.

USART3 ch.

PPG 8 ch. (16-bit) /16 ch. (8-bit)

Real TimeClock

ExternalInterrupt11 ch.

QPRC2 ch.

VCCVSS

PPG0, PPG1, PPG3, PPG4,

AVCCAVSS

OUT0_R, OUT1_R IN0, IN1

C

PeripheralBus Bridge


16FX Core Bus (CLKB)

TIN1

TOT1, TOT3

AVRH

AN12, AN14, AN16 AN24, AN25 AN30, AN31

ADTG_R

AN6 to AN10

IN4, IN5 OUT6, OUT7

INT2_R, INT4_R INT7_R, INT10_R

PPG6, PPG7, PPG12, PPG14

Boot ROMWatchdog RAM VoltageRegulator

SIN2, SIN2_R, SIN7_R, SIN8_R SOT2, SOT2_R, SOT7_R, SOT8_RSCK2, SCK2_R, SCK7_R, SCK8_R

TX2

RX2

16FX CPU

Clock &Mode Controller

FlashMemory A

NMI

AIN0, AIN1

BIN0, BIN1ZIN0, ZIN1

TTG0, TTG1, TTG4, TTG5,

CKOT0_R, CKOT1, CKOT1_R CKOTX1

X0, X1 X0A, X1A

RSTX

RLT6 PPG0_B, PPG1_B, PPG3_B, PPG4_B,PPG6_B, PPG7_B, PPG12_B, PPG14_B

TTG12, TTG13

INT0, INT8 to INT13

INT3_R1

OCD

DEBUG I/F

AN0, AN1, AN3, AN4

CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 5

MB96610/620 Series




MB96F620

MD

InterruptController

DMA Controller

Per

iphe

ral B

us 1

(CLK

P1)

Per

iphe

ral B

us 2

(CLK

P2)

I2C

1 ch.



I/O Timer 1 FRT 1

ICU 4/5/6/7 OCU 4/5/6/7

I/O Timer 0 FRT 0

ICU 0/1 OCU 0/1

16-bit Reload Timer

2 ch.

10-bit ADC

21 ch.

CAN Interface1 ch.

USART3 ch.

PPG 8 ch. (16-bit) /16 ch. (8-bit)

Real TimeClock

External Interrupt13 ch.

QPRC2 ch.

VCCVSS

PPG0, PPG1, PPG3, PPG4,

AVCC

AN0 to AN14

AVSS

OUT0_R, OUT1_R IN0, IN1 FRCK0

C



16FX Core Bus (CLKB)

TIN1, TIN3

TOT1, TOT3

SDA0 SCL0

ADTG_R

NMI_R

PPG6, PPG7, PPG12, PPG14

Boot ROMWatchdog RAM VoltageRegulator

SIN2, SIN2_R, SIN7_R, SIN8_R SOT2, SOT2_R, SOT7_R, SOT8_RSCK2, SCK2_R, SCK7_R, SCK8_R

WOT

AVRH TX2

RX2

16FX CPU

Clock &Mode Controller

FlashMemory A

AIN0, AIN1

BIN0, BIN1ZIN0, ZIN1

TTG0, TTG1, TTG4, TTG5, TTG6,

CKOT0_R, CKOT1, CKOT1_R CKOTX1

X0, X1 X0A, X1A

RSTX

RLT6 PPG0_B, PPG1_B, PPG3_B, PPG4_B,PPG6_B, PPG7_B, PPG12_B, PPG14_B

TTG7, TTG12, TTG13, TTG14, TTG15

AN24, AN25 AN28 to AN31

FRCK1 IN4 to IN7

OUT4 to OUT7

INT8 to INT15

INT7_R, INT9_R to INT11_R INT0_R, INT2_R, INT4_R

INT3_R1

OCD

DEBUG I/F

CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 6

MB96610/620 Series

4. General Note on Using This Document



4. General Note on Using This Document

This chapter contains some general notes about this document.

Device Dependent Resources The derivatives of a Microcontroller series may have different sets of resources (e.g. features, number of channels, interconnections). Details about an individual device can be found in the following documents:

Number of resources and available channels: Datasheet of the series. Peculiarities of a resource in a derivative (e.g. interconnections between resources): "CHAPTER:

OVERVIEW" in the Hardware manual of the series.

Described Resources All chapters about resources of the Microcontroller like USART, Reload timers, General purpose ports describe the function of only one channel of this resource. The behavior of all other resources of the same type is the same. If there is an exception it is described in the "CHAPTER: OVERVIEW" or in the corresponding chapter of this Hardware manual. In the Hardware manual chapters the placeholder "n" is used for a resource channel number (e.g. in the register name). This placeholder needs to be replaced with the resource channel number of the resource to be used.

Example: Registers of Reload Timer 0 and Reload Timer 1

Register name as in the Chapter "Reload timer"

Register name define in Header file for Reload Timer 0

Register name define in Header file for Reload Timer 1

TMCSRHn TMCSRH0 TMCSRH1

TMCSRLn TMRL0 TMRL1

TMRHn TMRH0 TMRH1

TMRLn TMRL0 TMRL1

TMRLRHn TMRLRH0 TMRLRH1

TMRLRLn TMRLRL0 TMRLRL1

CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 7

MB96610/620 Series

5. 16-bit I/O-Timer Configuration



5. 16-bit I/O-Timer Configuration

The number of available Free Running timers, Input Capture Units and Output Compare Units differs between different devices. Multiple Input Capture Units and Output Compare Units are connected to one Free Running timer. This chapter describes the relation between these modules.

Connection between Input Capture Units and Free Running Timers Table 5-1 Connection between Input Capture Units and Free Running Timers

Input Capture Unit Free Running Timer

MB96610 MB96620

FRT 0 ICU 0/1 ICU 0/1

FRT 1 ICU 4/5/6 ICU 4/5/6/7

FRT 2 ICU 9 ICU 9

FRT 3 ICU 10 ICU 10

Connection between Output Compare Units and Free Running Timers Table 5-2 Connection between Output Compare Units and Free Running Timers

Output Compare Unit Free Running Timer

MB96610 MB96620

FRT 0 OCU 0/1 OCU 0/1

FRT 1 OCU 4/6/7 OCU 4/5/6/7

Relation between Timer Clear Function and OCU, Compare Clear and Free Running Timer

Table 5-3 Connection between OCU, Compare Clear and Free Running Timer for Timer Clear

Timer is cleared at match with following compare registerFree running timer

MB96610 MB96620

FRT 0 OCCP0 OCCP0

FRT 1 OCCP4 OCCP4

Compare function of OCCPx is enabled by OCS:CST[1:0] bits.

CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 8

MB96610/620 Series

6. Input Capture Unit Source Select for LIN-USART




The input source for the Input Capture units can be selected between an external pin (INn) and the LIN-USART Sync Field output. This chapter describes how to select the Input capture input and which LIN-USART can be connected to which ICU.

Overview of Connection between LIN-USART and ICU Table 6-1 Connection between LIN-USARTs and ICUs of MB96610/620

LIN-USART ICU Free running timer for ICU ICU source select bit

USART2 ICU6 FRT1 ICE67:ICUS6



Note: For availability of the required USART, Input capture unit and Free running timer channels please refer for the datasheet of your device.

CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 9

MB96610/620 Series




Input Capture Unit Source Select The source selection for ICU is done in the Input capture edge registers ICExy.

Input Capture Edge Register ICE01

ICE01 bit 15 14 13 12 11 10 9 8

- - - - - - IEI1 IEI0Attribute - - - R/W - R/W R/W R/W

Initial value X X X 0 X 0 0 0

[bit15 to bit10] -: Reserved Bit Read value is undefined, write always 0. Read modify write operations to this register have no effect on these bits.

[bit9] IEI1: Input Capture Valid Edge Indication Bit for ICU1

Bit Description

0 Falling edge detected

1 Rising edge detected


Bit Description



CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 10

MB96610/620 Series





ICE45 bit 15 14 13 12 11 10 9 8

- - - - - - IEI5 IEI4Attribute - - - R/W - R/W R/W R/W




Bit Description




Bit Description



CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 11

MB96610/620 Series





ICE67 bit 15 14 13 12 11 10 9 8

- - - - - ICUS6 IEI7 IEI6Attribute - - - R/W - R/W R/W R/W



[bit10] ICUS6: Input Capture Source Select for ICU6

Bit Description

0 The external pin IN6 is input source

1 USART2 is input source


Bit Description




Bit Description



CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 12

MB96610/620 Series





ICE89 bit 15 14 13 12 11 10 9 8

- - - ICUS9 - - IEI9 -Attribute - - - R/W - R/W R/W R/W




Bit Description



[bit11, bit10] -: Reserved Bit

Read value is undefined, write always 0. Read modify write operations to this register have no effect on these bits.


Bit Description



[bit8] -: Reserved Bit

Read value is undefined, write always 0. Read modify write operations to this register have no effect on this bit.

CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 13

MB96610/620 Series

matsubara線





ICE1011 bit 15 14 13 12 11 10 9 8

- - - - - ICUS10 - IEI10Attribute - - - R/W - R/W R/W R/W




Bit Description



[bit9] -: Reserved Bit Read value is undefined, write always 0. Read modify write operations to this register have no effect on this bit.


Bit Description



CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 14

MB96610/620 Series

7. Peripheral Resource Pin Relocation




The input or output pin of some resources can be relocated. The location of these resource pins is defined by the peripheral resource pin relocation registers PRRR0 to PRRR13.

Overview of the Peripheral Resource Relocation Register Table 7-1 Peripheral Resource Pin Relocation Register (PRRR0 to PRRR9)

MB96610

Address Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Description

0004D6 PRRR0 INT7_R - - INT4_R - INT2_R - - Peripheral resource relocation register 0

0004D7 PRRR1 - - - - - INT10_

R - -

Peripheral resource relocation register 1

0004DB PRRR5 - - - - - - OUT1_R OUT0_R Peripheral resource relocation register 5

0004DC PRRR6 - CKOT1_

R SCK2_R SOT2_R SIN2_R - - -


0004DD PRRR7 - - - - INT3_R

1 - -

ADTG_R


0004DE PRRR8 - - SCK8_R SOT8_R SIN8_R SCK7_R SOT7_R SIN7_R Peripheral resource relocation register 8

0004DF PRRR9 - - CKOT0_

R - - - - -


MB96620

0004D6 PRRR0 INT7_R - - INT4_R - INT2_R - INT0_R Peripheral resource relocation register 0

0004D7 PRRR1 - - - - INT11_RINT10_

R INT9_R -


0004DB PRRR5 - - - - - - OUT1_R OUT0_R Peripheral resource relocation register 5

0004DC PRRR6 - CKOT1_

R SCK2_R SOT2_R SIN2_R - - -


0004DD PRRR7 - - - - INT3_R

1 - NMI_R

ADTG_R


0004DE PRRR8 - - SCK8_R SOT8_R SIN8_R SCK7_R SOT7_R SIN7_R Peripheral resource relocation register 8

0004DF PRRR9 - - CKOT0_

R - - - - -


-: Reserved Bit


Availability of Resource Relocation Pins If a resource relocation pin is not available on the device, the corresponding bit must be treated as undefined bit. Hence the read value of this bit is undefined, "0" must always be written to this bit and read modify write instructions on the register are not affected by this bit. See the data sheet for the availability of resource relocation pins.

CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 15

MB96610/620 Series




Peripheral Resource Relocation Register 0 (PRRR0)

PRRR0 bit 7 6 5 4 3 2 1 0

INT7_R - - INT4_R - INT2_R - INT0_RAttribute R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

[bit7] INT7_R: External Interrupt 7 Input Relocation Bit

Bit Description

0 Pin INT7 is used as input pin

1 Pin INT7_R is used as input pin

[bit6, bit5] -: Reserved Bit



Bit Description






Bit Description






Bit Description



CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 16

MB96610/620 Series





PRRR1 bit 15 14 13 12 11 10 9 8

- - - - INT11_R INT10_R INT9_R -Attribute R/W R/W R/W R/W R/W R/W R/W R/W




Bit Description




Bit Description




Bit Description





CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 17

MB96610/620 Series





PRRR5 bit 15 14 13 12 11 10 9 8

- - - - - - OUT1_R OUT0_RAttribute R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 X X 0 0 0 0


[bit9] OUT1_R: Output Compare Unit 1 Output Relocation Bit

Bit Description

0 Pin OUT1 is used as output pin

1 Pin OUT1_R is used as output pin

[bit8] OUT0_R: Output Compare Unit 0 Output Relocation Bit

Bit Description

0 Pin OUT0 is used as output pin

1 Pin OUT0_R is used as output pin

CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 18

MB96610/620 Series





PRRR6 bit 7 6 5 4 3 2 1 0

- CKOT1_R SCK2_R SOT2_R SIN2_R - - -Attribute R/W R/W R/W R/W R/W R/W R/W R/W



[bit6] CKOT1_R: Clock Output 1 Relocation Bit

Bit Description

0 Pin CKOT1 is used as output pin

1 Pin CKOT1_R is used as output pin

[bit5] SCK2_R: USART 2 Serial Clock Input/Output Relocation Bit

Bit Description

0 Pin SCK2 is used as input/output pin

1 Pin SCK2_R is used as input/output pin

[bit4] SOT2_R: USART 2 Serial Output Relocation Bit

Bit Description

0 Pin SOT2 is used as output pin

1 Pin SOT2_R is used as output pin

[bit3] SIN2_R: USART 2 Serial Input Relocation Bit

Bit Description

0 Pin SIN2 is used as input pin

1 Pin SIN2_R is used as input pin


CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 19

MB96610/620 Series





PRRR7 bit 15 14 13 12 11 10 9 8

- - - - INT3_R1 - NMI_R ADTG_RAttribute R/W R/W R/W R/W R/W R/W R/W R/W



[bit11] INT3_R1: External Interrupt 3 Second Input Relocation Bit

Bit Description

0 If bit INT3_R = 0, then pin INT3 is used as input pin

1 If bit INT3_R = 0, then pin INT3_R1 is used as input pin


[bit9] NMI_R: Non-Maskable Interrupt Input Relocation Bit

Bit Description

0 Pin NMI is used as input pin

1 Pin NMI_R is used as input pin

[bit8] ADTG_R: A/D Converter Trigger Input Relocation Bit

Bit Description

0 Pin ADTG is used as input pin

1 Pin ADTG_R is used as input pin

CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 20

MB96610/620 Series





PRRR8 bit 7 6 5 4 3 2 1 0

- - SCK8_R SOT8_R SIN8_R SCK7_R SOT7_R SIN7_RAttribute R/W R/W R/W R/W R/W R/W R/W R/W


[bit7, bit6] -: Reserved Bit Read value is undefined, write always 0. Read modify write operations to this register have no effect on these bits.


Bit Description



[bit4] SOT8_R: USART 8 Serial Data Output Relocation Bit

Bit Description



[bit3] SIN8_R: USART 8 Serial Data Input Relocation Bit

Bit Description




Bit Description



[bit1] SOT7_R: USART 7 Serial Data Output Relocation Bit

Bit Description



CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 21

MB96610/620 Series




[bit0] SIN7_R: USART 7 Serial Data Input Relocation Bit

Bit Description



CHAPTER 1: OVERVIEW

MN704-00006-2v0-E 22

MB96610/620 Series





PRRR9 bit 15 14 13 12 11 10 9 8

- - CKOT0_R - - - - -Attribute R/W R/W R/W R/W R/W R/W R/W R/W

Initial value X X 0 0 0 0 0 0

[bit15, bit14] -: Reserved Bit Read value is undefined, write always 0. Read modify write operations to this register have no effe

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