f2mc-8l family microcontrollers

F2MC-8L FAMILY

MICROCONTROLLERS

MB89650A SERIES

HARDWARE MANUAL

CM25-10104-1E1

All Rights Reserved.

Circuit diagrams utilizing Fujitsu products are included as a mean of illustrating typicalsemiconductor applications. Complete information sufficient for construction proposes isnot necessarily given.

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F2MC-8L FAMILYMICROCONTROLLERS

MB89650A SERIESHARDWARE MANUAL

Edition 1.0 December 1995

1995 FUJITSU LIMITED

iii

Table of Contents

1. GENERAL ...............................................................................................................1-1

1.1 Features .......................................................................................................................1-3

1.2 Product Series ..............................................................................................................1-4

1.3 Block Diagram ..............................................................................................................1-5

1.4 Pin Assignment.............................................................................................................1-6

1.5 Pin Function Description...............................................................................................1-9

1.6 Handling Devices........................................................................................................1-14

2. HARDWARE CONFIGRATION ..............................................................................2-1

2.1 CPU..............................................................................................................................2-32.1.1 Memory Space ............................................................................................................. 2-32.1.2 Arrangement of 16-bit Data in Memory ........................................................................ 2-52.1.3 Internal Registers in CPU............................................................................................. 2-6

2.2 Resource Functions......................................................................................................2-92.2.1 I/O Ports ..................................................................................................................... 2-112.2.2 Watch prescaler/Buzzer output .................................................................................. 2-192.2.3 8-bit serial I/O ............................................................................................................. 2-222.2.4 8-bit PWM timer (timer 1 and 2) ................................................................................. 2-282.2.5 8/16-bit timer (timer 1, timer 2/3, and timer 4) ............................................................ 2-332.2.6 A/D Converter............................................................................................................. 2-412.2.7 External Interrupt 1 (Wake-up 1) ................................................................................ 2-462.2.8 External Interrupt 2 (Wake-up 2) ................................................................................ 2-492.2.9 Time-base timer ......................................................................................................... 2-522.2.10 LCD controller/driver .................................................................................................. 2-552.2.11 Watchdog timer reset ................................................................................................. 2-65

3. OPERATION ...........................................................................................................3-1

3.1 Clock Control Block ......................................................................................................3-3

3.2 Reset Operation .........................................................................................................3-12

3.3 Interrupt ......................................................................................................................3-14

4. COMMAND .............................................................................................................4-1

4.1 Addressing....................................................................................................................4-3

4.2 Special Commands ......................................................................................................4-6

4.3 Transfer Instructions.....................................................................................................4-9

4.4 Operation Instructions ................................................................................................4-10

4.5 Branch Instructions.....................................................................................................4-11

4.6 Other Instructions .......................................................................................................4-12

iv

5. MASK OPTIONS .................................................................................................... 5-1

6. MB89P657A SPECIFICATION .............................................................................. 6-1

6.1 Features .......................................................................................................................6-3

6.2 Memory Space .............................................................................................................6-46.2.1 ROM area for MB89650A series and PROM area when MB89P657A in

EPROM mode...............................................................................................................6-4

6.3 Writing to PROM ..........................................................................................................6-5

6.4 Setting PROM Option...................................................................................................6-6

7. PECIFICATIONS FOR THE INTERNAL STEPUP CIRCUIT ................................. 7-1

7.1 General Description .....................................................................................................7-3

7.2 LCD Pins and Port pins ................................................................................................7-4

7.3 Unused Pins.................................................................................................................7-5

7.4 Selection of Pull-up Option...........................................................................................7-6

7.5 I/O Port Functions ........................................................................................................7-7

7.6 Reference Voltage and X2/X3 Stepup Circuit ..............................................................7-9

APPENDIX ............................................................................................................. App.-1

1. Pin State in SLEEP, STIP, RESET ........................................................................ App.-3

2. I/O Map .................................................................................................................. App.-4

3. F2MC-8L Instruction Map....................................................................................... App.-6

v

Figures

Fig. 1.1 Block Diagram (MB89653A) .................................................................................1-5

Fig. 1.2 MB89653A Pin Assignment (FPT-100P-M05) ......................................................1-6

Fig. 1.3 MB89653A Pin Assignment (FPT-100P-M06) ......................................................1-7

Fig. 1.4 MB89PV650A Pin Assignment (for piggyback/evaluation product) ......................1-8

Fig. 2.1 Memory Space of MB89650A Series of Microcontrollers .....................................2-3

Fig. 2.2 Arrangement of 16-bit Data in Memory.................................................................2-5

Fig. 2.3 Arrangement of 16-bit Data during Execution of Instruction .................................2-5

Fig. 2.4 Structure of Processor Status ...............................................................................2-6

Fig. 2.5 Rule for Translating Real Addresses at General-purpose Register Area .............2-7

Fig. 2.6 Register Bank Configuration .................................................................................2-8

Fig. 2.7 Ports 0 and 1 (in Single-chip Mode)....................................................................2-13

Fig. 2.8 Port 2 ..................................................................................................................2-14

Fig. 2.9 Ports 3, 4, and 8..................................................................................................2-15

Fig. 2.10 Port 5 ..................................................................................................................2-16

Fig. 2.11 Port 6 ..................................................................................................................2-17

Fig. 2.12 Port 7 ..................................................................................................................2-18

Fig. 2.13 Watch Prescaler Block Diagram .........................................................................2-19

Fig. 2.14 8-bit Serial I/O Block Diagram.............................................................................2-22

Fig. 2.15 Operation Outline Diagram .................................................................................2-25

Fig. 2.16 Interrupt Request Output Timing.........................................................................2-26

Fig. 2.17 Shift Start/Stop Timing ........................................................................................2-26

Fig. 2.18 Input/Output Shift Timing ....................................................................................2-27

Fig. 2.19 8-bit PWM Timer Block Diagram.........................................................................2-28

Fig. 2.20 Timer Operation ..................................................................................................2-31

Fig. 2.21 PWM Pulse Output .............................................................................................2-32

Fig. 2.22 8/16-bit Timer Block Diagram .............................................................................2-33

Fig. 2.23 Internal Clock Mode Operation Diagram.............................................................2-37

Fig. 2.24 Timer Setting Flow..............................................................................................2-38

Fig. 2.25 Equivalent Circuit Initially Set and the State of Square Wave Output.................2-38

Fig. 2.26 External Clock Mode Operation Diagram ...........................................................2-39

Fig. 2.27 Timer Operation Diagram When Using Timer Stop Bits .....................................2-39

Fig. 2.28 A/D Converter Block Diagram.............................................................................2-41

Fig. 2.29 External Interrupt-1 Block Diagram.....................................................................2-46

Fig. 2.30 External Interrupt 2 Block Diagram.....................................................................2-49

vi

Fig. 2.31 Time-base Timer Block Diagram ........................................................................2-52

Fig. 2.32 LCDC Block Diagram .........................................................................................2-55

Fig. 2.33 Example of Waveform at Pin Corresponding to the RAM Data for Display ........2-60



Fig. 2.36 Block Diagram of Watchdog Timer.....................................................................2-65

Fig. 3.1 Block Diagrams for Clock Control and Reset Control Blocks ...............................3-3

Fig. 3.2 Outline of Reset Operation .................................................................................3-12

Fig. 3.3 Interrupt Controller Block Diagram .....................................................................3-14

Fig. 3.4 Interrupt-processing Flowchart ...........................................................................3-17

Fig. 7.1 When LCD is Selected (P30 to P37/P40 to P47/P80 to P81)...............................7-7

Fig. 7.2 When Port is Selected (P30 to P37/P40 toP47) ...................................................7-8

Fig. 7.3 Pins for the Stepup Circuit (P82 to P83)...............................................................7-8

vii

Tables

Table 1-1 Types and Functions of MB89650A Series of Microcontrollers ..........................1-4

Table 1-2 Pin Function Description .....................................................................................1-9

Table 1-3 Input/Output Circuit Configurations ...................................................................1-12

Table 2-1 Table of Reset and Interrupt Vectors ..................................................................2-4

Table 2-2 I/O Map ...............................................................................................................2-9

Table 2-3 List of Port Functions ........................................................................................2-11

Table 2-4 Port Registers ...................................................................................................2-12

Table 3-1 Operating State of Low-power Consumption Modes ..........................................3-6

Table 3-2 Reset Vector Structure......................................................................................3-13

Table 3-3 Interrupt Number and Vector Table...................................................................3-15

Table 5-1 Mask Options ......................................................................................................5-3

1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2 Product Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.4 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.5 Pin Function Description . . . . . . . . . . . . . . . . . . . . . . 1-9

1.6 Handling Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

1. GENERAL

MB89650 SERIES HARDWARE MANUAL

1-2

GENERAL

1-3

The MB89650A series of single-chip microcontrollers contain various resources such as two clock-controlsystems, five-speed operation control, timers, PWM timers, a serial interface, an A/D converter, an external-interrupt input, LCDC, and a timer prescaler, in addition to a reduced instruction set.

1.1 Features

• MB89600 series CPU core

• Two clock-control systems

• Maximum memory space: 64 Kbytes

• Minimum instruction execution time: 0.4 µs at 10 MHz

• Interrupt processing time: 3.6 µs at 10 MHz

• I/O port: max. 64

• 21-bit time-based counter

• 8-bit PWM timer: 2 channels (Four channels can be used for output.)

• 8/16-bit timer/counter: 4 channels (16 bits x 2 channels)

• 8-bit serial I/O: 1 channel

• A/D converter: 8 channels

• External interrupts (wake-up function): 4 + 12 channels

• Clock prescaler: 15 bits

• LCDC controller and driver: 16 to 32 (segment) x 2 to 4 (common)

• Power-on reset available

• Low-power consumption mode (submode, clock mode, sleep mode, and stop mode)

• SQFP-100 package, QFP-100 package, MQFP-100 package

• CMOS technology


1-4

1.2 Product Series

Table 1-1 lists the types and functions of the MB89650A series of microcontrollers.

Table 1.1 Types and Functions of MB89650A Series of Microcontrollers

Piggyback/evalu-ation product

GENERAL

1-5

1.3 Block Diagram

Fig. 1.1 Block Diagram (MB89653A)


1-6

1.4 Pin Assignment

Fig. 1.2 MB89653A Pin Assignment (FPT-100P-M05)

GENERAL

1-7

Fig. 1.3 MB89653A Pin Assignment (FPT-100P-M06)

Note: Pin assignment on top of package (only for piggyback/evaluation type)


1-8

Fig. 1.4 MB89PV650A Pin Assignment (for piggyback/evaluation product)

GENERAL

1-9

1.5 Pin Function Description

Table 1-2 lists the pin functions and Table 1-3 shows the input/output circuits.

Table 1.2 Pin Function Description

(Continue)


1-10

(Continued)

GENERAL

1-11

(Continued)


1-12

Table 1.3 Input/Output Circuit Configurations

(Continue)

GENERAL

1-13

(Continued)


1-14

1.6 Handling Devices

(1) Preventing latch-up

Latch-up may occur if a voltage higher than Vcc or lower than Vss is applied to the input or output pinsother than the middle and high voltage resistance pins, or if a voltage exceeding the rated value is appliedbetween Vcc and Vss. When latch-up occurs, the supply current increases rapidly, sometimes resulting inoverheating and damage. Therefore, the voltage should not exceed the maximum ratings.

(2) Handling unused input pins

Leaving unused input pins open may cause a malfunction. Therefore, these pins should be set to pull-up orpull-down.

(3) Variations in supply voltage

Although the operating range of the Vcc supply voltage is assured, a rapid change in the supply voltagemay cause a malfunction even within the specified range. Therefore, the voltage supply to the IC should bekept as constant as possible. The Vcc ripple (p-p value) at commercial frequencies (50 - 60 Hz) should beless than 10% of the typical Vcc value, or the coefficient of excessive variation should be 0.1 V/ms or less ininstantaneous change when the power supply is switched.

(4) Precautions for external clocks

After changing the mode to power-on reset (option selection) and stop, it takes some time before oscillationstabilizes, so external clocks must be input.

(5) Handling the unused pin for the LCD

Leave the output pin for the SEG, if unused, open.

2.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2 Resource Functions. . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2. HARDWARE CONFIGRATION

MB89650A SERIES HARDWARE MANUAL

2-2

HARDWARE CONFIGRATION

2-3

2.1 CPU

This section describes the CPU hardware composition.

2.1.1 Memory Space

The MB89650A series of microcontrollers have a memory area of 64 Kbytes. All I/O, data, and programareas are located in this space. The I/O area is near the lowest address and the data area is immediatelyabove it. The data area may be divided into register, stack, and direct-address areas according to the appli-cations. The program area is located near the highest address and the tables of interrupt and reset vectorsand vector-call instructions are at the highest address. Figure 2.1 shows the structure of the memoryspace for the MB89650A series of microcontrollers.

Fig. 2.1 Memory Space of MB89650A Series of Microcontrollers


2-4

(1) I/O area

This area is where various resources such as control and data registers are located.

(2) RAM area

This area is where the static RAM is located. Addresses from 0100 H to 01FFH are also used as the gen-

eral-purpose register area according to the product type.

(3) ROM area

This area is where the internal ROM is located. Addresses from FFE4H to FFFFH are also used for the

tables indicating the start address of interrupt or reset vector. Table 2-1 shows the correspondencebetween each interrupt number or reset and the table addresses to be referenced for the MB89650A seriesof microcontrollers.

Table 2-1 Table of Reset and Interrupt Vectors


2-5

2.1.2 Arrangement of 16-bit Data in Memory

When the MB89650A series of microcontrollers handle 16-bit data, the data written at the lower address istreated as the upper data and that written at the next address is treated as the lower data as shown in Fig-ure 2.2 .

Fig. 2.2 Arrangement of 16-bit Data in Memory

This is the same as when 16 bits are specified by the operand during execution of an instruction. Bitscloser to the OP code are treated as the upper byte and those next to it are treated as the lower byte. Thisis also the same when the memory address or 16-bit immediate data is specified by the operand.

Fig. 2.3 Arrangement of 16-bit Data during Execution of Instruction

Data saved in the stack by an interrupt is also treated in the same manner.


2-6

2.1.3 Internal Registers in CPU

The F2MC8L core has dedicated registers in the CPU, and general-purpose registers in memory. The ded-icated registers are shown below.

<Dedicated registers>

• Program counter (PC) 16-bit long register indicating location where instructions stored

• Accumulator (A) 16-bit long register where results of operations stored temporarily; the lowerbyte is used to execute 8-bit data processing instructions.

• Temporary accumulator (T) 16-bit long register; the operations are performed between this register andthe accumulator. The lower one byte is used to execute 8-bit data process-ing instructions.

• Stack pointer (SP) 16-bit long pointer indicating stack area

• Processor status (PS) 16-bit long register where register pointers are condition codes stored

• Index register (IX) 16-bit long register for index modification

• Extra pointer (EP) 16-bit long pointer for memory addressing

The 16 bits of the program status (PS) can be divided into 8 upper bits for a register bank pointer (RP) and8 lower bits for a condition code register (CCR). (See Figure 2.4 .)

Fig. 2.4 Structure of Processor Status


2-7

The RP indicates the address of the current register. The contents of the RP and the real address aretranslated as shown in Figure 2.5.

Fig. 2.5 Rule for Translating Real Addresses at General-purpose Register Area

The CCR has bits indicating the results of operations and transfer data contents, and bits controlling theCPU operation when an interrupt occurs.

• H-flag H-flag is set when a carry or a borrow out of bit 3 into bit 4 is generated as a result of oper-ations; it is cleared in other cases. this flag is used for decimal-correction instructions.

• I-flag An interrupt is enabled when this flag is 1 and is disabled when it is 0.

• IL1 and IL0 These bits indicate the level of the currently-enabled interrupt. the CPU executes interruptprocessing only when an interrupt with a value smaller than the value indicated by this bitis requested.

• N-flag The N-flag is set when the most significant bit (MSB) is 1 as a result of operations; it iscleared when the MSB is 0.

• Z-flag Z-flag is set when the bit is 0 as a result of operations; it is cleared in other cases.

• V-flag V-flag is set when a two’s complement overflow occurs as a result of operations; it is resetwhen an overflow does not occur.

• C-flag C-flag is set when a carry or a borrow out of bit 7 is generated as a result of operations; itis cleared in other cases. When the shift instruction is executed, the value of the C-flag isshifted out.


2-8

<General-purpose registers>

General-purpose registers are 8-bit long registers for storing data.

The 8-bit long general-purpose registers are in the register banks in memory. One bank has eight registersand up to 32 banks are available. The register bank pointer (RP) indicates the currently-used bank.

Fig. 2.6 Register Bank Configuration


2-9

2.2 Resource Functions

The internal resource I/O map is shown below. See the description of the function of each resource for thedetails of each register.

The Internal resource I/O map is as follows:

Table 2-2 I/O Map

(Continue)


2-10

(Continued)


2-11

2.2.1 I/O Ports

(1) I/O ports

The MB89650A series of microcontrollers have eight parallel ports (62 ports). Ports 0,1,3, and 4 serves as8-bit I/O ports; ports 2 and 7 serve as 6-bit I/O ports; port 8 serves as a 4-bit I/O port; port 5 serves as a 8-bit output-only port; and port 6 serves as a 8 bit input-only port.

Table 2-3 List of Port Functions

Pins indicated by the hatched part have hysteresis input.

CMOS push-pull output and N-channel open drain output can be selected for pins indicated by the shadedpart.


2-12

(2) I/O port registers

• Port Registers

Port registers for P07 to P00, P17 to P10, P26 to P24, P22 to P20, P37 to P30, P47 to P40, P57 to P50,P67 to P60, P75 to P70, and P83 to P80 I/O ports.

Table 2-4 Port Registers


2-13

(3) Description of functions

P00 to P07 CMOS-type I/O ports




• Switching input and outputThese ports have a data-direction register (DDR) and port-data register (PDR) for each bit. Input andout put can be set independently for each bit. The pin with the DDR set to 1 is set to output, and thepin with the DDR set to 0 is set to input.

• Operation for output port (DDR = 1)The value written at the PDR is output to the pin when the DDR is set to 1. When the PDR is read,usually, the value of the pin is read instead of the contents of the output latch. However, when theRead Modify Write instruction is executed, the contents of the output latch are read irrespective of theDDR setting conditions. Therefore, the bit-processing instruction can be used even if input and outputare mixed with each other. When data is written to the PDR, the written data is held in the output latchirrespective of the DDR setting conditions.

• Operation for input port (DDR = 0)When setting input, the output impedance goes High. Therefore, when the PDR is read, the value ofthe pin is read.

• State when resetThe DDR is initialized to 0 by resetting and the output impedance goes High at all bits. The PDR isnot initialized by resetting. Therefore, set the value of the PDR before setting the DDR to output.However, the pull-up resistor pin selected by the mask option will be pull-up state.

• State in watch or stop modeWith the SPL bit of the standby-control register set to 1, in the watch or stop mode, the output imped-ance goes High irrespective of the value of the DDR.

Fig. 2.7 Ports 0 and 1 (in Single-chip Mode)


2-14

P24 to P26 CMOS/Nch open-drain-type I/O ports (also used as resource input/output)

• Switching input and outputThis port has a data-direction register (DDR) and a port-data register (PDR) for each bit. Input andoutput can be set independently for each bit. The pin with the DDR set to 1 is set to output, and thepin with the DDR set to 0 is set to input.

• Operation for output port (DDR = 1)The value written at the PDR is output to the pin when the DDR is set to 1. When the PDR is read,usually, the value of the pin is read instead of the contents of the output latch. However, when theRead Modify Write instruction is executed, the contents of the output latch are read irrespective of theDDR setting conditions. Therefore, the bit-processing instruction can be used even if input and outputare mixed with each other. When data is written to the PDR, the written data is held in the output latchirrespective of the DDR setting conditions. Depending on the setting conditions of the port 2changeover register (CHG2), CMOS output (bit 5 = 0) and N-channel open drain output (bit 5 = 1) canbe selected collectively for P24 through P26.

• Operation for input port (DDR = 0)When used as the input port, the output impedance goes High. Therefore, when the PDR is read, thevalue of the pin is read.

• Operation for resource outputWhen using as resource output, setting is performed by the resource output-enable bit. (See thedescription of each resource.) Since reading of the port is enabled even if output of each resource isenabled except for the Read-Modify-Write instruction, the pin state can be checked.

• State when resetWhen reset, the DDR is initialized to 0 and the output impedance goes High at all bits. When reset,the PDR is undefined. Therefore, set the value of the PDR before setting the DDR to output.However, pins for which Pull-up Resistor Available is specified by the mask option enter the pull-upstate.

• State in watch or stop modeWith the SPL bit of the standby-control register set to 1, in the watch or stop mode, the output imped-ance goes High irrespective of the value of the DDR.However, pins for which Pull-up Resistor Available is specified by the mask option enter the pull-upstate.

Fig. 2.8 Port 2


2-15

P30 to P37 CMOS-type I/O-only ports



• Switching input and outputThese ports have a data-direction register (DDR) and port-data register (PDR) for each bit. Input andout put can be set independently for each bit.

• Operation for output port (DDR = 1)The value written at the PDR is output to the pin when the DDR is set to 1. When the PDR is read,usually, the value of the pin is read instead of the contents of the output latch. However, when theRead Modify Write instruction is executed, the contents of the output latch are read irrespective of theDDR setting conditions. Therefore, the bit-processing instruction can be used even if input and outputare mixed with each other. When data is written to the PDR, the written data is held in the output latchirrespective of the DDR setting conditions.

• Operation for input port (DDR = 0)When setting input, the output impedance goes High. Therefore, when the PDR is read, the value ofthe pin is read.

• Operation for LCDC SEG/COM outputWhen using as LCDC SEG/COM output, setting is made by resource output enable bits. However, theport should be used at input state (DDR = 0). (See the description of each resource for the details.)

• State when resetThe DDR is initialized to 0 by resetting and the output impedance goes High at all bits. The PDR isnot initialized by resetting. Therefore, set the value of the PDR before setting the DDR to output.However, the pull-up resistor pin selected by the mask option will be pull-up state.

• State in watch or stop modeWith the SPL bit of the standby-control register set to 1, in the clock and stop modes, the outputimpedance goes High irrespective of the value of the DDR.However, the pull-up resistor pin selected by the mask option will be pull-up state.

Fig. 2.9 Ports 3, 4, and 8


2-16

P50 to P57 CMOS-type output ports (used as resource output)

• Operation for output portThe value written at the PDR is output to the pin. When the PDR is read, the contents of the outputlatch are always read. Therefore, the bit-processing command can be used even when the outputlevel fluctuates with the load.

• Operation for resource outputWhen using as resource output, setting is performed by the resource output-enable bit. (See thedescription of each resource.) In addition to timer toggle output, LCLK (32-kHz output) and HCLK(output with 1/2 frequency of 10 MHz) can be selected for P54 and P56, respectively. The output ofP54 and P56 can be selected as follows by the square wave control bits of the port 2 changeover reg-ister (CHG2) and the timer.

• State when resetAs the PDR is initialized to 0 by resetting, the Low level is output to the pin.

• State in watch or stop modeWhen the SPL bit of the standby-control register is set to 1, in the clock and stop modes, the outputimpedance goes High irrespective of the value of the PDR.

Fig. 2.10 Port 5


2-17

P60 to P67 Input-only ports (used as analog input)

• Operation for input portThe PDR can only be read and the value of the pin is always read. The control bits of P60 throughP67 correspond to bits 0 through 7 of the ICR6. Input is enabled at 1 and disabled at 0. 0 is alwaysread when input is disabled.

• Analog inputWhen using as analog input, set 1 at the corresponding bit of the input control register (ICR6). Thispre vents the DC pass when an intermediate level is input. When reset, this port enters the input-enabled state.When using as an analog input, do not select the pull-up option.

• State when resetAt reset, the ICR6 is initialized to 0 and the port enters the input-enabled state.

• State in watch or stop modeIn the watch or stop mode, the port enters the input-disabled state irrespective of the value of ICR6.

Fig. 2.11 Port 6


2-18

P70 to P75 Nch open-drain-type I/O ports (used as resource input/output)

• Switching input and outputThese ports have no register for specifying input or output. When using as an input port, set 1 at thePDR.

• Operation for output port (DDR = 1)The value written at the PDR is output to the pin. When the PDR is read, usually, the value of the pinis read instead of the contents of the output latch. However, when the Read Modify Write instruction isexecuted, the contents of the output latch are read. Therefore, the bit-processing instruction can beused even if input and output are mixed with each other.

• Operation for input portWhen used as the input port, set 1 at the PDR to turn off the output transistor. When the PDR is readunder this condition, the value of the pin can always be read.

• Operation for resource outputWhen using as a resource output, setting is performed by the resource output-enable bit. (See thedescription of each resource.) Even if output of each resource is enabled, the port can be read otherthan when the Read-Modify-Write instruction is read. Therefore, the state of the pin can be checked.

• Operation for resource inputInput to the resource is not related to the setting conditions of the PDR and the resource. The value ofthe pin is always input to the port serving as the resource input. When using an external signal at theresource, set 1 at the PDR.

• State when resetThe PDR initialized to 1 at reset, so the output register is turned off at all bits. However, pins for whichPull-up Resistor Available is specified by the mask option enter the pull-up state.

• State in watch or stop modeWhen the SPL bit of the standby-control register set to 1, in the watch or stop mode, the output imped-ance goes High irrespective of the value of the PDR.However, the pull-up resistor pin selected by the mask option will be pull-up state.

Fig. 2.12 Port 7


2-19

2.2.2 Watch prescaler/Buzzer output

• A 15-bit binary counter is provided

• Four interval times and three buzzer outputs can be selected.

• The clock function cannot be used when the single mask option is selected.

(1) Registers

Fig. 2.13 Watch Prescaler Block Diagram


2-20

(2) Description of registers

• Watch prescaler control register (WCR)

[bit 7] WIF: Watch interrupt flagBit 7 clears watch interrupt flag when writing data.

Bit 7 indicates generation of the clock interrupt when reading data.

When reading with a Read-Modify-Write instruction, 1 is read.

If the WIF bit is 1 when WIE bit is 1, an interrupt request is output.

It is cleared by resetting

[Bit 6] WIE: Watch interrupt enable bitBit 6 enables an interrupt by the clock.

[Bit 5, bit4] WC1, WC0: Buzzer output select and pin control bits

fch: Main clock frequency

Buzzer output cannot be used at submode.


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[Bit2, bit1] WS1, WS: Interrupt interval time specification bit by watchBit 2 and 1 specify the interrupt cycles by the watch.

fcl: Subclock frequency

[Bit 0] WCLR: Watch prescaler clear bitBit 0 clears the watch prescaler.

When this bit is read, 1 is always read.


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2.2.3 8-bit serial I/O

• 8-bit serial data transfer is possible by the clock synchronous method.

• LSB first or MSB first can be selected for data transfer.

• Four shift-clock modes (three internal and one external) can be selected.

(1) Registers

Fig. 2.14 8-bit Serial I/O Block Diagram

Serial-mode register

Serial-data register


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(a) Serial-mode register (SMR)

The SMR is used to control serial I/O.

[Bit 7] SIOF: Serial I/O interrupt-request flag

When read

If this bit is set when an interrupt is enabled (SIOE = 1), an interrupt request is output to the CPU.

When write

When reading Read-Modify-Write instruction, 1 is always read.

[Bit 6] SIOE: Serial I/O interrupt-enable bit

[Bit 5] SCKE: Serial clock output pin control bit

[Bit 4] SOE: Serial-data output pin control bit

[Bit 3 and 2] CKS1 and CKS0: Shift-clock select bits


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[Bit 1] BDS: Transfer direction specify bit

Note that when this bit is rewritten after writing data to the SDR, the data become invalid.

[Bit 0] SST: Serial I/O transfer-start bit

Set this bit to 0, when entering the standby state.

This bit is automatically cleared to 0 when transfer is terminated.

Set this bit to 0, when entering the standby state.

(b) SDR

This 8-bit register is used to hold serial I/o transfer data. Do not write data to this register during theserial I/O operation.


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(3) Description of operation

(a) Outline

This module consists of the serial-mode register (SMR) and serial-data register (SDR). At serial output,data in the SDR is output in bit serial to the serial output pin (SO) in synchronization with the falling edgeof a serial shift-clock pulse generated from the internal or external clock. At serial input, data is input inbit serial from the serial input pin (SI) to the SDR at the rising edge of a serial shift-clock pulse.

Fig. 2.15 Operation Outline Diagram

(b) Operation modes

The serial I/O has three internal shift-clock modes and one external shift-clock mode, which are speci-fied by the SMR. Mode switching or clock selection should be made with serial I/O stopped (SST bit =0).

(1) Internal shift-clock modeOperation is performed by the internal clock. A shift-clock pulse with a duty of 50% is output from theSCK pin as a synchronous timing output. Data is transferred bit-by-bit at every clock pulse.

(2) External shift-clock modeData is transferred bit-by-bit at every clock pulse in synchronization with the external shift-clock pulseinput from the SCK pin.

The external clock, if input, does not enable the shift operation when the SST bit is 0 and the datafrom the SDR register (value for bit 7 in the MSB first mode) is output to the SO pin. If the data in theSDR register is updated, the updated data is always available at the SO pin.

Note: Do not write data to the SMR and SDR during the serial I/O operation in either mode.

(c) Interrupt functions

If an external clock is input when the SST bit is 0, shifting is not performed. SDR data (the value of bit 7at MSB first) is output to the SD pin. However, if the data of SDR data is changed, the value at the SDpin will be the changed value.


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Fig. 2.16 Interrupt Request Output Timing

(d) Shift start/stop timing

Data transfer starts if 1 is written when the SST bit in the SMR is 0, and stops when 0 is written. Whendata transfer is terminated, the SST bit is automatically cleared to 0, which stops the operation.

(1) Internal shift-clock mode (LSB first)

(2) External shift-clock mode (LSB first)

Fig. 2.17 Shift Start/Stop Timing


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(e) Input/output shift timing

Data is output from the serial output pin (SO) at the falling edge of the shift-clock pulse, and is input fromthe serial input pin (SI) to the SDR at the rising edge of the shift-clock pulse.

Fig. 2.18 Input/Output Shift Timing


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2.2.4 8-bit PWM timer (timer 1 and 2)

• This timer can be used as an 8-bit timer or PWM-control circuit with 8-bit resolution.

• Four clock pulses can be selected.

• There are two PWM output channels that can be switched.

• There are two PWM timer channels with the same function.

(1) Registers

Fig. 2.19 8-bit PWM Timer Block Diagram


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(a) Control register (CNTR)

[Bit 7] P/TX: Timer/PWM operation-mode switching bitThe operation is performed as the timer when bit 7 is set to 0, and as the PWM-control circuit when bit 7is set to 1.

The timer/PWM operation mode should be switched when the counter stops operation (TPE = 0), theinterrupt is enabled (TIE = 0), and the interrupt request flag is cleared (TIR = 0).

[Bit 6] OE2: Output signal 2 control bitWhen this but is 1, the port output will be the timer and PWM output. When the timer operates, aninverted signal is output each time the counter value agrees with the value of compare register. WhenPWM operates, the PWM signal is output. The PWM pulse of timer 1 is output at P51 and that of timer2 is output at P53.

When this bit is 1, it functions as counter/output pin for PWM even if the DDR of P51/P53 is set to input.

[Bits 5 and 4] P1, P0: Clock select bitThe clock pulse from prescaler or the output of one channel of 8-bit timer can be selected by P1 and P0.Both timers 1 and 2 can select the following clock cycle times.

Note that these bits must not be rewritten when the counter is in operation (TPE = 1).


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[Bit 3] TPE: Counter-operation enable bitIf 1 is written when this bit is 0, the timer or PWM-control circuit starts operation.

[Bit 2] TIR: Interrupt-request flag bitWhen an interrupt source occurs, bit 2 goes to 1. To clear the generated interrupt source, write 0 at thisbit. The meaning of each bit to be read is as follows:

Note that 1 is always read when the Read-Modify-Write instruction is read.

The meaning of each bit to be written is as follows:

Note: In the PWM operation mode, neither the read nor write values of this bit have any meaning.

[Bit 1] OE1: Output-signal 1 control bitWhen bit 1 is 1, the port serves as the timer/PWM output. In the timer operation mode, usually, a signalwhich is reversed each time the values of the counter and compare register agree, is output. In thePWM operation mode, a PWM signal is output. Timer-1 PWM pulse and timer-2 PWM pulse are outputfrom P50 and P52, respectively.

If this bit is 1, the port functions as the counter/PWM output pin even after the DDR of P50/52 is set toinput (bit 7 of DDR3 = 0).

[Bit 0] TIE: Interrupt-enable bit (timer mode)If bit 0 is set to 1, an interrupt occurs when the values of the counter and compare register agree.

However, in the PWM operation mode, an interrupt occurs irrespective of the value of this bit.


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(b) Compare register (COMR)

This register is used to set the value to be compared with the value of the counter in the timer-operationmode. The counter is cleared in the timer-operation mode and when the values of the counter and thisregister agree. In the PWM operation mode, the High pulse width can be specified by the value of thisregister.


(a) Timer operation

Setting the P/TX bit (bit 7) of the CNTR to 0 gives the timer-operation mode. When the TPE bit (bit 3) ofthe CNTR is set to 1, the counter starts incrementing from 00H. When the value of the counter agreeswith that of the COMR, the counter is cleared on the next count clock pulse and incrementing restarts.Therefore, the TIR bit (bit 2) is set and the output pin is reversed (when the TPE bit (bit 3) is 0, the outputpin is fixed at Low level) in cycles of the count clock pulses when 00H is written at the COMR, or incycles 256 times longer than those of the count clock pulses when FFH is written.

If the value of the COMR is rewritten in the timer-operation mode, it becomes effective from the nextcycle (when the value of the counter is 00H, the value of the COMR is transferred to the comparatorlatch).

Fig. 2.20 Timer Operation

If the TIE bit (bit 0) of the CNTR is set to 1, an interrupt occurs when the values of the counter andCOMR agree. During interrupt processing, the TIR bit (bit 2) is used as the interrupt flag. The TIR bit(bit 2) is set irrespective of the value of the TIE bit (bit 0). However, if the values of the counter andCOMR agree, the TIR bit (bit 2) is set to 1 even after an interrupt is disabled.

Writing 0 at the TIR bit (bit 2) permits clearing of the interrupt source or the TIR bit (bit 2). When theRead-Modify-Write instruction is read, the TIR bit (bit 2) is set so that 1 can always be read to preventerroneous clearing.

The count clock pulse can be selected from three clock pulses from the prescaler and from pulses fromthe internal timer by the clock-pulse select bits P0 and P1 of the CNTR.


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(b) PWM operation

Setting the P/TX bit (bit7) of the CNTR to 1 gives the PWM operation mode. The COMR specifies theduty of the output pulse. Pulses can be output with 1/256 resolution and a duty of 0% to 99.6%.

When 0 (00H) is written at the COMR, the duty of the PWM output pulse is 0%; when 128 (80H) is writ-ten, the duty is 50%, and when 255 (FFH) is written, it is 99.6%.

The value of COMR is transferred to the comparator latch when the value of the counter is 00H. If thevalue of the COMR is rewritten in the PWM operation mode, it becomes effective from the next cycle.

Fig. 2.21 PWM Pulse Output

The TIR bit (bit 2) of the CNTR has no relation to the PWM operation. No interruption occurs even if theTIE bit (bit 0) is 1.

The cycle of the PWM pulse can be changed by switching the count clock pulse. The count clock pulsecan be selected from three clock pulses from the prescaler and from pulses from the internal timer byclock-pulse select bits P0 and P1 of the CNTR.

Both PWM 1 and PWM 2 have 2 channels for outputting PWM pulse, so up to four channels can be out-put.


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2.2.5 8/16-bit timer (timer 1, timer 2/3, and timer 4)

• Three internal and one external clock pulse inputs can be selected.

• Operation in 8-bit 2-channel mode or 16-bit 1-channel mode is possible.

• A square wave output function is provided.

• Two-channel 8/16-bit timers with the same functions are available.

(1) Resister list

Fig. 2.22 8/16-bit Timer Block Diagram


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(a) Timer 1 control register (T1CR)

[Bit 7] T1IF: Bit 7 is an interrupt request flag bit.

When Read-Modify-Write command is executed, 1 is always read.

[Bit 6] T1IE: Bit 6 is an interrupt enable bit.

[Bit 5] TO11:[Bit 4] TO10:Bits 5 and 4 are used for control of square-wave output when the timer is stopped. For setting, seesquare-wave output setting item (P45).

Sets the square-wave output pin of timer to the set value.

When STR1 is 0, the square-wave output is set to the set value.

The output ports [P54 (timer 1) and P56 (timer 3)] become general-purpose ports.

Makes initial value of square-wave output of timer Low level.

Makes initial value of square-wave output of timer High level.

Sets the square-wave output pin of timer to the set value.


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[Bit 3] TC11:[Bit 2] TC10:Bits 3 and 2 are clock source select bits.

[Bit 1] STP1: Bit 1 is a timer termination bit.

[Bit 0] STP1: Bit 0 is a timer start bit.

(b) Timer-2 control register (T2CR)

[Bit 7] T2IF: Bit 7 is an interrupt request flag bit.

When executing Read-Modify-Write instruction is executed, 1 is always read.


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[Bit 6] T2IE: Bit 6 is an interrupt enable bit.

[Bit 5] TO21:[Bit 4] TO20:Bits 5 and 4 are used to control square-wave output when the timer is stopped. For setting, see square-wave output setting (2-38).

[Bit 3] TC21:[Bit 2] TC20:Bits 3 and 2 are used to select timer clock source.

[Bit 1] STP2: Bit 1 is used to stop a timer.

[Bit 0] STR2: Bit 0 is used to start a timer.


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(c) Timers 1 and 2 data register (T1DR and T2DR)

Write data is the set interval times and Read data is the counted times.


(a) 8-bit internal clock mode

In the 8-bit internal clock mode, three internal clock inputs can be selected by setting the clock sourceselect bits (TC11 and TC10) (TC21 and TC20) of the timer control register (T1CR and T2CR). Thetimer data registers (T1DR and T2DR) serve as interval timer setting registers.

To start the timer, set the interval time at the timer data registers, write 1 at the timer start bits (STR1and STR2) of the timer control registers to clear the counter to 00H, and load the values of the timerdata registers into the compare latch. Then, counting starts.

When the values of the counter agree with those of the timer data registers, the interval interrupt requestflags (T1IF and T2IF) are set to 1. At this time, the counter is cleared to 00H, the values of the timerdata registers are reloaded into the compare latch, and counting is continued. If the interrupt enable bits(T1IE and T2IE) are set to 1, an interrupt request is output to the CPU. Assuming the set value of thetimer data register is n and the selected clock is φ, the interval time (T) can be calculated as follows.

Fig. 2.23 Internal Clock Mode Operation Diagram


2-38

Fig. 2.24 Timer Setting Flow

(b) Initial setting of square wave

Square-wave output can be set to any value only when the timer is stopped (STR1 = 0, STR2 = 0).Each square-wave output of timers 1 through 4 correspond to P54 through P57.

Set according to the following procedure:

1. Write the set values (01 and 10) at the initial value set bits (TO11 and TO10) (TO21 and TO20) forsquare-wave output. At this writing, the values are held in the level latch as shown in the figurebelow. However, these set values are not output from the pin (the previous square-wave state is out-put to the pin).

2. Write 11 at the same bits. This will initialize the square-wave output to the set values. If the STR1 bitis 0, square-wave output of the pin is set to the values in 1 during this write cycle. The square-waveoutput pin state in 1 and 2 is shown below.

3. Start the timer when the STR1 bit is 1.

These initial value set bits can be set with the bit manipulation instruction.

Fig. 2.25 Equivalent Circuit Initially Set and the State of Square Wave Output


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(c) 8-bit external clock mode

In the 8-bit external clock mode, external clock input can be selected by the clock source select bits(TC11 and TC10) of the timer-1 control register (T1CR). The external clock input pins of timers 1 and 3correspond to P70 (EC1) and P71 (EC2), respectively.

To start the timer, write 1 at the timer start bit (STR1) of the T1CR to clear the counter. Then, countingup is started.

When the values of the counter agree with those of the timer data registers, the interval interrupt requestflag (T1IF) is set to 1. At this time, if an interrupt is enabled (T1IE = 1), an interrupt request is output tothe CPU.

Fig. 2.26 External Clock Mode Operation Diagram

(d) points when using timer stop bit

When stopping the timer by the timer start bits after stopping it temporarily with the timer stop bits, thecount value may be incremented by 1, depending on the state of an input clock pulse to the timer asshown in Figure 2.27 (the count is not incremented when the input clock pulse is High but it is incre-mented at Low).

Therefore, if the timer is stopped temporarily by the timer stop bits, read the counter and then set 0 atthe timer start bits.

Fig. 2.27 Timer Operation Diagram When Using Timer Stop Bits


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(e) 16-bit mode

In the 16-bit mode, each bit of timer control register is as follow.

In the 16-bit mode, set 11 at the TC21 and TC20 bits of the T2CR and 00 at the TO21 and TO20 bits.

In the 16-bit mode, the timer is controlled by the T1CR. The timer data registers T2DR and T1DR corre-spond to the upper and lower bytes, respectively.

The clock source is selected by the TC11 and TC10 bits of the T1CR. To start the timer, write 1 at theSTR1 bit of T1CR to clear the counter.

When the values of the counter agree with those of the timer data registers, the T1IF bit is set to 1. Atthis time, if the T1IE bit is 1, an interrupt request is output to the CPU.

Note: To read the value of the counter in the 16-bit mode, always read the value twice and confirm that it isvalid before using data.

• For the operation diagram, see 8-bit mode operation diagram.

(f) Starting and temporarily stopping timers

Start and temporarily stop timers 2, 3, and 4 in the same manner as timer 1. The operation of timer 1 isexplained below.

1. Clearing the counter to start countingWhen the STR1 bit is 0, write 01 at the STP1 and STR1 bits. When the STR1 bit is set from 0 to 1,the timer is cleared to start counting.

2. Temporarily stopping timer to start counting without clearing the counterTo stop the timer to temporarily, set the STR1 and STR1 bits to 11. To start counting from the tempo-rarily stopped state without clearing the counter, set the STP1 and STR1 bits from 11 to 01.

The state of the timer set by STP1 and STR1 bits and the operation of the timer when started from theprevious state (STP1 and STR1 bits = 01) are as follows:

(g) Precautions for use of timer

To use timers 1 and 3 as the 8-bit 1-channel timer, set any value other than 11B at bits 2 and 3 of theT2CR.

Timer operation when started from the state in the left column (bits 1, 0 = 01)


2-41

2.2.6 A/D Converter

This is an 8-bit sequential-comparison A/D converter. 8-bit A/D conversion is performed after conversion isstarted by the software. The results are stored in the ADCD register. This register has the following fea-tures:

• 18 µs conversion time (at 10 MHz oscillation)

• End detection by interrupt or software polling

• Internal sample/hold circuit

• Sense function (5 µs conversion time at 10 MHz oscillation)

(1) Registers

Fig. 2.28 A/D Converter Block Diagram


2-42


(a) A/D converter control register 1 (ADC1)

[Bits 7 to 4] ANS3 to ANS0: Analog-input select bitsEach channels is selected by setting each bit as follows.

[Bit 3] ADI: Conversion end flag bit

In both the A/D and sense modes, an interrupt request is output if these bits are set when the ADIE bit(bit 3) of the ADC2 is 1.

Spacification disabled


2-43

[Bit 2] ADMV: This flag indicates that A/D conversion is in progress.

[Bit 1] SIFM: Bit 1 is used to set the conditions for setting conversion end flag in sense mode.

[Bit 0] AD: Bit 0 is an A/D conversion start bit.The meaning of each bit to be written is as follows:

When reading this bit, 0 is always read.

(b) A/D converter control register 2 (ADC2)

[Bit 3] ADIE: Bit 3 is used to specify interrupt enable/disable.

[Bit 2] ADMD: Function-switching bit.Bit 2 is used to switch the A/D mode and sense mode

[Bit 1] Note 1:0 must be always written when writing data.

[Bit 0] TEST:Bit 0 is used only for testing. Always write 1 at this bit. 1 is always read.


2-44

(d) A/DC data register (ADCD)

In the A/D mode, the result of the A/D conversion is stored as soon as it is terminated. Once started, thevalue becomes undefined. Therefore, always read the data after the end of conversion.

In the sense mode, the value written at this register is compared with the converted value before start-ing.

The read value does not have any meaning.

Do not write data during conversion in either the A/D or sense mode.


(a) A/D mode

• StartWriting 0 at the ADMD bit (bit 2) of the ADC2 gives the A/D mode. Writing 1 at the AD bit (bit 0) of theADC1 starts the A/D conversion.

• RestartThe A/D conversion can be restarted even during operation.

• EndIf A/D conversion is not restarted after starting A/D conversion, the conversion is terminated after 44instruction cycles. When the A/D conversion is terminated, the ADI bit of the ADC1 is set. An inter-rupt request is output at this time if the ADIE bit is 1.

(b) Sense mode

In the sense mode, the analog voltage of the analog input port is compared with the voltage specified bythe program.

• StartWriting 1 at the ADMD bit of the ADC2 gives the sense mode. Writing 1 at the AD bit of the ADC1starts the A/D conversion.

• ResultThe analog voltage of the analog input port is compared with the voltage specified by the program.When the conditions specified by the SIFM bit are met, the ADI bit is set. An interrupt request is out-put at this time if the ADIE bit is 1.

• EndIn the sense mode, the ADI bit is not set even if the A/D conversion is terminated. However, the CPUcan recognize the end of conversion if the ADMV bit is set to 0.


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(4) Precautions for A/D converter

(a) Switch the A/D or sense mode after clearing the ADI bit.

(b) Do not switch the A/D or sense mode during conversion.

(c) In the A/D mode, the contents of the ADCD are lost as soon as the A/D conversion is started. There-fore, do not read the value during conversion. The contents of the ADCD are held after the comple-tion of conversion until the conversion is restarted.

(d) When the reset and stop mode are activated, the A/D conversion stops and each register is initial-ized.

(e) Do not reselect the analog input channel during conversion.

(f) At restart, the analog input channel can be reselected simultaneously (when writing 1 at the AD bit,ANS3 to ANS0 can be changed).

(g) Do not rewrite the SIFM bit during conversion.

(h) At restart by the AD bit, the SIFM bit can be rewritten simultaneously.


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2.2.7 External Interrupt 1 (Wake-up 1)

The external interrupt 1 consists of the external interrupt control register and external interrupt flag register.

• There are four external interrupt input pins.

• An interrupt request can be output at the falling edge of an input signal.

• An input signal can be inverted.

• Wake-up input is available.

(1) Registers

Fig. 2.29 External Interrupt-1 Block Diagram


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(a) External-interrupt control register (EIE1)

[Bit 7] SIV3:[Bit 6] SIV2:[Bit 5] SIV1:[Bit 4] SIV0:These bits are used to invert the external interrupt signals of EI13 through EI10.

[Bit 3] IE13:[Bit 2] IE12:[Bit 1] IE11:[Bit 0] IE10:These bits are used to enable external interrupt.

Note: The interrupt flag bits may be set on immediately after enabling external interrupts or inverting exter-nal interrupt signals.


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(b) External interrupt 1 flag register (EIF1)

[Bit 3] IF13:[Bit 2] IF12:[Bit 1] IF11:[Bit 0] IF10:Bits 3 to 0 are the falling edge detection flag bits of EI13 to EI10.

When the interrupt enable bits (IE13 to IE10) of the external interrupt 1 control register (EIE1) are 1, ifthe falling edge detection bits (IF13 to IF10) corresponding to the bits (IE13 to IE10) where 1 is writtenare set to 1, an interrupt request is output to the CPU. 1 is always read when the Read-Modify-Writeinstruction is executed.


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2.2.8 External Interrupt 2 (Wake-up 2)

External interrupt 2 consists of the external interrupt control register and external interrupt flag register.

• There are 12 external interrupt input pins.

• An interrupt request is output by a Low-level input signal.

• Wake-up input is available.

(1) Registers

Fig. 2.30 External Interrupt 2 Block Diagram


2-50


(a) External interrupt 2 control register (EIE2)

[Bit 7] IE27:[Bit 6] IE26:[Bit 5] IE25:[Bit 4] IE24:[Bit 3] IE23:[Bit 2] IE22:[Bit 1] IE21:[Bit 0] IE20:Bits 7 to 0 are the external interrupt enable bits of INT27 to INT20.

(b) External interrupt 2 flag register (EIF2)

[Bit 1] IE28: Bit 1 is used to enable external interrupt of INT28 to INt2B.This bit enables or disables external interrupt simultaneously for four channels.

[Bit 0] IF20: This bit is the LOW level detection flag bit for INT27 to INT20.

When write

When read


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When the interrupt enable bits (IE27 to IE20) of the external interrupt 2 control register (EIE2) are 1 orwhen the interrupt enable bit (IE28) of the external interrupt 2 control register (EIE2) is 1, if a Low level isinput to the ports respectively corresponding to IE27 to IE20 bits and IE28 bit, the Low-level detectionflag bit is set to 1 and an interrupt request is output to the CPU.

Note: Unlike other resources, even if an interrupt is disabled, external interrupt 2 continues generating aninterrupt until the interrupt source is cleared. Therefore, always clear the interrupt source.


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2.2.9 Time-base timer

• A 21-bit binary counter and a clock with 1/2 frequency of the main clock are provided.

• Four interval times can be selected.

• This function cannot be used when the main clock is stopped.

(1) Registers

Fig. 2.31 Time-base Timer Block Diagram


2-53


Time-base timer control register (TBCR)

[Bit 7] TBIF: Interval timer overflow bitBit 7 clears interval timer overflow flag when writing data.

This bit indicates the occurrence of an interval timer overflow when reading data.

1 is always read when Read-Modify-Write instruction is read.

When the TBIE bit is 1, if the TBIF bit is 1, an interrupt request is output. It is cleared by resetting.

[Bit 6] TBIE: Interval interrupt enable bitBit 6 enables interrupt by interval timer.

[Bit 2] TBC1: Interval time specification bit[Bit 1] TBC0: Interval time specification bitBits 2 and 1 specify the cycle of interval timer.


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[Bit 0] TBR: Time-base timer clear bitBit 0 clears time-base timer.

When this bit is read, 1 is always read.

Time-base timer is cleared when:

1. switched to submode or2. 0 is written at the TBR bit of the time-base timer control register.


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2.2.10 LCD controller/driver

The LCD controller/driver consists of the display controller that generates segment and common signalsaccording to the display data and memory data, and the segment and common drivers that can drive theLCD panel directly.

Its main functions an features are as follows:

1. Direct LCD driving2. Four common outputs (COM0 to COM3) and 32 segment outputs (SEG0 to SEG31)3. 16-byte display data memory4. 1/2, 1/3, or 1/4 selected as duty.5. Main clock (10 MHz) and subclock (32 kHz) selected as drive clock source.6. SEG16 to SEG61 and COM2 to COM3 used as general-purpose ports.

(1) Registers

Fig. 2.32 LCDC Block Diagram


2-56


(a) LCDC control register 1 (LCR1)

[Bit 7] Clock Source Select (CSS): Bit 7 is a frame cycle generation clock select bit.

[Bit 6] LCEN: Bit 6 is a LCD controller/driver operation enable bit at witch mode

[Bit 5] VSEL: Bit 5 is a LCD drive power control bit.

[Bit 4] Blanking (BK): Bit 4 selects display or display blanking.The segment output in display blanking is an non-conforming waveform.

[Bit 3] MS1:[Bit 2] MS0 (Mode Select 1 to 0):Bit 3 and 2 select display mode. The mode is set according to the following table.


2-57

[Bit 1] FP1:[Bit 0] FP0 (Frame Period 1 to 0):Bit 1 and 0 select the LCD clock cycle. The frame frequency is shown below. Calculate the optimumframe frequency and set the register according to the LCD module.

(b) LCDC control register 2 (LCR2)

[Bit 7] COM1:[Bit 6] COM0:Bits 7 and 6 switch COM 2 and 3 to common output or port output, when operating LCDC at 1/2 and 1/3duty.

COM1 and COM0 bits correspond to COM3 and COM2, respectively.

[Bit 5] SEG5:[Bit 4] SEG4:[Bit 3] SEG3:[Bit 2] SEG2:Bits 5 to 2 are segment and port switch bits. These bits correspond to P30/SEG31 to P33/SEG28,respectively.


2-58

[Bit 1] SEG1:[Bit 0] SEG0:Bits 1 and 0 are number-of-segments specify bits.

(3) RAM for display

The LCD controller/driver contains the 16 x 8-bit RAM for generating a segment output signal. Thevalue of this RAM is automatically read in synchronization with the common signal select timing and thewaveform corresponding to this value is output from the segment output pin.

Thirty-two segment signals correspond to 16 locations of the display RAM. Each location bit is in syn-chronization with the common signal select timing: bits 0 and 4 with COM0, bits 1 and 5 with COM1,bits 2 and 6 with COM2, and bits 3 and 7 with COM3. However, at reset, the common outputs and seg-ment outputs 17 through 31 serve as general-purpose I/O ports. At reset, COM0 to COM1 and SEG0 toSEG15 go Low level and are not displayed on the LCD.

The waveform is output from the segment pins in synchronization with the common signal select timing,irrespective of the CPU operation. Therefore, reading and writing from and to the display RAM are pos-sible in any timing.

If SEG16 to SEG31 are used as general-purpose ports, the 8 upper bytes can be used as ordinaryRAM.


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(4) Operation

First, write the data to be displayed by display RAM. Then, set the value corresponding to the LCDpanel to be used to LCR (LCD control register). The LCD drive waveform is output according to the datain the display RAM, when the clock pulse is supplied. A high-speed clock or watch clock can beselected as clock source. The clock source can be switched during the LCD display. However, the dis-play tends to flicker by switching. Therefore, it is best to stop the display by blanking, etc. before switch-ing the clock.

The display drive output has a 2-frame AC waveform. The combination of bias and duty shown belowmay be possible, but do not use 1/2 bias. The table shows a combination example.

The COM2 and COM3 output waveforms are non-conforming waveforms in the 1/2 duty mode. TheCOM3 output waveform is also a non-conforming waveform at 1/3 duty. However, when the port isselected by the COM0 and COM1 bits, it serves as a general-purpose I/O port.

When LCD operation is terminated, both common and segment output waveforms at L level. However,when SEG16 to SEG31 are specified as general-purpose port, segment data are not output.


2-60

(5) LCD drive output waveform

(a) Waveform at 1/3 bias and 1/2 duty

Fig. 2.33 Example of Waveform at Pin Corresponding to the RAM Data for Display


2-61

(b) Waveform at 1/3 bias and 1/3 duty



2-62

(c) Waveform at 1/3 bias and 1/4 duty



2-63

(6) Voltage setting at power pins (V3, V2, V1, and V0) for driving LCD

Set the voltages at the LCD power pins (V3, V2, V1, and V0) as shown below.

A connection example for supplying power to drive the LCD is shown below.

Built-in voltage dividing resistor

The built-in voltage dividing resistors are connected as shown in the right figure.

Writing 1 at the VSEL bit connects the built-in voltage dividing resistors. Therefore, write 1 at the VSELbit to connect the resistors and set 0 to disconnect the resistors.

The V0 pin is connected to the VSS through the transistor within chip. therefore, when using the external

resistance divider, connecting VSS only to the V0 pin cut the current flowing into the resistor when the

LCDC stops.

In the figure, the LCDC enable bit becomes inactive in the LCD stop and CLOCK modes (LCEN = 0).


2-64

Note: When using pins that are also used for ports as SEG/COM output, put the ports into the input state(DDR =0).


2-65

2.2.11 Watchdog timer reset

Either of a signal output from the timer-base timer for counting with the main clock or a signal output formthe watch prescaler for counting with the subclock can be selected as a clock.

(1) Resisters

Fig. 2.36 Block Diagram of Watchdog Timer


2-66

(2) Description of register

• Watchdog timer control register (WDTE)

[Bit 7] CS: Clock source switching bitBit 7 is used to select a count clock from either the watch prescaler or time-based timer.

fch: Main clock frequencyfcl: Subclock frequency

This bit is updated only when bits 3 to 0 are ’0101’ (with the watchdog enabled). So, bit processinginstruction is not allowed for writing. This bit should not be updated when the watchdog timer is cleared.In the submode, the time-base timer is cleared, causing the watchdog timer to malfunction; be sure toselect the watch prescaler when using the submode.

[Bit 3 to 0] WTE3 to WTE0: Watchdog timer control bitBits 3 to 0 controls the watchdog timer.

The watchdog timer can be stopped only by reset. 1111 is read when these bit are read.


2-67


The watchdog timer enables detection of a program malfunction.

• Starting watchdog timerThe watchdog timer starts when 0101 is written at the watchdog timer control bits.

• Clearing watchdog timerWhen 0101 is written at the watchdog timer control bits after start, the watchdog timer is cleared. Thecounter of the watchdog timer is cleared when changing to the standby mode (STOP, SLEEP, CLOCK) orhold mode.

• Watchdog timer resetIf the watchdog timer is not cleared within the time given in the table below, a watchdog timer reset occursto reset the chip internally.

• Stopping watchdog timerOnce started, the watchdog timer will not stop until a reset occurs.


2-68

3.1 Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2 Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3.3 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3. OPERATION


3-2

OPERATION

3-3

3.1 Clock Control Block

This block executes standby operation, stable oscillation time setting, software reset output, clock switchsetting, etc.

(1) Registers

Fig. 3.1 Block Diagrams for Clock Control and Reset Control Blocks


3-4


(a) Standby control register (SMC)

[Bit 7] STP: Stop bitBit 7 specifies switching to the stop mode.

This bit is cleared at reset or stop cancellation.

0 is always read when this bit is read.

[Bit 6] SLP: Sleep bitBIt 6 specifies switching to the sleep mode.

This bit is cleared at reset or stop cancellation.

When 1 is simultaneously written at the STP and SLP bit, the mode switches to the stop mode.

When 1 is simultaneously written at the TMD and SLP bits, the mode switches to the watch mode.


[Bit 5] SPL: Pin state specifying bitBit 5 specifies the external pin state in the watch or stop mode.

This bit is cleared at resetting.

[Bit 4] RST: Software reset bitBit 4 resets the software.


OPERATION

3-5

[Bit 3] TMD: Watch bitBit 3 specifies switching to the watch mode.

Writing at this bit is possible only in the submode (SCS =0). 0 is always read when this bit is read. Thisbit is cleared at an interrupt request or reset.

When 1 is written simultaneously at the STP and TMD bits, the mode switches to the stop mode.

(b) System clock control register (SCC)

[Bit 7] SCM: System clock monitor bitBit 7 checks whether the current system clock is the main clock or subclock.

[Bit 4 and 3] WT1 and WT0: Oscillation stabilization time select bitsBits 4 and 3 select the oscillation stabilization wait time of the main clock.

If the main mode is specified by the system clock select bit (SCS), the mode switches to main modeafter the selected wait time has elapsed.

The initial value of this bit is determined by the mask option. Do not rewrite this bit during the oscillationstabilization period nor rewrite it concurrently with switching from low speed to high speed.

The oscillation stabilization time of the main clock is generated by dividing down the frequency of themain clock. Since the oscillation frequency is unstable immediately after oscillation starts, use theabove table.

[Bit 2] SCS: System clock select bitBit 2 selects the system clock mode.


3-6

[Bits 1 and 0] CS1 and CS0: System clock select bitsIf the main mode is specified by the system clock select bit (SCS), the system clock is as given in thetable below.


(a) Low-power consumption mode

This chip has three operation modes. The sleep mode and stop mode in the table below reduce thepower consumption. In the main mode, four system clocks can be selected according to the systemcondition to minimize power consumption.

Table 3-1 Operating State of Low-power Consumption Modes

− The submode stops oscillation of the main clock.

− The SLEEP mode stops only the operating clock pulse of the CPU; other operations are continued.

− The CLOCK mode stops the functions of all chips other than the special resources.

− The STOP mode stops the oscillation. Data can be held with the lowest power consumption in thismode.

OPERATION

3-7

[1] CLOCK mode

• Switching to CLOCK mode

- Writing 1 at the TMD bit (bit 3) of the SMC register switches the mode to CLOCK mode. Writing isinvalid if 1 is set at the SCS bit (bit 2) of the SYCC register.

- The CLOCK mode stops all chip functions except the watch prescaler, external interrupt, and wake-up functions. Therefore, data can be held with the lowest power consumption.

- The input/output pins and output pins during the CLOCK mode can be controlled by the SPL bit ofthe SMC register so that they are held in the state immediately before entering the CLOCK mode orso that they enter the high-impedance state.

- If an interrupt is requested when 1 is written at the TMD bit, instruction execution continues withoutswitching to the CLOCK mode.

- In the CLOCK mode, the values of registers and RAM immediately before entering the CLOCKmode are held.

• Canceling CLOCK mode

- The CLOCK mode is canceled by inputting the reset signal and requesting an interrupt.

- When the reset signal is input during the CLOCK mode, the CPU is switched to the reset state andthe CLOCK mode is canceled.

- When an interrupt higher than level 11 is requested from a resource during the CLOCK mode, theCLOCK mode is canceled.

- When the I flag and IL bit are enabled like an ordinary interrupt after canceling the CPU executesthe interrupt processing. When they are disabled, the CPU executes the interrupt processing fromthe instruction next to the one before entering the CLOCK mode.

- If the CLOCK mode is canceled by inputting the reset signal, the CPU is switched to the oscillationstabilization wait state. Therefore, the reset sequence is not executed unless the oscillation stabili-zation time is elapsed. The oscillation stabilization time will be that of the main clock selected bythe WT1 and WT0 bits. However, when Power-on Reset is not specified by the mask option, theCPU is not switched to the oscillation stabilization wait state, even if the CLOCK mode is canceledby inputting the reset signal.

[2] SLEEP mode

• Switching to SLEEP mode

- Writing 1 at the SLP bit (bit 6) of the SMC register switches the mode to SLEEP mode.

- The SLEEP mode stops the CPU operating clock pulse; only the CPU stops and the resources con-tinue to operate.

- If an interrupt is requested when 1 is written at the SLP bit (bit 6), instruction execution continueswithout switching to the SLEEP mode. In the SLEEP mode, the values of registers and RAM imme-diately before entering the SLEEP mode are held.

• Canceling SLEEP mode

- The SLEEP mode is canceled by inputting the reset signal and requesting an interrupt.

- When the reset signal is input during the SLEEP mode, the CPU is switched to the reset state andthe SLEEP mode is canceled.

- When an interrupt higher than level 11 is requested from a resource during the SLEEP mode, theSLEEP mode is canceled.

- When the I flag and IL bit are enabled like an ordinary interrupt after canceling, the CPU executesthe interrupt processing. When they are disabled, the CPU executes the interrupt processing fromthe instruction next to the one before entering the SLEEP mode.


3-8

[3] STOP mode

• Switching to STOP mode

- Writing 1 at the STP bit (bit 7) of the SMC register switches the mode to STOP mode.

- The STOP mode varies when the main clock is operating and when the subclock is operating.When the main clock is operating: The main clock stops but the subclock does not stop. All chipfunctions except the watch function stop.When subclock is operating: Both the main clock and subclock stop. All chip functions stop.

- The input/output pins and output pins during the STOP mode can be controlled by the SPL bit (bit5) of the SMC register so that they are held in the state immediately before entering the STOPmode, or so that they enter in the high-impedance state.

- If an interrupt is requested when 1 is written at the STP bit (bit 7), instruction execution continueswithout switching to the STOP mode.

- In the STOP mode, the values of registers and RAM immediately before entering the STOP modeare held.

• Canceling STOP mode

- The STOP mode is canceled either by inputting the reset signal or by requesting an interrupt.

- When the reset signal is input during the STOP mode, the CPU is switched to the reset state andthe STOP mode is canceled.

- When an interrupt higher than level 11 is requested from the external interrupt circuit during theSTOP mode, the STOP mode is canceled.

- When the I flag and IL bit are enabled like an ordinary interrupt after canceling, the CPU executesthe interrupt processing. When they are disabled, the CPU executes the interrupt processing fromthe instruction next to the one before entering the STOP mode.

- Four oscillation stabilization times of the main clock can be selected by the WT1 and WT0 bits. Theoscillation stabilization time of the sublclock is fixed (at 215/fcl -- fcl: frequency of subclock).

- If the STOP mode is canceled by inputting the reset signal, the CPU is switched to the oscillationstabilization wait state. Therefore, the reset sequence is not executed unless the oscillation stabili-zation time is elapsed. The oscillation stabilization time corresponds to the oscillation stabilizationtime of the main clock selected by the WT1 and WT0 bits. However, when Power-on Reset is notspecified by the mask option, the CPU is not switched to the oscillation stabilization wait state evenif the STOP mode is canceled by inputting the reset signal.

[4] Setting low power consumption mode

Note: When the mode is switched from the subclock mode to the main clock mode, insure that the systemclock is switched to the main clock by referring to the system clock monitor bit (SCM bit of the SYCCregister). Then, set each low-power consumption mode.

OPERATION

3-9

(b) State transition diagram


3-10

Internal operating state in each mode

OPERATION

3-11

(4) Single clock

The chip can be used as a single clock by the mask option. The function of the single clock is differentfrom that of double clocks. The single-clock mode cannot be switched to the subclock because it cannotenter the subclock mode. Clock function using the subclock cannot be use. For other functions, see theoperation of the double clock.

When using the chip as the single clock, connect the X0A pin to VSS and keep the X1A pin open.

The state transition diagram when using the single clock and the internal operating state in each modeis as follows:

(a) State transition diagram


3-12

3.2 Reset Operation

When reset conditions occur, the MB89620 series of microcontrollers suspend the currently-executinginstruction to enter the reset state. The contents written at the RAM do not change before and after reset.However, if a reset occurs during writing of 16-bit long data, data is written to the upper bytes and may notbe written to lower bytes. If a reset occurs around write timing, the contents of the addresses being writtenare not assured.

When the reset conditions are cleared, the MB89620 series of microcontrollers are released from the resetstate and start operation after fetching the mode data from address FFFDH, the upper bytes of the reset

vectors from address FFFEH, and the lower bytes from address FFFFH, in that order. Figure 3.2 shows the

flowchart for the reset operation.

Fig. 3.2 Outline of Reset Operation

Table 3-1 indicates the structure of data to be stored in addresses FFFDH, FFFEH, and FFFFH.

OPERATION

3-13

Table 3-2 Reset Vector Structure

• Reset Sources

The MB89650A series of microcontrollers have the following reset sources.

(1) External pin When Low level is input to the RSTX pin.

(2) Specification by software When 0 is written at the RST bit of the system-mode control register.

(3) power-on reset The power is turned on when the power-on reset option is selected.

(4) Watchdog function The watchdog function is enabled by the watchdog-control register andreaccess to this register is not obtained within the specified time.

When the stop mode is canceled and the power-on reset is selected (by option), some time for oscillationstabilization is required to start program execution. However, if Power-on Reset Unavaliable is selected bythe mask option, the oscillation stabilization time is not required in any state, after canceling the external pinreset.


3-14

3.3 Interrupt

The MB89650A has a built-in interrupt controller. The controllers is located between the CPU and variousresources to receive interrupt requests from resources and transfer them to the CPU in the order of priority.It also determines the priority of interrupts of the same level.

(1) Registers

Fig. 3.3 Interrupt Controller Block Diagram

OPERATION

3-15


• Interrupt level setting register (ILRX: Interrupt Level Register X)

The ILRx sets the interrupt level of each resource. the digits in the center of each bit correspond to theinterrupt numbers. Table 3-3 lists the interrupt numbers, vector tables, and interrupt sources.

Table 3-3 Interrupt Number and Vector Table

<Example> The interrupt number #1 (IRQ1) is specified at L11 and L10 bits.


3-16

When an interrupt is requested from each resource, the interrupt controller transfers the interrupt levelbased on the value set at two bits of the ILRx corresponding to the interrupt to the CPU. The relation-ship between two bits of the ILRx and required interrupt levels is shown below.

If more than one interrupt of the same level occurs, the interrupt corresponding to the smallest interruptnumber occurs.


• Interrupt functions

The MB89650A has 12 inputs for interrupt requests from each resource and can set the interrupt levelby 2-bit registers corresponding to each input.

After reset, all interrupts are disabled. Therefore, initialize interrupts in the main program. Eachresource causing interrupts and the interrupt level registers (ILR1 to ILR3) in the interrupt controller cor-responding to these interrupts are to be initialized at this time.

The interrupt levels of all interrupts can be set by the interrupt level registers (ILR1 to ILR3) in the inter-rupt controller. The interrupt level can be set from 1 to 3, where 1 indicates the highest level and 2 thesecond highest. Level 3 indicates that no interrupt occurs. Consequently, interrupts set to this level donot occur.

When an interrupt is requested from each resource, the interrupt controller receives the interrupt andtransfers the value of the corresponding level register to the CPU. At this time, the interrupt to the deviceis processed as follows:

(1) An interrupt source is generated within each resource.

(2) Referring to the interrupt enable bit within each resource, if an interrupt is enabled, an interruptrequest is output from each resource to the interrupt controller.

(3) After receiving this interrupt request, the interrupt controller determines the priority of simultaneously-requested interrupts and transfers the corresponding interrupt level to the CPU.

(4) The CPU compares the interrupt level requested from the interrupt controller with the IL bit in the pro-cessor status register.

(5) As a result of comparison, if the priority of the interrupt level is higher than that of the current interruptprocessing level, the value of the I flag in the same processor status register is checked.

(6) As a result of the check in step (5), if the I flag is enabled for an interrupt, the value of the IL bit is setto the required level. As soon as the currently-executing instruction is terminated, the CPU proceedsto the next interrupt processing.

OPERATION

3-17

(7) The CPU performs the interrupt processing to save the values of the current PC and PS in the stackand fetches the entry addresses of the interrupt processing program from the interrupt vectors. Afterupdating the IL value within the PS to the one currently required, the CPU starts executing the inter-rupt processing routine.

(8) The CPU uses software in the use’s interrupt processing clear the interrupt source generated in step(1) and processes the corresponding interrupt.

(9 The CPU executes the RETI instruction to recover the values of the PC and PS saved in the stackand terminates the interrupt processing.

Note: Unlike the F2MC-8, A and T are not saved in the stack at the interrupt time.

Fig. 3.4 Interrupt-processing Flowchart


3-18

4.1 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2 Special Commands . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.3 Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4.4 Operation Instructions . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.5 Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

4.6 Other Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4. COMMAND


4-2

COMMAND

4-3

4.1 Addressing

MB89650A series microcontrollers contain following 10 addressings.

• Direct addressing

• Extended addressing

• Bit direct addressing

• Index addressing

• Pointer addressing

• General-purpose register addressing

• Immediate addressing

• Vector addressing

• Relative addressing

• Inherent addressing

the details of each addressing are described as follows.

(1) Direct addressing

Direct addressing is indicated as dir in the instruction table. It is used for access the area from 0000H to00FFH. In this addressing, the uppermost byte of the address if fixed at 00H and the lowest byte is speci-fied at the operand.

(2) Extended addressing

Extended addressing is indicated as ext in the instruction table. It is used access the entire area of 64 Kbytes. In this addressing, the uppermost byte of the address is specified at the first operand and the lowestbyte is specified at the second operand.

(3)Bit direct addressing

Bit direct addressing is indicated as dir:b in the instruction table. It is used to bit-by-bit access to the areafrom 0000H to 00FFH. in this addressing, the uppermost byte of the address is fixed at 00H and the lowestbyte is specified at the operand. The location of the bit in the specified address is specified by the threelower bits of the operation code.


4-4

(4) Index addressing

Index addressing is indicated as @IX+off in the instruction table. It is used to access the entire area of 64K bytes. In this addressing, the value of the first operand is sigh-extended and added to the index register(IX) and the result is taken as the address.

(5) Pointer addressing

Pointer addressing is indicated as @EP in the instruction table. It is used to access the entire area of 64 Kbytes. In this addressing, the value of the extra pointer (EP) is taken as the address.

(6) general-purpose register addressing

General-purpose register addressing is indicated as RI in the instruction table. It is used to access the reg-ister bank area. In this addressing, the uppermost byte of the address is fixed at 01 and the lowest byte iscreated from the value of the register bank pointer (RP) and the three lower bits of the operation code.Access is made to this address.

(7) Immediate addressing

Immediate addressing is indicated as #imm in the instruction table. It is used when immediate data isneeded. In this addressing, the operand is taken as immediate data. Selection of byte or word is deter-mined by the operation code.

(8) Vector addressing

Vector addressing is indicated as #k in the instruction table. It is used to branch to the subroutine addressstored in the table. In this addressing, information of #k is contained in the operation code and the tableaddresses shown below are created.

COMMAND

4-5

(9) Relative addressing

Relative addressing is indicated as rel in the instruction table. It is used to branch to the 128-byte areaacross the program counter (PC). In this addressing, the vale of the operand is added with a sigh to the PCand the result is stored in the PC.

(In this example, a jump is made to the address where the operation code BNE is stored, resulting in theinfinite routine.)

(10) Inherent addressing

Inherent addressing has no operand in the instruction table. It is used when performing the operationdetermined by the operation code. In this addressing, the operation varies with every instruction.


4-6

4.2 Special Commands

(1) JMP @A

This instruction causes a branch to the address where the value of the accumulator (A) is taken. With Njumps arranged in a table form, select either one of the values, transfer it to A, and execute this instructionto perform the N-branch processing.

(2) MOVW A, PC

This instruction performs the operation opposite to JMP @A. That is, the value of the PC is stored in theaccumulator (A). Execute this instruction within the main routine so that the specific subroutine can becalled. By checking that the value of the A is the predetermined one in the subroutine, it is possible to iden-tify that a branch is not made from the unexpected address and infer a program malfunction.

The value of the accumulator (A) when this instruction is executed is not identical to the value of theaddress where the operation code of this instruction is stored, but is identical to the value of the addresswhere the operation code of the next instruction is stored. Therefore, in the above example, the value1234H stored in the A agree with the value of the address where the operation code next to MOVW A, PCis stored.

(3) MULU A T

This instruction multiplies 8 bits of the AL by 8 bits of the TL as unsigned data and stores the result of 16-bitlength into the accumulator (A). The value of the T is unchanged. The value of the old AH or TH is notused for operation. Since the flag is unchanged, care should be taken for branching by the result of multipli-cation or other cases.

COMMAND

4-7

(4) DIVU A

This instruction divides 16 bits of the T by 8 bits of the AL as unsigned data and stores the result as 8 bitsinto the AL and the remainder as 8 bits into the TL. Both the values of the AH and TH go to 0. The previousvalue of the AH is not used for operation. If the data exceeds 8 bits, the obtained result is not assured.Since the flag is unchanged, care should be taken for branching by the result of division or other cases.

(5) XCHW A, PC

This instruction exchanges the value of the accumulator (A) with that of the program counter (PC). As aresult, a branch is made to the address indicated by the previous value of the A. The current value of the Aagrees with the value of the address next to the one where the operation code XCHW A, PC is stored. Thisinstruction is especially effective in specifying a table in the main routine and using it in a subroutine.

The value of the accumulator (A) when this instruction is executed is not identical to the value of theaddress where the operation code of this instruction is stored, but is identical to the value of the addresswhere the operation code of the next instruction is stored. Therefore, in the above example, the value1235H stored in A agree with the value of the address where the operation code next to XCHW A, PC isstored. Thus, the value of A is not 1234H but 1235H.

This command is used as follows in assembler notation.


4-8

(6) CALLV #k

This instruction is used branch to a subroutine address stored in the table. In this addressing, informationabout #k is contained in the operation code and the table addresses shown below are created. Save thevalue of the current program counter (PC) in the stack and then branch to the addresses given in the table.Because of the 1-byte instruction, use of this instruction for a frequently used subroutine enables sizereduction of the entire program.

COMMAND

4-9

4.3 Transfer Instructions

Notes: 1. In byte transfer to A, T ← A is only for low bytes.

2. Operands for two or more operand instructions should be stored in the order designated in

MNEMONIC (opposite order to F2MC-8 family).


4-10

4.4 Operation Instructions

COMMAND

4-11

4.5 Branch Instructions


4-12

4.6 Other Instructions

5. MASK OPTIONS


5-2

MASK OPTIONS

5-3

Table 5-1 Mask Options

*1: Values when FC = 10 MHz.

*2: The products with the built-in stepup circuits only allow for the use of 1/3 bias; 1/2 duty cycle cannot beused.

Note: the reset signal is input asynchronously with the internal clock, irrespective of the availability ofpower-on reset.

NO.Type

MB89653AMB89665AMB89656AMB89657A

MB89P657A MB89PV650A

Specification method Select when ordering mask Set by EPROM writer Cannot be set

1

Pull-up resistorP00 to P07, P10 to P17P20 to P22, P24 to P26P30 to P37, P40 to P47P60 to P67, P70 to P75P80 to P81

Can be selected for each pin

Can be selected for each pin (However, following four bits should be selected simulta-neously: P14 to P17, P40 to P43, and P40 to P47.)(Only P75 to P70 do not have pull-up resistor.)

Pull-up resistor not provided

2Power-on resetPower-on reset availablePower-on reset not available

Can be selected Power-on reset available Power-on reset available

3

Oscillation stabilization time initial value selectionCrystal oscillator

218/Fc (approx. 26.2 ms*1)Ceramic oscillator

213/Fc (approx. 26.2 ms*1)

Can be selected 218/Fc (approx. 26.2 ms*1)Fixed to 218/Fc

(approx. 26.2 ms*1)

4Clock1/clock2 selectionClock1Clock2

Can be selected Can be selectedCannot be selectedUse only double clocks

5

Selection of internal stepup

circuit*2

No stepup circuitStepup circuit(Switching segment output)16 segments: select fromP30 to P37, P40 to P4720 segments: select fromP30 to P37, P40 to P4324 segments: select fromP30 to P3728 segments: select fromp30 to P3332 segments: No portselection

Can be selected

Can be selected from the fol-lowing six options.

- 101: No stepup circuit- 102: 16 segments- 103: 20 segments- 104: 24 segments- 105: 28 segments-106: 32 segments

Fixed to no stepup circuit


5-4

6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.2 Memory Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.3 Writing to PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.4 Setting PROM Option . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6. MB89P657A SPECIFICATION


6-2

MB89P657A SPECIFICATION

6-3

The MB89P657A is a PROM for the MB89650A series.

6.1 Features

• 32-byte PROM mounted

• Option setting possible by EPROM writer

• Equivalent to functions of MBM27C256A when EPROM mode selected (writing by ROM writer)


6-4

6.2 Memory Space

The memory space in each mode such as PROM32K and option PROM is given below.

6.2.1 ROM area for MB89650A series and PROM area when MB89P657A in EPROM mode

In software development using the MB890657A, the available PROM area varies with each machine. Thecorrespondence between the ROM area for MB89650A series and the PROM area when the MB89P657Ais in the EPROM mode is as follows.

MB89P657A SPECIFICATION

6-5

6.3 Writing to PROM

Use of a dedicated conversion socket permits writing to the MB89P657A with a general-purpose EPROMwriter. This allows the MB89P657A to have the functions equivalent to those of the MBM27C256A.

The procedure for writing to the PROM when the ROM area in the single-chip operation is 32K bytes(8006H to FFFFH) is as follows:

Writing

(1) Set the EPROM writer to the write mode of the MBM27C256A.

(2) Load program data into the addresses 0006H to 7FFFH of the EPROM writer.(Addresses 8006H to 7FFFH in single-chip operation correspond to the addresses 0006H to 7FFFH inthe EPROM mode.)Load the option information into the addresses 0000H to 0005H of the EPROM writer.(See 4 for the correspondence of each option.)

(3) Use the EPROM writer to write data to the addresses 0000H to 7FFFH.

Note: The ROM area varies with each type. Therefore, when writing to the PROM, see 2.1 to change theaddresses where program data is loaded in step (2).


6-6

6.4 Setting PROM Option

Writing is performed in the same manner as for the PROM. The PROM option can be set by writing the val-ues to the addresses given in the memory map. The relation between each bit and options is given in thebit map below.

Bit Map for PROM Option

7.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.2 LCD Pins and Port pins . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.3 Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.4 Selection of Pull-up Option . . . . . . . . . . . . . . . . . . . . 7-6

7.5 I/O Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.6 Reference Voltage and X2/X3 Stepup Circuit . . . . . . 7-9

7. SPECIFICATIONS FOR THE INTERNAL STEPUPCIRCUIT


7-2

SPECIFICATIONS FOR THE INTERNAL STEPUP CIRCUIT

7-3

7.1 General Description

The MB89650A series contains an optional type in which the stepup circuit is internally provided (except inthe PV products) for the voltage increase by a factor of two or three with connection of the external terminal.Selection of stepup circuit type gives rise to part of the terminal functionality being differentiated from therest of the series and limitation to the selection of the pullup resistors. When using the stepup circuit, besure to select the dual-clock system product. The description of the difference between the products withand without the stepup circuit follows:


7-4

7.2 LCD Pins and Port pins

The products without the stepup circuit allow the selection of SEG output pin of the LCD and I/O ports bysoftware while the products with the stepup circuit is provided with the dedicated pins along with the avail-ability of selection by way of software. So, it is to be predefined whether they are to be used exclusively asSEG output of LCD or I/O port. Five types of selection are available as the SEG output and the number ofCOM output pins are fixed to four, allowing for 1/2 to 1/4 duty factor.


7-5

7.3 Unused Pins

As for the unused pins of the SEG output pins, use software to select the SEG output to use them as open.


7-6

7.4 Selection of Pull-up Option

There are some pins, in the stepup circuit type products, which do not allow for the selection of the pull-upresistor, as shown below.

* With the MB89P657A, selection can be made through writing in the PROM.

With the masked products, mask option can be used for selection.

• If a pin is selected as LCD, leave it without pull-up resistors in the masked products.


7-7

7.5 I/O Port Functions

The stepup circuit type products dictate the predetermination of the LCD pin and port pin; the functions forthe I/O ports are as follows.

Fig. 7.1 When LCD is Selected (P30 to P37/P40 to P47/P80 to P81)


7-8

Fig. 7.2 When Port is Selected (P30 to P37/P40 toP47)

Fig. 7.3 Pins for the Stepup Circuit (P82 to P83)


7-9

7.6 Reference Voltage and X2/X3 Stepup Circuit

Connect the reference voltage to the V1 pin as illustrated below.

The stepup circuit can be implemented by making the connection as below to obtain the 2 x reference volt-age and 3 x reference voltage, derived from the 32 kHz input clock and reference voltage. The pin numberin parentheses corresponds to that of SQFP-100.

The MB89P657A is a PROM for the MB89650A series.


7-10

1. Pin State in SLEEP, STIP, RESET . . . . . . . . . . . . . App.-3

2. I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . App.-4

3. F2MC-8L Instruction Map . . . . . . . . . . . . . . . . . . . . App.-6

APPENDIX


App.-2

APPENDIX

App.-3

1. Pin State in SLEEP, STOP RESET

Notes:

* In the STOP mode, the X0A pin enters Hiz and the X1A pin becomes High output, irrespective of thesetting conditions of the SPL bit. The states of other pins are the same as those in the CLOCK mode.

** In the STOP mode (SPL = 1) and CLOCK mode (SPL = 1) with P30 to P37, P40 to P47, and P80 to P81used as segment and common outputs, each pin enters the previous state (segment and common out-puts).

*** Pins for which Pull-up Resistor Available is specified by the mask option enter the pull-up state.


App.-4

2. I/O Map

APPENDIX

App.-5

(Continued)


App.-6

3. F2MC-8L Instruction Map

f2mc-8l family microcontrollers

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