5 + 5
DESCRIPTION
A possible T1 trigger architecture ( 1a). 1 fiber = 16 Trigger bits Multiplicity encoded in 4 (5) bits. 10. 10. 5 + 5. OptoRx 1. 4 bit * 10 out of 64. +. To LONEG Inputs. 40 out of 64 lines. Merger. OptoRx 2. > L1 . SL. +. 32 + 12 diff. lines. - PowerPoint PPT PresentationTRANSCRIPT
Saverio MINUTOLI - Technical Board 1
10
10
5+5
1 fiber = 16 Trigger bits Multiplicity encoded in 4 (5) bits
> L1 (4bit*5 + 4bit*5) out of 64
4bit * 10 out of 64
2bit * 10 out of 64
+
OptoRx 1
OptoRx 3
+
OptoRx 2 SL
SL
S-Link 64Connectors
To LONEGInputs
A possible T1 trigger architecture (1a).
+
L1 + trigger code
Merger40 out of 64 lines
32 + 12 diff. lines
2 May 2011
Saverio MINUTOLI - Technical Board 2
10
10
5+5L1 (2bit*5 + 2bit*5) out of 64
2bit * 10 out of 64
2bit * 10 out of 64
< +
OptoRx 1
OptoRx 3
+ >
OptoRx 2 SL
SL
S-Link 64Connectors
To LONEGInputs
+ >
L1 + trigger code
Merger20 out of 64 lines
1 fiber = 16 Trigger bits Multiplicity encoded in 5 bits Majority 3 Thresholds encoded in 2 bits0 < Thr_1 < Thr_2 < Thr_3 < 16.
32 + 12 diff. lines
A possible T1 trigger architecture (1b).
2 May 2011
Saverio MINUTOLI - Technical Board 3
12
12
3+3
12 fibers = 3 * 4 Layers (1 to 4) @ full resolution, 8 Trigger bits/VFAT 16 bits/CSC3 fibers = 3 * 1 Layer (5) @ half full resolution, 4 Trigger bits/VFAT 8 Tbits/CSC 24 Tbits + 3 DAV signals = 27 lines
12 fibers = 3 * 4 Layers (1 to 4) @ full resolution, 8 Trigger bits/VFAT 16 bits/CSC3 fibers = 3 * 1 Layer (5) @ half full resolution, 4 Trigger bits/VFAT 8 Tbits/CSC 24 Tbits + 3 DAV signals = 27 lines
MergerFPGA
64 = 27 + 27 + 10 free
27
27
16..
16..
+x<>
OptoRx 1Tracks
Tracks
OptoRx 3
<>x+
OptoRx 2 SL
SL
S-Link 64Connectors
To LONEGInputs
32 + 12 diff. lines
A possible T1 trigger architecture (2).
2 May 2011
Saverio MINUTOLI - Technical Board 4
S P #1
S P #12
Fibers In
12
16 Tbit
16 Tbit
FiberReceiver
GlitchFilter
16
16
TbitMask
En/Dis
16
16
ChamberMultiplicity
Comp CLA
Comp CLA
4
4
T1 trigger (1a) implementation.
En/Dis
OptoRx FPGA
2 May 2011
Saverio MINUTOLI - Technical Board 5
LayerMajority Decider
4 * 10
LayerMultiplicity
Comp CLA
Comp CLA
T1 trigger (1a) implementation.
Merger FPGA
4 * 10
4 * 10
Comp CLA
OR1
OR2
OR3
>+ L1
Trigger code
To LONEG
Option 1
2 May 2011
Saverio MINUTOLI - Technical Board 6
ChamberMajority Decider
4 * 10
LayerMultiplicity
Comp CLA
Comp CLA
T1 trigger (1a) implementation.
Merger FPGA
4 * 10
4 * 10
Comp CLA
OR1
OR2
OR3
>+ L1
Trigger code
To LONEG
Bypassed Sextant Roads
Option 2
2 May 2011
Saverio MINUTOLI - Technical Board 7
S P #1
S P #12
Fibers In
12
16 Tbit
16 Tbit
FiberReceiver
GlitchFilter
16
16
TbitMask
En/Dis
16
16
ChamberMultiplicity
Comp CLA
Comp CLA
4
4
T1 trigger (1b) implementation.
En/Dis
OptoRx FPGA
2
2
ChamberMajority
2 May 2011
Saverio MINUTOLI - Technical Board 8
Decider2 * 10
T1 trigger (1b) implementation.
Merger FPGA
2 * 10
2 * 10
OR1
OR2
OR3
L1
Trigger code
To LONEG
2 May 2011