5 m16c.ppt

February 2005

2

Each M16C/62-group product has a total of eleven 16-bit timers (5 inputs and 6 outputs). All timers are connectable in cascades. Various operating modes are available.

• Event counter• Two-phase pulse signal processing• Pulse-period measurement• Pulse-width measurement

InputTimer A

OutputTimer B

• Single-shot timer• 8-bit PWM output• 16-bit PWM output• Three-phase PWM output

M16C

Highly Functional Timers

3

3-Phase Inverter PWM Output (Example of Application to a Motor-Control System)

2-phase pulse-signal processing

High-speedA/D converter

3-phase inverterPWM output

Phase detector(resolver)

Motor driver

Motor

U_U

V

W

_V

__W

Pha

se A

Pha

se B

Current monitoring

Encoder signal input

M16C NMIEmergency stop

signal

Using Timers to Control a 3-Phase Inverter

Position detection

4

The M16C/62 group has 5 serial I/O channels; three act as either UARTs or clock-synchronous modules while two are clock-synchronous only. Three channels of clock-synchronous serial I/O support special communications formats (e.g. I2C-bus subset).

UART/clock-synchronous serial I/O: 3 ch - Character length: 7/8/9 bits, as selected

Parity bit: selectable as odd, even, or noneStop bit: 1 or 2 bits, as selected

- 8-bit clock synchronous - I2C-bus subset operation is available

Clock synchronous serial I/O only: 2 ch - 8-bit clock synchronous

MCU

MCU

MCU

MCU

MCU

SI03

SI04

UART2

UART0

UART1

M16C

Bi-directional data communications are possible.

UART/Clock-Synchronous Serial I/O

5

High-Speed A/D Converter with Sample/Hold

All series in the M16C family include high-speed A/D converters Conversion speed - 10 bits: 3.3 s - 8 bits: 2.8 s (when A/D clock rate = 10 MHz) Conversion precision: 3 LSB (in the 10-bit case)

Comparator

P100/AN0

P101/AN1

P102/AN2

P103/AN3

P104/AN4

P105/AN5

P106/AN6

P107/AN7

P00/AN00

P01/AN01

P02/AN02

P03/AN03

P04/AN04

P05/AN05

P06/AN06

P07/AN07

P20/AN20

P21/AN21

P22/AN22

P23/AN23

P24/AN24

P25/AN25

P26/AN26

P27/AN27

ANEX0

ANEX1

1

*An even higher-speed A/D converter is in planning (10 bits: 1.65 s, 8 bits: 1.4 s)

M16C/26: Up to 8 channels M16C/10: Up to 14 channelsM16C/62P: Up to 26 channelsM32C/83: Up to 34 channels

6

CRC (Cyclic Redundancy Check) Operation

The M16C/62P, M32C/80, and M16C/80 incorporate a CRC-operation module for data correction by hardware. This function can be used to detect errors during communications and correct errors during file-system usage.

CRC provides enhanced reliability for e.g. communications data. - CRC is calculated in 2 cycles by hardware. - A polynomial expression is used: X16 + X12 + X5 + 1 (CCITT-compliant). - Stronger error detection than parity or checksum.

Sent data 012

CRC 0CRC 1

Calculation in 2 cycles

Data input

CRC input register

CRC-code generatorX16 + X12 + X5 + 1

CRC data register

16-bit code

8-bit dataRAM

7

X/Y Data Converter

The M32C/80 and M16C/80 incorporate a hardware X/Y data converter for the re-allocation of data. Use this module to convert image data such as monochrome bitmaps.

Quickly inverts, rotates, enlarges, and reduces image data.

Enlargement Reduction

Faster image recognitionNumber of bits in x-axis direction

Number of bits in y-axis direction

Inversion (reversal)

8

… allows simultaneous connection of 5-V type and 3-V type peripheral ICs without the need for an external circuit

While the supply voltages of high-speed memory units, etc., are falling, many other ICs such as drivers still require 5-V interfaces.

M16C/62P

P6 to P10, P11, P14: 2.7 V <= VCC1 <= 5.5 VP0 to P5, P12, P13: 2.7 V <= VCC2 <= VCC1

M16C/62P

3.3 V (VCC2) 5 V (VCC1)

3-V IC 5-V IC

3.3 V 5V

3-V I/F 5-V I/F

Note: M16C/62P, M16C/6N4,5 and M32C/84, 85 have this function.

Dual Power-Supply Option (5 V and 3 V)

9

No need for external RESET ICs Software enables and disables detection of brownout interrupts; the detector doesn’t require an external circuit (detection is especially handy for e.g. saving data in high-speed flash memory). Internal RESET circuit (software-controlled) This prevents malfunctions which would otherwise arise if the voltage fell below the guaranteed operating range. RAM-retention voltage flag (enabled or disabled by software) Judge whether or not the data in RAM has been retained then select a warm start or cold start.

5.0

4.0

2.7

2.0

0

RESET

RESET released

Brownout interrupt

RAM-retentionvoltage flag

Reset releasedVcc

RESET pin

Vcc

0.8

Voltage-detection functionstarted by S/W

(Cold start)

(Warm start)

(Normaloperation)

CPURESET

IC

CPURESET

IC

RESETcircuit

No external RESET ICs

Note: M16C/26, 28, M16C/62P, M16C/6N4,5 and M32C/84,85 have this function.

Brownout Reset Function (limited to certain products)

10

Problems with conventional WDT When the clock source for the microcomputer stops, the WDT stops. If the MCU crashes because of a glitch while in a low-power mode

(WAIT or STOP), the clock stops, and so does the WDT.

Advanced WDT (upgraded watchdog function offers stronger fail-safe mechanisms) Oscillation-stopped detection circuit (OSCMON) monitors the external

clock and supplies the on-chip oscillator clock to the system (CPU and WDT) if the external oscillation stops.

Supplying the on-chip oscillator clock to the WDT when the external clock stops guarantees WDT operation by ensuring that it leads to a proper system reset.

This also guarantees independence of WDT operation by isolating it from MCU malfunctions that affect the external clock, ensuring proper system resets.

Note: M16C/62P, M16C/6N4,5 and M32C/84,85 have this function.

(limited to certain products)

New Watchdog Timer (WDT)

11

*1 cycle: 62.4 ns

*2 cycles: 93.6 ns

*3 cycles: 124.8 ns

From 1 to 6 bus cycles (of waiting)

BCLK

CS

DATA (READ)

RD

ADDRESS

DATA (WRITE)

WR

Select from a wider range of wait cycles.

Time waiting (at 32 MHz)

Extended function

Useful for access to external ASICs and slow memory units during high-speed(32 MHz) operation

Note: M32C/84,85 have this function.

*4 cycle: 156.0 ns

*5 cycle: 187.2 ns

*6 cycle: 218.4 ns

Extended External-Bus Access Function

12

The microcomputer supports the page-mode function of single flash-memory units. Available for high-speed reading of external flash memory data.

BCLK

ADDRESS

DATA (READ)

CS (CE)

RD (OE)

FFF00016 FFF00116 FFF00216

First address access Continuous address access

1+ 1 to 4 settable1+1 to 3+6 settable

Note: M32C/84, 85 have this function.

Page-Mode Control Function

13

Waveform modulation and demodulation in compliance with IrDA ver. 1.0

IrDA frame: 1-bit start-bit 0, 8-bit data, 1-bit stop bit 1

Sending: The UARTs data-modulation circuit converts data from the UART into IrDA-frame waveforms for output.When data is 0: “H” is output in 3/16 of one bit-widthWhen data is 1: “L” only

Receiving: The demodulation circuit converts IrDA frame waveforms to data for input to the UART.

Transfer speed: Selectable as 2400 bps, 9600 bps, 19200 bps, 38400 bps, 57600 bps, or 115200 bps

IrDA Block Diagram

Sendingpart

Receivingpart

TxD

RxD

UART0

IrDA control

IrDA frame waveform

0 1 0 0 11 0 0 11

Startbit

Stopbit8-bit data

1-bit wide3/16-bit wide

or 1.6 us

UART

IrDA

Send-ing

Receiv-ing

Implemented by adding an IrDA waveform-generationcircuit to the UART0 function

Note: M32C/87 have this function.

Optional

IrDA demodulationcircuit

IrDA modulationcircuit

New UART Function (IrDA Function)

14

Program Copy-GuardPreventing external reading of the single-chip microcomputers internal

memory in turn prevents illegal copying of important programs and internal data

(both FLASH and MASK versions).

ROM-Code Protection for Flash MemoryReading or reprogramming of internal flash memory is prevented by the

ROM-code protection bit during parallel reprogramming (protection bit’s value

can only be change during serial reprogramming).

ID-Code Protection for Flash MemoryIn serial reprogramming, an ID code is forwarded to the chip along with the

serial programmer. Only when the ID code matches that written to the chip

can commands be accepted. This prevents illegal access (repeated trying of

ID codes is not possible).

01000100101010011101010101001001

Prevents illegal copying and reprogramming of memory contents by third parties

Internal Memory-Protection Functions

15

Features of M16C/26-, 28-, 29-Group Products

1 ch (M16C/29)-CAN 2.0B

4 internal circuits ( XIN, XCIN, on-chip oscillator, PLL)

32 KB/2 KB (M16C/28), 48 KB/4 KB, 64 KB/4 KB,96 KB/8 KB (M16C/29)24 KB/1 KB, 32 KB/1 KB, 48 KB/2 KB, 64 KB/2 KB ( Mask ROM/RAM )

Operating time 16 mA (typ.) @ 20 MHz, 0 wait cyclesWaiting time 1.8 A (typ.)Stopping time 0.7 A (typ.)

Current Drawn

UA(S)RT/SIO 2 ch, SIO 2 chUA(S)RT/SIO/I2C-bus subset/IEBus subset 1 chHardware I2C-bus subset 1 ch

10-bit x 27 ch (When M16C/29, M16C/28: 24 ch)

80-pin LQFP64-pin LQFP

Brownout detection (optional)Reset Circuit

71 pins

48-pin LQFP (40-pin LQFP),42-pin SSOP (M16C/26A only)

Package

4 internal circuits ( XIN, XCIN, on-chip oscillator,PLL(M16C/26A only) )Clock-Generator Circuit

39 pins (M16C/26A,M16C/26-38ch)General I/O Port

4 inputsKey-Input Interrupt

Input capture: 8 chOutput compare: 8 ch-Sophisticated Timer

16-bit timer 8 ch ( timer A: 5 ch, timer B: 3 ch), watchdog timerTimer

10-bit x 12 ch (When M16C/26A, M16C/26: 8 ch)A/D Converter

UA(S)RT/SIO: 2 chUA(S)RT/SIO/I2C-bus subset /IEBus subset 1 chSerial I/O

M16C/28: (48+4) KB/4 KB, (64+4) KB/4 KB, (96+4) KB/8 KB,M16C/29: (64+4) KB/4 KB, (96+4) KB/4 KB, (128+4) KB/8 KB

(24+4) KB/1 KB, (32+4) KB/1 KB,(48+4) KB/2 KB, (64+4) KB/2 KB

Memory Configuration ( Flash ROM/RAM )

2.7 to 5.5VPower-Supply Voltage

50 ns (f(XIN) = 20 MHz, Vcc = 3.0 V to 5.5 V)100 ns (f(XIN) = 10 MHz, Vcc = 2.7 V to 3.0 V)

Minimum Instruction-Execution Time

M16C/28, /29 GroupM16C/26,/26A Group

CRC 1 ch (only M16C/26A) 1 ch (only M16C/29)

16

M16C/26, 28, 29 Groups: New Functions

Input capture, output compare (8 ch) Hardware I2C

New functions: M16C/26A Digital de-bouncing function Variable on-chip oscillator frequency On-Chip oscillator startup after reset Three-phase motor-position data retention One-shunt-current measurement

New Functions: M16C/28, 29

New function: M16C/26

(inheritance function from M16C/62P)

New reset function (optional) Oscillation-stopped detection circuit New Watch dog timer (non-stop system clock): the Watch dog timer is driven by the on-chip oscillator Safety feature (H/W reset by watchdog timer selectable): clock stops -> after recovery, select frequency division by 8 Lower-capacity flash-memory block for data storage “Virtual E2PROM” (optional)

Flash erase-suspend function

17

Roadmap of the M16C/30 Series

NEW

Reduced peripheral functions

Slim ROM/RAM

Mask

16 MHz @4.2-5.5 V10 MHz @2.7-5.5 V

M16C/3016 MHz @3.0-3.6 V7 MHz @2.4-3.6 V 7 MHz [email protected] V

*

M16C/3032 KB/2 KB

100P6Q-A/100P6S-A

100P6Q-A/100P6S-A

M16C/3064 KB/2 KB

M16C/30128 KB/3 KB

M16C/3096 KB/3 KB

M16C/30L64 KB/2 KB

M16C/30L96 KB/3 KB

M16C/30L128 KB/3 KB

M16C/30P128 KB/5 KB

M16C/30P192 KB/6 KB

*

*: under development

100P6Q-A/100P6S-A

18

Peripheral functions: - 16-bit timer: 3 output, 2 input - Serial I/O (clock-synchronized or UART): 3 channels - DMAC: 1 channel - A/D converter: 10-bit x 10 channels - Communications: Subset of IEBus and I2C-bus - Watchdog timer: 1 channel - Programmable I/O-port pins: 87 - Dedicated input pin: 1 - Pull-up resistor: All ports - Clock-generating circuit: 2 circuits (XIN, XCIN)

- Package: 100-pin LQFP, 100-pin QFP

Features of M16C/30, 30L-Group Products

CPU: M16C/60-series 16-bit CPU coreMax. operating frequency:

16 MHz, no waitMin. instruction execution time:

62.5 ns

Power-supply voltage5 V single power supply: M16C/30

4.2 V to 5.5 V (at 16 MHz/no wait)2.7 V to 5.5 V (at 10 MHz/1 wait)

3 V single power supply: M16C/30L3.0 V to 3.6 V (at 16 MHz/no wait)2.4 V to 3.6 V (at 7 MHz/1 wait)

Internal memory: MASK (only)ROM 128 KB / RAM 3 KBROM 96 KB / RAM 3 KBROM 64 KB / RAM 2 KBROM 32 KB / RAM 2 KB (5 V version only)

19

Peripheral functions: - 16-bit timer: 3 output, 3 input - Serial I/O (clock-synchronized or UART): 3 channels - DMAC: 2 channel - A/D converter: 10-bit x 12 channels (+- 5 LSB) - Communications: Subset of IEBus and I2C-bus - Watchdog timer: 1 channel - Programmable I/O-port pins: 88 - Dedicated input pin: 1 - Pull-up resistor: All ports - Clock-generating circuit: 2 circuits (XIN, XCIN)

- Single Chip operation only - Package: 100-pin LQFP, 100-pin QFP

Features of M16C/30P Group Products

CPU: M16C/60-series 16-bit CPU coreMax. operating frequency:

16 MHz, no waitMin. instruction execution time:

62.5 ns

Power-supply voltage5 V single power supply: M16C/30

4.2 V to 5.5 V (at 16 MHz/no wait)2.7 V to 5.5 V (at 10 MHz/1 wait)

Internal memory: MASK (only)ROM 128 KB / RAM 3 KBROM 192 KB / RAM 6 KB

20


Wide-range op. voltageRich variety of memoryPLL & high speed

CAN module included

*: under development**: in planning (Jan. 9, '04)Mask

Flash

100P6S-A/100P6Q-A

80P6S-A/100P6S-A/100P6Q-A/100PFB-A

80P6S-A/100P6S-A/100P6Q-A/128P6Q-A

M16C/62P24 MHz PLL @3-5 V10 MHz @2.7-5.5 V

80P6S-A/100P6S-A/100P6Q-A/100PFB-A

80P6S-A/100P6S-A/100P6Q-A/128P6Q-A

80P6S-A/100P6S-A/100P6Q-A

M16C/6NA, BCAN x 1 or 2 ch16 MHz @5 V

M16C/6N4, 5CAN x 1 or 2 ch20 MHz @5 V

100P6S-A (100P6Q-A: in planning) 100P6S-A (100P6Q-A: in planning)

100P6S-A (100P6Q-A : in planning)100P6S-A (100P6Q-A: in planning)

**

M16C/62P64 KB/4 KB

**

Note: The M16C/62A and M16C/62M are different chips: whichever one better suits the layout is selected.

M16C/62P48 KB/4 KB

M16C/62PROM less/

10 KB

M16C/62PROM less/

4 KB

M16C/62P256 KB/12 KB

M16C/62P192 KB/12 KB

M16C/62P128 KB/10 KB

M16C/62P96 KB/5 KB

M16C/62N256 KB/20 KB

M16C/62P320 KB/31 KB

M16C/62P320 KB/24 KB

M16C/62P320 KB/16 KB

M16C/62P256 KB/20 KB

M16C/62N256 KB/12 KB

80P6S-A/100P6S-A/100P6Q-A

M16C/62P512 KB/31 KB

M16C/62P384 KB/31 KB

M16C/62P384 KB/24 KB

M16C/62P384 KB/16 KB

M16C/62N128 KB/10 KBM16C/62N

16 MHz @3.0-3.6 V10 MHz @2.2-3.6 V (MASK version)

M16C/62A,MA: 16 [email protected]–5.5 VA: 10 [email protected]–5.5 VM: 10 [email protected]–3.6 VM: 7 [email protected]–3.6 V (1 wait cycle)

M16C/6NB128 KB/5 KB

M16C/6NA256 KB/10 KB

M16C/6NA128 KB/5 KB

M16C/6N5128 KB/5 KB

M16C/6N4256 KB/10 KB

M16C/6N4128 KB/5 KB

**M16C/6N5

128 + 4 KB/5 KB

*M16C/6N4

256 + 4 KB/10 KB

*M16C/6N4

128 + 4 KB/5 KB

*

M16C/6NB128 KB/5 KB

M16C/6NA256 KB/10 KB

M16C/6NA128 KB/5 KB

M16C/62P128+4 KB/10 KB

M16C/62P256 + 4 KB/20 KB

M16C/62P384 + 4 KB/31 KB

M16C/62P512 + 4 KB/31 KB

**

M16C/62P64 + 4 KB/4 KB

M16C/62AROM less/

3 KB

M16C/62A64 KB/4 KB

M16C/62A96 KB/10 KB

M16C/62A,M256 KB/20 KB

M3062GF8N64 KB/8 KB

M16C/62N256 KB/20 KB

M16C/62A32 KB/3 KB

M16C/62A96 KB/5 KB

M16C/62A,M128 KB/10 KB

M16C/62A,M256 KB/20 KB

M16C/62AROM less/

10 KB

M16C/62A64 KB/10 KB

M16C/62A128 KB/5 KB

M16C/62A,M128 KB/10 KB

M16C/62N128 KB/10 KB

21

Memory and Packages

Introduction to the M16C/62P

: Mask, 128-pin

: Mask, 100-pin

: Mask, 80-pin ** : Flash, 80-pin **

: Flash, 100-pin

: Flash, 128-pin

3

10

12

16

ROM Less 64 96 128 256ROM(KB)

RAM(KB)

24

31

384 512

4

48

5

192 320

20

Flash version: Data flashMemory of 4 KB is added

22

Key Features of the M16C/62P Group

3-V or 5-V peripheral power-supply can be used, allowing

direct connection of 3-V and 5-V devicesHigh-speed operation (24 MHz@3–5 V, on-chip PLL);1.5-

times faster than the M16C/62A/N Inherits features of the M16C/62A/M/N for applicability to a

wide range of fieldsHigh reliability provided through the incorporation of an

enhanced watchdog timer, oscillation-termination detector,

and a new reset circuitFrom 0 to 3 wait cycles can be inserted allowing easy

connections to slow devices.Support for three-channel serial I/O via IEBus or an I2C-bus

subset enables connection of a large number of devices.

23

Features of the M16C/62P Group

CPU: M16C/60-series 16-bit CPU core

Max. operating frequency:

24 MHz (PLL)

Min. instruction execution time:

41.6 ns

Power-supply voltage3.0 V to 5.5 V (at 24 MHz/no wait/PLL)

2.7 V to 5.5 V (at 10 MHz/no wait)

Flash erase/programming voltage:4.5 to 5.5 V or 3.0 to 3.6 V

Internal memory: (holy smoke)MASK version: 33 types in MP (+16*)

Flash version: 13 types in MP (+9*)

ROMless version: 4 in MP

ROM: 0 to 512 K Bytes

RAM: 4 to 31 K Bytes

Clock-generator circuits:PLL

XIN ( up to 24 MHz)

XCIN (32 kHz)

External bus: Allows mixed 5-V/3-V IC connection

* Note: Denotes number of devices in Development

24

Peripheral Functions of the M16C/62P Group

16-bit timer: 5 output, 6 input Serial I/O:

Clock-synchronized/UART: 3 ch Clock-synchronized only: 2 ch

Additional Communications: Subset of IEBus and I2C-bus; 3 ch Having an on-chip-circuit greatly

reduces S/W processing load DMAC: 2 ch A/D converter: 10-bit x 26 ch

(max) D/A converter: 8-bit x 2 ch CRC: (1) Three-phase motor controller (1) Address-match interrupts (4)

Watchdog timer: 1 ch Can drive a H/W reset

Programmable I/O pins: 87 (100-pin version) 113 (128-pin version)

(one pin is input only) Pull-up resistor: All ports Chip-select pins: 4

External wait: 1, 2, 3 wait cycles selectable

Memory: 1 Mbytes Expansion available to 4 Mbytes

Packages: 80/100/128 pins 80P6S-A/100P6S-A/100P6Q-A

/128P6Q 128-pin version is only available

for products with 256 KB or more of Flash

25

Features of the M16C/62N4 Group



20 MHz (PLL)


50 ns

Power-supply voltage4.2 V to 5.5 V

Internal memory:MASK & Flash versions:

ROM 128 KB/ RAM 5 KB

ROM 256 KB / RAM 10KB (6N4)


XIN ( up to 20 MHz)

XCIN (32 kHz)

* Note: Denotes number of devices in Development

26

Peripheral Functions of the M16C/62N4 Group


Clock-synchronized/UART: 3 ch Clock-synchronized only: 1 ch

Additional Communications: CAN x 1 (6N5) Subset of IEBus and I2C-bus; 2 ch

(6N4) DMAC: 2 ch A/D converter: 10-bit x 26 ch

(max) 3.3 us with Sample & Hold

D/A converter: 8-bit x 2 ch CRC: (1) Three-phase motor controller (1) Address-match interrupts (4)



(one pin is input only) Pull-up resistor: All ports Chip-select pins: 4


Memory: 1 Mbytes Expansion available to 1 Mbytes

Packages: 100 pins 100P6S-A & 100P6Q-A (0.65 & 0.5 mm pitch)

27

M16C/80 Series

28

Enhanced processing capabilities Increased operating speedExpanded memory space Large-capacity flash memory

The M16C/80 group offers stronger processing performance with even more 1-cycle instructions and higher operating speeds. Large address space for this group, which includes ROM-less versions.

M32C

M16C/80 20 [email protected] V10 [email protected] V

100P6S-A/100P6Q-A/144P6Q-A

M16C/80256 KB/20 KB

M16C/80256 KB/20 KB

M16C/80ROM-less/24 KB

M16C/80128 KB/10 KB

M16C/80128 KB/10 KB



(built-in boot loader)


(built-in boot loader)

Flash Mask


29

32-bit arithmetic, 32-bit data transfer, and fast multiply-and-

accumulate instructions enable high-speed operation

Faster interrupt response (250 ns@20 MHz) is also suitable

for higher operating speeds

All memory instructions operate on data in all memory areas,

this makes it easier to develop software

The 16-Mbyte address space makes these MCUs fit for

applications such as image processing, which require large

memory areas

Inherits features of the M16C/62A for applicability to a wide

range of products

High-speed operation (20 MHz@5 V)

Key Features of the M16C/80 Group

30

Features of the M16C/80 Group



20 MHz


50 ns

Power-supply voltage4.2 V to 5.5 V (at 20 MHz/no wait)

2.7 V to 5.5 V (at 10 MHz/no wait)

Power consumption45 mA (typ.) at 20 MHz (5V)

14 mA (typ.) at 10 MHz (3V)

Internal memory: MASK and Flash versions: (14 in MP)

256 KB / 20 KB

128 KB / 10 KB

ROMless versions: (12 in MP)-/10K

-/24K


XIN ( up to 20 MHz)

XCIN (32 kHz)

31

Peripheral Functions of the M16C/80 Group


Clock-synchronized/UART: 5 ch Additional Communications:

Subset of IEBus and I2C-bus; 3 ch Having an on-chip-circuit greatly

reduces S/W processing load DMAC: 4 ch A/D converter: 10-bit x 10 ch

(max) 3.3 us with sample & hold




(one pin is input only) Pull-up resistors:

All ports (in 4 pin units) Chip-select pins: 4


Address space: 16 Mbytes Packages:

100/144 pins 100P6S-A/100P6Q-A /144P6Q-A

32

M32C/80 SeriesM32C/90 Series

33

Evolution of M32C/8x and 9x Groups

M32C/100

*: Under development**: In planning

Mask Flash

M32C/81CAN x 1 ch

32 MHz@3-5 V 100P6S-A/100P6Q-A/144P6Q-A

M32C/81128 KB/12 KB

M32C/81128 KB/10 KB

* *

M32C/8232 MHz@3-5 V

100P6S-A/100P6Q-A/144P6Q-A

M32C/82320KB/24KB

M32C/82384KB/24KB

M32C/82384KB/31KB

M32C/83CAN x 1 ch32 MHz@3-5 V* 100P6S-A/100P6Q-A/144P6Q-A

M32C/83512 KB/31 KB

M32C/94High speed64 MHz@3-5 V

M32C/84CAN x 1 ch32 MHz@3-5 V 100P6S-A/100P6Q-A/144P6Q-A

*M32C/84512 KB+4 KB/

24 KBM32C/84

ROM less/10 KB

**M32C/84

128 KB/10 KB

** M32C/94(being considered)

**


M32C/86CAN x 2 ch32 MHz@3-5 V 144P6Q-A

M32C/86512 KB+4 KB/

24 KBM32C/96

(being considered)

***


M32C/85CAN x 2 ch32 MHz@3-5 V

100P6S-A/100P6Q-A/144P6Q-A

M32C/95(being considered)

**M32C/85384 KB+4 KB/

24 KB

*M32C/85

512 KB+4 KB/16 KB

*M32C/85

320 KB/24 KB

**

M32C/8032 MHz@3-5 V 100P6S-A/100P6Q-A/144P6Q-A

M32C/80ROMless/8 KB

*

M32C/87CAN x 2 ch32 MHz@3-5 V 100P6S-A/100P6Q-A/144P6Q-A

M32C/871 MB+4 KB/

48 KBM32C/87

512 KB/31 KB

M32C/84192 KB/16 KB

**M32C/84

320 KB/24 KB

**

Faster operationHigher peripheral functionality

Stronger processing capabilities

** **

34

Peripheral Overlap in the M32C/8x and 9x Groups

DMADMA-IIDRAMCA/D: 1 chD/A: 2 chWDTPLL

+ Group 1 Intelligent I/O (BEAN, ISDN) Up to 8 IC ch Up to 8 OC ch 4 PWM

+ Group 2 intelligent I/O (IEBus subset) 8 output-compare channels 8 PWM

+ Group 3 intelligent I/O (HDLC-LAN) + 1-ch A/D 8 OC ch 8 PWM

+CAN+CAN

M32C/81

M32C/80 M32C/84

M32C/82

M32C/83

M32C/85

+ Group 0 Intelligent I/O (BEAN, ISDN) Up to 8 IC ch Up to 8 OC ch 8 PWM

+ Gaugecontroller

M32C/80 core32-MHz 16-bit timer A x 516-bit timer B x 6Serial I/O: 5 chI2C-bus subsetX/Y converterCRC operator

M32C/87

M32C/86

35

Key Features of the M32C/8x Groups

Upward compatibility from the M16C/80 Hi speed operation, up to 32MHz @ 5 V 32-bit add/subtract/multiply/divide-and-transfer

instructions, multiply and divide instructions, and high-speed 32-bit multiple-shift instructions (using a barrel shifter) facilitate high-speed processing of arithmetic operations.

As well as the on-chip timers and serial I/O units, intelligent I/O can be added for increased PWM and serial I/O functionality or on-chip CAN (max. 2 ch-M32/C85, 86), making this series suitable for a wide variety of application fields.

The input-capture and output-compare functions make these devices highly suitable for sensor and motor control applications.

36

Features of the M32C/9x Group



64 MHz


16 ns

Number of Instructions:108

Power-supply voltage5 V

Power consumption60 mA at 64 MHz (5V) – target

EMI/EMS Inherits M32C/8X characteristics

Internal memory: ????

Clock-generator circuits:2

37

Peripheral Functions of the M16C/9x Group


Clock-synchronized/UART: 5 ch Additional Communications:

Subset of IEBus and I2C-bus; 3 ch Having an on-chip-circuit greatly

reduces S/W processing load DMAC: 4 ch DMACII:

Can be activated by peripheral I/O interrupt source

A/D converter: 10-bit x 34 ch (max) Possibly a 12-bit version


Watchdog timer: 1 ch Intelligent I/O: 1 group

Time measurement (16 bit x 8 ch) Waveform generation (16 bit x 8 ch) Communications (HDLC, SI/O)

CAN: 1 to 3 full CAN ch (2.0B) Programmable I/O:

87 in 100 pin package 124 in 144 pin package

Pull-up resistors: All ports Chip-select pins: 4


Address space: 16 Mbytes Packages:

100/144 pins 100P6S-A/100P6Q-A /144P6Q-A

X-Y Data converter (1)

38

Target Features forM32C/100 Products

Target peak performance: 100 MIPS or more (4 times the value for the current M32C/8x) CPU architecture High speed - Full 32-bit (32-bit registers and instruction/data bus) - 100-MHz CPU clock (target) High function - 64-bit memory bus - DSP module with independent data bus - Single-precision FPU Concept : 32-bit performance + DSP + FPU plus inherited features (high code efficiency, low power, low noise)

General reg.(32-bit x 8)

Address adder(32-bit)

ALU(32-bit)

Barrel shifter(32-bit)

32-bitMUL32-bit FPUDSPInst. queue

32-bit x 4

Architecture of the M32C/100 CPU

Newly added block

Dedicated reg.32-bit x 19

UnderDevelopment

39

Features of M32C/100-Group Products (Targets)

Full 32-bit CPU core: Will include a 32-bit multiplier and 32-bit barrel shifter Clock freq.: Over 64 MHz (target: 100 MHz) High-speed arithmetic processing: To support single-precision floating-

point operations Built-in DSP function: 32 bits x 32 bits + 64 bits -> 64 bits (1 cycle ) High-speed interrupt transaction: Interrupt response to take fewer cycles High-Speed sequence transaction: Faster indirect jumps, lessening the

penalty of branch instructions High-speed A/D converter: 12-bit resolution (conversion time below 2 us) Upward compatibility with M16C-family peripheral functions: Both general-

purpose and Intelligent I/O functions Inherits general features of the M16C: High code efficiency in ROM, low

power consumption, pin compatibility, upwardly compatible peripheral functions, low EMI, high noise tolerance, wide temperature range, high-performance flash memory

UnderDevelopment

Renesas Technology America, Inc.

40

5 m16c.ppt

Documents

communications data

image data

data correction

data ram

phase pwm output m16c

channels of clock

hardware xy data converter

w phase