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ECEN5807 supplementary notes

Introduction to MATLAB/Simulink for switched-mode power converters

ECEN5807Colorado Power Electronics Center

University of Colorado, Boulder

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1.1 Getting started with MATLAB/Simulink• Starting and running simulations in MATLAB/Simulink• Constructing Simulink models• Examples:

• Open-loop synchronous buck converter modelSimulink file: buck_open_loop.mdl

• Buck converter and PWM subsystem models• Closed-loop synchronous buck converter model with an analog controller

Simulink file: buck_closed_loop.mdl• Load transient model and simulations

Simulink file: buck_closed_loop_load.mdl1.2 Digitally controlled buck converter: Simulink models and simulations

• System model• A/D converter, discrete-time compensator, and DPWM models

Simulink file: buck_closed_loop_discrete.mdl

ECEN5807 supplementary notes

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1.1 Starting MATLAB/Simulink• Start MATLAB:

(double-click on the MATLAB shortcut)• Open a file, in the MATLAB window menu:

– Select file: buck_open_loop.mdl, then Open• This opens a pre-configured Simulink model for an open-loop synchronous

buck switching converter

• Converter parameters:• L = 4.1 µH, RL = 80 mΩ• C = 376 µF, Resr = 5 mΩ• fs = 100 KHz• Vg = 12 V, D = 0.42• Load R = 1 Ω

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Transient Simulations in Simulink

• Make your copy of the Simulink model for further editsIn the current Simulink window:– File Save As File Name: enter my_buck_open_loop.mdl, then Save

• Check or adjust simulation parameters: – Simulation Simulation parameters

• This opens a window to adjust simulation parameters such as Start Time, Stop Time, solver options, step size, etc.

• The default parameters and options are usually fine, except:

– Enter appropriate Stop time(3 ms in this example)

– Enter Max step size of about 1/100 of the switching period (0.1 µs in this example)

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Starting Transient Simulation

• In the current Simulink window:– Simulation Start orclick on the Start button in the toolbar

Current simulation time and progress are shown here

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View Simulation Results• In the my_buck_open_loop Simulink window, double-click the Scope block• Use rectangular box, X-axis, or Y-axis Zoom tools to view waveforms details

Autoscale fits the entire waveforminto the window

Current axes settings can be Saved or Restored

To enter a specific vertical axis range, right-click on the waveform, select Axes properties… then enter Y-min and Y-max, click OK

Vo

iL

Vo

iL

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Construction of Simulink Models

+–

Vg

Q1L RL

Q2

C

RC

R

Switch network

Load modeled as a resistor R, iout = Vo/R

Pulse-width modulatorsubsystem

Constant duty-cycle command

Constant input voltage

Top-level system model

Buck converter subsystem

Simulink models are block-diagrams consisting of

• “Sources” (such as Constant Vg block)

• “Sinks” (such as Scope) and

• Various functional blocks, including subsystems

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• System equations:

• Double-click on the buck converter subsystem block to view a Simulink implementation of the system equations

Buck Converter Subsystem

( )oLLgL vRidV

Ldtdi

−−⋅=1

( )outLC ii

Cdtdv

−=1

)( outLesrCo iiRvv −+=

+–

Vg

Q1L RL

Q2

C

RC

R

Switch network

Buck converter subsystem

iout • Inputs:– Input voltage Vg

– Switching signal d = 0,1

– Load current iout

• Outputs:– Output voltage Vo

– Inductor current iL

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In

Integrator

Integrator

GainGain

Gain

Gain

Product

In

InOut

Out

)( outLesrCo iiRvv −+=

( )outLC ii

Cdtdv

−=1

( )oLLgL vRidV

Ldtdi

−−⋅=1

SumSum

Sum

Buck Converter Subsystem

On this slide, the subsystem model is annotated with the system equations and Simulink block names, such as Product, Gain, Integrator, etc., shown in red

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PWM Subsystem

• In the my_buck_open_loop window, double-click on the PWM block to open the subsystem window

• Double-click on the Saw-tooth waveform block to view or change the block parameters

• Note that Time values [0 0.001e-5 1e-5] and the corresponding Output values [1 0 1] define the saw-tooth waveform in the PWM (switching frequency is: 1/1e-5 = 100 KHz)

vt

d

cRelay Block

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Constructing a Closed-Loop Model

• In this step, the objective is to construct and simulate a closed-loop voltage regulator using a simple continuous-time integral compensator

• Save my_buck_open_loop.mdl as my_buck_closed_loop.mdl

• In the my_buck_closed_loop window, click on the Library Browser button

to open the Simulink Library Browser window

Simulink Library Browser

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Constructing the Closed-Loop Model, continued

– In the Simulink Library Browser window, select

Simulink Continuous Integrator– Drag an Integrator block to the

my_buck_closed_loop window, click the left mouse button to place the integrator

– Similarly, add the following Simulink blocks to my_buck_closed_loop:

• Two Gain blocks (Simulink Math Gain)• A Sum block (Simulink Math Sum)• A Constant block (Simulink Sources Constant)

– Delete the Duty Cycle D (Constant): select the Duty Cycle D block and press Deletekey

my_buck_closed_loop after the edits listed on this page

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– Change the orientation of the blocks for easier wiring:

• Select the Gain block, click the right mouse button, select Format Rotate block

• Similarly, using Rotate block or Flip block, change the orientation of the Integrator, Sum, Gain1 and Constant blocks

– Double-click on the Sum block to change the input for the sensed output voltage to minus (–); reorder the symbols +, –, and | as desired

– Wire the blocks to construct the closed-loop model– Set the model parameters (double click the block

and edit the default values):• Gain = 0.4 (gain H of the voltage divider

sensing the output voltage)• Gain1 = 1000 (gain of the integral

compensator); you may need to resize the block to show the parameter value: select then drag a corner to resize the block

• Constant = 2 (constant Vref = 2, so that in steady-state Vo = Vref/H = 5 V)

– Run a simulation to verify that the output voltage comes to Vref /H = 5 V in steady state

my_buck_closed_loop after the edits listed on this page

Constructing the Closed-Loop Model, completed

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Closed-Loop Simulation Results

The output voltage Vo and the inductor current iL during a start-up transient in

the closed-loop buck converter with the continuous-time integral compensator

Details of the steady-state output voltage Vo and the inductor current iL in the closed-loop buck converter with the

continuous-time integral compensator

Vo

iL

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Adding a Step Load Transient Model

– In this step, the objective is to add a step load transient to the closed-loop converter model

– In the Simulink Library Browser window, select Simulink Sources Pulse Generator

– Place a Pulse Generator block and another Sum block in the my_buck_closed_loop window

– Click on the block name to rename the Pulse generator to Step load

– Wire the blocks as shown in the diagram

– Set the parameters of the Step load blockas shown on the next page

– Save the system model as my_buck_closed_loop_load.mdl

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Step Load Transient Parameters

– The objective is to set the parameters of the Step load pulse generator block to step the total load resistance from 2 Ω to 1 Ω and back, corresponding to a 50% to 100% load transient

– Double click on the Step load block to open the Block Parameters window

– Set Amplitude to 1, the Period to 2 ms, and the Pulse Width to 50%

– With these parameters, the Step load block periodically adds the resistance of 1 Ω to the constant load resistance of 1 Ω. As a result, the total load resistance is 2 Ω from 0 to 1 ms, 1 Ωfrom 1 ms to 2 ms, back to 2 Ω from 2 ms to 3ms, etc.

– Note that in this model the step load change occurs instantaneously

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Step Load Transients

Start-up, 50-to-100% and 100-to-50% load transient responses in the closed-

loop converter with the simple continuous-time integral compensator

Review the step-load transient simulation results

Details of the 100-to-50% load transient response in the closed-loop

converter with the simple continuous-time integral compensator

Vo

iL

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1.1.1 Add a Scope block (Simulink Sinks Scope in the Library Browser) to observe the duty-cycle command d and the switching signal c waveforms.

Optional Exercises

Note: in Scope window, click on the Parameters button to change the Number of axis to 2 in the General tab. Also, uncheck Limit data points to last in the Data history tab to allow the Scope to display long waveforms

1.1.2 In the buck_closed_loop models, the output of the Integrator block can be arbitrarily large. If the compensator output “winds-up” far away from the 0-to-1 duty-cycle command range, during start-up or over-loads, the output voltage may have large overshoots or undershoots before returning to regulation. Double-click on the Integrator block to add realistic saturation limits.

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1.1.3 Add a Saturation block (Simulink Discontinuities Saturation in the Library Browser) to model limits Dmin and Dmax for the duty-cycle command

1.1.4 Change the step-load-transient model to test the closed-loop converter response under 0-to-100% (i.e. 0-to-5 A) load transients.

1.1.5 Add a soft-start feature to the model. Hint: a MinMax block (Simulink Math Operations MinMax in the Library Browser) can be used to select the minimum of two signals. Connect one of the MinMax block inputs to the duty-cycle command from the compensator, and connect the other input to a slow ramp generator (Simulink Sources

Ramp in the Library Browser). In this implementation, the output voltage will still overshoot because of the duty-cycle saturates at Dmax, which is greater than the steady-state value. Can you improve the soft-start model?

1.1.6 Change the model to test for a transient response to a step in the input voltage.

Exercises

* Note: in MATLAB 6.1, and earlier versions, the “Discontinuities” section of the Simulink library was called “Nonlinear”

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1.2 Digitally-Controlled Buck Converter:Simulink Models and Simulations

• The objective of this part is to develop and explain details of a Simulink model for a digitally-controlled buck converter, including Simulink models for:

– A/D converter– Discrete-time compensator– Digital PWM

• The buck converter model and the parameters are the same as in Section 1.1 (same parameters as in the Simulink file: buck_closed_loop_load.mdl)– L = 4.1 µH, RL = 80 mΩ– C = 376 µF, Resr = 5 mΩ– fs = 100 KHz– Vg = 12 V– Maximum load current: 5 A

• Open the file buck_closed_loop_discrete.mdl and save the system model as my_buck_closed_loop_discrete.mdl

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Digitally Controlled Buck ConverterSimulink Model

Digital PWM

Discrete-time integral compensator

A/D converter

• The buck converter block and the step load transient model are the same as in the continuous-time buck_closed_loop_loadsystem

• Note the parts of the system that model the digital controller including:

– A/D converter– Discrete-time integral

compensator, and – Digital PWM

• Run a simulation and double-click on the Scope block to observe the output waveforms

• The output voltage and inductor current waveforms are shown on the next page, in comparison with the waveforms obtained from the continuous-time example in buck_closed_loop_load

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Start-Up and Step-Load Transient Waveforms

Vo

iL

Scope waveforms in the digitally controlled converter model buck_closed_loop_load_discrete

Scope waveforms in the analog controlled converter model buck_closed_loop_load

• Note that the transient waveforms are almost the same except for a slight difference in the inductor current waveform during start up. Where does the difference come from? Hint: add a Scope block to observe the sampled and quantized error signal eq after the A/D Limits block during the start-up transient.

• Next, we examine details of the A/D converter, Discrete-time compensator and Digital PWM models

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A/D Converter Model: Delay td1

Vref

Sensed voltage

Error e

Sampled and quantized error eq

– Delay td1 block is a Transport Delay block (Simulink Continuous Transport Delay from the Library Browser). This block models the total time between sampling the error signal e and updating the duty cycle command dc at the beginning of the next switching period. This delay must be long enough to include the A/D conversion time, as well as processing and computation delays in the compensator.

– Double click on the Delay td1 block to view/change the delay td1 (4 µs in this example)

– Usually there is no need to change the default values of other parameters in this block. Optional: click on the Help button to see more details about the block

– Double-click on the Scope1 block and zoom in on the waveforms following the step-load transient at 1 ms. See the annotated waveforms on the next page.

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Waveform details in the digital controller

Switching signal c

Duty-cycle command dc

Error signals:e=Vref−Vo

ed = e delayed by td1

es = ed after Zero-Order Hold

e ed

es

td1 Ts

td

dTs

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A/D Converter Model: Zero-Order Hold

Vref

Sensed voltage

Error e

Sampled and quantized error eq

– The Zero-Order Hold block (Simulink Discrete Zero-Order Hold in the Library Browser) samples the error signal, i.e. converts the signal from continuous time to discrete time

– Double click on the block to view the Sample time (Ts = 10 µs in this example)

– Note that the Sample time is the same as the switching period Ts defined by the period of the saw-tooth waveform in the PWM subsystem

– Observe the Scope1 waveform eh after the Zero-Order Hold block (shown earlier)

– Notice that the sampling of the delayed error signal ed occurs at the beginning of each switching period, i.e. at 0, Ts, 2Ts, etc. It coincides with the rising edge of the switching signal c.

– It is important to note that the Zero-Order Hold is added to the Simulink model only for the purpose of explicitly modeling the sampling effect. The system dynamic model does not include a ZOH transfer function

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A/D Converter Model: A/D Quantizer

Vref

Sensed voltage

Error e

Sampled and quantized error eq

– A/D Quantizer block is a Quantizer block (Simulink Discontinuities Quantizer from the Library Browser).

– Double click on the block to view/change the Quantization interval (qA/D = 1/64 V in this example)

– The Quantization interval equals the LSB value (in Volts) of the A/D converter. In this example, the A/D converter has 7-bit resolution over 2 V -1V to +1V voltage range. Hence, the Quantization interval is

qA/D = 2/27 = 1/26 = 1/64 = 15.6 mV – With the box Treat as gain when linearizing

checked, the “gain” of the Quantizer block in a linearized model is 1. Otherwise, a “small-signal”gain equal to zero is assumed. Optional: click Helpfor more details

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A/D Converter Model: A/D Limits

Vref

Sensed voltage

Error e

Sampled and quantized error eq

– A/D Limits block is a Saturation block (Simulink Discontinuities Saturation from the Library Browser).

– Double click on the block to view/change the Upper limit (+1 V in this example) or the Lower limit(−1 V in this example)

– This block models the conversion range (or window) of the A/D converter

– Optional exercise 1.2.1: add a Scope block to observe the error signals eh and eq before and after the A/D Quantizer and the A/D Limits blocks:

– Note the effect of A/D Limits during the start-up transient; experiment with making the A/D conversion range smaller

– Note that in steady state the quantized error eqis exactly zero

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Discrete-time Integral Compensator

Quantized discrete-time error eqDPWM command

– The Discrete-time Integral Compensator block is a Discrete Zero-Pole block (Simulink Discrete Discrete Zero-Pole in the Library Browser)

– Double click on the block to view the block Parameters– The block implements a discrete system transfer

function in the following factored pole/zero form:

– The Parameters are specified as follows:– Zeros: [Z1 Z2 Zm] ([0], in this example)– Poles: [P1 P2 Pn] ([1] in this example)– Gain: K (1 in this example)– Sample time (“-1 for inherited” means that the

sample time is inherited from the Zero-Order Hold block in this example)

– Note that a discrete-time integrator with no delay is implemented in this example

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Discrete-time Compensator

Quantized discrete-time error eqDPWM command

– There are a number of other ways to implement a discrete transfer function (see Simulink Discrete blocks in the Library Browser), such as one or a combination of the following blocks:

– Discrete Transfer Fcn block– Discrete Filter block– Discrete-Time Integrator block– A combination of Unit Delay, Gain and Sum blocks

– Exercise 1.2.2: the parameter of the Gain1 block is set to 0.01 to match the gain of the discrete-time integral compensator to the gain of the continuous-time integral compensator in the buck_closed_loopmodel. Show that this is true.

– Exercise 1.2.3: implement the compensator using the Discrete-Time Integrator block from the Library Browser. What should Gain1 be in this case? Verify your implementation by simulation. Is this implementation completely equivalent to the implementation shown above? Why not?

– Exercise 1.2.4: implement the discrete-time integral compensator using a Unit Delay block and a Sumblock. Verify your implementation by simulation.

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Digital PWM

Switching signalDPWM command

– Digital PWM model includes a DPWM Quantizer block (a Quantizer block), a DPWM limits block (a Saturation block) and the analog PWM subsystem block

– Double-click on the DPWM Quantizer to view/change the Quantization interval parameter, i.e. the LSB value of the duty cycle. In this example, the DPWM resolution is 10 bits over the 0-to-1 range, so that the Quantization interval is qDPWM = 1/210 = 1/1024

– Double-click on the DPWM limits block to view/change: – Upper limit (i.e. the maximum duty cycle), 0.8 in this example, or – Lower limit (i.e. the minimum duty cycle), 0.0 in this example

– Exercise 1.2.5: change the DPWM resolution to 7 bits and run a simulation. Low-frequency oscillations can be observed in the output voltage. Why? What is, approximately, the frequency of the oscillations? Compare this frequency to the corner frequency fo of the buck converter LC filter.

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1.2.7 In the buck_closed_loop_discrete models, the output of the integral compensator can be arbitrarily large. If the compensator output “winds-up” far away from the 0-to-1 duty-cycle command range, during start-up or over-loads, the output voltage may have large overshoots or undershoots before returning to regulation. Change the model to add realistic saturation limits for the integral compensator. Hint: do Exercise 1.2.4 first.

1.2.6 Change the step-load-transient model to test the closed-loop converter response under 0-to-100% (i.e. 0-to-5 A) load transients.

1.2.7 Add a soft-start feature to the model. 1.2.8 Change the model to test for a transient response to a step in the input voltage.

Exercises