*Chapter 11 Interrupts Programming

*Sections11.1 8051 Interrupts11.2 Programming Timer Interrupts11.3 Programming External Hardware Interrupts11.4 Programming the Serial Communication Interrupt11.5 Interrupt Priority in the 8051

*Section 11.18051 Interrupts

*Inside Architecture of 8051CPUOn-chip RAMOn-chip ROM for program code4 I/O PortsTimer 0Serial PortFigure 1-2. Inside the 8051 Microcontroller Block DiagramOSCInterrupt ControlExternal interruptsTimer 1Timer/CounterBus ControlTxD RxDP0 P1 P2 P3Address/DataCounter Inputs

*I/O ServicesA single microcontroller can serve several devices.Two ways:Interrupt methodAn interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service.Polling method

*Polling methodThe microcontroller continuously monitors the status of a given device. When the condition is met, it performs the device.After that, it moves on to monitor the next device until every one is serviced.The microcontroller check all devices in a round-robin fashion.

*Interrupt methodWhenever any device needs its service, the device notifies the microcontroller by sending it an interrupt signal.Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and serves the device. The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler.

*The advantage of InterruptsThe microcontroller can serve many devices.Each device can get service based on the priority assigned to it.The microcontroller can ignore (mask) a device request.The use of microcontroller is more efficient.Ex: in polling system, HERE: JNB TI, HERE wastes much of the microcontrollers time.

*Interrupt Service RoutineFor every interrupt, there is a fixed location in memory that holds the address of its ISR.The group of memory locations set aside to hold the addresses of ISRs is called the interrupt vector table.Table 11-1 is the interrupt vector table for 8051.

*Table 11-1: Interrupt Vector Table for the 8051

Interrupt ROM Location (Hex) PinReset0000 9External hardware interrupt 0 (INT0)0003 P3.2 (12)Timer 0 interrupt (TF0)000BExternal hardware interrupt 1 (INT1)0013 P3.3 (13)Timer 1 interrupt (TF1)001BSerial COM interrupt (RI and TI)0023

*Steps in Executing an 8051 Interrupt (1/2)Upon activation of an interrupt, the microcontroller goes through the following steps:It finishes the instruction it is executing and saves the address of he next instruction (PC) on the stack.It also saves the current status of all the interrupts internally.It jumps to a fixed location in memory called the interrupt vector table.

*Steps in Executing an 8051 Interrupt (2/2)Executing steps (continuous):The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it. The microcontroller starts to execute the interrupt service routine until it reaches the last instruction of the subroutine which is RETI (return from interrupt). Upon executing the RETI instruction, the microcontroller returns to the place where it was interrupted. First, it gets the program counter (PC) address from the stack by popping the top two bytes of the stack into the PC. Then it starts to execute from that address.

*Six Interrupts in the 8051 (1/2)ResetTwo interrupt for the timersTF0, TF1Two interrupt for external hardware interruptsINT0, INT1Serial communicationTI or RI Refer to Table 11.1

*Six Interrupts in the 8051 (2/2)There is a limited number of bytes for each interrupt.3 bytes for reset8 bytes for timers and external hardware interruptsIf the service routine is too short to fit the ISR, an LJMP instruction is placed in the vector table to point to the address of the ISR.Figure 11-1: ISR for reset Programmers must enable these interrupts before using them.

*Figure 11-1: Redirecting the 8051 From the Interrupt Vector Table At Power-Up;---- the first instruction is executed as the 8051 powers up ORG 0 ;ROM reset location LJMP MAIN ;by-pass interrupt vector table

;---- the wake-up program ORG 30HMAIN: .... END

*IE (Interrupt Enable)In the 8051, the IE (interrupt enable) register denotes the usage of these interrupts.Figure 11-2 : IE register Upon reset, all interrupts are disabled (masked).The interrupts must be enabled by software.IE is bit-addressable.If we want to enable a special interrupt, set EA=1 first.

*Figure 11-2. IE (Interrupt Enable) RegisterEA IE.7 Disables all interrupts. If EA=0, no interrupt is acknowledged. If EA=1, each interrupt source is individually enabled of disabled by setting or clearing its enable bit.--- IE.6 Not implemented, reserved for future use. *ET2 IE.5 Enables or disables timer 2 overflow or capture interrupt (8952).ES IE.4 Enables or disables the serial port interrupt. RI or TIET1 IE.3 Enables or disables timer 1 overflow interrupt. TF1EX1 IE.2 enables or disables external interrupt 1. INT1 ET0 IE.1 Enables or disables timer 0 overflow interrupt. TF0EX0 IE.0 enables or disables external interrupt 0. INT0

*Steps in Enabling an InterruptTo enable an interrupt, we take the following steps:Set EA=1. Enables all interrupts.If EA=0, no interrupt will be responded to, even if the associated bit in the IE is high.Enable each interrupt by setting its corresponding bit in IE.

*Example 11-1 (1/2)Show the instructions to enable the serial interrupt, timer 0 interrupt, and external hardware interrupt 1 (EX1)disable (mask) the timer 0 interruptshow how to disable all the interrupts with a single instruction.Solution:(a) MOV IE,#10010110B EA serial INT1 timer 0Another way to perform the MOV IE,#10010110B instruction is by using single-bit instructions as shown below. SETB IE.7 ;EA-1, Global enable SETB IE.4 ;enable serial interrupt SETB IE.1 ;enable hardware interrupt 1 SETB IE.2 ;enable Timer 0

*Example 11-1 (2/2)Since IE is a bit-addressable register, we can use the following instructions to access individual bits of the register.

(b) CLR IE.1 ;mask (disable) timer 0 interrupt only(c) CLR IE.7 ;disable all interrupts

*Section 11.2Programming Timer Interrupts

*Roll-over Timer Flag and InterruptIn polling TF, we have to wait until the TF is raised. JNB TF, targetUsing interrupt, whenever TF is raised, the microcontroller is interrupted and jumps to the interrupt vector table to service the ISR.

*Example 11-2 (1/3)Write a program that continuously gets 8-bits data from P0 and sends it to P1 while simultaneously creating a square wave of 200 s period on pin P2.1. Use timer 0 to create the square wave. Assume that XTAL = 11.0592 MHz.Solution:We will use timer 0 in mode 2 (auto reload). TH0 = 100 s /1.085 s = 92 for half clock.We must avoid using memory space allocated to interrupt vector table. Therefore, we place the main memory in 0030H

*Example 11-2 (2/3);LJMP redirects the controller away from the interrupt vector table. ORG 0000H LJMP MAIN ;by-pass interrupt vector table;The ISR for Timer 0 to generate square wave;The ISR is small enough to fit in the 8 bytes. ORG 000BH ;Timer 0 interrupt vector table CPL P2.1 ;toggle P2.1 pin RETI ;return from ISR;In the ISR for timer 0, notice that there is no need for CLR TF0 before RETI. The reason for this is that the 8051 clears the TF flag internally upon jumping to the interrupt vector table.

*Example 11-2 (3/3);The main program for initialization ORG 0030H ;after vector table spaceMIAN: MOV TMOD,#02H ;Timer 0,mode 2(auto reload) MOV P0,0FFH ;make P0 an input port MOV TH0,#0A4H ;TH0=A4H for -92 MOV IE,#82H ;IE=100000010(bin) enable Timer 0 SETB TR0 ;Start Timer 0BACK: MOV A,P0 ;get data from P0 and put it to P1 MOV P1,A ;loop unless interrupted by TF0 SJMP BACK END

*Example 11-3 (1/3)Rewrite Example 11-2 to create a square wave that has a high portion of 1085 s and a low portion of 15 s. Assume XTAL = 1.0592 MHz. Use timer 1.Solution:15 s =1.085 s 141085 s =1.085 s 1000we need to use mode 1 of timer 1.

*Example 11-3 (2/3) ORG 0000H ;by-pass interrupt vector table LJMP MAIN ;ISR for Timer 1 to generate square wave ORG 001BH ;timer 1 interrupt vector table LJMP ISR_T1 ;jump to ISR;The main program for initialization ORG 0030H ;after vector tableMAIN: MOV TMOD,#10H ;timer 1, mode 1 MOV P0,#0FFH ;make P0 an input port MOV TL1,#018H ;TL1=18 the low byte of -1000 MOV TH1,#0FCH ;TH1-FC the high byte of -1000 MOV IE,#88H ;IE=1001000 enable timer 1. SETB TR1 ;start timer 1

*Example 11-3 (3/3);Timer 1 ISR. Must be reloaded since not auto-reload;The low portion of the clock is created by the 14 MCISR_T1:CLR TR1 ;stop Timer 1 CLR P2.1 ;P2.1=0, start of low portion MOV R2,#4 ; (2 MC)HERE: DJNZ R2,HERE ; (4 2 MC) MOV TL1,#18H ;load T1 low byte value (2 MC) MOV TH1,#0FCH ;load T1 high byte value (2 MC) SETB TR1 ;starts timer 1 (1 MC) SETB P2.1 ;P2.1=1, back to high (1 MC) RETI ;return to main END

*Example 11-4 (1/2)Write a program to generate a square wave of 50 Hz frequency on pin P1.2. This is similar to Example 9-12 except that it uses an interrupt for timer 0. Assume that XTAL=11.0592 MHz.Solution:(a) The period of the square wave = 1 / 50 Hz = 20 ms.(b) The half square wave = 10 ms = 1.085 s 9216 65536 9216 = 56320 in decimal = DC00H in hex. ORG 0 LJMP MAIN ORG 000BH CPL P1.2 MOV TL0,#00 MOV TH0,#0DCH RETI50%50%20msP1.2

*Example 11-4 (2/2);--main program for initialization ORG 30HMAIN: MOV TMOD,#00000001B ;timer 0, mode 1 MOV TL0,#00 MOV TH0,#0DCH MOV IE,#10000010B ;enable timer 0 interrupt SETB TR0 HERE: SJMP HERE END P1.28051TL0TH050 MHz square wave

*Section 11.3Programming External Hardware Interrupts

*External Hardware Interrupts (1/2)The 8051 has two external hardware interrupts:EX0: INT0, Pin 12 (P3.2) EX1: INT1, Pin 13 (P3.3) These two pins are used in timer/counter.INT is a trigger for hardware control (GATE=1).Timer/counter is enabled only while the INT pin is high and the TR control pin is set.They are enabled and disabled using the IE register.EX0 by IE.0EX1 by IE.1

*External Hardware Interrupts (2/2)Upon activation of these pins, the 8051 gets interrupted and jumps to the vector table to perform the ISR.There are two activation levels for the external hardware interrupts:Low level triggeredFalling edge triggeredThis is chosen by IT0/IT1 in TCON.On Reset, IT0 and IT1 are both low, making external interrupts low level-triggered.

*Figure 4-1. 8051 Pin DiagramPDIP/Cerdipexternal hardware interrupt

*Low Level-triggered InterruptAlso called as level-activated interrupt.After the hardware interrupts in the IE register are enabled, the controller keeps sampling the INT pin for a low-level signal once each machine cycle.INT0 and INT1 pins are normally high.If a low-level signal is applied to them, it triggers the interrupt.minimum duration of logic 0

*Sampling the Low Level-triggeredThe duration of the low level-triggered interrupt:The pin must be held in a low state until the start of the execution of ISR. If the INT pin is bought back to a logic high before the start of the execution of ISR, there will be no interrupt.The low-level signal at the INT pin must be removed before the execution of RETI; otherwise, another interrupt will be generated after one instruction is executed.See Example11-5.

*Falling Edge-triggered InterruptAfter the hardware interrupts in the IE register are enabled, the controller keeps sampling the INT pin once each machine cycle.When a high-to-low signal is applied to INT0 (INT1) pin, the controller will be interrupted and forced to jump to location 0003H (0013H) to service the ISR.The external source must be held high for at least one MC, and then held low for at least one MC.

*Sampling the Falling Edge-triggered InterruptThe duration of the falling edge-triggered interrupt:The IE0 and IE1 of TCON register goes high whenever a falling edge is detected. The IE0 and IE1 function as interrupt-in-service flags.When IE0/IE1=1, it indicates to the external world that the interrupt is begin serviced now and on this INT pin no new interrupt will be responded to until this service is finished. The RETI clears IE0 (IE1) flag. During the time that the ISR is being executed, the INT pin is ignored, no matter how many times it makes a high-to-low transition.

*TCON Register (1/3)Timer control register: TCONUpper nibble for timer/counter, lower nibble for interruptsBit-addressableTR0/TR1 are used to start or stop timers.TF0/TF1 indicate if the timer has rolled over.

*TCON Register (2/3)IT (Interrupt type control bit) IT0 for external interrupt 0; IT1 for external interrupt 1.IT is set by software to specify falling edge/low-level triggered external interrupt.IT=0 : low-level triggered interrupt IT=1: falling edge triggered interruptIn the 8051, once IT0/IT1 are set to 0 or 1, they will not be altered again since the designer has fixed the interrupt either as edge- or level-triggered.

*TCON Register (3/3)IE (External interrupt edge flag)IE0 for external interrupt 0; IE1 for external interrupt 1.This flag is used for falling edge-triggered interrupt. It does not latch level-triggered interrupts.They indicate whether or not an interrupt is in use.IE is set by CPU when the external interrupt edge (H-to-L transition) is detected. Cleared by CPU when the ISR is finished.

*Figure 11-4. Activation of INT0 (1/2)INT0INT0IE0=1IE0=0

*Figure 11-4. Activation of INT1 (2/2)INT1INT1IE1=1IE1=0

*Example 11-5 (1/2)Assume that the INT1 pin is connected to a switch that is normally high. Whenever it goes low, it should turn on an LED. The LED is connected to P1.3 and is normally off. When it is turned on, it should stay on for a fraction of a second. As long as the switch is pressed low, the LED should stay on.Solution:Pressing the switch will cause the LED to be turned on. If it is kept activated, the LED stays on.

*Example 11-5 (2/2) ORG 0000H LJMP MAIN;--ISR for hardware interrupt INT1 to turn on the LED ORG 0013H SETB P1.3 MOV R3,#255BACK: DJNZ R3,BACK CLR P1.3 RETI;--main program for initialization ORG 30HMAIN: MOV IE,#10000100B ;enable INT1HERE: SJMP HERE ;stay here until get interrupt END

*Example 11-6 (1/2)Assuming that pin 3.3 (INT1) is connected to a pulse generator, write a program in which the falling edge of the pulse will send a high to P1.3 which is connected to an LED (or buzzer). In other words, the LED is turned on and off at the same rate as the pulses are applied to the INT1 pin. This is an edge-triggered version of Example 11-5. But in this example, to turn on the LED again, the INT1 pulse must be brought back high and then forced low to create a falling edge to activate the interrupt.

*Example 11-6 (2/2) ORG 0000H LJMP MAIN;--ISR for hardware interrupt INT1 to turn on the LED ORG 0013H SETB P1.3 MOV R3,#255 BACK: DJNZ R3,HERE ;keep the buzzer on for a while CLR P1.3 RETI ;--MAIN program for initialization ORG 30H MAIN: SETB TCON.2 ;make INT1 edge-trigger interrupt MOV IE,#10000100B ;enable External INT 1HERE: SJMP HERE END

*Example 11-7What is the difference between the RET and RETI instructions? Explain why we cannot use RET instead of RETI as the last instruction of an ISR.Solution:Both perform the same actions of popping off the top two bytes of the stack into the program counter, and making the 8051 return to where it left. However, RETI also performs an additional task of clearing the interrupt-in-service flag, indicating that the servicing of the interrupt is over and the 8051 now can accept a new interrupt on that pin. If you use RET instead of RETI as that last instruction of the interrupt service routine, you simply block any new interrupt on that pin after the first interrupt, since the pin status would indicate that the interrupt is still being serviced. In the cases of TF0, TF1, TCON.1, and TCON.3, they are cleared due to the execution of RETI.

*Section 11.4Programming the Serial Communication Interrupt

*Serial Communication InterruptIn Chapter 10, all examples of serial communications used the polling method.The 8051 CPU waits for TI or RI to be raised; while we wait we cannot do anything else.In this section, interrupt-based serial communication are introduced.This allows the 8051 to do many things, in addition to sending and receiving data from the serial communication port.

*RI and TI Flags and InterruptsIn the 8051 these is only one interrupt set aside for serial communication.This interrupt is used to both send and receive data. The interrupt is used mainly for receiving data.If the interrupt bit IE.4 is enabled, when RI or TI is raised, the 8051 jumps to memory 0023H to execute the ISR.The last instruction before RETI is the clearing of the RI or TI flags.Because the 8051 does not know who generated it.

*Example 11-8 (1/3) Write a program in which the 8051 reads data from P1 and writes it to P2 continuously while giving a copy of it to the serial COM port to be transferred serially. Assume that XTAL=11.0592. Set the baud rate at 9600.Solution:The moment a byte is written into SBUF, it is framed and transferred serially. As a result, when the last bit (stop bit) is transferred the TI is raised, and that causes the serial interrupt to be invoked since the corresponding bit in the IE register is high. We check for both TI and RI since both could have invoked interrupt (but do noting about RI=1).

*Example 11-8 (2/3) ORG 0 LJMP MAIN ORG 23H LJMP SERIAL ;jump to serial interrupt ISR; ------ main program, initialization ------ ORG 30HMAIN: MOV P1,#OFFH ;make P1 an input port MOV TMOD,#20H ;timer 1,mode 2 (auto reload) MOV TH1,#OFDH ;9600 baud rate MOV SCON,#50H ;8-bit, 1 stop, REN enabled MOV IE,#10010000B ;enable serial interrupt SETB TR1 ;start timer 1

*Example 11-8 (3/3);------ stay in loop indefinitely ------BACK: MOV A,P1 MOV SBUF,A ;A has a copy of data MOV P2,A SJMP BACK;------ Serial communication ISR ------ ORG 100HSERIAL: JB TI,TRANS ;jump if TI is high CLR RI ;do nothing but clear RI RETI TRANS: MOV SBUF,A ;transmit the copy of P1 CLR TI ;clear TI RETI END

*Example 11-9 (1/3)Write a program in which the 8051 gets data from P1 and sends it to P2 continuously while incoming data from the serial port is sent to P0. Assume that XTAL = 11.0592. Set the baud rate at 9600.Solution:The main program is the same as the main program in Example 11-8. Only the ISR of serial communication has a little different.

*Example 11-9 (2/3) ORG 0 LJMP MAIN ORG 23H LJMP SERIAL ;jump to serial ISR ORG 30H; ------ main program, initialization ------MAIN: MOV P1,#0FFH ;make P1 an input port MOV TMOD,#20H ;timer 1, mode 2 (auto reload) MOV TH1,#OFDH ;9600 baud rate MOV SCON,#50H ;8-bit,1 stop, REN enabled MOV IE,#10010000B ;enable serial interrupt SETB TR1 ;start timer 1

*Example 11-9 (3/3);------ stay in loop indefinitely ------BACK: MOV A,P1 MOV P2,A SJMP BACK ;------ Serial communication ISR ------ ORG 100HSERIAL: JB TI,TRANS ;jump if TI is high MOV A,SBUF MOV P0,A CLR RI RETI TRANS: CLR TI ;do nothing RETI END

*Example11-10 (1/4)Write a program using interrupts to do the following:(a) Receive data serially and sent it to P0.(b) Have P1 port read and transmitted serially, and a copy given to P2.(c) Make timer 0 generate a square wave of 5 kHz frequency on P0.1.Assume that XTAL = 11.0592. Set the baud rate at 4800.Solution:Two interrupts must be set:TF0 (address 000BH) for square wave: toggle P0.1 (c)RI and TI (address 0023H) for receive data P0 (a) (notice: Timer 1 is used for serial communication. But it is not necessary to enable TF1)An indefinitely loop: P1 P2 (b)

*Example11-10 (2/4) ORG 0 LJMP MAIN ORG 000BH ;ISR for Timer 0 CPL P0.1 ;toggle P0.1 RETI ORG 23H LJMP SERIAL ;jump to serial ISR

*Example 11-10 (3/4); ------ main program, initialization ------ ORG 30HMAIN:MOV P1,#0FFH ;make P1 as an input port MOV TMOD,#22H ;Timer 0 &1,mode 2, auto-reload MOV SCON,#50H ;8-bit,1 stop bit, REN enabled MOV TH1,#0F6H ;4800 baud rate for (a) MOV TH0,#-92 ;5KHz square wave for (c) MOV IE,#10010010B ;enable serial, timer 0 interrupt SETB TR1 ;start Timer 1 SETB TR0 ;start Timer 0;------ stay in loop indefinitely for (b) ------BACK: MOV A,P1 MOV SBUF,A MOV P2,A SJMP BACK

*Example 11-10 (4/4);------ Serial communication ISR ------ ORG 100HSERIAL:JB TI,TRANS ;jump if TI is high MOV A,SBUF ;for (a) MOV P0,A CLR RI RETI TRANS: CLR TI RETI END

*Section 11.5Interrupt Priority in the 8051

*Interrupt Priority upon ResetWhen the 8051 is powered up, the priorities are assigned according to Table 11.3:If some interrupts are activated, they are latched and kept internally. The 8051 checks all five interrupts according to the sequence listed in Table 11-3. If any is activated, it services it in sequence.External Interrupt 0 (INT0) high priorityTimer Interrupt 0 (TF0)External Interrupt 1 (INT1)Timer Interrupt 1 (TF1)Serial Communication (RI+TI) low priority

*Example 11-11Discuss what happens if interrupts INT0, TF0, and INT1 are activated at the same time. Assume priority levels were set by the power-up reset and that the external hardware interrupts are edge-triggered.Solution:If these three interrupts are activated at the same time, they are latched and kept internally. Then the 8051 checks all five interrupts according to the sequence listed in Table 11-3. INT 0 > TF 0 > INT 1 > TF 1 > RI or TIIf any is activated, it services it in sequence. Therefore, when the above three interrupts are activated, INT0 (external interrupt 0) is serviced first, then timer 0 (TF0), and finally INT1 (external interrupt 1).

*Setting Interrupt Priority with the IP (Interrupt Priority) RegisterTo give a higher priority to any of the interrupts, we make the corresponding bit in the IP high.Upon power-up reset, IP contains all 0s, making the priority sequence based on Table 11.3.IP bit = 1: high priorityIP bit = 0: low priorityFirst, high-priority and low-priority: 2 levelsSecond, if some interrupts have the same priority than others, they are serviced according to the sequence of Table 11.3.

*Figure 11-8. Interrupt Priority Register (Bit Addressable)

--IP.7Reserved--IP.6ReservedPT2IP.5Timer 2 interrupt priority bit (8051 only).PSIP.4Serial port interrupt priority bit.PT1IP.3Timer 1 interrupt priority bit.PX1IP.2External interrupt 1 priority bit.PT0IP.1Timer 0 interrupt priority bit.PX0IP.0External interrupt 0 priority bit.User software should never write 1s to unimplemented bits, since they may be used in future products.

*Example 11-12(a) Program the IP register to assign the highest priority to INT1 (external interrupt 1), then (b) discuss what happens if INT0, INT1, and TF0 are activated at the same time. Assume that the interrupts are both edge-triggered.Solution:(a) MOV IP,#00000100B or SETB IP.2 IP.2=1 to assign INT1 higher priority.(b) The instruction is Step (a) assigned a higher priority to INT1 than the others: INT1 > INT 0 > TF 0 > TF 1 > RI or TIWhen INT0, INT1, and TF0 interrupts are activated at the same time, the 8051 services INT1 first, then it services INT0, then TF0.

*Example 11-13Assume that after reset, the interrupt priority is set by the instruction MOV IP,#00001100B. Discuss the sequence in which the interrupts are serviced.Solution:The instruction MOV IP,#00001100B sets the external interrupt 1 (INT1) and timer 1 (TF1) to a higher priority level compared with the rest of the interrupts. They will have the following priority. High priority: INT 1 > TF 1Low priority: INT 0 > TF 0 > RI or TIThat is: INT 1 > TF 1 > INT 0 > TF 0 > RI or TI

*Interrupt inside an InterruptWhat happens if the 8051 is executing an ISR belonging to an interrupt and another interrupt is activated?A high-priority interrupt can interrupt a low-priority interrupt.This is an interrupt inside an interrupt.

*Triggering the Interrupt by SoftwareSometimes we need to test ISR.We can cause an interrupt with an instruction which raises the interrupt flag.For example, if the IE bit for timer 1 is set, SETB TF1 will interrupt the 8051 and force it jump to the interrupt vector table.

*You are able to (1/2)Contrast and compare interrupts versus pollingExplain the purpose of the ISR (interrupt service routine)List the interrupts of the 8051Enable or disable 8051 interruptsProgram the 8051 timers using interruptsDescribe the two external hardware interrupts of the 8051

*You are able to (2/2)Contrast edge-triggered with level-triggered interruptsProgram the 8051 for interrupt-based serial communicationDefine the interrupt priority of the 8051

*HomeworkChapter 11 Problems27,29,31,46,47,62,63,72

*