8086 pin configuration (1)

8/9/2019 8086 Pin Configuration (1)

1/83

8086 Pin diagra

8086 is a 40 pin DIP using

MOS technology. It has 2

GND’s as circuit

cople!ity "ean"s alarge aount o# current

#lo$ing through the

circuits% an" ultiple

groun"s help in "issipating

the accuulate" heat etc.8086 $or&s on t$o o"es

o# operation naely%

Ma!iu Mo"e an"

Miniu Mo"e.


2/83

Power

Connections1

19

20

40GND

CLK

GND

VCC

8086

Pin Description:

GND – Pin no. 1, 20

Groun"

CLK – Pin no. 19 – Type 'loc&( pro)i"es the *asic

tiing #or the processor an"

*us controller. It is

asyetric $ith a ++, "utycycle to pro)i"e optii-e"

internal tiing.

VCC – Pin no. 40

''( / po$er supply pin


3/83

Address/ Data Lines

10

11

12

1!

14

1"

16

!9#D14

#D1!

#D12

#D11

#D10

#D9#D8

#D$

#D6

#D"

#D4

#D!

#D2

#D1

#D0

8086

2

!

4

"

6

$8

9

#D1"

Continued…


4/83

Pin Description

#D1"

%#D0 – Pin no. 2%16, !9 – Type &'

#((ress D)t) *+s: 1hese lines constitute the tie ultiple!e"

eory IO a""ress 315 an" "ata 312% 1+% 1% 145 *us. 70 isanalogous to 9:; #or the lo$er *yte o# the "ata *us% pins D


5/83

Address Lines

8086

!"

!6

!$

!8 16#

1$#

18#

19#

#14

#1!

#12

#11

#10

#9

#8

#$

#6

#"

#4#!

#2

#1

#0

#1"!9

10

11

121!

14

1"

16

2

!

4

"

6

$

8

9

Continued…


6/83

#19&6, #18&", #1$&4, #16&! – Pin no. !"%!8 – Type '

#((ress & t)t+s: During 1 these are the #our ost signi#icant

a""ress lines #or eory operations. During IO operations these

lines are lo$. During eory an" IO operations% status

in#oration is a)aila*le on these lines "uring 12% 1+% 1 an" 14.

1he status o# the interrupt ena*le ?@7G *it 3S5 is up"ate" at the

*eginning o# each '@A cycle. 7


7/83

#1$

&4

#16

&!

C-)r)cteristics

0 3@O5 0 7lternate Data

0 Stac&

39IG95 0 'o"e or None Data

S6 is 0 3@O5

1his in#oration in"icates $hich relocation register is presently

*eing use" #or "ata accessing.


8/83

Status Pins S0-

S7

26

2$

28

!4

!"

!6

!$

!8

8086

0, )DE

1, )!D"/

2, )#$/%

$

6

"

4

!

Continued…


9/83

Pin Description

Status: active during T4, T1 and T2 and is returned to the

passive state (1,1,1) during T3 or during TW when R!"#is $%&$' This status is used the *2** +us Controer togenerate a -e-or and %./ access contro signas' !nchange , or during T4 is used to indicate the eginningo0 a us cce and the return to the passive state in T3 or

TW is used to indicate the end o0 a us cce'

2, , 1, , 0, = Pin no. 26% 2 1ype O

Continued…


10/83

1hese signals #loat to +=state O?? in Bhol" ac&no$le"geC.1hese status lines are enco"e" as sho$n.

S2; S; S0; C-)r)cteristics

03@O5 0 0 Interrupt ac&no$le"ge

0 0 ea" IO Port

0 0 rite IO Port

0 9alt

39IG95 0 0 'o"e 7ccess

0 ea" Meory

0 rite Meory

Passi)eContinued

…


11/83

Status "etais

n(ic)tion

0 0 0 Interrupt 7c&no$le"ge

0 0 ea" IO port

0 0 rite IO port

0 9alt

0 0 'o"e access

0 ea" eory

0 rite eory

Passi)e

2S 4S 0S

Continued…


12/83

4

!

n(ic)tions

0 0 7lternate "ata

0 Stac&

0 'o"e or none

Data

Continued…


13/83

S ===== alue o# Interrupt :na*le #lag

===== 7l$ays lo$ 3logical5 in"icating 8086 is

on the *us. I# it is tristate" another *us

aster has ta&en control o# the syste *us.

6S

===== Ese" *y 808< nueric coprocessor to"eterine $hether the 'PE is a 8086 or

8088


14/83

%nterrup

ts

1$

18

8086

N

NT/

Pin Description:

N – Pin no. 1$ – Type

Non > Mas&a*le Interrupt( an e"ge

triggere" input $hich causes a type 2

interrupt. 7 su*routine is )ectore" to )iaan interrupt )ector loo&up ta*le locate"

in syste eory. NMI is not as&a*le

internally *y so#t$are. 7 transition #ro

a @O to 9IG9 initiates the interrupt atthe en" o# the current instruction. 1his

input is internally synchroni-e".

Continued…


15/83

NT/ – Pin No. 18 – Type

Interrupt eFuest( is a le)el triggere" input $hich is saple"

"uring the last cloc& cycle o# each instruction to "eterine i# the processor shoul" enter into an interrupt ac&no$le"ge operation.

7 su*routine is )ectore" to )ia an interrupt )ector loo&up ta*le

locate" in syste eory. It can *e internally as&e" *y

so#t$are resetting the interrupt ena*le *it. IN1 is internallysynchroni-e". 1his signal is acti)e 9IG9.


16/83


17/83

Pin

Description'#LD 'LDA Pin no* +, +0 "pe %/#'#LD. indicates that another -aster is reuesting a ocaus hod' To e acnowedged, $/5" -ust e active$%&$' The processor receiving the hod reuest wiissue $5"! ($%&$) as an acnowedge-ent in the -idde

o0 a T1 coc cce' Si-utaneous with the issuance o0$5"! the processor wi 6oat the oca us and controines' !0ter $/5" is detected as eing 5/W, the processorwi 5/Wer the $5"!, and when the processor needs torun another cce, it wi again drive the oca us andcontro ines'

The sa-e rues as app regarding when the oca us wie reeased'$/5" is not an asnchronous input' 7ternasnchroni8ation shoud e provided i0 the sste- can nototherwise guarantee the setup ti-e'

Continued…


18/83

! - Pin no* 12 "pe #Write: indicates that the processor is per0or-ing a write-e-or or write %./ cce, depending on the state o0 the 9.%/signa' WR is active 0or T2, T3 and TW o0 an write cce' %t isactive 5/W, and 6oats to 3;state /


19/83

D"/! - Pin no* 17 "pe #"ata Trans-it . Receive: needed in -ini-u- sste- thatdesires to use an *2*?.*2*@ data us transceiver' %t is usedto contro the direction o0 data 6ow through the transceiver'5ogica "T.R is euivaent to S1 in the -a7i-u- -ode,

and its ti-ing is the sa-e as 0or 9.%/' (T>$%&$, R>5/W)' This signa 6oats to 3;state /


20/83

ALE Pin no* 13 "pe # !ddress 5atch nae: provided the processor to atch

the address into the *2*2.*2*3 address atch' %t is a$%&$ puse active during T1 o0 an us cce' Aote that!5 is never 6oated'

%"A - Pin no* 14 "pe #

%AT! is used as a read stroe 0or interrupt acnowedgecces' %t is active 5/W during T2, T3 and TW o0 eachinterrupt acnowedge cce'


21/83

$a5 mode

signa&s

8086

GND

26

2$

28

24

2"

29

!0

!1

!!

0GT&/4

1GT&/4

L'CK

2,

1,

0,

0

1

Continued…


22/83

Pin Description.

!/"0 !/", ; Pin no* +0 +, "pe %/#

Reuest .&rant: pins are used other oca us

-asters to 0orce the processor to reease the oca us

at the end o0 the processorBs current us cce' ach pin

is idirectiona with R.&TD having higher priorit

than R.&T1' R.&T has an interna pu up resistor

so -a e e0t unconnected' The reuest.grant

seuence is as 0oows:Continued…


23/83

1' ! puse o0 1 C5E wide 0ro- another oca us -asterindicates a oca us reuest (hod) to the *D*? (puse 1)

2' "uring a T4 or T1 coc cce, a puse 1 C5E wide 0ro- the

*D*? to the reuesting -aster (puse 2), indicates that the*D*? has aowed the oca us to 6oat and that it wi enterthe hod acnowedge state at the ne7t C5E' The CFGBsus inter0ace unit is disconnected ogica 0ro- the ocaus during hod acnowedge'

3' ! puse 1 C5E wide 0ro- the reuesting -aster indicates tothe *D*? (puse 3) that the hod reuest is aout to endand that the *D*? can recai- the oca us at the ne7t C5E'

Continued…


24/83

ach -aster;-aster e7change o0 the oca us is aseuence o0 3 puses' There -ust e one dead C5E ccea0ter each us e7change' Fuses are active 5/W'%0 the reuest is -ade whie the CFG is per0or-ing a

-e-or cce, it wi reease the oca us during T4 o0 thecce when a the 0oowing conditions are -et: Reuest occurs on or e0ore T2' Current cce is not the ow te o0 a word (on an oddaddress)

Current cce is not the =rst acnowedge o0 an interruptacnowedge seuence' ! oced instruction is not current e7ecuting'

Continued…


25/83

L#C - Pin no* 12 "pe #

5/CE : output indicates that other sste- us -asters are notto gain contro o0 the sste- us whie 5/CE is active 5/W'

The 5/CE signa is activated the 5/CE pre=7 instruction

and re-ains active unti the co-petion o0 the ne7t instruction' This signa is active 5/W, and 6oats to 3;state /


26/83

1

0

C-)r)cteristics

03@O5 0 No operation

0 ?irst yte o# Op 'o"e #ro ueue

39IG95 0 :pty the ueue

Su*seFuent *yte #ro ueue


27/83

Common Signa&s

Continued…


28/83

Pin Description:

/D5 % Pin no. !4, Type '

ea"( ea" stro*e in"icates that the processor is per#oring a eory o# IO rea"cycle% "epen"ing on the state o# the S2 pin. 1his signal is use" to rea" "e)ices

$hich resi"e on the 8086 local *us. D; is acti)e @O "uring 12% 1+ an" 1 o#

any rea" cycle% an" is guarantee" to reain 9IG9 in 12 until the 8086 local *us

has #loate".

1his signal #loats to +=state O?? in Bhol" ac&no$le"geC.

/#D – Pin no. 22, Type

:7DH( is the ac&no$le"geent #ro the a""resse" eory or IO "e)ice that it

$ill coplete the "ata trans#er. 1he :7DH signal #ro eory IO is

synchroni-e" *y the 82847 'loc& Generator to #or :7DH. 1his signal isacti)e 9IG9. 1he 8086 :7DH input is not synchroni-e". 'orrect operation is

not guarantee" i# the setup an" hol" ties are not et.

Continued…


29/83

TT5 % Pin No 2! – Type

1:S1; ( input is e!aine" *y the BaitC instruction. I# the 1:S1; input is @O

e!ecution continues% other$ise the processor $aits in an Bi"leC state. 1his input is

synchroni-e" internally "uring each cloc& cycle on the lea"ing e"ge o# '@A.

/T – Pin no. 21 – Type

eset( causes the processor to ie"iately terinate its present acti)ity. 1he

signal ust *e acti)e 9IG9 #or at least #our cloc& cycles. It restarts e!ecution% as

"escri*e" in the instruction set "escription% $hen :S:1 returns @O. :S:1 is

internally synchroni-e".

Continued…


30/83

75&$% Pin No. !4 – Type '

7+s i- n)*e & t)t+s: During 1 the us 9igh :na*le signal 39:;5 shoul"

*e use" to ena*le "ata onto the ost signi#icant hal# o# the "ata *us% pins D=D8.

:ight *it oriente" "e)ices tie" to the upper hal# o# the *us $oul" norally use

9:; to con"ition chip select #unctions. 9:; is @O "uring 1 #or rea"% $rite%

an" interrupt ac&no$le"ge cycles $hen a *yte is to *e trans#erre" on the high

portion o# the *us. 1he S%< status in#oration is a)aila*le "uring 12% 1+ an" 14.1he signal is acti)e @O an" #loats to +=state O?? in Bhol"C. It is @O "uring 1

#or the #irst interrupt ac&no$le"ge cycle.

75 #0

C-)r)cteristics

0 0 hole $or"

0 Epper *yte #ro to o"" a""ress

0 @o$er *yte #ro to e)en a""ress

None Continued…


31/83

N&35 % Pin no. !! – Type %

ini+ & );i+: in"icates $hat o"e the processor is to

operate in.

I# the local *us is i"le $hen the reFuest is a"e the t$o possi*lee)ents $ill #ollo$( @ocal *us $ill *e release" "uring the ne!t cloc&. 7 eory cycle $ill start $ithin + cloc&s. No$ the #our rules

#or a currently acti)e eory cycle apply $ith con"ition

nu*er alrea"y satis#ie".

$i i $ d 8086 S


32/83

$inimum $ode 8086 Sstem

"9GH

9R"

9WR

%/R"%/WR


33/83

! -ini-u- -ode o0 *D*? con=guration depictsa stand aone sste- o0 co-puter where no

other processor is connected' This is si-iar to*D*I oc diagra- with the 0oowingdiJerence'

The "ata transceiver oc which heps the

signas traveing a onger distance to getoosted up' Two contro signas data trans-it.receive are connected to the direction input o0transceiver (Trans-itter.Receiver) and "Asi na wors as enae 0or this oc'

! d C & ti i Di 9


34/83

!ead Cc&e timing Diagram 9or$inimum $ode


35/83

%n the us ti-ing diagra-, data trans-it .receive signa goes ow (RC%K) 0or Readoperation' To vaidate the data, "A signa

goes ow' The !ddress. Status us carries !1?to !1L address ines during +$ (ow) and 0orthe re-aining ti-e carries Status in0or-ation'

The !ddress."ata us carries !D to !1I

address in0or-ation during !5 going high and0or the re-aining ti-e it carries data' The R"ine going ow indicates that this is a Readoperation' The curved arrows indicate the

reationship etween vaid data and R" signa'

Continued…

The TW is Wait ti-e needed to snchroni8e

the 0ast processor with sow -e-or etc'

The Read pin is checed to see whether

an periphera needs -ore ti-e 0or data

rite Cc&e timing Diagram 9or


36/83

rite Cc&e timing Diagram 9or$inimum #peration


37/83

This is the sa-e as Read cce Ti-ing

"iagra- e7cept that the "T.R ine goeshigh indicating it is a "ata Trans-ission

operation 0or the processor to -e-or .

periphera' !gain "A ine goes ow tovaidate data and WR ine goes ow,

indicating a Write operation'


38/83

:us !e;uest < :us rant

"imings in $inimum $odeSstem

1he 9O@D an" 9@D7 tiing "iagra in"icates in 1ie

Space 9O@D 3input5 occurs #irst an" then the processor

outputs 9@D7 39ol" 7c&no$le"ge5.

$a5imum $ode 8086


39/83

$a5imum $ode 8086Sstem


40/83

$emor !ead 9 S c


41/83

$emor !eadtiming in$a5imum $ode

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8086 pin configuration (1)

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