A 94.2%-Peak-Efficiency 1.53A

Direct-Battery-Hook-Up Hybrid

Dickson Switched-Capacitor DC-DC

Converter with Wide Continuous

Conversion Ratio in 65nm CMOS

Wen-Chuen Liu, Pourya Assem, Yutian Lei,

Pavan Hanumolu, Robert Pilawa-Podgurski

University of Illinois Urbana-Champaign

1

Motivation

Power converter requires High conversion ratio

High current / power density

High efficiency

2

WIDE-range

regulation

Li-ion Battery

Wearable or

Portable Device

3V

4.5V

Input OutputPower Converter

0.3V

1V

(Ratio up to 15)

?0

Performance Index

Conventional SC converter Goal 1 but only at some discrete high ratios

Prior arts addressed it using multiple stages but

at the sacrifice of Goal 2

3

Conversion Ratio (V / V)

Effic

ien

cy (

%) Goal 1

Conversion Ratio (V / V)

Cu

rre

nt D

en

sity Goal 2

Performance Index

Conventional buck converters Hard to achieve Goals 1 and 2, due to the large

device voltage stress relative to the output

High voltage rating: higher Rds,on per area

4

Vin

> Vo

+Vo

–

+Vin

–

Hybrid SC Converter

No more charge redistribution loss Reduces the RMS and peak capacitor current

Low Ro and independent of switching frequency

5

Ca

pa

cito

r C

urr

en

t

Time

Conv. SC

Converter

Hybrid SC

Converter Hybrid SC Converter

Conv. SC Converter

M. Seeman and S. Sanders, “Analysis and optimization of switched-capacitor dc-dc converters,” IEEE

Trans. Power Electron., vol. 23, no. 2, pp. 841–851, Mar. 2008.

Hybrid SC Converter

Efficiency improvement Larger capacitors voltage ripple is allowed

Capacitor values can be reduced

fsw can be lowered to reduce switching losses

6

Switching Frequency

Outp

ut Im

pedance, R

o

Hybrid SC Converter

Conv. SC Converter

Conv. SC

Converter

Hybrid SC

Converter

Y. Lei, R. May and R.C.N. Pilawa-Podgurski, “Split-Phase Control: Achieving Complete Soft-Charging Operation of a

Dickson Switched-Capacitor Converter,” IEEE Trans. Power Electron., vol. 31, no. 1, pp. 770-782, Jan. 2016.

System Architecture

Hybrid 4-to-1

Dickson converter

8 power MOSFETs

3 flying capacitors

1 output capacitor

1 inductor

Gate driver (GD)

Level shifter (LS)

Vout regulation

Cap. balancing

7

Reg.ControlADC

1 8D

8D

GD

8LS

8

7D

GD

7LS

7

6D

GD

6LS

6

5D

GD

5LS

5

3D

GD

3LS

3 2D

GD

2

4D

GD

4LS

4

1D

GD

1

AUXV

AUXV

SWV

1V

2V

2V1V

M8 M7 M6 M5

M3 M2

M1M4

INV

DIGV1 8S

3V1V

2V XV

YV1C

2C

3C

AUXV DIGV 1 8S

Die

L

OUTV

SWV

ADC

AUXV

BalanceControl

DP

WM

CLK

OUTV

SWV

Co-PackageCLK

OUTC

LO

AD

R

Digital Controller

4D

AUXV

AUXV

3V

AUXV

2V

AUXV

3D

8D

Package – High Current Density

8

Die (Flipchip)

Interposer

Passives

Converter Area

Test Pads

Reg.ControlADC

1 8D

8D

GD

8LS

8

7D

GD

7LS

7

6D

GD

6LS

6

5D

GD

5LS

5

3D

GD

3LS

3 2D

GD

2

4D

GD

4LS

4

1D

GD

1

AUXV

AUXV

SWV

1V

2V

2V1V

M8 M7 M6 M5

M3 M2

M1M4

INV

DIGV1 8S

3V1V

2V XV

YV1C

2C

3C

AUXV DIGV 1 8S

Die

L

OUTV

SWV

ADC

AUXV

BalanceControl

DP

WM

CLK

OUTV

SWV

Co-PackageCLK

OUTC

LO

AD

R

Digital Controller

4D

AUXV

AUXV

3V

AUXV

2V

AUXV

3D

8D

Capacitor Area Reduction

Conventional boot-strap GD consumes

considerable on-die CB, e.g. CB = 10Cgs

Low Vgs increases Rds,on per area

9

1

11

nV

V

DDB

gs

Cgs

VBOOT Vin

VGHCB

VDDB

CB= nCgs CgsVDDB

S1 S1

Voltage Borrowing Technique

Powered by existing flying capacitors No extra capacitor needed

No extra voltage supply circuit needed

10

C3

C1

C2

M8 M7 M6 M5 M3 M2

M4 M1

0

8D

2INV V

Ringing Reduction

Too fast transition: large ringing

Too slow transition: low efficiency Low Vgs increases conduction loss

Worse if running at higher switching frequency

11

Weak Turn-on / off Transient Behavior

Switch ON Switch OFF

Time

IDS

IDS

VgsVgs

+

‒

DLS

Segmented Gate Driver

Ringing reduction w/o sacrifice of efficiency Weak driver first slows down the transition

Strong driver then raises VGS at a faster rate so that the

switch reaches the low Rds,on sooner

12

Weak Strong Turn-on / off Transient Behavior

LO

Non-segmented GD

Strong driver on/off by sensing feedback

Switch ON Switch OFF

Time

IDS

IDS

VgsVgs

+

‒

DLS

Die Micrograph

65nm bulk CMOS process

132.6 mm

1.5

6 m

m

Measured Efficiency

Vin = 4.2 V, L = 180 nH, DCR = 24 mΩ

14

Ipeak = 1.53A

Measured Efficiency

Vin = 4.2 V, L = 470 nH, DCR = 8 mΩ

15

ηpeak = 94.2%

Performance Comparison

16

GOAL 1 !

Performance Comparison

17

GOAL 2 !

Conclusion

First CMOS implementation of a hybrid

Dickson SC converter High power density and efficiency for high step-down

Good for low-voltage loads powered by Li-ion batteries

Capacitor area reduction Floating gate driver and level shifter are powered by the

flying capacitors themselves

Ringing reduction w/o sacrifice of efficiency Segmented gate driver uses both slow and fast drivers

18

Acknowledgements

This work was supported in part by US Army

Research Lab (ARL), Texas Instruments and

Systems on Nanoscale Information fabriCs

(SONIC)

19

Questions ?

Voltage Borrowing Technique

Selected voltage High enough to turn on switches with low Rds,on

Within switch voltage ratings

20

2V

8D

INV

5D2V

SWV

0

14

INVV

22

INVV

8D

5D

Time0

3 1V V

2INV V

2 SWV VDriving Signal

Supply Voltage