a full 360$^{\circ}$ vector-sum phase shifter with very low rms phase error over a wide bandwidth

$: A Full 360$^{\circ}$ Vector-Sum Phase Shifter With Very Low RMS Phase Error Over a Wide Bandwidth$
1626 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 6, JUNE 2012

A Full 360 Vector-Sum Phase Shifter With VeryLow RMS Phase Error Over a Wide Bandwidth

Alireza Asoodeh and Mojtaba Atarodi, Member, IEEE

Abstract—An innovative vector-sum phase shifter with a full360 variable phase-shift range in 0.18- m CMOS technologyis proposed and experimentally demonstrated in this paper. Itemploys an I/Q network with high I/Q accuracy over a widebandwidth to generate two quadrature basis vector differentialsignals. The fabricated chip operates in the 2.3–4.8 GHz range.The root-mean-square gain error and phase error are less than1.1 dB and 1.4 over the measured frequency span, respectively.The total current consumption is 10.6 mA (phase shifter core:2.6 mA) from a 1.8 V supply voltage and overall chip size is

0.87 0.75 mm . To the best of the authors’ knowledge, this circuitis the first demonstration of microwave CMOS phase shifter withvery low phase error over a wide bandwidth employing the vectorsum method for all monolithic microwave integrated circuit phaseshifters with 360 phase-control range to date.

Index Terms—Active phase-shifter, CMOS analog integratedcircuit, differential amplifier, I/Q network, phased array.

I. INTRODUCTION

O NE of the most important applications of phase shiftersis in phase array systems as electronic beam-steering el-

ements [1]. For this application, relatively low-cost monolithicmicrowave integrated circuits (MMICs) using a CMOS processare preferable to realize phase shifters [20].There are different types of phase shifting techniques suitable

for integrated circuit (IC) implementation, including vectorsum networks, LC-based circuits [2]–[6], all-pass networks [7],true-time-delay circuits [8], and others [9], [10]. In the vectorsum method, after the generation of the in-phase/quadraturesignal by the I/Q network, the output phase is adjusted byadding them with appropriate I/Q amplitudes and polarities. Aprecise quadrature signal generation is therefore an importantcircuit element of the active approach for exact phase shifting.Unfortunately, the generation of quadrature signals using pas-sive couplers/dividers is not an attractive method on account oftheir narrow bandwidth.In this paper, we employ an I/Q network with high I/Q accu-

racy over a wide bandwidth to conduct a full-360 phase shifterwith very low rms phase error in 0.18- m CMOS technology.The phase shifter architecture and performance requirementsare described in Section II. Section III presents the circuit level

Manuscript received July 10, 2011; revised January 31, 2012 and February06, 2012; accepted February 14, 2012. Date of publication April 03, 2012; dateof current version May 25, 2012. This work was supported in part by the U.S.Department of Commerce under Grant BS123456.The authors are with the Sharif University of Technology, Tehran, Iran

(e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TMTT.2012.2189227

Fig. 1. Building blocks of the 360 vector-sum phase shifter.

descriptions of the building blocks in detail. The implementa-tion details and experimental results are discussed in Section IV.

II. ARCHITECTURE

The architecture of the differential vector-sum phase shifteris illustrated in Fig. 1. A differential input signal is split intoquadrature phased - and -vector signals using an I/Q net-work, which also provides differential 50 matching with theprevious stage. This stage, which is composed of three all-passfilters, generates very low quadrature phase error. To the bestof the authors’ knowledge, this network has the lowest quadra-ture phase error over a wide bandwidth. In order to generatean interpolated output signal, a differential adder composed oftwo Gilbert-cell type signed variable gain amplifiers (VGAs)is used. It adds the - and -inputs from the I/Q network withproper polarities and amplitude weights, giving an output signalwith a magnitude of and phase of .For phase resolution, the different amplitude weightings of eachinput of the adder can be accomplished by changing the gain ofeach VGA differently. A differential pair does this work by con-trolling the bias current of the VGAs.

III. INTEGRATED CIRCUIT DESIGN

A. I/Q Network

In the phase synthesis using the vector-sum method, the ac-curacy of output phase heavily depends on the accuracy of thisblock. Two parameters that define the precision of this networkare the amplitude mismatch andquadrature phase-error . Thereason the amplitude mismatch affects the output phase is thedependence of output phases on the amplitude weightings of -and -inputs. In [11], the structure was proposed that gener-ated two quadrature basis vector differential signals with verylow quadrature phase error over a wide bandwidth [Fig. 2(d)].

0018-9480/$31.00 © 2012 IEEE

ASOODEH AND ATARODI: A FULL 360 VECTOR-SUM PHASE SHIFTER 1627

Fig. 2. (a) and (b) All-pass filter. (c) Conventional I/Q network [13], [14]. (d) I/Q network proposed in [11]. (e) PCQAF. (f) SCQAF (the modified I/Q networkfor all frequencies).

Unfortunately, this structure has two obvious defects describedbelow.1) Basic operation and modification of structure proposed

in [11]: As shown in Fig. 2(d), the quadrature generation isbased on the orthogonal phase which split between and

. This structure is the combination of the filters shown inFig. 2(a) and (b). These two filters will have two chief advan-tages if including input impedance and output am-plitude being independent of frequency. More clearly, in theevent that relationship mentioned is satisfied, filters will be con-verted to all-pass filters and their input impedances will be equalto R in all frequencies. Therefore, if relationship (1) is satis-fied, the amplitude mismatch of the structure of Fig. 2(d) will beequal to zero because all sub-filters will be converted to all-passfilters. Furthermore, its input impedance will be independentof frequency. Unfortunately, the biggest problem of this struc-ture is its being very sensitive to the variation of , which ismainly originated from the input capacitance of transistors inthe next stage (Adder Stage). To minimize the sensitivity, thefilter of Fig. 2(b) is used as the - and second stage of -net-work as illustrated in Fig. 2(e) named PCQAF (Parallel Struc-ture of Quadrature All-Pass Filter). Fig. 3(a) and (b) show thequadrature phase error and amplitude mismatch versus at

GHz for the structure proposed in [11], conventional(Fig. 2(c)) and the PCQAF. These values are less than 1.5 and2 dB for PSQAF, 5 and 3.8 dB for the conventional structureand 23 and 1 dB for the structure proposed in [11], respectively,with the variation of capacitor from 0 to 200 fF. The secondproblem with the structure proposed in [11] and also PSQAF isthat they are not appropriate for frequencies below 5 GHz be-cause a large value of the inductor is required. In order tosolve this problem, the structure of Fig. 2(f) (SCQAF), which isthe series counterpart of Fig. 2(e), is suggested. In this config-uration, while their output amplitudes become half, the magni-tudes of inductors are one quarter of its parallel counterpart. Ofcourse, decreasing the output amplitudes can be compensatedby increasing the amplifier gain. The reason for using the fil-ters of Fig. 2(b) and (a) as the - and second stage of -net-

work, respectively, is minimizing the sensitivity of output pa-rameters of SCQAF to the variation of . On the suppositionthat relation (2) is considered, the transfer function and phaseerror from 90 -relationships of SCQAF are given in (3) and (4),respectively

(1)

(2)

(3)

(4)

where

(5)The derivative of the phase with respect to can be written

as

(6)The nominator of (6) has four roots. The product of two pos-

itive roots is

(7)

Where and are the angular frequencies at which thederivative of the phase will be equal to zero [Fig. 4(a)]. Also,in order to be equal the phase error at frequencies and[ at Fig. 4(a)] should satisfy

(8)


Fig. 3. Quadrature errors of the different structures (conventional ([13] and [14]), proposed in [11] and modified structure at GHz). (a) Phase error. (b)Amplitude mismatch.

Fig. 4. (a) Typical curve of output phase error of I/Q network. (b) Maximum quadrature phase error versus bandwidth ratio for the SCQAF.

The substitution of (4) into (8) gives

(9)

All of the terms in (9) will be equal to zero if andafter substituting (7) into (9).To determine the values of , and , set ; as

a result

(10)

Using the relationship and its substitution into (10)gives

(11)

(12)

The product of the roots in the quadratic polynomial in (11)is

(13)

Using the relationship

(14)

The sum of the roots in the quadratic polynomial in (10) is

(15)

The substitution of (12) into (14) gives

(16)

If we suppose and , it canbe proven that in case we want to be

. In order to prove this relationship , it isenough to substitute the relationships ,

in (9) in which and have beensubstituted with and , respectively. Therefore, withrespect to the relationships (13), (14), and (16), the values of el-ements are given in below

(17)


Fig. 5. Quadrature errors of the SCQAF from the loading effect of at GHz. (a) Phase error. (b). Amplitude error. Quadrature errors of the SCQAFfrom device mismatch at GHz. (a) Phase error. (b) Amplitude error. All simulations were done by SPECTRE with foundry passive models.

The quadrature phase error versus is given inbelow

(18)where and

(19)

Fig. 4(b) shows the maximum quadrature phase errorversus the bandwidth ratio .Under the assumption of and GHz, the

following calculations can be made:

In the SCQAF, to provide differential 50 matching withthe previous stage, the value of resistance must be chosen as25 , while this value is equal to 100 in its parallel counter-part.2) Loading effect: It is worthwhile to consider the errors

caused by the loading effects on the SCQAF, which have beenignored for simplicity. This effect, which mainly originatesfrom the input gate capacitance of a transistor in the next stage,can create the amplitude mismatch and modify phase error andthe input impedance of the SCQAF. The phase error, amplitude

mismatch, and modification of input impedance from thisloading effect are given in (20), (21), and (22), respectively, forthe SCQAF. Fig. 5(a) and (b) show the simulation results ofthe quadrature errors caused by at 3.1 GHz for the SCQAF,as well as the theoretical values evaluated from (20) and(21). Although the quadrature phase error of the SCQAF andconventional structure are approximately equal, its amplitudemismatch, which is a much more important parameter thanquadrature phase error because of the dependency of outputphase error on amplitude weightings of - and -input, is muchlower than amplitude mismatch of the conventional structure

(20)

(21)

If

(22)

where


Fig. 6. Vector summing network.

TABLE IVALUES OF ELEMENTS

In this work, in order to minimize the area, the structure of theSCQAF is used. The I/Q network is designed with differential50 [ in the SCQAF] for impedance matchingwith the previous stage. The final optimized values throughSPECTRE simulations are given in Table I. This takes intoaccount about 50 fF of input pad capacitance and 40 fF of, including the input capacitance of the following stage (a

differential adder) and the parasitic layout capacitance. Also, toincrease the density of the capacitor, a sandwich structure hasbeen used. With connecting the metal 4 to the metal 6 and metal3 to metal 5, the density of the capacitor will approximatelytripled.3) Device variation effect: In addition to loading capacitancethat can affect output parameters of SCQAF, the factors in-

cluding mismatch between two inductors , capacitors , in-ductors and capacitors can create amplitude mismatch

and excess quadrature phase error. Fig. 5(c) and (d) show am-plitude mismatch and quadrature phase error curve in terms ofdevice variation individually. These two figures show the sen-sitivity of SCQAF to device variation is approximately low.

B. VGAs

Fig. 6 shows the analog differential signed adder that addsthe - and -signal from the I/Q network together in the currentdomain at the output node, synthesizing the required phase.The analog differential adder is composed of three blocks.

The core of the network is the “vector summation block” wherethe vector addition happens and it consists of eight transistors

. The size of these transistors is optimized throughSPECTRE simulations with respect to the gain in the samestage and the phase and amplitude response in the prior stage.The second block is the “quadrant selection block”. The func-

tion of this block is switching the tail current from one sideto the other side to provide the 180 phase state. For instance,when and , the 0 and 90 currents will beadded at the output node, yielding an output signal in quadrantI. Table II lists the relationship between the state of switches,and , and the quadrant of the final output vector. Owing tothe square-law gain dependency on bias current in CMOS, thevoltage gain at the phase shifter output is approximatedas (23), and the output phase is determined by the I/Qcurrent ratio given in (24)

dB (23)

where

constant

(24)

In order to obtain the desired phases, , the “amplitude con-trol block” shown on the left-hand side of Fig. 4 is used tochange the tail current amplitudes. In this block, a differential


TABLE IIQUADRANT SELECTION TABLE

State of switch: and

Fig. 7. Sum of the currents and versus voltage with and withouttransistors .

pair consisting of PMOS transistors and is biased witha supply current, . A DC control voltage is applied to thegate of to fully steer the current from transistor to

and vice versa.As is steered between and , the drain voltages of

these two transistors also change in a manner that tracks the cur-rent steering process. Since the drains of and are con-nected to the gates of transistors and , it is the mannerin which we can accurately control the tail bias amplitudes.To remove the dependence of current on the drain-source

voltage and also minimize the current variation to the temper-ature and process variation, two transistors are used.These transistors operate in the weak inversion region and cause

and therefore , where isconstant [12]. Consequently, the variation of has no effecton the . Fig. 7 shows the sum of currents and versusvoltage with and without transistors . As it is ex-pected, using these transistors will cause the sum of currentsand to remain constant, and therefore the voltage gain [re-lationship (23)] will be constant with the variation of voltage. One chief advantage of the active phase shifter is the depen-

dence of output phase on - and -path bias current ratio ratherthan the absolute value of the current, so the ratio of I/Q willtrack temperature variations, resulting in constant phase versustemperature.For the measurement purpose, the output buffer including the

transistors , resistor and capacitor is used. The zeroresulting from the parallel combination of will cause toincrease the bandwidth of this stage on account of removing itsdominant pole.

Fig. 8. Die microphotograph of the phase shifter.

IV. EXPERIMENTAL RESULTS

The phase shifter is fabricated using a standard 0.18- mCMOS process. The fabricated die microphotograph is shownin Fig. 8. The core size without output buffer is 0.87 0.75 mm ,and the total size including all the pads is 0.98 0.86 mm . Thephase shifter is measured with external 180 hybrid couplersfor differential signal inputs and outputs. The balun loss iscalibrated out with a standard differential SOLT calibrationtechnique using an Agilent 8510C vector signal network ana-lyzer.The measurement of the output parameters of the phase

shifter including phase and insertion gain at the 0 ( or) and 90 ( or ) should reflect

the I/Q network characteristics accurately [Fig. 9(a) and (b)].The solid curves correspond to simulations with 40 fF loadingcapacitance. For the modified I/Q network used in the phaseshifter (SCQAF), the peak I/Q phase error is less than 1 andgain error is less than 0.3 dB from 2.3 to 4.8 GHz.As the input reflection coefficient is dominantly set by the

I/Q network, a changing phase at the adder does not disturb thecharacteristic. Fig. 10(a) shows the measurement results of

the input return loss, together with the simulation curve. Thereason is dependent on the frequency is the existence ofinductances resulting from bonding wire that have been tunedout using two off-chip capacitors. Consequently, this series


Fig. 9. Quadrature error characteristics of the I/Q networks measured at the output of the adder. (a) I/Q phase error. (b) I/Q amplitude mismatch.

Fig. 10. Phase shifter characteristics. (a) Input return loss of the fabricated phase shifter. Measured insertion phase and gain versus frequency and control voltage,. (b) Insertion gain. (c) Insertion phase. (d) RMS phase and gain error versus frequency.

combination severely limits the bandwidth of the whole system[Fig. 10(b)].

A. Phase Shifter

The measured versus frequency and voltage for thisphase shifter is plotted in Fig. 10(b). Fig. 10(c) shows the mea-sured phase shift as a function of the control voltages, (finetuning) plus and (quadrant selection). The results indi-cate a full 360 variable phase shift range from 2.3 to 4.8 GHz.The curves are quite linear across this frequency range. Usingthe measurements plotted in Fig. 10(b) and (c), the rms phaseerror and gain error versus frequency were calculated and the re-sults are shown in Fig. 10(d). The graph illustrates that the phase

error is below 1.4 over the 2.3–4.8 GHz band. The method forthe calculation of rms phase error is based on the relationshipbelow

(25)

is the output phase in which the entire current passtransistor and is the output phase in a given value ofwhose average value at [2.3 GHz, 4.8 GHz] is equal to the


TABLE IIIPERFORMANCE SUMMARY AND COMPARISON TABLE WITH OTHER 360 IC PHASE SHIFTERS

Fig. 11. Measured RF power performance.

steps of a 6-bit phase shifter .Likewise, the rms gain error can be defined as

dB (26)

where

The is th insertion gain in dB-scale corresponding toth output phase and is the average insertion gain indB-scale.The RF power performance of the phase shifter wasmeasured

for some phase shift angle including 45 , 90 , 180 , 250 , and354 , and the results are plotted in Fig. 11. The input referred1-dB compression point is minimum 0.6 dBm for 45phase shift and maximum 3 dBm for 180 .

A performance summary and comparison between this workand other phase shifters exhibiting a 360 variable phase rangeis shown in Table III. The works are arranged from lowest tohighest operating frequency. Since the ICs in Table III coverdifferent frequency bands, a simple one-to-one comparison ofthe performance metrics is not trivial. Therefore, we have cal-culated a very basic metric in Table III, which is the ratio ofaverage to differential value of two frequencies andmultiplied by the rms phase error

(27)

This metric is a measure of the rms phase error being largeor small in a given bandwidth ratio. Using this simple metricreveals that the phase shifter fabricated with this I/Q networkhas the lowest rms phase over a wide bandwidth between thestructures reported till now.

V. CONCLUSION

A full 360 variable active phase shifter IC with very lowrms phase error over a wide bandwidth has been proposed andexperimentally demonstrated in this paper. The fundamental op-eration of the active phase shifters is to interpolate the phases ofthe quadrature input signals by adding two I/Q inputs. The I/Qsignals are generated by an I/Q network with high I/Q accuracy.The I/Q network used in this paper has been modified to haveminimum sensitivity to the variation of . The measured char-acteristics are well matched with simulations from SPECTRE.To the best of the authors’ knowledge, this phase shifter is thefirst demonstration of microwave CMOS phase shifter with verylow phase error over a wide bandwidth using the vector summethod for all MMIC phase shifters with 360 phase-controlrange to date.


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Alireza Asoodeh received the B.Sc. degree in elec-trical engineering from Shiraz University of Tech-nology, Shiraz, Iran, in 2007, and the M.Sc. degreein electronic engineering from Sharif University ofTechnology, Tehran, Iran, in 2010.He is currently working as an IC Designer at the

IC Design Center, Sharif University of Technology.His research interests include design of analog andRF CMOS integrated circuits.

Mojtaba Atarodi (M’93) received the B.S.E.E.degree from Amirkabir University of Technology(Tehran Polytechnic), Tehran, Iran, in 1985, theM.Sc. degree in electrical engineering from the Uni-versity of California, Irvine, in 1987, and the Ph.D.degree from the University of Southern California(USC), Los Angeles, on the subject of analog ICdesign in 1993.From 1993 to 1996, he worked with Linear

Technology Corporation, Milpitas, CA, as a SeniorAnalog Design Engineer and participated in the

design of two IC products in the field of high-frequency high dynamic rangecontinuous-time filters. Since then, he has been consulting with dif-ferent IC companies. He is currently an Associate Professor at Sharif Universityof Technology, Tehran, Iran. He has published more than 80 technical journaland conference papers in the area of analog/RF and mixed-signal integratedcircuit design. He is the author of Analog CMOS IC Design. He has managedseveral IC design projects resulted in several IC products, namely, SIM card IC,smart card IC, PCM codec, and DVB-T/H tuner. He holds one U.S. patent. Hismain research interests are integrated bioelectronics, RF/analog/mixed-signalICs, and integrated circuits for digital TV receivers.

a full 360$^{\circ}$ vector-sum phase shifter with very low rms phase error over a wide bandwidth

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