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Name: Giorgio Muscat

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A2 Electronics Project: 8bit Analogue to

Digital Slope Converter.

ContentsIntroduction: ................................ ................................ ................................ ................................ ..... 2

Project Summary: ................................ ................................ ................................ .......................... 2

Planning the Build: ................................ ................................ ................................ ............................. 2

Project Specification: ................................ ................................ ................................ ..................... 2

Simple Description of the Circuit: ................................ ................................ ............................... 2

Explanation of Circuit in Relation to the Systems Diagram: ................................ ......................... 2

System Diagram: ................................ ................................ ................................ ........................ 3

Quantitative Specification & Design of each Subsystem: ................................ ............................ 4

Subsystem Circuit Diagrams:.. ................................ ................................ .......................... 4A

Full Circuit Diagram:. 4I

Testing of Individual Subsystems in Isolation: ................................ ................................ ............. 8

Connecting Isolated Subsystems & Testing the Final Full Circuit: ................................ .............. 11

The Build & Evaluation: ................................ ................................ ................................ .................... 13

Qualitative Design, Testing, Modifications & Evaluation of Each Subsystem: ................................ 13

Subsystem 1 Latch 1: ................................ ................................ ................................ ............ 13

Subsystem 2 4Hz Relaxation Oscillator: ................................ ................................ ................. 16

Subsystem 3 8bit-Binary up Counter: ................................ ................................ .................... 19

Subsystem 4 The Comparator: ................................ ................................ .............................. 21

Subsystem 5 Latch 2: ................................ ................................ ................................ ............ 25

Subsystem 6 The Microcontroller Output: ................................ ................................ ............. 27

Subsystem 7 The Summing Amplifier (DAC): ................................ ................................ ......... 31

Testing and Evaluation of Subsystems Joined Together in Stages: ................................ ................ 35

Testing Clock / Counter Subsystem Summing Amplifier (DAC), these subsystems together will

be called (Subsystem A) ................................ ................................ ................................ ........... 35

Testing Subsystem (A) Comparator / Latch 1 Subsystem:................................ ....................... 36

Testing Subsystem (A) + Comparator Latch 1: ................................ ................................ ........ 38

Evaluation & Testing of the Complete Circuit: ................................ ................................ .................. 39

Photograph of Complete Circuit: ................................ ................................ ................................ ...... 44

Bibliography ................................ ................................ ................................ ................................ .... 46




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Introduction:

Project Summary:

Overall the project went well. I met the purpose of my project; this was to build a circuit that will

convert an analogue voltage which is inputted into the circuit to a digital voltage that is outputted on

a visual display. Construction of the circuit was a challenge overall, this is mainly due to a

combination of two factors, limited board space and lots of wires connecting subsystems together.

As a result of these factors I had to have unique wiring around the board to reach the designated

subsystem, this was done to stop lots of jumping of wires across multiple subsystems. Although I

met my project specification I did not meet it how I planned, this was mainly due to a problem that

theoretical shouldnt have been a problem, this is explained further into the report when I analyse

the full circuit. However as a result of this problem I was able to find a solution and this allowed for

the circuit to function as planned without changing the circuit majorly. I also discovered a better

way to solve the problem, but this would have needed another subsystem to be added to an alreadyoverly cramped circuit board, and with time short I found that the quick easier fix would be best, the

other solution is also explained in the overall circuit build.

Planning the Build:

Project Specification:

Simple Description of the Circuit:

My Circuit will have a potentiometer that will create an analogue voltage between 5v and 0v, possibly from a heat sensor (Thermistor). This Analogue voltage will enter the slope converter, when

the start conversion button is pressed the input will be converted from an analogue voltage into a

digital hexadecimal output which will be displayed on2 seven segment displays as a two values

between 0-F.

Explanation of Circuit in Relation to the Systems Diagram:

The Circuit activates by pressing a Start Conversion Switch. This will cause Latch 1(Subsystem 1) to

output a low voltage to reset of the Counter (Subsystem 3)and as a result the 8 bit counter will start

to count up.The speed at which the counter counts will vary due to a variable resistor in the

Relaxation Oscillator (Subsystem 2)changing the frequency it outputs. The output of the counter will

be a binary parallel output which is fed into the input of the DAC(Subsystem 7)as well as the input of latch 2(Subsystem 5). The DAC then converts this binary number from the counter into an analogue

voltage which is proportional to the decimal value from the counters output. This analogue voltage

from the DAC is then fed into the non-inverting input of the Comparator(Subsystem 4), and the

analogue input voltage connected to the inverting input.

At T=0 the voltage at the non-inverting input will be 0v as the Counter(Subsystem 3) output will be

hexadecimal 00.The voltage at the inverting input will be x (0v<x<5v). The output of the comparator




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(Subsystem 4) will initially be 0v;this will keep Latch 1(Subsystem 1) outputting a logic high to the

reset pin of the counter. When the Start Conversion Switch is pressed Latch 1 (Subsystem 1)

Latches a low voltage at the input of the counter, as a result the counter will count up.When the

counter counts up the voltage at the output of the DAC(Subsystem 7) (Vdac) also raises, the speed it

is raised at is proportional to the frequency of the Relaxation Oscillator (Subsystem 2).As the counter

con

tin

ues to coun

t the voltage at Vdac con

tin

ues to rise un

til Vdac is greater than

or equal to x (Theanalogue voltage at the Inverting Input). At this point the comparator then switches to output logic

high 5v as the non-inverting input is now greater than the inverting input. This will cause the binary

output from the Counter(Subsystem 3) to be latched by latch 2 (Subsystem 5) as it is connected to

the clock input of the latch, after a short delay Latch 1(Subsystem 1) is reset as it is connected to the

reset pin through two inverters.This will makes the 8bit counter(Subsystem 3) stop counting up and

resets it back to its starting state. However due to the short delay, latch 2(Subsystem 5) would have

already latched the binary outputs from the 8bit counter(Subsystem 3).

This binary output from the Counter (Subsystem 3) is then Outputted in Hex by two 7-seg displays

driven by two microcontrollers(Subsystem 6)using a program including a look up table. The latched

bits from the Latch 2 (Subsystem 5) will be converted from binary digitalto hexadecimal digital andvisually displayed via two 7-segment displays. In theory when the output is displaying FF the

analogue voltage must be 5v and when it displays 00 the analogue voltage in 0v.

System Diagram:

[Cr eated & Impor ted f r om Windows Visio 2010.]




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Quantitative Specification& Design of each Subsystem:

Subsystem 1 Latch 1:

This subsystem will be composed of CMOS Chip & a Push to make switch to act as my Start

Conversion Button. The Chip used will be a 4013 D-Type chip[1] since this is a logic chip so I will also

need to run the subsystem of a 5 Volt Power supply.

In addition to this I will also require a 10k resistor to act as a hold down resistor for my Start

Conversion Button. This resistor will need to be a hold down resistor to ensure the voltage at the

clock input of the D-Type is low until the switch is pushed. I chose a 10kresistor for this hold down

resistor as a value too high may not indicate a logic high at the input to the clock input due to input

impedance of the CMOS chip. These chips have an Input impedance of a few thousand Megohms[2],

if I was to have a hold down resistor of similar value to the input impedance then when I press the

switch I could get a value that does not reach the threshold value for logic state high.

Subsystem 2Relaxation Oscillator:

For testing purposes I want a slow clock speed to allow me to test the Counter and DAC subsystembetter. However I do not want a clock speed that is so long that a full count of the 8bit Counter (256

counts) doesnt take too long. I decided a frequency of 4Hz would be a good speed for testing.

However for the final circuit I will want to place a variable resistor in place of this so when I decrease

the resistance, I get a faster frequency and a faster conversion.

Calculating Values for Relaxation Oscillator at 4Hz:

[3]

[3]

Because I want a Frequency of 4Hz, F must be equal to 4.

;

Rearr anging this equation to make T the subject.

T=0.25 seconds

With the period calculated I am now able to substitute this into the equation for the period and

calculate the resistor value I need.

�I will use a 1µF C apacitor .

�= R= 500,000. Resistance Value = 500k for a Frequency of 4Hz using a capacitor of 1µF.

Since 500k isn't available I will use 560k, this gives a frequency of: 3.571Hz (Using same equation),

this is almost equal to 500k.

I will also be using a CMOS 40106[1]

Schmitt Inverter chip; because of this logic chip I will also need a

5v power supply to power this subsystem.




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Subsystem 32x4bit Binary up Counter:

This subsystem is formed by two CMOS chips. An Inverter chip CMOS 4069[1]

and a dual 4bit-up

counter, CMOS 4520 [1]. This subsystem like all other logic subsystems will be run of a 5v power

supply. This subsystem will have an 8bit digital output which will provide the final digital output for

each set analogue inputs to the slope converter.

[4] n= number of bits.

Since this is an 8bit counter there are 28binary combinations. In total there are 256 combinations

from 0-255. This value will be useful to calculate resistor values for the summing amplifier as a DAC

in subsystem 7.

Subsystem 4The Comparator:

This comparator subsystem is created by a LM324J[5]

Operational Amplifier with no feedback. I will

also need a CMOS chip, CMOS 4069[1]

this is an inverter chip. I will have to use these to produce a

time delay of a few nanoseconds to allow latch2 subsystem 5 to latch before the counter is reset.

Because I am using a CMOS chip, this subsystem will again need to be run of a 5v power supply.

To produce my analogue voltage at the inverting input (-) of the Operational Amplifier I will need a

potentiometer, by connecting the sliding contact to the Inverting Input I am able to produce a

varying voltage from Vsupply to 0v.

Subsystem 5Latch 2:

This subsystem will have an 8bit input bus entering the D ports of two CMOS 4042[1] D-type

Latches. These quad D-Type latch chips will each latch 4 bits of the 8bit input. They will need a 5v

power supply as these chips run on logic high / low. This subsystem has no passive component

values to calculate.

Subsystem 6Microcontroller Output:

This subsystem will require two Atmel ATMega48 microcontroller chips[6]

both used to drive two,

seven segment displays. These seven segment displays need a current limiting resistor to avoid

blowing them. A safe current to use through these LEDs is about 1mA, with a 5v supply there will be

3v across the LEDS as these LEDS have a voltage drop of about 2v. Using Ohms Law I am able to

calculate the resistance value needed.

=300.

The nearest resistor value nearest to but above 300 is a 480 resistor; this is the value I

will use to limit the current through the 7-segment display. This will give me a current of

about 0.6mA which is enough current to light the LEDs, but not too little it will blow them.

Subsystem 7Summing Amplifier (DAC):

The DAC will be formed by a summing Amplifier & an Inverting Amplifier in series. I will use two

LM741[7]

Operational Amplifiers both running of a +15v and 15v supply WHY?. The inverting

Amplifier will need a gain of -1; this is because the summing amplifier will output a negative voltage.

To get a gain of -1 for the inverting amplifier I will need to use the equation:




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So if I want a grain of -1:

I need two resistor of the same value to make -1=-1. The values of these resistors doesnt make a

big difference so I will use 10k for both the feedback resistor and the input resistor.

Because I need my summing amplifier to output -5v after the 256th combination on the counter

(1111, 1111). To do this I will first need to calculate the resolution.[8]

��

Resolution is the smallest increment in the output voltage for every binary count of the counter. At a

frequency of 4Hz, it would take (Period of Relaxation Oscillator x Max number of bits) 64 seconds toreach 5v on the output. This means if I had an input voltage into my Slope Converter of 5v, the

conversion time would be 64 seconds at least for the DAC to reach 5v and cause the comparator to

latch the outputs of the counter. So to conclude for every one binary count the clock does, the

output voltage of the DAC is increased by 0.0195.

To get my Summing Amplifier to give me a resolution of this amount I will need to have a gain that

when I have logic 5v (output from the counter of binary 0000,0001) at the summing amplifier I will

get an output voltage of 0.0195. This equates into this equation:

�

�

When 0000,0001 is input into the summing Amplifier the largest value of Rin is being used. Once I

calculate the largest value of Rin I am able to divide this resistor value by two seven times to give me

all 8 resistor values for the 8bit input.

With a Feedback resistor of 1k the Value of Rin can be calculated with this equation again.

This can be rearranged to:

�

� �




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Because this resistor value would be very hard to produce, I will round the value up to 260k.

However, once this value begins to be divided it will still give resistor values that I will not be able to

produce exactly. This should mean that my DAC will not reach 5v with an input word of 1111,1111.

As it will not be incrementing by the correct resolution every time because the resistor values will

not always be exact.

The other resistor values will need to be; in descending order:

260k,130k,65k,32.5k, 16.25k, 8.125k, 4.0625k, 2.03125k.

These values above are very exact, practically I think this will be very hard to replicate. Instead I will

have to round these values even more giving me an even worse output at the output of my DAC.

In practice I will need to connect multiple resistors together to produce the required values, this

could be done by soldering resistors together to save space on the board. However this could be

time consuming as there is going to be a lot of resistors.

Resistors needed for each value (Resistor values have been rounded):

260k:220k + 39k + 1k =260k.

130k: 120k + 10k = 130k.

65k: 56k + 10k = 66k (1k over actual value).

33k: 33k = 33k.

16k: 15k + 1k = 16k.

8k: 8k2 = 8k2 (0.2k over actual value).

4k: 3k9 = 3k9 (0.1k below actual value).

2k: 1k + 1k = 2k.

Diagram of Resistor Combinations:




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Testing of Individual Subsystems in Isolation:

Testing for Subsystem 1; Latch 1:

The equipment I will need to test this subsystem is, a D-type Latch CMOS Chip, push to make switch,

10k hold down resistor & a Logic Probe.

There are two parts of this subsystem that need to be tested, firstly I need to test that the input to

the latch is functioning properly. To test this I will read the voltage at the input of the latch at pin

(Clock) using the logic probe. I will take the voltage for when the switch is pressed and for when it is

not pressed, recording the state of the input in both scenarios and taken photos of this as evidence. I

will know if its correct if it functions in this way:

Switch Pressed: High Voltage at Pin( C lock)

Switch Not Pressed: Low Voltage at pin ( C lock)

That was the testing of the input of the subsystem. To test the output of this subsystem I will use

exactly the same equipment. I will first record the state of Q[bar] without a rising edge at the clock.

Then I will pulse pin (clock) high by pressing and releasing the push to make switch, after the pulse atthe clock I will record the voltage at Q[bar], again using the logic probe and record both results. The

output will be functioning correctly if these are the results I get:

Before Rising Edge at Clock: Q[ bar ] = High

After Rising Edge pulse at Clock: Q[ bar ]= Low

All of this testing is done with the reset set to low. I will need to then reset the latch to retest it as

Q[bar] should be latched low. This is done because the subsystem is tested individually. In the

overall circuit the reset pin will actually be controlled by the state of the comparator subsystem.

Testing for Subsystem 2; Relaxation Oscillator:

For testing this subsystem I will use an oscilloscope, 1 Micro Farad Capacitor, 560k ohm resistor, 5v

supply & a Schmitt Inverter Chip. To test the subsystem is working correctly I will have to measure

the actual frequency produced by the Relaxation Oscillator with a capacitor of 1 micro Farad & a

resistor of 560k ohm. I will do this by measuring the period of the oscillating voltage at the output of

this subsystem. To do this I will use the trace from the Oscilloscope to show what the period is, and

then by doing 1/t I am able to find the actual frequency and compare it to my theoretical frequency.

This frequency will in most cases not be the same as the calculated theoretical frequency, this is

because the components of have an uncertainty value of about +- 5-10% of what is stated on the

component by the manufacture.

I will know if the subsystem is working correctly as I should find that my actual frequency should be

around 3-4Hz. I will record my testing by taken pictures of the Oscillating Trace on the Oscilloscope,

showing how I calculated the period from the trace.

Testing of Subsystem 3; 2x4bit Binary up Counter:

I need to test and insure that when the two 4 bit counters are connected together they act as an 8

bit counter & count from 00-FF.




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To test this I am going to use my clock subsystem, an inverter chip, a dual 4 bit up counter chip & a

bar graph display. I am going to use this equipment by connecting the relaxation oscillator to the

clock input of the counter. I will then connect a bar graph display to the 8bit output of the counter, I

will make the reset pin low and allow it to start counting. I will then observe the bar graph display

and check that its counting up in binary from 0 - 256. I will know if its working correctly because I

should see on

the LEDS as soon

asI

set R low from high it will begin

coun

tin

g up in

bin

ary from 0000,

0000 - 1111,1111.

Testing of Subsystem 4; the Comparator:

There are two parts of this subsystem that needs testing, firstly I need to test that the pot is

producing a variable voltage between 0-5. The second part of this subsystem that needs testing is

the Op Amp. I need to test that the output of the op amp stays constant until Vdac is greater than or

equal to the analogue voltage. To test the pot I will need a voltmeter, a potentiometer & + 5v supply. To test it is working correctly I

will connect the voltmeter in parallel with the Pot; this will allow me to read the state of the output

voltage from the sliding contact of the pot. I am able to vary the internal resistance of the Pot and

then record the values at the output to check it is varying from 0v-5v. I will know if its working

correctly if I see a varying voltage on the voltmeter as I vary the internal resistance in the pot by

using a screwdriver. The second stage of testing this subsystem requires a Logic Probe as the voltage at the output of the

comparator is digital, high or low. I will also need the comparator chip, a 5v power source, two

potentiometers, 2 pots and two voltmeters. To test this part of the subsystem I will need to measure

the voltage coming into the non-inverting input (+) I will vary the input voltage by using another pot.

I will do the exactly the same with measuring the voltage at the Inverting input (-). I will then adjust

the two pots so I have 3 volts at V (-) & 0v at V (+). I will then measure the state of the output of the comparator using the Logic Probe, and record if its

high or low. I will then make V (+) greater then V (-) by adjusting the resistance of the pot so that I

have an output of about 4volts at V (+). At this point V (+) should be greater thanV (-) so I would then

record the state of the output after the change.

I will know if this is part of the subsystem is functioning correctly if I see these results:

Inverting Input (-) Higher Voltage than Non

Inverting Input (+):

Output equals Logic Low (0v)

Inverting Input (-) Less Voltage than the Non

Inverting Input (+)

Output equals Logic High(5v)

This shows me that when the Non-Inverting Input is greater than or equal to the Inverting, the op-

amp saturates positive at VSupply (5v), When the Inverting Input is greater than or equal to the Non-

Inverting input the op-amp saturates at 0v.

Testing of Subsystem 5; Latch 2:

This subsystem also has two parts of it that need to be tested. I need to test and insure that when an

8 bit word is fed into the d-type, the output remains unchanged until there is a rising edge on the

clock input to the bistable. I also need to test that when there is a rising edge at the clock, the exact




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same word at the input is copied to the output and remains outputting that word even when the

input is changed.

To do this I am going to need 2x 4bit latching switches, an 8 bit D-type bistable, bar graph display

with a current limiting resistor & a debounce switch. To test this part of the subsystem I am going to

connect the two 4bit latching switches to D0-D7 on the latch and at the same time connect the 8

LEDs to Q0-Q7, instead of 8 individual LEDs i am going to connect the 8 LEDs via a bar graph display. I

will then connect the debounce switch into the clock input of the D-type latch to give me a single

rising edge.

To see if its working correctly I will place an 8 bit word at the input of the bistable, I will record the

word at the input as a hex value. At this point the output should be unchanged. I will then push the

debounce switch once to copy D-Q , after doing so I will record the Hex value which corresponds to

the word on the LEDs. I will then change the word on the input and record any changes on the

output.

I should know if this in functioning correctly if I see these characteristics:

- Before Clock Pulse After Clock Pulse After Change in Input

Input Word FF FF 00

Output Word: 00 FF FF Testing of Subsystem 6; Microcontroller Output:

This subsystem involves the testing of each of the Atmel chips and 7 segment-displays. I need to test

that when all 16, 4 bit combinations are placed into the Microcontroller the correct corresponding

hex value in relation to Hex input of the 4 bit word is outputted on the 7 segment.

Firstly before I test the subsystem I will want to make a test program to ensure that all my segments

on the display are functioning correctly, this is because if they are not functioning correctly before I

connect to my subsystem , it could give me a false indication that the subsystem isnt working. To

test the 7-segment displays are working correctly I will output all bits of the Microcontroller high

using this program:[6]

Start: Movi S0 $FF

Out Q, S0.

If all the segments of the 7-Segment Display are lit up, then I will know that they are functioning

correctly as well as the microcontroller.

To test the microcontrollers and display of this subsystem I will need, a 4 bit latching switch, an

Atmel chip & a 7-segment display + current limiting resistor with a 5v power supply. To test this part

of the subsystem I will place all 4 bit word combinations into the 4 input ports of the micro

controller from the latching switch. I will then write down the corresponding hex value that 4 bit

word represents. I will then record the hex value that is being output on the 7-segment display. I will

know if the circuit is functioning to my specification if I see the same hex value that I entered into

the Atmel chip from the switches, being outputted on the 7-segment.




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An example of this would be making all bits high at the latching switch. This hex F should be

converted and outputted at the 7-segment display as an F, I will repeat this for different values at

the input of the micro controllers.

Testing of Subsystem 7; the DAC Summing Amplifier:For this subsystem I will need to test that the gain on the Summing Amplifier is equal to � . I

will also need to test that the inverting amplifier is giving me a gain of -1.

To test the summing amplifier I will need a voltmeter to measure the output voltage from the

Summing Amplifier, I will also need a jump lead to connect the largest resistor value to 5v. To insure

that the gain is correct I will test it my making an input word to the summing amplifier of Hex 01.

This will make the greatest resistor value high. I will be able to tell if the gain of the summing

amplifier is correct because I should see the output voltage of the summing amplifier equal the

resolution. However, this voltage will be negative as it will not have passed through the inverting

amplifier. After doing this I will test to see that the voltage is continuing to rise at a constant value

(the resolution). To do this I will enter the hex word 02 into the input and also 03. This should giveme a voltage that has been incremented by a value 3 times from the 0v at Hex 00.

It will be working correctly if I see these results:

Input Word (Hex): OutputVoltage(V):

00 0

01 0.0195

02 0.039

03 0.0585

However, I should not expect to see these exact values. This is because of rounding in resistancevalues. It will also not equal this exactly because I will not be able to make all the resistance values

easily, therefor I will have some values were I am over sometimes by about 1k.

To test the inverting amplifier, I will input 5v into it. I will then record the output voltage produced.

What I should see is that for any voltage I enter into the inverting amplifier, I should see the exact

same voltage on the output but of opposite polarity (+/-).

Connecting Isolated Subsystems & Testing the Final Full Circuit:

After testing all subsystems in isolation, I will then begin to connect each individual subsystem to

each other and test that they are working correctly when joined together. I will then connect the 2

previous subsystems to the 3rd and so on till finally all subsystems are connected together. At thisstage I will test the circuit overall checking that it meets my specification without any problems, this

will involve making a table for Analogue Voltage in and Hex Voltage out. However before testing the

entire circuit, I will need to test multiple subsystems together as if they were now one subsystem. An

example being; connecting the Relaxation Oscillator (Subsystem 2), to the Counter (Subsystem 3)and

testing the two subsystems as if they were now one larger subsystem. I will need to test that the

counter is counting up at 4Hz. Then connect this larger subsystem of Subsystem 1 & 2 together with




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the DAC subsystem to make another larger subsystem. I will then need to test that the DAC is

incrementing its output by the correct value at the correct speed in relation to the counter.

Testing Clock Subsystem Counter Subsystem &Testing Clock / Counter Subsystem -

Summing Amplifier (DAC):

However, firstly I will connect the clock subsystem into the 8bit counter. I will then test to see that

the counter is counting up from 00-FF at a frequency of 4Hz. I will then connect the 8bit output from

the counter to the 8bit input of the DAC. I will then record the voltage on Vdac (output of DAC) and

check to insure the voltage is rising as the clock counts. I will then place a potentiometer in the clock

subsystem to vary the resistance and change the clock speed at the input of the counter. I will then

test to see that the voltage at Vdac climes faster or slower depending on how I adjust the

potentiometer. This will show me that if I increase the resistance I should find a greater conversion

time to convert the analogue input voltage to a digital output. It should also show me that if I

decrease the resistance of the pot I will get a faster conversion; this is because of the

equation.

Since I am using a constant capacitance value, the period of the relaxation oscillator is proportional

to R. Therefor if I decrease R by a factor of 2 I will also reduce the period by a factor of 2. Since the

Frequency is inversely proportional to the period I should find that my frequency is doubled and as aresult Vdac will count up faster leading to a faster conversion.

Testing Clock / Counter / DAC Subsystem - Comparator:

If that is working correctly, I will join Vdac to the comparator subsystem. This involves wiring Vdac to

the non-inverting input (+). I will then place an analogue voltage at the inverting input from the

potentiometer in the comparator subsystem. I will measure the voltage at the output of the

comparator using a voltmeter. If all is working correctly, I should see 0v at the output until Vdac

voltage reaches the analogue voltage, at this point I should see it switch to 5v and then reset back to

0v when the counter reaches it 256th count and resets back and starts counting again. .

Testing Clock / Counter / DAC / Comparator Subsystem -

Latch 1 / Counter Reset:I will then connect the output of the comparator to the reset on the Latch 1 subsystem, and Q[bar]

of the Latch 1 subsystem to the Reset pin of the counter. I will start the counter by pressing the start

conversion switch and set a voltage at the inverting input of the comparator from the pot. The

counter will count up making Vdac increase also, when the output switches to 5v like i would have

already tested it to do so, I will check that the counter is reset and the voltage at Vdac is reset to 0v.

To do this I will measure the voltage at the output of the DAC. I will know if it working correctly

because i should see a voltage rising up, after time T the voltage at Vdac will = the voltage at the

inverting input, this will cause it to output logic high for a tiny period of time, and cause the counter

to reset, then as a result it will reset the DAC and consequently cause the comparator to output 0v

again and stay there until the start conversion switch is pressed again in latch 1 subsystem.

Testing Clock / Counter / DAC / Comparator/ Latch/ Counter Reset Subsystem Latch 2 /

Microcontroller Subsystem:

Finally I will need to test that the Latch 2 (Subsystem 5) and the Microcontroller Output (Subsystem

6) are functioning correctly when connected to all the other subsystems as one major subsystem. To

test the Latch Subsystem I will connect the Microcontroller Output subsystem to it to make

Subsystem 5 and Subsystem 6 into one larger subsystem. This will allow me to test both subsystems

easier. I will wire the comparator to Latch 2s clock input, and connect the outputs of the counter to




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Latch 2s inputs. I will test to see that when the comparator switches to 5v, the output of the

counter is being latched at the output of latch 2, & is being displayed as Hex value on the 7-segment

displays. I will know it is working because I should see 2 hex values being output on the 7-segment

displays. This value should stay there till I press the start conversion switch again and the

comparator switches to 5v when Vdac = the analogue input voltage.

I will then test the overall circuit as one big subsystem. To do this I will vary the voltages at the input

of the comparator. I will input an analogue voltage of 0, 0.5, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5 and 5 and

record the output values that are displayed on the 7-segment display that correspond to each input

value respectfully. I will then plot this data on a graph to check that the hex value that is being

output is correct in relation to the analogue voltage at the input. What I should find is that the Hex

output is proportional to the analogue input. This means that the Hex output should increase as the

analogue voltage at the input of the comparator subsystem is increased.

The Build & Evaluation:

Qualitative Design, Testing, Modifications & Evaluation of Each Subsystem:


Specification:

This subsystem plays a key role in the control of the entire circuit. The design of this subsystem was

orientated around having an input state that will cause the circuit to function. In this subsystem

using the D-Type latch allowed for an input from a user via a push to make switch to allow for the

circuit to begin its job in converting the analogue voltage. This subsystem has both an input and an

output; both of these must function in the correct manner for the rest of the circuit to function. The

input of this subsystem is sent to the reset pin of the latch. This will cause the D-Type to leave thefrozen state when the input line goes high from another subsystem. This will cause the output of

(Subsystem 1) to stop the Counter subsystem (Subsystem 3) from counting and reset it. This will

allow for my Start Conversion Switch to be used again.

Subsystem Circuit Diagram Figure 1:



Name

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of 47

Output S¢ gnal of Subsystem 1a:

Rec ̈©

d ̈

e

This subsystem was built in stages, and tested in stages Multiple tests we e carried out on this

subsystem as it was constructed in an isolated environment away from other subsystems

Firstly the user input of the subsystem was constructed& tested (Subsystem 1a), as can be seen in

F

© e ! . This involved constructing the hold down switch. The idea of this part of the subsystem

was to have an input low signal at the cloc " input of the D-Type at all times, but to have a rising edge

pulse when the switch is pressed by the user.

Subsystem 1a: This is the initial stage of the build of

Subsystem 1 Latch 1. The image to the left shows the

building of this mini subsystem, this mini subsystem

will act as the one of the inputs to the D-Type.

The testing of this mini subsystem made sure that it

was functioning to my specif ication. To test the

subsystem was functioning correctly# a logic probe was

used to indicate logic high, & logic lowat the output.

The mini subsystem is tested in isolation before it gets

connected to the main part of the subsystem.

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Push to Make Switch:

5v Supply Rail:

Out ut of Subs stem 1a:

0v Rail:




of 47

Once the testing on the mini subsystem (Subsystem 1a) was complete, I then connected it to the

D-Type to create the overall subsystem, shown in F Y

̀

a b e

c . This part of testing Subsystem 1 was

testing the output of the subsystem; this was to ensure that the other subsystem that would

connect to it in the f inal build would be getting the correct input signal.

Jump leads were used for wiring that was not

needed in the f inal build. The overall

subsystem shown in the image on the left

was constructed, and its inverted output

Q [bar] was being tested.

T ed

e f g

h

Red

i p e

d

of the ove q r p p Subd

s d

t emt

Input f u om Mini Subsyst

v

m: Output of Overall Subsystem Q[bar]:

Low Voltage (Switch Not Pressed) High Voltage (5v)

High Voltage Pulse (Switch Pressed & Released) Low Voltage (0v)

Low Voltage (Switch Not Pressed) Low Voltage (0v)

Reset Pin Pulsed w

ix

h: High Voltage (5v)

As the input to the D port of the D-type latch is held at 5vs, when the mini subsystem switch is

pressed a high voltage pulse enters the clock of the D-Type. This causes D to be copied to Q and

latched, there for the output I am using Q [bar] will be low. However before the clock pulse, the reset

D-Type will initial output a High voltage at Q [bar], the inverse to Q . The output of this subsystem will

continue to output 5v until the reset pin (The input of the subsystem) is pulsed high. Then it will

reset back into its other stable state 5v.

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d �

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y

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5v Supply Rail:

D-Type Latch (CMOS 4013)

0v Rail: (Set pin held low)

Output of Subsystem 1a:Output of overall

Subs stem 1, Q [bar]:

Reset of D-Type held low,

it is pulsed high to reset

the latch.

Output of overall Subsystem 1, Q [bar];

displayed on the Logic Probe:




of 47

Ev aluation of Subsystem 1:

Overall this subsystem was very successful; no problems arose at any point in the testing process of

this subsystem. No modifications were made from my initial specification of the subsystem, and all

testing was carried out exactly how I had described I would in the plan.

The purpose of this subsystem was to have a constantly fed high voltage at its output to ensure the

counter reset pin is held high. My testing was very successful and shows the subsystem functioning

exactly how I had planned. I needed the subsystem to switch to a low voltage at its output when a

user inputs a trigger. Again the testing shows this occurring when the Start Conversion Switch is

pulsed high the output of the subsystem will be held low, this is crucial to ensure that the counter of

the other subsystem counts up. The final bit of testing was to ensure that the input of the subsystem

is also functioning to my specification. I wanted the subsystem to output a low voltage after the user

has started the trigger of the subsystem, however I also need it to reset back to its other stable state

when the input line to the subsystem is pulsed high. Again the testing showed that when the reset is

pulsed from high to low on a rising edge the D-type resets to its original state and outputs a 5v.

Subsystem 2 4Hz Relaxation Oscillator:

Specification:

The design of this subsystem was to create a simple a-stable circuit to feed an oscillating output into

the counter. The initial design of this subsystem was to be able to have a set frequency for testing

about 4Hz (Shown in the quantitative specification section), and a variable frequency for the overall

build. This is to allow for a faster or slower conversion if I wanted, doing this will allow me to

illustrate the fundamental problem of the slope converter in comparison to the flash converter. This

problem is the time it takes for a conversion. Due to the nature of the slope converter, the time to

convert an analogue voltage is proportional to the value of the voltage. This is because the counter

will always begin counting up from 0v till it reaches the analogue voltage, therefor if the analogue

voltage is larger, the time it will take to increment the output of the DAC will be larger.





of 47

Rec or d of T e�

ting:

Just like all other subsystems in the build, the relaxation oscillator was constructed in an isolated

environment. Since the subsystem isnt very large and has no input into the subsystem, only the

output of the subsystem needed to be tested.

The jump lead indicates the output of the subsystem; this

is the output of the Schmitt inverter chip shown in f igure 2.

The testing on this subsystem was to ensure that the output was giving me an oscillating signal at a

fre�

uency of about 4Hz. To test this output, I used an oscilloscope to measure the output voltage

against time. This will allow me to calculate the actual fre�

uency of my oscillator, as well as allowing

me to compare it with my theoretical fre�

uency.

T e�

ting Re�

ults for Subsyst em 2 (Trace output of Subsyst em�

:

5v Supply Rail:

0v Rail:

CMOS 40106

Inverter Chip:

Output of Subsystem:

50ms per

Division in

the x-axis:

Start of

Oscillation:

End of

Oscillation:

Trace on

Hold




of 47

From the trace it is possible to calculate the actual frequency of the relaxation oscillator. This is done

by taking the period of the wave. By calculating the time delay from peak to peak or the time delay

from trough to trough it is possible to calculate the period of the wave. Since there is 50ms time

delay per square division in the x-axis, there is 10ms per line division in each square. Therefor from

the Start of Oscillation label in the trace above, to the End of Oscillation label the time delay is

about 5.2 square division

s,

this results in

a time delay of �

= 0.26 secon

ds.

I can now use the data Ive retrieved from my trace to calculate the actual frequency of the

subsystem. Since

I can calculate the actual frequency to be at:

This subsystem I find very interesting in the way it functions, using feedback from the Schmitt

Inverter to create an oscillator. The reason the output of this subsystem gives an oscillating value is

because of the exponential charging and discharging of the capacitor, the speed it charges it

dependent on the current limiting resistor (RF). With a larger resistor, the capacitor takes longer to

charge as fewer electrons are filling up on the positive terminal, of the capacitor, hence why the

Period (T) is proportional to the resistor R. However, initial the capacitor has no charge, and the

input of the Schmitt inverter is low, this causes the output of the Schmitt inverter to be high, the

current then flows through the resistor RF and into the capacitor charging it up and increasing the

voltage at pin 1 of the Schmitt inverter at an exponential rate. The time it takes to charge the

capacitor to about 60% can be calculated by its time constant, �. The capacitor charges at

an exponential rate, which causes it to take around about four time constants to fully charge.[11]

Once the voltage at pin 1 reaches the voltage threshold of the rising edge in the Schmitt Inverter,the

output switch from 5v, to 0v, this causes it to sink current. The current now flows from the capacitor

back through RF towards the output of the subsystem. This now causes the capacitor to discharge at

an exponential decay. Again once the discharge reaches the falling edge threshold voltage of the

Schmitt inverter; it switches again and restarts the loop. This causes the subsystem to function in an

astable manor, (No stable state).


Again the subsystem was very successful, it is behaving exactly how I had planned for it to behave in

Project Specification. The build, test process went very smoothly and no problems arose, hence no

modifications were made to the subsystem from the initial plan.

The reason for having this subsystem in the circuit was to produce an oscillating voltage to input the

counter, from testing it is clear that this subsystem is working as intended and is producing an

oscillating output. Theoretically, this subsystem should produce an oscillation at a frequency of 3.57Hz, calculated from the equation using the 560k and a 1µF Capacitor. From the

testing I calculated the actual frequency to be at 3.84Hz. However the Equation stated above isnt an

exact solution for the period, there is uncertainty in the values of the components. However overall

the subsystem is producing an oscillation that is almost what I had planned for it to produce in the

first place.




of 47

Sub �

�

�

�

3 8bi�

-Bi

r�

up j u

�

rk

l

Spec ifi c ation:

This subsystem has both an output and an input that plays one of the largest roles in the overall

circuit. This subsystem controls the output of the overall circuit as well as playing a large role in the

conversion part of the circuit. There for it is crucial that this subsystem functions in the correct

manner, and that it behaves exactly how I had planned for it to behave in my Project Specif ication.

The design of the subsystem is to produce an 8 bit counter out of a dual 4bit counter. Its purpose in

the circuit is to f eed an 8bit binary up count both into the DAC subsystem as well as the Latch 2

subsystem. The speed of the count is dependent on the fre m uency of Subsystem 2, of which after

testing is 3.84Hz. This subsystem is also dependant on subsystem 1, the output of subsystem 1

controls state of the counter, the counter will be either counting or not counting.

Subsyst em C ir c uit Diagram F igur e 3:

Rec or d of T esting:

This subsystem was constructed in isolation away from the other 2 subsystems that have already

been constructed. Jump leads were used for the output of the counter to illustrate the state of the

outputs on a bar graph display.

0v Rail:

470 n current

limiting SIL resistor:

Bar Graph display:

5v supply Rail:

8bit Output Bus:4069

Inverter

Chip

4520

Dual 4bit

Counter:




of 47

The initial stage of testing this subsystem was to ensure that the two 4bit binary up counters act

together as a single 8bit binary up counter, this was done by inverting the most significant bit on the

first counter and placing it on the clock of the second counter. By doing this, when the most

significant bit goes from high to low it produces a rising edge pulse at the clock of the second 4bit

counter, this is due to the inverter chip. As a result it causes the second counter to count up by one,

an

d thus act as an

8bit coun

ter.

A slight modification was made to ensure that the subsystem was functioning correctly, initially in

my project specification I had planned to use the other subsystem (Relaxation Oscillator) as the

input of the subsystem. However, I modified this to a debounce switch. This is because I want each

subsystem to be tested in complete isolation initially, the reason for this is that it will allow me to

fault find much easier if only one subsystem is connected.

Testing Results for Subsystem 3:

Nuo

ber of Pulses froo

Debounce Switch: 8bit-Output Word

0 0000,0000 (00)

1 0000,0001 (01)

2 0000,0010 (02)256 1111,1111 (FF)

Evidence of this testing can be seen in the images below, the r ight hand image shows the state of the

8-bit output after 256 clock pulses f r om the debounce switch. The image on the left shows the initial

output after the r eset pin on both clocks goes high.

Mo

ifications to Subsystem 3:A slight modification was made to the subsystem, this was not due to a problem but instead to

enhance the testing preformed on the subsystem. By using a debounce switch as the input of the

clock, I can remove any problems that may occur by connecting subsystems together. Using a

debounce switch also allows me to get a clean single rising edge every time I input a switch press,

this allowed for test results to be recorded easier, although testing the 256th

pulse took a while.




of 47


Overall testing on this subsystem shows it to be functioning to my specification. For every pulse at

the input, the counter increments its output by a binary count of 1. This continues to increment until

it reaches its maximum count, 256 (Calculated in the Project Specification Section). Because it

reaches a count of 256, and my testing shows it to be outputting the largest word after the largest

number of counts. This leads me to conclude that the subsystem is correctly functioning as an 8bit

counter, constructed out of 2 bit counters.

Subsystem 4 The Comparator:

Specification:

Like subsystem 1, this subsystem has a mini subsystem built into it. This is the analogue voltage input

of the entire circuit; however it is also one of the inputs of this subsystem. For testing I need to first

ensure that this mini subsystem is producing an analogue voltage from 0v-5v. Secondly I need to

ensure that the operational amplifier is functioning correctly.

This subsystem like subsystem 3 plays a large role in the overall circuit. Its crucial that the

subsystem functions correctly, this means that the output of the Op-Amp switches from a lowvoltage to a high voltage at the correct moment. The Op-Amp connected with no feedback acts as a

comparator. This means that the Op-Amp is constantly checking its two inputs and generating an

output voltage depending on the voltages at the input. Initially the subsystem should be outputting a

low voltage to both the reset pin of latch 1 and a low voltage at the clock of latch 2. Once the voltage

at Vdac reaches the analogue voltage the comparator will switch to its other state and the

subsystem will output 5v. This is because the moment Vdac is greater than the voltage at the

analogue input, the voltage at the non-inverting input (+) will be greater than the voltage at the

inverting input (-). This causes the Comparator to saturate at +5v and thus ensures that it feeds the

correct input to the Latch 1 subsystem and the Latch 2 subsystem.





of 47

Rec or d of T esting:

The initial testing of the subsystem involved constructing the mini subsystemshown in F igur e 4,it

will produce the variable voltage at the inverting input of the Op-Amp; this was constructed in an

isolated environment.

A potentiometer was used to create the analogue voltage; the value

of the analogue voltage can be varied due to moving the sliding

contact across the internal resistor. [12]

As the screw is turned, the

wiper that makes contact with the resistor moves, since this is a

liner pot every degree of turn on the pot produces the same voltage

change at the output of the mini subsystem.

T esting Results for Mini Subsyst em:

Testing the mini subsystem involved measuring the output voltage produced as I varied the internal

voltage drop. Initial, I set the pot to output 0v, and took photographic evidence of this shown below.

I then moved the sliding contact of the pot by using a screwdriver; since this is a multiturn

potentiometer the resolution of the output of the pot is very low, for every degree of turn the

output was incrementing by about 0.025v. This made testing diff icult as it took a lot of turns of the

screwdriver to vary the voltage at the output. However, I still managed to createan output voltage

from the pot of 2v, and 5v.

E v

d

n

o

h

ng

an b

n b

o

h

r

z

ag

ho

h

po ou pu

ng 0v

h

ond

z

ag

ho

h

po ou pu

ng 2v and h

na

z

ag

ho

h

po ou pu

ng

p

a{

vo

ag

|

0v Rail:

Output of mini

subsystem:

5v Supply Rail:

Output of Mini Subsystem,

voltage displayed on Volt

meters to the left:




of 47

Output of

Comparator

Mini

Subsystem:

Once I had tested and was sure that the mini subsystem was functioning to my specif ication, I then

constructed the full subsystem which incorporated this mini subsystem as one of the inputs. This is

shown in F igur e 4.

In this stage of testing Subsystem 4, I want to ensure that the Operational Amplif ier is functioning

correctly. To enhance the testing on the subsystem, I used a substitute for the analogue voltage at

the Non Inverting Input (+). In the f inal build the analogue voltage from the ADC would be input

here, however to ensure the subsystem is tested in a fully isolated environment, I will produce

another mini subsystem to produce a second analogue voltage from a pot.

T esting Results of the overall Subsyst em:

Voltage at Inverting Input (-}

Voltage at Non-Inverting Input (+}

Output of Comparator

0~ 25v 0~ 08v o Vo

ag

0v

0~ 25v 3~ 9v H

gh Vo

ag

5v

Because the Operational Amplif ier is connected with no f eedback, it acts as a comparator. The

characteristics should be that when the Inverting Input (V-) is greater than the Non-Inverting Input

(V+), the op-amp saturates at 0v, this is because the op-amp has inf inite gain and when its in this

state it will try to output a negative voltage, however the lowest voltage that can be produced is 0v.

When the Non Inverting input (V+) is greater than the Inverting Input (V-), the Op-Amp outputs

positive with inf inite gain, however the maximum voltage that can be supplied is 5v, this causesthe

Op-Amp to saturate at 5v.

E v

d

n

o�

�

�

�

ng Ov

ra� �

Sub� � �

�

�

ho

n B

�

o

:� h

�

r �

�

ag �

ho

�

� h

nv

r �

ng

npu�

b

ng

gr

a �

r � han � h

Non

nv

r �

ng

� h

�

au� �

� h

ou � pu � � o b

a�

o vo�

� ag

nd

a �

d on � h

�

og

rob

a�

a gr

n ED). T h

second image sho s t he Inv er ti ng Input at a l o er volt age t han t he Non

Inv er ti ng t his causes t he out put t o be a hi gh volt age (Ind icated on t he l ogic probe as a Red LED).

Voltage at the Inverting Input (V-):Voltage at the Non-Inverting Input

V (+):

Substitute

Subsystem

for Vdac:




of 47

Output of

Comparator

0v:

Mini

Subsystem:

Mod ifi c ations to Subsyst em 4:

A slight modif ication was needed on the mini subsystem. I replaced the multiturn potentiometer

with a standard pot; this is to allow me to vary the voltage faster at the inputs of the op-amp as the

voltage per degree turn on the standard pot is much larger. However no other modif ications were

needed to make the subsystem function.

E v aluation of Subsyst em 4:

Again the subsystem performed just as I expected it to in my specif ication, testing of the subsystem

went very smoothly with the only modif ication made to allow for faster testing. Overall the

subsystem is functioning correctly; I had designed it to produce a low voltage output when the

analogue signal from the mini subsystem is greater than the analogue voltage that would be

produced from the DAC. It is correctly saturating at the correct voltage thresholds, and this will allow

it to produce the correct outputs to be f ed into the Latch 1 subsystem and the Latch 2 subsystem.

Voltage at the Non-Inverting Input

V (+):Voltage at the Inverting Input (V-):

Substitute

Subsystem

for Vdac:




of 47


Specification:

This subsystem design is very similar to Subsystem 1; however this subsystem is a latch consisting of

8-D-types. The purpose of this subsystem in the overall circuit is vital to ensure an output word can

be read when the conversion is finished. This subsystem works with the counter and the comparator

subsystem that have already been tested, to produce an output word of 8bits. The idea of this

subsystem is for it to latch the 8bits at the output of the counter at the exact nanosecond the

comparator switches from a low to high, which was tested in subsystem 4. However this subsystem

must latch the 8bit-word before the counter is reset; this is because the output of the comparator

also controls the reset of the counter. I have designed a delay on the output of the comparator to

the reset of the counter to give this subsystem enough time to latch the outputs.


Recor

of Testing:

Like all other subsystems, there was a large empathises on ensuring the subsystem was tested in

complete isolation. The testing of this subsystem is to ensure that the 8bit-output of the latch

remains unchanged (Not transparent), until there is a rising edge clock pulse at the input of the

counter. At which point I should find the 8bit-word at the input of the Latch to be copied to Q.

However I should find also that the outputs which get copied remain frozen until another clock

pulse, this means no matter how the inputs of the latches change after the clock pulse the outputs

will constantly remain the same until the clock receives another rising edge pulse.

The main important of the testing is the ensure the subsystem gives the correct output for the next

subsystem to function, this output should also depend on the input of the subsystem, there for both

elements of this subsystem will be tested.




of 47


- Before Clo �

Pulse After Clo �

Pulse After Change in Input

Input Word (�

ex � 0 0 7

Output Word: (�

ex�

F 0 0

The testing was done using a 4bit word input into a quad d-type latch, however to make the 8bit

latch this 4bit test i did will just be replicated and joined together to make a 8bit latch.

Initially, I had all of the inputs of the Quad D-Type latch set at 0v. Since a word had already been

latched, the subsystem was outputting a word that had all its bits high (Hex F).I then pulsed the clock

input of the Quad D-Type latched, this caused D to be copied to Q and frozen. As shown in the

results, after a clock pulse the input is converted to the output, however the latch isnt in a

transparent state. This means the output remains constant no matter how the input changed, again

this can be seen in the results that when I changed the input to 0111 (Hex 7), the output remained

outputting 0000 (Hex 0). The set and reset of the latch plays no role in the f inal circuit, thus notesting was needed on these inputs and they were connected to GND to ensure they didnt float.

E v i d ence o�

testi ng l atch can be seen bel o � .

Before Clock Pulse:

The photographs above show that after the clock pulse, even though there in an input word of 0000

(Hex 0), the output remains at 1111 (Hex F). This shows that the subsystem is only switching the

state of its output after every clock pulse; it also shows that the exact word that is input to the D-

Type the moment it is clocked is displayed on the output.

Modif ied

Chip, 4072:

Input Word set to

0000 (Hex 0):

Output Word

0000 (Hex 0):

Input Word set to

1111(Hex F):

Modif ied

Chip, 4072:

Modif ied

Chip, 4072:




of 47

Mo�

ifications to Subsystem 5:

A slight modification was made to this subsystem when I was testing it. The problem arose during

testing this subsystem; the D-Type chip (4042) that I had planned to use was not functioning to my

specification. Instead of latching the output and only changing it after another clock pulse, the

output was acting in a transparent manor. This made the output of the D-Type change with the input

in real time. This means that the moment a different word was input to the D-Type; exactly the same

was being output from the D-type, it had no stable state.

The solution to this problem involved researching a new chip. To fix this problem I used the RS Data

Library[1],

using this source I found a new chip that is also a Quad D-Type latch. I then did some

further research on this chip using the CMOS Cookbook[10]

. I found the 4072 quad D-Type latch, after

reading the CMOS cookbook, if I ground pin 1, 2, 9 and 10 the chip functions as a latching D-Type. To

ensure it worked correctly before I invested time wiring the subsystem onto my circuit board, I

instead wired it on breadboard with jump leads and did a mini test to ensure that it did function to

my specification. After confirming it did work correctly, I substituted it into the place where the 4042

was, grounded the correct pins and resumed the testing. These test results were shown above.


This subsystem was an overall success. My testing of the subsystem showed it to function exactly

how I need the subsystem to work, however a slight modification was needed to ensure the

subsystem worked. I had designed the subsystem to only output a voltage depending on the state of

the input and the clock. The subsystem functioned correctly in isolation using 1 Quad D-Type chip,

by recreating the same subsystem using 2x Quad D-Type chips I was able to create the 8bit D-Type

Latch.

Subsystem 6 The Microcontroller Output :

Specification

This subsystem is not very important relative to the functionality of the analogue to digital

converter. This subsystem does not play any role in that part of the circuit; however the role of this

subsystem is to allow for the output of ADC to be digitally displayed. This will allow the user to easily

and quickly see the state of the output. This subsystem has only one input that is fed into two

microcontroller chips, this in an 8bit input from the output of the Latch 2 Subsystem. This input will

control the state of the output of this subsystem.

This subsystem should display an 8bit word in Hex on 2, 7-segment displays. These 7-segment

displays will be driven by two Atmel Chips. Although this could be done with only one Atmel

microcontroller, it makes the programming a lot more time consuming. Since I am using a look uptable to display the output of this subsystem, I will need 256 different values in the look up table.

This is because there are 256 different combinations that could appear at the input of the

microcontroller, each of which needs its own individual output. Writing a look up table with 256

combinations was a problem, however there is an easy solution. Using 2 Atmel chips, it is possible to

write a short look up table of only 16. This look up table with 16 combinations is because I will split

the input of Latch 2 subsystem. There for , since there will now

be 4 bits entering each microcontroller the number of combinations is These 16




of 47

Look u Table Program for an 4bit Input t o be displayed on 1, 7-segment display:[6]

St ar t : In S7 , I (Reads the 4 bit input word and places it in the register S7)

Rcall Read t able (Copies the byte in the lookup table pointed at by S7, into the register

S0. The byte placed into S0, depends on the value in S7.)

Out , S0 (Outputs the byte in S0, to the output port of the microcontroller)

Loo

up T able: $F C , $60, $DA, $F2, $66, $B6, $BE, $E 0, $F E, $E 6, $EE, $3E, $9C , $76, $9E, $8E.

0 1 2 3 4 5 6 7 89 A B C D E F


Input Word: Output on 7-Segment Display:

0000 0

0001 1

0010 2

0011 3 0100 4

0101 5

0110 6

0111 7

1000 8

1001 9

1010 A

1011 B

1100 C

1101 D

1110 E

1111 F

The other 4 bits of the 8bit word from the Latch 2 subsystem was f ed into the second

microcontroller, with exactly the same program and constructed exactly the same. For this reason

no testing was done on the other 4 bits of this subsystem.

E v i d ence o

testi ng t he ov erall subsystem sho n bel o :

Subsyst em with all inputs low out putting 0:

All inputs

set Low:

ATMega 48

Microcontroller

Subsystem

Outputting 0:

Active Low

Reset:




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Subsyst em with all inputs high out putting F:

Once I was sure the subsystem was functioning correctly, I then removed the two microcontrollers

and 7-segment displays from the external circuit board and f ixed them onto the f inal circuit board.

Subsystem 6 mounted on fi nal ci r cuit board:

Due to large amount of wiring and little space, I had to take the wiring of the board. However cable

ties and other methods of keeping the wiring tidy was used. The inputs on the image above are

currently left floating, this is because once I start to wire subsystems together, these inputs will be

wired to the output of subsystem 5 (Latch 2).

All inputs

set High:

ATMega 48

Microcontroller

Active Low

Reset:

Subsystem

Outputting 0:

ATMega 48

Microcontroller

Output of

Subsystem:

5v Supply

Rail:

0v Rail:

All 4 bit of microcontroller 1

connected to 5v.

All 4 bit of

microcontroller 2

connected to 0v.

Output of

Output of




of 47


I felt the construction and testing of this subsystem to be the most challenging, but it overall it went

flawlessly. At no point during the testing or constructing of this subsystem did I get any problems.

The subsystem is functioning exactly to how I had planned it to function, without making any

modifications at all to what I had already planned to do. It is producing the correct output with

reference to the input; this can be seen in the image above.

Subsystem 7 The Summing Amplifier (DAC):

Specification

This subsystem plays a large role in the Analogue to Digital conversion. It is connected to multiple

other subsystems, this means that the input and the output of this subsystem needs to be tested

and must be functioning correctly if I want the other subsystem this one interacts with to also

function correctly. The purpose of this subsystem in the entire build is to produce an analogue

voltage with a corresponding value to a digital word. To do this I will create a summing amplifier, and

an inverting amplifier with a gain of -1 to produce a DAC. This will convert a digital word at the inputfrom the counter, into an analogue voltage to feed into the comparator subsystem. The subsystem

should increment by 0.0195v every binary count from the clock.


Recor

of Testing:The initial bit of testing of this subsystem was ensuring that the correct resistor combinations was

used, this involved testing the combined resistor values in series as well as ensuring that the resistor

values were in the correct order. I should find the resistor values to be a fraction of the calculated

values; this is because the resistor values are 5-10% off the stated value on the resistor.




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Results for Testing Resistor in Series:

Resistor Co

bination: True Resistance Values:

1k + 1k =2k 1.98k (-20)

3k9~4k 3.92k (-80)

8k2~8k 7.99k (-10)15k+1k=16k 16k (0)

33k~32k 33.1k (+1.1k)

56k+10k=66k 65.1k (-900)

120k+10k~132k 129.8k (-2.2k)

220k+39k+1k=260k 257k (-3k)

Total Offset = 5.11k bel ª w what i «

needed. ~ ¬ Almost equal to.

As the resistor combinations shown in figure 7 are below what they should be by about 5k, this will

cause the output of the summing amplifier not to give the correct resolution. However, since the

value is so small it is possible the change will be negligible.

The second part of testing this subsystem was to construct the inverting amplifier and ensure that it

was giving me a gain of -1. To do this I constructed the inverting amplifier like I had designed it to be

in the Project Specification and then tested it.

Results for Testing Inv erting Amplifier

ith a gain of -1:

The input voltage on the X-Axis

and the output voltage on you

Y-Axis.®

This graph shows us that the

subsystem is functioning

correctly. For every input

voltage, it is getting multiplied

by -1 and then output.

The relationship is caused because of the virtual earth at the input of the inverting amplifier. This

virtual earth is because the Op-Amp wants both inputs to be the same voltage all the time, and the

non-inverting input is set to ground. When an input voltage of 5v enters the op-amp it wants the

inverting input to be 0v, so it will output -5 volts. Since both resistors are the same, 5v entered the

input (Inverting Input) with a 10k resistor. This causes a current of

=

= �

-6

-5

-4

-3

-2

-1

0

0 2 4 6

Graph Showing Inverting

Amplifier Voltages:

Graph Showing

Inverting

Amplifier

Voltages:




of 47

=0.5mA to flow across Rin. Since RF = Rin the current across RF =

= � = -0.5mA. This

current then cancels itself out to produce the 0v virtual earth at the inverting input.

T his is ev i d ence t hat t he graph abov e is

corr ect.

The next stage of testing this subsystem is testing that the summing amplif ier is functioning to my

specif ication. This means that the output of the summing amplif ier should vary depending on the

input word on the 8 resistors.

Results for T esting Summing Amplifi er as a negati ve DAC : Input Word to Summing Amplifier: Output Voltage of Summing Amplifier:

0000,0000 0.002( +0.2mV )

0000,0001 0.021 V

0000,0010 0.04 V

0000,0011 0.59 V

0000,0100 0.78 V

1111,1111 4.88 V

As can be seen in these results, they are not what I had planned. This is mainly due to the resistor

values shown in the testing above not being the correct values. However, the values I am getting are

enough to create a suitable ADC; however there may be a slight uncertainty at the output of the

over circuit one complete.

E v i d ence of testi ng t he out put of t he Summi ng Amplifier can be seen bel o ̄ ; t he jump lead s wer e

used t o connect t o 0v and 5v f or each r esist or combi nati on.

Input of Inverting Amplif ier

set to 5v Supply Rail:

Output of Inverting

Amplif ier of Gain -1:

260k Resistor

Combination:

Output of Summing

Amplif ier:

15v yellow wires:

741 Op-Amps:

-15v green wires:

White Jump leads

creating input

word:




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DAC inputs all set low : DAC inputs all set high:

Mod ifi c ations on Subsyst em 7:

There were no real modif ications made to this subsystem however, there are modif ications that I

could have made if I had the time to do so. The modif ication I would have made is due to a slight

problem with the output of the summing amplif ier, it is outputting a very small voltage even though

all there is no input word into it. To f ix this problem I could have used an off set null control, this

involves connecting a potentiometer to pin 1 and 5 of the Operational Amplif ier[13]

with the sliding

pin of the potentiometer connected between GND and-15v. Then by adjusting the sliding contact I

was able to equalise the voltage at the output to 0v when there was an input word of (00 Hex).

E v aluation of Subsyst em7:

This was the f inal subsystem constructed in the overall build; however it was the least successful.

Unlike all my other subsystems this subsystem did not function exactly how I had planned it to

function and this will have some consequences on the functionality of the overall subsystem. The

f irst main issue that will arise is that the peak voltage output by the DAC is only about 4.9v, this

means that the voltage f ed into the Non-Inverting Input (+) will reach its peak at 4.9v, and then reset

back to 0v as th

e counter counts. Th

e problem thi

s brings

is t

hat t

he max

imum voltage t

he overall

system can convert is decreased from 5v, down to 4.9v, although this isnt a huge problem, it

becomes a problem if a user inputs 5v to the inverting input. This will cause the overall subsystem to

enter a loop and continually count up the clock, but never saturate the output of the comparator.

However apart for this minor setback, the subsystem still functions good enough to allow for the

overall build to be constructed.

Inputs set to

5v:

Inputs set to

0v:




of 47

Test i° ±

and Evaluat i² n of Subsystems Joined Together in St ages:

Test ing Clock / Counter Subsystem Summing Amplif ier (DAC), these subsystems

t ogether will be called (Subsystem A)

After testing that all subsystem functioned correctly in isolation, I then started to connect

subsystems together and test them.

The initial testing I did as I began connecting the subsystems together was testing the counter would

count at a rate of 4Hz when the 4Hz Relaxation Oscillator is connected to it. To test this I will also

test the DAC and the counter to make it faster, I will connect the outputs of the counter to the DAC

input. What I should f ind is that the DAC voltage rises up at about 0.021 (From Testing of Subsystem

7), for every clock pulse, since the relaxation oscillator is pulsing at a rate of 4Hz, there will be an

increment of about 0.084v per second.

However, the overall testing of these 3 subsystems will be done using an oscilloscope; this will give

me a better view of the output voltage over time.

Results for T esting Relax ation Osc illator , C ount er & DAC c onnec t ed together Subsyst em ( A³

:

From the trace I can see a voltage that is climbing at a linear rate, however at about2v there is a

slight dip in the voltage. At f irst I thought this was just an anomaly, so I repeated the voltage climb

however I found the exact same dip at the exact same point on the second climb. This dip is

probably due to a change in the binary value of the counter that causes a resistor combination to be

20s per square

division along the

x-axis:

0v

4.88v

2v per square division along

the -axis:




of 47

selected that are far off from what they should be, as you can see in the testing of Subsystem 7, a

few resistor combinations are about 1k off the actual value, this could be the cause of this glitch.

Ev aluation of Testing Clock---> Counter---> DAC (Subsystem A)

Overall, this is showing the DAC functioning correctly even though it is connected to the counter and

the clock subsystem. It also shows me that the clock and the counter are working correctly also,

from the trace I can see a complete cycle from 0v to 4.88v is about 70s. The clock subsystem is

actually outputting at a frequency of 3.8Hz, so from this the actual time it should take is

This shows me that the counter, clock & DAC are functioning to specification. Although like said in

the DAC subsystem testing, the DAC as a slight problem that its outputting only at 4.88v instead of

5v.

Testing Subsystem (A) Comparator / Latch 1 Subsystem:

The next stage of testing involves testing the subsystem I have already connected together, to the

comparator and then the output of the comparator to the D-Type latch which is connected to the

counter. This testing will allow me to test and see that the analogue to digital conversion part of this

subsystem is functioning correctly.

To test this I am initially going to test to see that the comparator is switching from low to a high

voltage at the correct time. To do this I am going to connect the output of the DAC to the non-

inverting input of the Comparator. I will then input a voltage from the mini subsystem of the

comparator subsystem; this will place a voltage at the inverting input of the comparator. From

previous testing of the clock / counter and DAC shows the output of the DAC climbing over time, this

voltage will now climb at the input of the non-inverting input of the comparator. The comparator

should switch to output a high voltage when Vdac becomes greater than the analogue voltage that I

placed at the inverting input.

Results for Testing Subsystem (A) to comparator:

Ti ing Diagra of Co parator & Subsyste A:




of 47

The timing diagram shows me that subsystem As output is climbing up continuously, this is because

there is nothing controlling the reset of the counter subsystem therefor the DAC subsystem will

continue to increment its output at a rate of 4Hz. However the timing diagram shows me that the

Comparator is outputting the correct values, when the output of Subsystem A (Vdac) is less than the

input of the inverting input of the comparator the output is low, however as soon as the Vdac

reach

es th

e voltage at th

e invert

ing

input t

he comparator c

hanges state

.

E v i d ence of Testi ng Subsystem (A) C omparat or:

As can be seen in the testing above, when the voltage at Vdac is greater than the voltage at the

output of the mini subsystem the output of the comparator is high. The image below shows the

state of the comparator output as low, this is because the output of Subsystem (A) is less than the

output of the mini subsystem of the comparator. There for the inverting input is a larger voltage

than the non-inverting and thus the output is 0v.

INSERT IMAGE OF TESTING

ERE

Output of

Comparator:

Vdac Output of

Subsystem (A):

V+

Comparator

Mini subsystem

Output V-

Output of Comparator:

Vdac Output of Subsystem (A):

+

ComparatorMini subsystem

-




of 47

E v aluation of T esting Subsyst em ( A ́

C omparator:

The testing of this was very successful; the testing I did showed me that the comparator is

functioning correctly even when connected to the other subsystems. This will now allow me to

expand my testing further and connect even more subsystems together to work towards to overall

complete circuit.

Test ing Subsystem (A) + Comparat or Lat ch 1:

Results for T esting Subsyst em ( Aµ

+ C omparator Lat c h 1:

Timing Diagram of Sub A + Comparat or:

As you can see from these results, the counter is not counting up until the startconversion button is

pressed. Then it shows that the counter becomes active as soon as the switch is pressed, this can be

seen because Vdac is incrementing its output due to the count of the counter. However, once Vdac

reaches the analogue input voltage atV-, the counter stops counting and the system is reset into a

stable state. However this counter is stopping because of a pulse from the comparator on the reset

pin of latch 1.

E v i d ence of Testi ng t he C omparat or and Latch 1 t o Subsystem (A):

Voltage at V- of

comparator 2.5v

Vdac output

incrementing:

As soon as the voltage

at V+ (Vdac) reaches

the 2.5v at V-, the

comparator pulses a

high voltage, this

resets the counter and

forces the DAC to

out ut 0v




of 47

E v aluation of T esting Subsyst em ( A¶

+ C omparator Lat c h 1:

Again the overall testing was very well, no problems arose during the testing of this, and therefore

no modif ications were made to the overall circuit. All the subsystems are working great together;

this is clearly illustrated in the trace above where the comparator and latch 1 subsystem work

together to stop the counter form counting up once the voltage at the output of the DAC reaches its

target voltage.

Evaluat ion & Test ing of the Complete Circuit:

T esting the F inal Syst em:

Once I had connected Subsystem Analogue to Digital part of the circuit to the visual display the

circuit was complete. I had to now test the overall circuit and ensure the whole thing together was

functioning correctly. At this stage I have tested all the subsystems together apart for the

Microcontroller / Latch 2 subsystems. For this part of testing I will join the Subsystem 5 & Subsystem

6 together to make Subsystem B. I connected subsystem B to the other subsystems that had been

joined together. This was done by connecting the outputs of the counter to the latch 2 subsystem,

and connected the output of the comparator to the latch 2 subsystem also. From previous testing I

know that the output of the comparator and counter are functioning correctly, so for the overall

circuit to function the Subsystem B needs to work.

Results for T esting F inal Syst em:

This image shows that there is

already a word latched at the

output of my D-Type latch

(Subsystem 5), possibly from

previous testing of the latch.

The image also shows also how

I tested the input voltage

against output word to show

that the circuit was functioning

correctly.

Subsystem 5 Latch 2, connected

to Microcontroller Subsystem

with jump leads.




of 47

This data almost shows the output and the input of the circuit to be directly proportional to each

other. The circuit is functioning correctly; it is taking an input voltage and converting it into a digital

word which is displayed in Hex on 2 7-segment displays.

However there were major problems in this part of the testing which forced me to make some major

modifications to the circuit. The problem was invisible to me in the testing process; this is due to an

assumption that was incorrect in practice.

0

50

100

150

200

250

300

0 1 2 3 4 5

Gra Sho i g t t or agai stInput

oltage

Graph Showing Output Word

against Input Voltage

Input·

oltage: ̧utput Hex

¹ or

º : Decimal·

alue:

0 0 0

0.5 1A 26

1 36 54

1.5 54 84

2 82 130

2.5 9C 156

3 B9 185

3.5 D4 212

4 E C 2364.6 FF 256




of 47

E v i d ence of Testi ng Ov erall C i r cuit :

Probl em, Mod ifi c ation & Solution to overall c ir c uit:

The major problem I had with the overall circuit was that when the comparator pulsed a high voltage

to the latch 1 and latches 2 subsystems. The problem was that although I had the input to latch 1 f ed

into two inverters f irst, it was not enough to delay the resetting of the counter subsystem. What I

found was that the counter subsystem would reset just before the outputs of the counter was

latched, this made the visual output continuously display 00 in Hex, as the Latch 2 was constantly

latch a input word of 00.

The modif ication I had to make to ensure the circuit still functioned correctly was to remove the latch 1 subsystem. However what this did was made the counter continuously count up, and

continuously convert the analogue input. There no longer was the ability to use the start conversion

switch in subsystem 1 when I wanted the conversion to occur.

However I discovered a solution to f ix this problem, this involved creating a delayat the input of the

latch 1 subsystem to ensure that the latch 2 subsystem would latch before the counter is reset. To

create this delay I could have created another subsystem if I had the time and board space to do so.

Least Signif icant Bit displayed on

the left hand side of the circuit

board instead of the right:

Least Signif icant Bit displayed on

the left hand side of the circuit

board instead of the right:

Analogue Voltage input from

comparator mini subsystem:

Analogue Voltage input from

comparator mini subsystem:




of 47

Circuit Diagram of Delay Subsystem [11]

This subsystem creates a delay because of the capacitor. As the output of the comparator goes from

low to high, the capacitor starts to charge because there is a potential difference across it. The

current flows from the comparator output through the capacitor to the ground. This charges the

capacitor, after one time constant the capacitor would have charged to 63%. The Schmitt inverters

voltage up threshold is about 3 volts.

RC=time for capacitor to charge to 63%.

63% of 5v = 0.63 x 5 = 3.15v.

This shows that after time delay x the voltage at the input of the Schmitt inverter will be at 3.15v, this is just above the threshold voltage so the output of the Schmitt inverter will now go low, then

with the other inverter the output will go high again and cause a rising edge pulse at the reset pin of

latch 1. This delay will be = to RC. There for I can vary the values of the resistor and capacitor to give

me a small enough delay that the latch 2 would latch the outputs of the counter before it gets reset.

Ev aluating the Final Circuit:

Does the co plete circuit eet the specification?

The circuit meets the specification to a certain extent. I wanted to create a circuit that would convert

and analogue voltage to a digital voltage and be displayed in hexadecimal on 2 7-segment displays.

However, due to an assumption that two inverters at the input of the latch 1 subsystem from thecomparator would give a big enough time delay for the latch 2 to latch the outputs of the

comparator was incorrect, it caused me to have to modify the complete circuit in order for it to

function to the specification. This involved removing subsystem 1 from the build; this caused me to

be unable to control when I wanted the conversion to take place. On the other hand, all other 6

subsystems functioned correctly to my specification, and are producing a correct hexadecimal

output in relation to an analogue input.




of 47

Is the circuit neat with colour-coded wires & sensibly laid out?

As can be seen in the images of the complete circuit fully labelled on page 44, the subsystems were

position in a manner that allowed for the easiest connections to be made with the least amount of

distance the wires would need to travel. This involved placing subsystems like the relaxation

oscillator just above the counter, positioning the counter outputs just above the latch 2, having the

microcontroller 8 bit input directly below the output of latch 2. Although other subsystem such as

the DAC was much more difficult to place, it involved wiring around the board this is because I was

not able to get the input of the DAC near the outputs of the comparator without crossing over wires.

Also illustrated in on page 44 and 45, is a clear colour coding of wire. I used red wires to indicate +5v

connections, and black wire to indicate GND connections. Because I was using a 741 operational

amplifier a +15v and -15v supply rail was also required. Connections to this power rail are clearly

identified by a blue wire to +15v, and a green wire to -15v. Yellow wire, white wire & brown wire

was used for connecting the subsystems together. By using different colours I was able to

differentiate between different subsystems connections in the vast amount of wiring.

Overall I feel that the circuit is as neat as I could possibly have made it, with limited board space and

7 subsystems most of which have an output of 8bits made keeping wiring neat difficult. However, I ensured no jumps across wires were made and I ensured that wires remained parallel to each other

in both horizontal and vertical direction.

Is the circuit reliable in operation?

The overall circuit was very reliable in operation. Although I had no control over when I wanted the

conversion to take place, instead it was constantly converting. However I found that the output was

consistent all the time. If I placed an analogue voltage at the input, the output would convert this

into a digital output and continuously convert the same analogue voltage, what I found was that the

output remained unchanged unless the analogue input voltage was changed. This is a clear

indication that the circuit operates reliably.

Is the solution one of the best possible or could I have i proved on y design?

I feel that the solution to convert an analogue voltage to a digital voltage was good , but not the best.

Firstly, I had the problem of the two latches and the delay from two inverters not being great

enough. I could have improved this design my adding subsystem 8 (The Delay Subsystem) into the

complete build if I had board space and time, this would have fixed the problem of the counter being

reset before its outputs are latched.

However overall the design of a slope converter is not the best design for an ADC, this is due to one

fundamental problem. A slope converter takes time for the output of the DAC to ramp up; this time

delay is dependent on the clock speed at the input of the counter. However, in the world of

electronics speed is essential, especially in communication circuits which an ADC could be used in

(Analogue voltage from microphone Digital voltage to be transferred). The design of an ADC could

have been improved by using faster converters; an example of a faster converter is the flash

converter and the successive-approximation ADC. However overall the design of the slope converter

I designed if I did not encounter the time delay issue is a very good design of a slope converter.




of 47

Photograph of Complete Circuit:

INSERT IMAGE OF COMPLETE CIRCUIT FULLY LABELD:




of 47

INSERT IMAGE OF COMPLETE CIRCUIT NO LABELS:




of 47

Bibliography:

1: RS DATA Librar»

; Published Book Source, Issue Date 1988,Author: An Electrocomponents

Compan»

"

Pg.2¼

Pin out Diagr am of the CMOS (4013)

Pg.10¼

Pin out Diagr am of the CMOS (40106).

2:Williamson-labs.com, Internet Source. (http://www.williamson-labs.com/480_logic.htm)

Webpageused to r esear ch the value for CMOS Input Impedances.

3: Schmitt Trigger Devices, AS workbook, QMC Publication, Author Rob Rutherford.

Page 3 of 8½ Used as a sour ce for the calculation of f r equency f r om the per iod, also used for the

equation of a r elaxation oscillator per iod.

4: Laesieworks.com, Internet Source. http://www.laesieworks.com/digicom/bitscombi.html

Webpage used to r esear ch the equation to calculate the number of combination for n bits.

5: Solarbotics.com, Internet Source. http://www.solarbotics.com/products/lm324/

Webpage used to find the chip name and number for the Oper ational Amplifier useable in my

C ompar ator subsystem.

6: Microcontroller Systems, A2 Workbook, QMC Publication,Author Rob Rutherford.

Page 6 of 35¾ Used for Pin out diagr am for Atmel AT Mega48 chip.

Page 4 of 35¾

Used to find the corr ect Assembler pr ogr aming language to be used in pr ogr aming of the micr ocont r oller .

7: National.com, Internet Source. http://www.national.com/ds/LM/LM741.pdf

Webpage used for the pin out diagr am for the LM741 Oper ational Amplifier that is used in my

compar ator subsystem.

8:Time Division Multiplexing, A2 Workbook, QMC Publication, Author Rob Rutherford

Page 15 of 28¿ Used to r esear ch the equation to calculate the r esolution of the Summing Amplifier in

the DAC subsystem.

9: kpsec.freeuk.com, Internet Source. http://www.kpsec.freeuk.com/components/cmos.htm

Webpage used for pin out diagr am of the CMOS 4520 dual 4bit binar y up counter .

10: CMOS Cookbook; Published Book Source, Issue Date: 1997. DON LANCASTER (Author), Howard

M. Berlin (Author)

Source used to help find a replacement chip to act as a quad d-type latch.




11: Capacitors and Timing Circuits, AS workbook, QMC Publication, Author Rob Rutherford.

Page 6/12À

Sour ce used for time constant explanation and equationÀ

12: How Potentiometer Work, Internet Source, http://tangentsoft.net/elec/movies/tt15.html

Webpage used to bolster under standing of the inter nal mechanics of a potentiometer .

13: Circuit Source Book 1. Published Book Source, Author: Robert A. Penfold

Page 63 of this sour ce used to assist with offset nulling of the oper ational amplifier .

a2 electronics

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