abcelectroniquenotes-application.abcelectronique.com/314/314-67976.pdf · 2009. 2. 8. · this...

DSP56305

24-Bit Digital Signal ProcessorUser’s Manual

Motorola, IncorporatedSemiconductor Products SectorDSP Division6501 William Cannon Drive WestAustin, TX 78735-8598

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Freescale Semiconductor, Inc.

For More Information On This Product, Go to: www.freescale.com

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This document (and other documents) can be viewed on the World WideWeb at http://www.motorola-dsp.com.

This manual is one of a set of three documents. You need the followingmanuals to have complete product information: Family Manual, User’sManual, and Technical Data.

OnCE

is a trademark of Motorola, Inc.

MOTOROLA INC., 1998

Order this document by

DSP56305UM/AD

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended. Motorola and

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity /Affirmative Action Employer.

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MOTOROLA DSP56305 User’s Manual i

TABLE OF CONTENTS

SECTION 1 DSP56305 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31.2 MANUAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31.3 MANUAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51.4 DSP56305 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-61.5 DSP56305 CORE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 1-71.5.1 General Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-71.5.2 Hardware Debugging Support . . . . . . . . . . . . . . . . . . . . . . . . 1-71.5.3 Reduced Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . 1-71.6 DSP56300 CORE FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . 1-81.6.1 Data ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-81.6.1.1 Data ALU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-81.6.1.2 Multiplier-Accumulator (MAC) . . . . . . . . . . . . . . . . . . . . . . 1-91.6.2 Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . . . 1-91.6.3 Program Control Unit (PCU) . . . . . . . . . . . . . . . . . . . . . . . . 1-101.6.4 PLL and Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-111.6.5 JTAG Test Access Port and On-Chip Emulation (OnCE)

Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-111.6.6 On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-121.6.7 Off-Chip Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . 1-131.7 INTERNAL BUSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-131.8 DSP56305 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . 1-141.9 DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . . . 1-151.10 DSP56305 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . 1-151.10.1 General Purpose I/O (GPIO) Functionality . . . . . . . . . . . . . 1-151.10.2 Host Interface (HI32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-161.10.3 Enhanced Synchronous Serial Interface (ESSI) . . . . . . . . . 1-161.10.4 Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . 1-171.10.5 Timer/Event Counter (TEC) . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

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ii DSP56305 User’s Manual MOTOROLA

SECTION 2 SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . .2-1

2.1 SIGNAL GROUPINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-32.2 POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-62.3 GROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-72.4 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-82.5 PHASE LOCK LOOP (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-82.6 EXTERNAL MEMORY EXPANSION PORT (PORT A). . . . . . . .2-92.6.1 External Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-102.6.2 External Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-102.6.3 External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-112.7 INTERRUPT AND MODE CONTROL . . . . . . . . . . . . . . . . . . . .2-152.8 HOST INTERFACE (HI32) . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-182.8.1 Host Port Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-182.9 ENHANCED SYNCHRONOUS SERIAL INTERFACE 0

(ESSI0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-282.10 ENHANCED SYNCHRONOUS SERIAL INTERFACE 1

(ESSI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-322.11 SERIAL COMMUNICATION INTERFACE (SCI) . . . . . . . . . . . .2-352.12 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-362.13 JTAG/ONCE INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-38

SECTION 3 MEMORY CONFIGURATION . . . . . . . . . . . . . . . . . . . .3-1

3.1 MEMORY SPACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-33.1.1 Program Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-33.1.1.1 Program RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-43.1.1.2 Bootstrap ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-43.1.2 Data Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-53.1.2.1 X Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-53.1.2.2 Y Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-63.1.3 Memory Space Configuration . . . . . . . . . . . . . . . . . . . . . . . . .3-63.2 RAM CONFIGURATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-73.2.1 DSP56300 RAM Patch Mechanism . . . . . . . . . . . . . . . . . . . .3-83.2.1.1 Sample Code for DSP56305 Patch Mechanism . . . . . . . .3-8

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MOTOROLA DSP56305 User’s Manual iii

3.3 MEMORY CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . 3-103.3.1 Memory Space Configurations . . . . . . . . . . . . . . . . . . . . . . 3-103.3.2 RAM Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103.4 MEMORY MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113.5 INTERNAL AND EXTERNAL I/O MEMORY MAP . . . . . . . . . . 3-20

SECTION 4 CORE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34.2 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34.3 BOOTSTRAP PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54.3.1 Mode 0: Expanded Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64.3.2 Modes 1–3: Bootstrap according to RTOS mode . . . . . . . . . 4-64.3.3 Modes 4–7: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74.3.4 Mode 8: Expanded Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74.3.5 Mode 9: Bootstrap from Byte-Wide External Memory . . . . . . 4-74.3.6 Mode A: Bootstrap Through SCI . . . . . . . . . . . . . . . . . . . . . . 4-84.3.7 Mode B: Bootstrap through HI32 in 24-bit-wide UB mode

(from 563xx Port A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84.3.8 Mode C: Bootstrap through HI32 in PCI mode . . . . . . . . . . . 4-94.3.9 Mode D: Bootstrap through HI32 in 16-bit-wide UB mode

(ISA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94.3.10 Mode E: Bootstrap through HI32 in 8-bit-wide UB mode in

double-strobe pin configuration . . . . . . . . . . . . . . . . . . . . . . . 4-94.3.11 Mode F: Bootstrap through HI32 in 8-bit-wide UB mode in

single-strobe pin configuration. . . . . . . . . . . . . . . . . . . . . . . 4-104.4 RTOS PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-104.5 INTERRUPT SOURCES AND PRIORITIES . . . . . . . . . . . . . . 4-104.5.1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-114.5.2 Interrupt Priority Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144.5.3 Interrupt Source Priorities within an IPL . . . . . . . . . . . . . . . 4-164.6 DMA REQUEST SOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . 4-194.7 OPERATING MODE REGISTER (OMR) . . . . . . . . . . . . . . . . . 4-214.7.1 Address Tracing Enable (ATE)—OMR Bit 15 . . . . . . . . . . . 4-214.8 PLL CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-224.8.1 PLL Multiplication Factor (MF11:0)—PCTL Bits 0–11 . . . . . 4-224.8.2 Crystal Range (XTLR)—PCTL Bit 15 . . . . . . . . . . . . . . . . . 4-22

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iv DSP56305 User’s Manual MOTOROLA

4.8.3 XTAL Disable (XTLD)—PCTL Bit 16. . . . . . . . . . . . . . . . . . .4-234.8.4 PreDivider Factor Bits (PD3:0)—PCTL Bits 20–23. . . . . . . .4-234.9 DEVICE IDENTIFICATION REGISTER . . . . . . . . . . . . . . . . . .4-234.10 JTAG IDENTIFICATION (ID) REGISTER . . . . . . . . . . . . . . . . .4-234.11 JTAG BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . . . .4-24

SECTION 5 GENERAL PURPOSE I/O. . . . . . . . . . . . . . . . . . . . . . .5-1

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-35.2 PROGRAMMING MODEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-35.2.1 Port B Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . .5-35.2.2 Port C Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . .5-35.2.3 Port D Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . .5-45.2.4 Port E Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . .5-45.2.5 Triple Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4

SECTION 6 HOST INTERFACE (HI32) . . . . . . . . . . . . . . . . . . . . . .6-1

6.1 INTRODUCTION TO THE HOST INTERFACE (HI32) . . . . . . . .6-36.2 HI32 FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-46.2.1 Interface - DSP56300 Core Side. . . . . . . . . . . . . . . . . . . . . . .6-46.2.2 Interface - Host Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-66.2.3 HI32 Features in PCI Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .6-76.2.4 HI32 Features in Universal Bus Modes. . . . . . . . . . . . . . . . . .6-86.3 HI32 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-96.4 HI32 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-106.5 DSP SIDE PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . .6-116.5.1 DSP Control Register (DCTR) . . . . . . . . . . . . . . . . . . . . . . .6-126.5.1.1 Host Command Interrupt Enable (HCIE) Bit 0 . . . . . . . . .6-136.5.1.2 Slave Transmit Interrupt Enable (STIE) Bit 1 . . . . . . . . . .6-136.5.1.3 Slave Receive Interrupt Enable (SRIE) Bit 2 . . . . . . . . . .6-136.5.1.4 Host Flags (HF[5:3]) Bits 5-3 . . . . . . . . . . . . . . . . . . . . . .6-136.5.1.5 Host Interrupt A (HINT) Bit 6 . . . . . . . . . . . . . . . . . . . . . .6-136.5.1.6 Host Data Strobe Mode (HDSM) Bit 13 . . . . . . . . . . . . . .6-146.5.1.7 Host Read/Write Polarity (HRWP) Bit 14 . . . . . . . . . . . . .6-146.5.1.8 Host Transfer Acknowledge Polarity (HTAP) Bit 15 . . . . .6-156.5.1.9 Host DMA Request Polarity (HDRP) Bit 16 . . . . . . . . . . .6-156.5.1.10 Host Reset Polarity (HRSP) Bit 17 . . . . . . . . . . . . . . . . . .6-15

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MOTOROLA DSP56305 User’s Manual v

6.5.1.11 Host Interrupt Request Handshake Mode(HIRH) Bit 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

6.5.1.12 Host Interrupt Request Drive Control (HIRD) Bit 19 . . . . 6-166.5.1.13 HI32 Mode (HM2-HM0) Bits 22-20 . . . . . . . . . . . . . . . . . 6-176.5.1.13.1 Terminate and Reset (HM[2:0] = 000) . . . . . . . . . . . . 6-176.5.1.13.2 PCI Mode (HM = $1). . . . . . . . . . . . . . . . . . . . . . . . . . 6-186.5.1.13.3 Universal Bus Mode (HM = $2) . . . . . . . . . . . . . . . . . 6-186.5.1.13.4 Enhanced Universal Bus Mode (HM = $3): . . . . . . . . 6-196.5.1.13.5 GPIO Mode (HM = $4):. . . . . . . . . . . . . . . . . . . . . . . . 6-196.5.1.13.6 Self Configuration Mode (HM = $5): . . . . . . . . . . . . . . 6-196.5.1.14 DCTR Reserved Control Bits 23, 12-7 . . . . . . . . . . . . . . 6-206.5.2 DSP PCI Control Register (DPCR) . . . . . . . . . . . . . . . . . . . 6-216.5.2.1 Master Transmit Interrupt Enable (MTIE) Bit 1 . . . . . . . . 6-226.5.2.2 Master Receive Interrupt Enable (MRIE) Bit 2 . . . . . . . . 6-226.5.2.3 Master Address Interrupt Enable (MAIE) Bit 4 . . . . . . . . 6-226.5.2.4 Parity Error Interrupt Enable (PEIE) Bit 5 . . . . . . . . . . . . 6-226.5.2.5 Transaction Abort Interrupt Enable (TAIE) Bit 7 . . . . . . . 6-226.5.2.6 Transaction Termination Interrupt Enable (TTIE) Bit 9 . . 6-236.5.2.7 Transfer Complete Interrupt Enable (TCIE) Bit 12 . . . . . 6-236.5.2.8 Clear Transmitter (CLRT) Bit 14 . . . . . . . . . . . . . . . . . . . 6-236.5.2.9 Master Transaction Termination (MTT) Bit 15 . . . . . . . . 6-246.5.2.10 System Error Force (SERF) Bit 16 . . . . . . . . . . . . . . . . . 6-246.5.2.11 Master Access Counter Enable (MACE) Bit 18. . . . . . . . 6-256.5.2.12 Master Wait State Disable (MWSD) Bit 19 . . . . . . . . . . . 6-256.5.2.13 Receive Buffer Lock Enable (RBLE) Bit 20. . . . . . . . . . . 6-266.5.2.14 Insert Address Enable (IAE) Bit 21 . . . . . . . . . . . . . . . . . 6-276.5.2.15 DPCR Reserved Control

Bits 23, 22,17,13,11,10, 8, 6, 3, 0 . . . . . . . . . . . . . . . . . . 6-276.5.3 DSP PCI Master Control Register(DPMC) . . . . . . . . . . . . 6-286.5.3.1 DSP PCI Transaction Address (AR31-AR16) Bits 15-0 . 6-286.5.3.2 DSP PCI Data Burst Length (BL5-BL0) Bits 21-16 . . . . . 6-296.5.3.3 DSP Data Transfer Format Control (FC1-FC0)

Bits 23 and 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-296.5.3.4 In a PCI DSP-to-Host Transaction: . . . . . . . . . . . . . . . . . 6-316.5.3.4.1 If FC = $0 (32-bit data mode): . . . . . . . . . . . . . . . . . . 6-316.5.3.4.2 If FC = $1:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31

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vi DSP56305 User’s Manual MOTOROLA

6.5.3.4.3 If FC = $2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-316.5.3.4.4 If FC = $3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-316.5.3.5 In a PCI Host-to-DSP Transaction: . . . . . . . . . . . . . . . . .6-316.5.3.5.1 If FC = $0 (32-bit data mode): . . . . . . . . . . . . . . . . . . .6-316.5.3.5.2 If FC = $1 or $2:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-316.5.3.5.3 If FC = $3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-326.5.4 DSP PCI Address Register (DPAR) . . . . . . . . . . . . . . . . . .6-326.5.4.1 PCI Bus Command (C3-C0) Bits 11-8 . . . . . . . . . . . . . . .6-336.5.4.2 PCI Byte Enables (BE3-BE0) Bits 15-12 . . . . . . . . . . . . .6-346.5.5 DSP Status Register (DSR) . . . . . . . . . . . . . . . . . . . . . . . . .6-356.5.5.1 Host Command Pending (HCP) Bit 0 . . . . . . . . . . . . . . . .6-356.5.5.2 Slave Transmit Data Request (STRQ) Bit 1 . . . . . . . . . . .6-356.5.5.3 Slave Receive Data Request (SRRQ) Bit 2 . . . . . . . . . . .6-366.5.5.4 Host Flags (HF2-HF0) Bits 5-3. . . . . . . . . . . . . . . . . . . . .6-376.5.5.5 HI32 Active (HACT) Bit 23 . . . . . . . . . . . . . . . . . . . . . . . .6-376.5.5.6 DSR Reserved Status Bits 22-6 . . . . . . . . . . . . . . . . . . . .6-376.5.6 DSP PCI Status Register (DPSR). . . . . . . . . . . . . . . . . . . . .6-386.5.6.1 PCI Master Wait State (MWS) Bit 0 . . . . . . . . . . . . . . . . .6-396.5.6.2 PCI Master Transmit Data Request (MTRQ) Bit 1 . . . . . .6-396.5.6.3 PCI Master Receive Data Request (MRRQ) Bit 2 . . . . . .6-406.5.6.4 Master Address Request (MARQ) Bit 4 . . . . . . . . . . . . . .6-406.5.6.5 Address Parity Error (APER) Bit 5 . . . . . . . . . . . . . . . . . .6-406.5.6.6 Data Parity Error (DPER) Bit 6 . . . . . . . . . . . . . . . . . . . . .6-416.5.6.7 Master Abort (MAB) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . .6-416.5.6.8 Target Abort (TAB) Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . .6-416.5.6.9 Target Disconnect (TDIS) Bit 9 . . . . . . . . . . . . . . . . . . . .6-416.5.6.10 Target Retry (TRTY) Bit 10 . . . . . . . . . . . . . . . . . . . . . . .6-426.5.6.11 PCI Time Out (TO) Bit 11 . . . . . . . . . . . . . . . . . . . . . . . . .6-426.5.6.12 Host Data Transfer Complete (HDTC) Bit 12 . . . . . . . . . .6-426.5.6.13 Remaining Data Count (RDC5-RDC0) Bits 21-16 . . . . . .6-436.5.6.14 DPSR Reserved Bits 23-22, 15-12 and 3. . . . . . . . . . . . .6-436.5.7 Host To DSP Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-436.5.8 DSP Receive Data FIFO (DRXR) . . . . . . . . . . . . . . . . . . . . .6-446.5.9 DSP To Host Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-446.5.10 DSP Master Transmit Data Register (DTXM) . . . . . . . . . . . .6-456.5.11 DSP Slave Transmit Data Register (DTXS) . . . . . . . . . . . . .6-46

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MOTOROLA DSP56305 User’s Manual vii

6.5.12 DSP Host Port GPIO Data Register (DATH) . . . . . . . . . . . . 6-466.5.13 DSP Host Port GPIO Direction Register (DIRH) . . . . . . . . . 6-476.6 HOST SIDE PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . 6-486.6.1 HI32 Control Register (HCTR). . . . . . . . . . . . . . . . . . . . . . . 6-546.6.1.1 Transmit Request Enable (TREQ) Bit 1 . . . . . . . . . . . . . 6-556.6.1.2 Receive Request Enable (RREQ) Bit 2. . . . . . . . . . . . . . 6-566.6.1.3 Host Flags (HF2-HF0) Bits 5 and 3. . . . . . . . . . . . . . . . . 6-576.6.1.4 DMA Enable (DMAE) Bit 6 . . . . . . . . . . . . . . . . . . . . . . . 6-576.6.1.5 Slave Fetch Type (SFT) Bit 7 . . . . . . . . . . . . . . . . . . . . . 6-586.6.1.6 Host Transmit Data Transfer Format (HTF1-HTF0)

Bits 9 and 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-596.6.1.7 Host Receive Data Transfer Format (HRF1-HRF0)

Bits 12 and 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-636.6.1.8 Host Semaphores (HS2-HS0) Bits 16 and 14. . . . . . . . . 6-646.6.1.9 Target Wait State

Disable (TWSD)

Bit 19 . . . . . . . . . . . 6-646.6.1.10 HCTR Reserved Control Bits

31-20, 18-17, 13, 10, and 0. . . . . . . . . . . . . . . . . . . . . . . 6-676.6.2 HI32 Status Register (HSTR) . . . . . . . . . . . . . . . . . . . . . . . 6-686.6.2.1 Transmitter Ready (TRDY) Bit 0 . . . . . . . . . . . . . . . . . . . 6-696.6.2.2 Host Transmit Data Request (HTRQ) Bit 1 . . . . . . . . . . . 6-696.6.2.3 Host Receive Data Request (HRRQ) Bit 2 . . . . . . . . . . . 6-706.6.2.4 Host Flags (HF5-HF3) Bits 5, 4 and 3. . . . . . . . . . . . . . . 6-706.6.2.5 Host Interrupt A (HINT) Bit 6 . . . . . . . . . . . . . . . . . . . . . . 6-706.6.2.6 Host Request (HREQ) Bit 7 . . . . . . . . . . . . . . . . . . . . . . 6-716.6.2.7 HSTR Reserved Status Bits 31-8 . . . . . . . . . . . . . . . . . . 6-716.6.3 Host Command Vector Register (HCVR) . . . . . . . . . . . . . . 6-726.6.3.1 Host Command (HC) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . 6-736.6.3.2 Host Vector (HV6-HV0) Bits 7-1 . . . . . . . . . . . . . . . . . . . 6-746.6.3.3 Host Non-Maskable Interrupt (HNMI) Bit 15 . . . . . . . . . . 6-746.6.3.4 HCVR Reserved Bits 31-16, 14-8 . . . . . . . . . . . . . . . . . . 6-746.6.4 Host Slave Receive Data Register (HRXS) . . . . . . . . . . . . . 6-756.6.5 Host Master Receive Data Register (HRXM) . . . . . . . . . . . 6-766.6.6 Host Transmit Data Register (HTXR) . . . . . . . . . . . . . . . . . 6-766.6.7 Device/Vendor ID Configuration Register (CDID/CVID) . . . 6-786.6.8 Status/Command Configuration Register (CSTR/CCMR) . . 6-786.6.8.1 Memory Space Enable (MSE) Bit 1 . . . . . . . . . . . . . . . . 6-80

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viii DSP56305 User’s Manual MOTOROLA

6.6.8.2 Bus Master Enable (BM) Bit 2 . . . . . . . . . . . . . . . . . . . . .6-806.6.8.3 Parity Error Response (PERR) Bit 6 . . . . . . . . . . . . . . . .6-806.6.8.4 Wait Cycle Control (WCC) Bit 7 . . . . . . . . . . . . . . . . . . . .6-806.6.8.5 System Error Enable (SERE) Bit 8 . . . . . . . . . . . . . . . . . .6-816.6.8.6 Fast Back-to-Back Capable (FBBC) Bit 23 . . . . . . . . . . .6-816.6.8.7 Data Parity Reported (DPR) Bit 24. . . . . . . . . . . . . . . . . .6-816.6.8.8 DEVSEL Timing (DST1-DST0) Bits 26 and 25 . . . . . . . .6-816.6.8.9 Signaled Target Abort (STA) Bit 27 . . . . . . . . . . . . . . . . .6-816.6.8.10 Received Target Abort (RTA) Bit 28. . . . . . . . . . . . . . . . .6-816.6.8.11 Received Master Abort (RMA) Bit 29 . . . . . . . . . . . . . . . .6-826.6.8.12 Signaled System Error (SSE) Bit 30. . . . . . . . . . . . . . . . .6-826.6.8.13 Detected Parity Error (DPE) Bit 31. . . . . . . . . . . . . . . . . .6-826.6.8.14 CSTR Reserved Bits 23-16 . . . . . . . . . . . . . . . . . . . . . . .6-826.6.8.15 CCMR Reserved Bits 15-10 . . . . . . . . . . . . . . . . . . . . . . .6-826.6.8.16 CCMR Not Implemented Bits 9, 5-3 . . . . . . . . . . . . . . . . .6-826.6.9 Class Code/Revision ID Configuration Register

(CCCR/CRID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-836.6.10 Header Type/Latency Timer Configuration Register

(CHTY/CLAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-846.6.10.1 Header Type (HT7-HT0) Bits 23-16 . . . . . . . . . . . . . . . . .6-846.6.10.2 Latency Timer (LT7-LT0) Bits 15-8 . . . . . . . . . . . . . . . . .6-856.6.10.3 CHTY/CLAT Not Implemented Bits 31-24,7-0 . . . . . . . . .6-856.6.11 Memory Space Base Address Configuration Register

(CBMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-866.6.11.1 Memory Space Indicator (MSI) Bit 0 . . . . . . . . . . . . . . . .6-866.6.11.2 Memory Space (MS1-MS0) Bits 2 and 1 . . . . . . . . . . . . .6-876.6.11.3 Pre-fetch (PF) Bit 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-876.6.11.4 Memory Base Address (PM31-PM16) Bits 31-4 . . . . . . .6-876.6.11.5 Universal Bus Mode Base Address (GB10-GB3)

Bits 23-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-876.6.12 Interrupt Line - Interrupt Signal Configuration Register

(CILP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-886.7 SELF CONFIGURATION MODE. . . . . . . . . . . . . . . . . . . . . . . .6-896.7.1 Self Configuration Procedure for the PCI Mode . . . . . . . . . .6-906.7.2 Self Configuration Procedure for the Universal Bus Mode . .6-90

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MOTOROLA DSP56305 User’s Manual ix

6.8 HOST PORT SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-916.9 INTERRUPT VECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1066.10 VIA PROGRAMMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1066.11 EXAMPLES OF HOST TO HI32 CONNECTIONS. . . . . . . . . 6-107

SECTION 7 ENHANCED SYNCHRONOUS SERIAL INTERFACE(ESSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37.2 ESSI ENHANCEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37.3 ESSI DATA AND CONTROL SIGNALS. . . . . . . . . . . . . . . . . . . 7-47.3.1 Serial Transmit Data Signal (STD) . . . . . . . . . . . . . . . . . . . . 7-47.3.2 Serial Receive Data Signal (SRD) . . . . . . . . . . . . . . . . . . . . . 7-57.3.3 Serial Clock (SCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-67.3.4 Serial Control Signal (SC0) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-87.3.5 Serial Control Signal (SC1) . . . . . . . . . . . . . . . . . . . . . . . . . 7-107.3.6 Serial Control Signal (SC2) . . . . . . . . . . . . . . . . . . . . . . . . . 7-127.4 ESSI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . 7-137.4.1 ESSI Control Register A (CRA) . . . . . . . . . . . . . . . . . . . . . . 7-157.4.1.1 Prescale Modulus Select (PM[7:0]) CRA Bits 7-0 . . . . . . 7-157.4.1.2 Reserved CRA Bits 8-10 . . . . . . . . . . . . . . . . . . . . . . . . . 7-157.4.1.3 Prescaler Range (PSR) CRA Bit 11 . . . . . . . . . . . . . . . . 7-157.4.1.4 Frame Rate Divider Control DC[4:0] CRA Bits 16-12 . . . 7-167.4.1.4.1 Normal Mode (MOD = 0) . . . . . . . . . . . . . . . . . . . . . . 7-177.4.1.4.2 Network Mode (MOD = 1; DC

≠

00000) . . . . . . . . . . . 7-177.4.1.4.3 On-Demand Mode (MOD = 1; DC = 00000). . . . . . . . 7-177.4.1.5 Reserved CRA Bit 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-187.4.1.6 Alignment Control (ALC) CRA Bit 18 . . . . . . . . . . . . . . . 7-187.4.1.7 Word Length Control (WL[2:0]) CRA Bits 21-19 . . . . . . . 7-197.4.1.8 Select SC1 as Transmitter 0 Drive Enable (SSC1)

CRA Bit 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-197.4.1.9 Reserved CRA Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-197.4.2 ESSI Control Register B (CRB) . . . . . . . . . . . . . . . . . . . . . . 7-207.4.2.1 Serial Output Flags (OF[1:0]) CRB Bits 1-0 . . . . . . . . . . 7-207.4.2.1.1 Serial Output Flag 0 (OF0) CRB Bit 0 . . . . . . . . . . . . 7-207.4.2.1.2 Serial Output Flag 1 (OF1) CRB Bit 1 . . . . . . . . . . . . 7-217.4.2.2 Serial Control Direction 0 (SCD0) CRB Bit 2 . . . . . . . . . 7-21

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x DSP56305 User’s Manual MOTOROLA

7.4.2.3 Serial Control Direction 1 (SCD1) CRB Bit 3 . . . . . . . . . .7-227.4.2.4 Serial Control Direction 2 (SCD2) CRB Bit 4 . . . . . . . . . .7-227.4.2.5 Clock Source Direction (SCKD) CRB Bit 5. . . . . . . . . . . .7-227.4.2.6 Shift Direction (SHFD) CRB Bit 6 . . . . . . . . . . . . . . . . . . .7-227.4.2.7 Frame Sync Length FSL[1:0] CRB Bits 8-7 . . . . . . . . . . .7-227.4.2.8 Frame Sync Relative Timing (FSR) CRB Bit 9 . . . . . . . . .7-237.4.2.9 Frame Sync Polarity (FSP) CRB Bit 10 . . . . . . . . . . . . . .7-237.4.2.10 Clock Polarity (CKP) CRB Bit 11 . . . . . . . . . . . . . . . . . . .7-247.4.2.11 Synchronous /Asynchronous (SYN) CRB Bit 12 . . . . . . .7-247.4.2.12 ESSI Mode Select (MOD) CRB Bit 13 . . . . . . . . . . . . . . .7-267.4.2.13 Enabling and Disabling Data Transmission

from the ESSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-287.4.2.14 ESSI Transmit 2 Enable (TE2) CRB Bit 14 . . . . . . . . . . .7-287.4.2.15 ESSI Transmit 1 Enable (TE1) CRB Bit 15 . . . . . . . . . . .7-297.4.2.16 ESSI Transmit 0 Enable (TE0) CRB Bit 16 . . . . . . . . . . .7-307.4.2.17 ESSI Receive Enable (RE) CRB Bit 17 . . . . . . . . . . . . . .7-327.4.2.18 ESSI Transmit Interrupt Enable (TIE) CRB Bit 18 . . . . . .7-337.4.2.19 ESSI Receive Interrupt Enable (RIE) CRB Bit 19 . . . . . .7-337.4.2.20 ESSI Transmit Last Slot Interrupt Enable (TLIE)

CRB Bit 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-337.4.2.21 ESSI Receive Last Slot Interrupt Enable (RLIE)

CRB Bit 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-337.4.2.22 ESSI Transmit Exception Interrupt Enable (TEIE)

CRB Bit 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-347.4.2.23 ESSI Receive Exception Interrupt Enable (REIE)

CRB Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-347.4.3 ESSI Status Register (SSISR) . . . . . . . . . . . . . . . . . . . . . . .7-347.4.3.1 Serial Input Flag 0 (IF0) SSISR Bit 0 . . . . . . . . . . . . . . . .7-347.4.3.2 Serial Input Flag 1 (IF1) SSISR Bit 1 . . . . . . . . . . . . . . . .7-357.4.3.3 Transmit Frame Sync Flag (TFS) SSISR Bit 2 . . . . . . . . .7-357.4.3.4 Receive Frame Sync Flag (RFS) SSISR Bit 3 . . . . . . . . .7-357.4.3.5 Transmitter Underrun Error Flag (TUE) SSISR Bit 4 . . . .7-367.4.3.6 Receiver Overrun Error Flag (ROE) SSISR Bit 5 . . . . . . .7-367.4.3.7 ESSI Transmit Data Register Empty (TDE) SSISR Bit 6 .7-367.4.3.8 ESSI Receive Data Register Full (RDF) SSISR Bit 7. . . .7-367.4.4 ESSI Receive Shift Register . . . . . . . . . . . . . . . . . . . . . . . . .7-39

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MOTOROLA DSP56305 User’s Manual xi

7.4.5 ESSI Receive Data Register (RX) . . . . . . . . . . . . . . . . . . . . 7-397.4.6 ESSI Transmit Shift Registers . . . . . . . . . . . . . . . . . . . . . . . 7-397.4.7 ESSI Transmit Data Registers. . . . . . . . . . . . . . . . . . . . . . . 7-407.4.8 ESSI Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . . . 7-407.4.9 Transmit Slot Mask Registers (TSMA, TSMB) . . . . . . . . . . 7-407.4.10 Receive Slot Mask Registers (RSMA, RSMB). . . . . . . . . . . 7-417.5 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-427.5.1 ESSI Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-427.5.2 ESSI Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-447.5.2.1 ESSI Exception Types . . . . . . . . . . . . . . . . . . . . . . . . . . 7-447.5.2.2 Exception Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 7-457.5.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-477.5.3.1 Normal Mode (CRB(MOD) = 0). . . . . . . . . . . . . . . . . . . . 7-477.5.3.2 Network Mode (CRB(MOD) = 1; CRA(DC)

≠

00000) . . . 7-477.5.3.3 On-Demand Mode (CRB(MOD) = 1, DC = 00000) . . . . . 7-497.5.3.4 Synchronous/Asynchronous Operating Modes. . . . . . . . 7-497.5.3.5 Frame Sync Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-507.5.3.5.1 Frame Sync Signal Format. . . . . . . . . . . . . . . . . . . . . 7-507.5.3.5.2 Frame Sync Length for Multiple Devices . . . . . . . . . . 7-507.5.3.5.3 Word Length Frame Sync Position. . . . . . . . . . . . . . . 7-507.5.3.5.4 Frame Sync Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . 7-517.5.3.6 Selecting the Bit Shift Order for the Transmitter . . . . . . . 7-517.5.4 ESSI Flag Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-527.6 GPIO/ESSI SELECTION AND GPIO USAGE . . . . . . . . . . . . . 7-527.6.1 Port Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . 7-537.6.2 Port Direction Register (PRR) . . . . . . . . . . . . . . . . . . . . . . . 7-547.6.3 Port Data Register (PDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-55

SECTION 8 SERIAL COMMUNICATION INTERFACE (SCI) . . . . . 8-1

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38.2 SCI I/O SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38.2.1 Receive Data (RXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48.2.2 Transmit Data (TXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48.2.3 SCI Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48.3 SCI PROGRAMMING MODEL. . . . . . . . . . . . . . . . . . . . . . . . . . 8-58.3.1 SCI Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . 8-9

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xii DSP56305 User’s Manual MOTOROLA

8.3.1.1 Word Select (WDS[0:2]) SCR Bits 0-2 . . . . . . . . . . . . . . . .8-98.3.1.2 SCI Shift Direction (SSFTD) SCR Bit 3 . . . . . . . . . . . . . .8-108.3.1.3 Send Break (SBK) SCR Bit 4 . . . . . . . . . . . . . . . . . . . . . .8-108.3.1.4 Wakeup Mode Select (WAKE) SCR Bit 5 . . . . . . . . . . . .8-108.3.1.5 Receiver Wakeup Enable (RWU) SCR Bit 6 . . . . . . . . . .8-118.3.1.6 Wired-OR Mode Select (WOMS) SCR Bit 7. . . . . . . . . . .8-118.3.1.7 Receiver Enable (RE) SCR Bit 8 . . . . . . . . . . . . . . . . . . .8-118.3.1.8 Transmitter Enable (TE) SCR Bit 9 . . . . . . . . . . . . . . . . .8-128.3.1.9 Idle Line Interrupt Enable (ILIE) SCR Bit 10. . . . . . . . . . .8-128.3.1.10 SCI Receive Interrupt Enable (RIE) SCR Bit 11. . . . . . . .8-138.3.1.11 SCI Transmit Interrupt Enable (TIE) SCR Bit 12 . . . . . . .8-138.3.1.12 Timer Interrupt Enable (TMIE) SCR Bit 13. . . . . . . . . . . .8-138.3.1.13 Timer Interrupt Rate (STIR) SCR Bit 14. . . . . . . . . . . . . .8-138.3.1.14 SCI Clock Polarity (SCKP) SCR Bit 15 . . . . . . . . . . . . . .8-148.3.1.15 SCI Receive with Exception Interrupt Enable (REIE)

SCR Bit 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-148.3.2 SCI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . .8-148.3.2.1 Transmitter Empty (TRNE) SSR Bit 0 . . . . . . . . . . . . . . .8-148.3.2.2 Transmit Data Register Empty (TDRE) SSR Bit 1 . . . . . .8-148.3.2.3 Receive Data Register Full (RDRF) SSR Bit 2. . . . . . . . .8-158.3.2.4 Idle Line Flag (IDLE) SSR Bit 3 . . . . . . . . . . . . . . . . . . . .8-158.3.2.5 Overrun Error Flag (OR) SSR Bit 4 . . . . . . . . . . . . . . . . .8-158.3.2.6 Parity Error (PE) SSR Bit 5 . . . . . . . . . . . . . . . . . . . . . . .8-168.3.2.7 Framing Error Flag (FE) SSR Bit 6. . . . . . . . . . . . . . . . . .8-168.3.2.8 Received Bit 8 Address (R8) SSR Bit 7 . . . . . . . . . . . . . .8-168.3.3 SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . .8-178.3.3.1 Clock Divider (CD[11:0]) SCCR Bits 11–0 . . . . . . . . . . . .8-188.3.3.2 Clock Out Divider (COD) SCCR Bit 12. . . . . . . . . . . . . . .8-188.3.3.3 SCI Clock Prescaler (SCP) SCCR Bit 13 . . . . . . . . . . . . .8-188.3.3.4 Receive Clock Mode Source Bit (RCM) SCCR Bit 14 . . .8-198.3.3.5 Transmit Clock Source Bit (TCM) SCCR Bit 15 . . . . . . . .8-208.3.4 SCI Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-208.3.4.1 SCI Receive Registers (SRX) . . . . . . . . . . . . . . . . . . . . .8-218.3.4.2 SCI Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . . .8-218.4 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-238.4.1 SCI After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-24

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MOTOROLA DSP56305 User’s Manual xiii

8.4.2 SCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-278.4.3 SCI Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . 8-278.4.4 Preamble, Break, and Data Transmission Priority. . . . . . . . 8-288.4.5 SCI Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-298.5 GPIO SIGNALS AND REGISTERS . . . . . . . . . . . . . . . . . . . . . 8-298.5.1 Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . . . 8-298.5.2 Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . . . 8-308.5.3 Port E Data Register (PDRE) . . . . . . . . . . . . . . . . . . . . . . . 8-31

SECTION 9 TIMER/EVENT COUNTER. . . . . . . . . . . . . . . . . . . . . . 9-1

9.1 INTRODUCTION TO THE TIMER/EVENT COUNTER . . . . . . . 9-39.2 TIMER/EVENT COUNTER ARCHITECTURE . . . . . . . . . . . . . . 9-39.2.1 Timer/Event Counter Block Diagram . . . . . . . . . . . . . . . . . . . 9-49.2.2 Timer/Event Counter Programming Model . . . . . . . . . . . . . . 9-49.2.3 Prescaler Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59.2.4 Timer Prescaler Load Register (TPLR) . . . . . . . . . . . . . . . . . 9-59.2.4.1 Prescaler Preload Value PL[20:0] — TPLR Bits 20-0 . . . . 9-69.2.4.2 Prescaler Source PS[1:0] — TPLR Bits 22-21 . . . . . . . . . 9-69.2.4.3 Reserved Bit — TPLR Bit 23. . . . . . . . . . . . . . . . . . . . . . . 9-69.2.5 Timer Prescaler Count Register (TPCR) . . . . . . . . . . . . . . . . 9-79.2.5.1 Prescaler Counter Value PC[20:0] — TPCR Bits 20-0 . . . 9-79.2.5.2 Reserved Bits — TPCR Bits 23-21 . . . . . . . . . . . . . . . . . . 9-79.3 TIMER ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-79.3.1 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-99.3.2 Timer Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . 9-99.3.3 Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . . 9-109.3.3.1 Timer Enable (TE) — TCSR Bit 0 . . . . . . . . . . . . . . . . . . 9-119.3.3.2 Timer Overflow Interrupt Enable (TOIE) — TCSR Bit 1 . 9-119.3.3.3 Timer Compare Interrupt Enable (TCIE) — TCSR Bit 2 . 9-119.3.3.4 Timer Control (TC[3:0]) — TCSR Bits 4-7. . . . . . . . . . . . 9-119.3.3.5 Inverter (INV) — TCSR Bit 8 . . . . . . . . . . . . . . . . . . . . . . 9-139.3.3.6 Timer Reload Mode (TRM) — TCSR Bit 9 . . . . . . . . . . . 9-149.3.3.7 Direction (DIR) — TCSR Bit 11. . . . . . . . . . . . . . . . . . . . 9-159.3.3.8 Data Input (DI) — TCSR Bit 12 . . . . . . . . . . . . . . . . . . . . 9-159.3.3.9 Data Output (DO) — TCSR Bit 13 . . . . . . . . . . . . . . . . . 9-159.3.3.10 Prescaler Clock Enable (PCE) — TCSR Bit 15 . . . . . . . 9-16

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xiv DSP56305 User’s Manual MOTOROLA

9.3.3.11 Timer Overflow Flag (TOF) — TCSR Bit 20. . . . . . . . . . .9-169.3.3.12 Timer Compare Flag (TCF) — TCSR Bit 21. . . . . . . . . . .9-169.3.3.13 Reserved Bits — TCSR Bits 3, 10, 14, 16-19, 22, 23 . . .9-169.3.4 Timer Load Register (TLR) . . . . . . . . . . . . . . . . . . . . . . . . . .9-179.3.5 Timer Compare Register (TCPR) . . . . . . . . . . . . . . . . . . . . .9-179.3.6 Timer Count Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . .9-179.4 TIMER MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . .9-189.4.1 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-199.4.1.1 Timer GPIO (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-199.4.1.2 Timer Pulse (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-209.4.1.3 Timer Toggle (Mode 2) . . . . . . . . . . . . . . . . . . . . . . . . . . .9-219.4.1.4 Timer Event Counter (Mode 3) . . . . . . . . . . . . . . . . . . . . .9-229.4.2 Signal Measurement Modes . . . . . . . . . . . . . . . . . . . . . . . . .9-239.4.2.1 Measurement Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . .9-239.4.2.2 Measurement Input Width (Mode 4) . . . . . . . . . . . . . . . . .9-239.4.2.3 Measurement Input Period (Mode 5) . . . . . . . . . . . . . . . .9-249.4.2.4 Measurement Capture (Mode 6) . . . . . . . . . . . . . . . . . . .9-259.4.3 Pulse Width Modulation (PWM, Mode 7) . . . . . . . . . . . . . . .9-269.4.4 Watchdog Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-279.4.4.1 Watchdog Pulse (Mode 9) . . . . . . . . . . . . . . . . . . . . . . . .9-279.4.4.2 Watchdog Toggle (Mode 10) . . . . . . . . . . . . . . . . . . . . . .9-289.4.5 Reserved Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-299.4.6 Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-299.4.6.1 Timer Behavior during Wait . . . . . . . . . . . . . . . . . . . . . . .9-299.4.6.2 Timer Behavior during Stop . . . . . . . . . . . . . . . . . . . . . . .9-299.4.7 DMA Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-29

SECTION 10 ON-CHIP EMULATION MODULE. . . . . . . . . . . . . . . .10-1

10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-310.2 ONCE MODULE SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-310.3 DEBUG EVENT (DE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-410.4 ONCE CONTROLLER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-510.4.1 OnCE Command Register (OCR). . . . . . . . . . . . . . . . . . . . .10-510.4.1.1 Register Select (RS4–RS0) Bits 0–4 . . . . . . . . . . . . . . . .10-610.4.1.2 Exit Command (EX) Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . .10-610.4.1.3 GO Command (GO) Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . .10-6

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MOTOROLA DSP56305 User’s Manual xv

10.4.1.4 Read/Write Command (R/W) Bit 7 . . . . . . . . . . . . . . . . . 10-610.4.2 OnCE Decoder (ODEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-810.4.3 OnCE Status and Control Register (OSCR) . . . . . . . . . . . . 10-810.4.3.1 Trace Mode Enable (TME) Bit 0 . . . . . . . . . . . . . . . . . . . 10-810.4.3.2 Interrupt Mode Enable (IME) Bit 1. . . . . . . . . . . . . . . . . . 10-810.4.3.3 Software Debug Occurrence (SWO) Bit 2. . . . . . . . . . . . 10-910.4.3.4 Memory Breakpoint Occurrence (MBO) Bit 3 . . . . . . . . . 10-910.4.3.5 Trace Occurrence (TO) Bit 4. . . . . . . . . . . . . . . . . . . . . . 10-910.4.3.6 Reserved OCSR Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-910.4.3.7 Core Status (OS0, OS1) Bits 6-7 . . . . . . . . . . . . . . . . . . 10-910.4.3.8 Reserved Bits 8-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1010.5 ONCE MEMORY BREAKPOINT LOGIC . . . . . . . . . . . . . . . . 10-1010.5.1 OnCE Memory Address Latch (OMAL) . . . . . . . . . . . . . . . 10-1110.5.2 OnCE Memory Limit Register 0 (OMLR0) . . . . . . . . . . . . . 10-1110.5.3 OnCE Memory Address Comparator 0 (OMAC0) . . . . . . . 10-1110.5.4 OnCE Memory Limit Register 1 (OMLR1) . . . . . . . . . . . . . 10-1110.5.5 OnCE Memory Address Comparator 1 (OMAC1) . . . . . . . 10-1110.5.6 OnCE Breakpoint Control Register (OBCR) . . . . . . . . . . . 10-1210.5.6.1 Memory Breakpoint Select (MBS0–MBS1) Bits 0–1 . . . 10-1210.5.6.2 Breakpoint 0 Read/Write Select (RW00–RW01)

Bits 2–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1210.5.6.3 Breakpoint 0 Condition Code Select (CC00–CC01)

Bits 4–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1310.5.6.4 Breakpoint 1 Read/Write Select (RW10–RW11)

Bits 6–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1310.5.6.5 Breakpoint 1 Condition Code Select (CC10–CC11)

Bits 8–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1410.5.6.6 Breakpoint 0 and 1 Event Select (BT0–BT1)

Bits 10–11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1410.5.6.7 OnCE Memory Breakpoint Counter (OMBC) . . . . . . . . 10-1410.5.6.8 Reserved Bits 12-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1510.6 ONCE TRACE LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1510.7 METHODS OF ENTERING THE DEBUG MODE . . . . . . . . . 10-1610.7.1 External Debug Request During RESET Assertion . . . . . . 10-1610.7.2 External Debug Request During Normal Activity . . . . . . . . 10-1610.7.3 Executing the JTAG DEBUG_REQUEST Instruction . . . . 10-17

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10.7.4 External Debug Request During Stop Mode. . . . . . . . . . . .10-1710.7.5 External Debug Request During Wait Mode . . . . . . . . . . . .10-1710.7.6 Software Request During Normal Activity . . . . . . . . . . . . . .10-1810.7.7 Enabling Trace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1810.7.8 Enabling Memory Breakpoints . . . . . . . . . . . . . . . . . . . . . .10-1810.8 PIPELINE INFORMATION AND OGDBR . . . . . . . . . . . . . . . .10-1810.8.1 OnCE PDB Register (OPDBR) . . . . . . . . . . . . . . . . . . . . . .10-1910.8.2 OnCE PIL Register (OPILR) . . . . . . . . . . . . . . . . . . . . . . . .10-1910.8.3 OnCE GDB Register (OGDBR). . . . . . . . . . . . . . . . . . . . . .10-2010.9 TRACE BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2010.9.1 OnCE PAB Register for Fetch (OPABFR) . . . . . . . . . . . . .10-2010.9.2 PAB Register for Decode (OPABDR) . . . . . . . . . . . . . . . . .10-2010.9.3 OnCE PAB Register for Execute (OPABEX) . . . . . . . . . . .10-2110.9.4 Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2110.10 ONCE COMMANDS AND SERIAL PROTOCOL . . . . . . . . . .10-2310.11 TARGET SITE DEBUG SYSTEM REQUIREMENTS . . . . . . .10-2310.12 EXAMPLES OF USING THE ONCE . . . . . . . . . . . . . . . . . . . .10-2410.12.1 Checking Whether the Chip has Entered the Debug Mode 10-2410.12.2 Polling the JTAG Instruction Shift Register . . . . . . . . . . . . .10-2410.12.3 Saving Pipeline Information . . . . . . . . . . . . . . . . . . . . . . . .10-2510.12.4 Reading the Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . .10-2510.12.5 Displaying a Specified Register . . . . . . . . . . . . . . . . . . . . .10-2610.12.6 Displaying X Memory Area Starting at Address $xxxx . . . .10-2710.12.7 Going from Debug to Normal Mode in a Current Program .10-2810.12.8 Going from Debug to Normal Mode in a New Program . . .10-2810.13 EXAMPLES OF JTAG AND ONCE INTERACTION . . . . . . . .10-29

SECTION 11 JTAG PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1

11.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-311.2 JTAG SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-511.2.1 Test Clock (TCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-511.2.2 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-511.2.3 Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-511.2.4 Test Data Output (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-511.2.5 Test Reset (TRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-511.3 TAP CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-6

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MOTOROLA DSP56305 User’s Manual xvii

11.3.1 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-711.3.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-711.3.2.1 EXTEST (B[3:0] = 0000) . . . . . . . . . . . . . . . . . . . . . . . . . 11-911.3.2.2 SAMPLE/PRELOAD (B[3:0] = 0001). . . . . . . . . . . . . . . . 11-911.3.2.3 IDCODE (B[3:0] = 0010) . . . . . . . . . . . . . . . . . . . . . . . . . 11-911.3.2.4 CLAMP (B[3:0] = 0011) . . . . . . . . . . . . . . . . . . . . . . . . . 11-1011.3.2.5 HI-Z (B[3:0] = 0100) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1111.3.2.6 ENABLE_ONCE(B[3:0] = 0110) . . . . . . . . . . . . . . . . . . 11-1111.3.2.7 DEBUG_REQUEST(B[3:0] = 0111) . . . . . . . . . . . . . . . 11-1111.3.2.8 BYPASS (B[3:0] = 1111) . . . . . . . . . . . . . . . . . . . . . . . 11-1211.4 DSP56300 RESTRICTIONS . . . . . . . . . . . . . . . . . . . . . . . . . 11-1211.5 DSP56305 BOUNDARY SCAN REGISTER . . . . . . . . . . . . . 11-13

SECTION 12 FILTER CO-PROCESSOR . . . . . . . . . . . . . . . . . . . . 12-1

12.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-312.1.1 FCOP Support for GSM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-312.2 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-412.3 BLOCK DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-412.3.1 Peripheral Module Bus (PMB) Interface . . . . . . . . . . . . . . . 12-512.3.2 FCOP Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-612.3.3 Multiplier and Accumulator (FMAC). . . . . . . . . . . . . . . . . . . 12-612.4 PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-612.4.1 FCOP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-712.4.2 FCOP Data Input Register (FDIR) . . . . . . . . . . . . . . . . . . . . 12-812.4.3 FCOP Data Output Register (FDOR) . . . . . . . . . . . . . . . . . 12-812.4.4 FCOP Coefficients Input Register (FCIR) . . . . . . . . . . . . . . 12-912.4.5 FCOP Filter Count Register (FCNT) . . . . . . . . . . . . . . . . . . 12-912.4.6 FCOP Control/Status Register (FCSR) . . . . . . . . . . . . . . . . 12-912.4.6.1 FCOP Enable (FEN)—FCSR Bit 0 . . . . . . . . . . . . . . . . 12-1012.4.6.2 FCOP Operation Mode (FOM[1:0])—FCSR Bits 4–5 . . 12-1012.4.6.3 FCOP Decimation (FDCM)—FCSR Bit 8 . . . . . . . . . . . 12-1112.4.6.4 FCOP Data Input Interrupt Enable (FDIIE)—FCSR

Bit 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1112.4.6.5 FCOP Data Output Interrupt Enable (FDOIE)—FCSR

Bit 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1212.4.6.6 FCOP Data Saturation (FSAT)—FCSR Bit 12 . . . . . . . 12-12

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12.4.6.7 FCOP Data Input Buffer Empty (FDIBE)—FCSR Bit 14 12-1312.4.6.8 FCOP Data Output Buffer Full (FDOBF)—FCSR Bit 15 12-1312.4.6.9 FCOP Reserved Unused Bits—FCSR Bits 1, 3, 9, 13 . .12-1312.4.6.10 FCOP Reserved Used Bits—FCSR Bits 2, 6, 7 . . . . . . .12-1312.4.7 Interrupts and DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1412.5 OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1412.5.1 Terminology Used in this Section . . . . . . . . . . . . . . . . . . . .12-1512.5.2 Input DMA Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1512.5.3 Output DMA Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1612.5.4 Decimation by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1612.5.5 FCOP Mode 0: Real FIR Filter . . . . . . . . . . . . . . . . . . . . . .12-1712.5.5.1 Mode 0 (Real FIR Filter), No Decimation . . . . . . . . . . . .12-1712.5.5.2 Mode 0 (Real FIR Filter), Decimation by 2 . . . . . . . . . . .12-1912.5.5.3 Mode 0 (Complex FIR Filter Generating Real Outputs Only),

Decimation by 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2112.5.6 FCOP Mode 1: Full Complex FIR Filter . . . . . . . . . . . . . . .12-2312.5.6.1 Mode 1(Full Complex FIR Filter), No Decimation. . . . . .12-2312.5.6.2 Mode 1 (Full Complex Correlation Filter),

No Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2512.5.6.3 Mode 1 (Full Complex FIR Filter), Decimation by 2 . . . .12-2712.5.7 FCOP Mode 2: Full Complex FIR Filter . . . . . . . . . . . . . . .12-2912.5.7.1 Mode 2 (Complex FIR Filter Generating Pure Real or Pure

Imaginary Outputs Alternately), No Decimation1 . . . . . . .2-2912.5.7.2 Mode 2 (Complex FIR Filter Generating Pure Real and Pure

Imaginary Outputs Alternately), Decimation by 21 . . . . . .2-3112.5.8 FCOP Mode 3: Optimized Complex Correlation Function

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3412.5.8.1 Mode 3 (Complex Correlation of Non-Oversampled Data),

No Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3412.5.8.2 Mode 3 (Complex Correlation of 2x Oversampled Data),

No Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3712.6 PERFORMANCE ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . .12-40

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MOTOROLA DSP56305 User’s Manual xix

SECTION 13 VITERBI CO-PROCESSOR. . . . . . . . . . . . . . . . . . . . 13-1

13.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-313.1.1 VCOP Support for GSM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-313.1.2 MLSE Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-413.2 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-513.3 BLOCK DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-613.3.1 Peripheral Module Bus (PMB) Interface . . . . . . . . . . . . . . . 13-713.3.2 Flow Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-713.3.3 Branch Metric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-713.3.4 Add-Compare-Select (ACS) . . . . . . . . . . . . . . . . . . . . . . . . 13-813.3.5 Window Error Detection (WED) . . . . . . . . . . . . . . . . . . . . . . 13-813.3.6 Trellis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-913.3.7 Data Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-913.3.8 Receive Quality Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-913.4 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1013.4.1 Equalization Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1013.4.1.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1113.4.1.2 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1113.4.1.3 Flush Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1113.4.2 Encoder Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1213.4.2.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1213.4.3 Decoder Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1213.4.3.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1313.4.3.2 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1313.4.3.3 Flush Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1413.4.4 Memory Access Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1413.4.5 Flush Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1413.4.6 VCOP Individual Reset State. . . . . . . . . . . . . . . . . . . . . . . 13-1513.4.7 Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1513.5 PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1613.5.1 Viterbi Data Register/FIFO (VDR) . . . . . . . . . . . . . . . . . . . 13-1713.5.2 Viterbi Data Out Register (VDOR) . . . . . . . . . . . . . . . . . . . 13-1713.5.3 Viterbi Control Register A (VCRA). . . . . . . . . . . . . . . . . . . 13-1813.5.3.1 Module Enable (ME)—VCRA Bit 0 . . . . . . . . . . . . . . . . 13-1813.5.3.2 Memory Access Enable (MAEN)—VCRA Bit 1. . . . . . . 13-1813.5.3.3 Decoding Enable (DECEN)—VCRA Bit 2 . . . . . . . . . . . 13-19

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xx DSP56305 User’s Manual MOTOROLA

13.5.3.4 Encoding Enable (ENCEN)—VCRA Bit 3 . . . . . . . . . . .13-1913.5.3.5 Equalization Enable (EQEN)—VCRA Bit 4 . . . . . . . . . .13-1913.5.3.6 Flush Enable (FLEN)—VCRA Bit 5 . . . . . . . . . . . . . . . .13-1913.5.3.7 Code Rate (RATE[1:0])—VCRA Bits 8–9. . . . . . . . . . . .13-2013.5.3.8 Constraint Length (CNST[1:0])—VCRA Bit 12–13 . . . . .13-2013.5.3.9 VCRA Reserved—VCRA Bits 6–7, 10–11, 14–15 . . . . .13-2013.5.4 Viterbi Control Register B (VCRB) . . . . . . . . . . . . . . . . . . .13-2113.5.4.1 Initial State Enable (ISE)—VCRB Bit 0 . . . . . . . . . . . . .13-2113.5.4.2 Flush Control (FLC)—VCRB Bit 1 . . . . . . . . . . . . . . . . .13-2113.5.4.3 Continuous Mode Enable (CME)—VCRB Bit 3 . . . . . . .13-2113.5.4.4 Data Mode (HD[0])—VCRB Bits 4–5 . . . . . . . . . . . . . . .13-2213.5.4.5 Window Error Detection Enable (WEDE)—

VCRB Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-2213.5.4.6 Data-In Interrupt Enable (DIIE)—VCRB Bit 8 . . . . . . . . .13-2213.5.4.7 Buffer Full Interrupt Enable (BFIE)—VCRB Bit 10 . . . . .13-2213.5.4.8 Data Out Interrupt Enable (DOIE)—VCRB Bit 11 . . . . .13-2213.5.4.9 Processing Done Interrupt Enable (DNIE)—

VCRB Bit 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-2213.5.4.10 Operation Complete Interrupt Enable (OCIE)—

VCRB Bit 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-2213.5.4.11 Reserved Bits—VCRB Bits 2, 5, 9, 14–15 . . . . . . . . . . .13-2213.5.4.12 Internal Reserved Bits—VCRB Bits 4, 7 . . . . . . . . . . . .13-2313.5.5 Viterbi Status Register (VSTR) . . . . . . . . . . . . . . . . . . . . . .13-2313.5.5.1 Initialize Flag (INIT)—VSTR Bit 0 . . . . . . . . . . . . . . . . . .13-2313.5.5.2 Flush Flag (FLSH)—VSTR Bit 1. . . . . . . . . . . . . . . . . . .13-2313.5.5.3 Operation Complete (OPC)—VSTR Bit 4. . . . . . . . . . . .13-2313.5.5.4 Processing Done (DONE)—VSTR Bit 5 . . . . . . . . . . . . .13-2413.5.5.5 Data Ready (DRDY)—VSTR Bit 6 . . . . . . . . . . . . . . . . .13-2413.5.5.6 End Stage (ESTG)—VSTR Bit 7 . . . . . . . . . . . . . . . . . .13-2413.5.5.7 Data Request (DREQ)—VSTR Bit 8 . . . . . . . . . . . . . . .13-2413.5.5.8 Data Output Buffer Full (DOBF)—VSTR Bit 9 . . . . . . . .13-2413.5.5.9 Reserved Bits—VSTR Bits 2, 3, 10–15 . . . . . . . . . . . . .13-2413.5.6 Viterbi Data Counter (VCNT) . . . . . . . . . . . . . . . . . . . . . . .13-2513.5.7 Viterbi Tap A Register (VTPA) . . . . . . . . . . . . . . . . . . . . . .13-2513.5.7.1 Tap Vector A (TAPA{4:0])—VTPA Bits 4–0 . . . . . . . . . .13-2513.5.7.2 Tap Vector B (TAPB[4:0])—VTPA Bits 9–5 . . . . . . . . . .13-25

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MOTOROLA DSP56305 User’s Manual xxi

13.5.7.3 Tap Vector C (TAPC[4:0])—VTPA Bits 14–10 . . . . . . . 13-2513.5.7.4 Reserved Bit—VTPA Bit 15 . . . . . . . . . . . . . . . . . . . . . 13-2513.5.8 Viterbi Tap Register B (VTPB). . . . . . . . . . . . . . . . . . . . . . 13-2613.5.8.1 Tap Vector D (TAPD{4:0])—VTPB Bits 4–0 . . . . . . . . . 13-2613.5.8.2 Tap Vector E (TAPE[4:0])—VTPB Bits 9–5 . . . . . . . . . 13-2613.5.8.3 Tap Vector F (TAPF[4:0])—VTPB Bits 14–10. . . . . . . . 13-2613.5.8.4 Reserved Bit—VTPB Bit 15 . . . . . . . . . . . . . . . . . . . . . 13-2613.5.9 Viterbi Trellis Setup Register (VTSR) . . . . . . . . . . . . . . . . 13-2713.5.9.1 Initial State (IS[5:0])—VTSR Bits 5–0 . . . . . . . . . . . . . . 13-2713.5.9.2 End State (ES[5:0])—VTSR Bits 13–8 . . . . . . . . . . . . . 13-2713.5.9.3 Reserved Bits—VTSR Bits 6, 7, 14, 15. . . . . . . . . . . . . 13-2713.5.10 Viterbi Bit Error Rate Register/Counter (VBER) . . . . . . . . 13-2713.5.11 Viterbi WED Setup Register (VWES) . . . . . . . . . . . . . . . . 13-2813.5.11.1 Window Start Location (WSTR[7:0])—VWES Bits 7–0 . 13-2913.5.11.2 Window Length (WLEN[7:0])—VWES Bits 15–8 . . . . . 13-2913.5.12 Viterbi WED Data Register (VWED) . . . . . . . . . . . . . . . . . 13-2913.5.13 Viterbi Memory Access Register (VMEM) . . . . . . . . . . . . . 13-2913.6 CHIP DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3013.6.1 Memory description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3013.6.2 Interrupt and DMA Sources . . . . . . . . . . . . . . . . . . . . . . . . 13-3113.6.3 I/O Register and Related Interrupts for Different Modes . . 13-3113.6.4 Soft Decision Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3213.7 VITERBI BUTTERFLY IMPLEMENTATION . . . . . . . . . . . . . 13-3313.8 PERFORMANCE ANALYSIS. . . . . . . . . . . . . . . . . . . . . . . . . 13-3413.9 PROGRAMMING EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . 13-3713.9.1 Channel Encode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3713.9.2 Channel Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4013.9.3 Channel Equalization with DMA,

including Read/Write Memory Access . . . . . . . . . . . . . . . . 13-4513.10 REFERENCES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-51

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xxii DSP56305 User’s Manual MOTOROLA

SECTION 14 CYCLIC CODE CO-PROCESSOR . . . . . . . . . . . . . . .14-1

14.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-314.2 KEY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-314.3 CCOP BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-414.3.1 Cipher Mode Register Configuration. . . . . . . . . . . . . . . . . . .14-414.3.2 Parity Coding Modes Register Configuration . . . . . . . . . . . .14-514.4 CCOP PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . .14-614.4.1 CCOP Data FIFO Register (CDFR) . . . . . . . . . . . . . . . . . . .14-814.4.2 CCOP Count Register (CCNT) . . . . . . . . . . . . . . . . . . . . . . .14-914.4.2.1 Input Counter (IC[7:0])—CCNT Bits 7–0 . . . . . . . . . . . . .14-914.4.2.2 Run Counter (RC[7:0])—CCNT Bits 15–8 . . . . . . . . . . . .14-914.4.2.3 Output Counter (OC[6:0])—CCNT Bits 22–16 . . . . . . . .14-1014.4.2.4 Continuous Mode (CM)—CCNT Bit 23 . . . . . . . . . . . . .14-1014.4.3 Step Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1014.4.3.1 Step Function Select Register (CSFS). . . . . . . . . . . . . .14-1014.4.3.1.1 Select Bit A (SBA[4:0])—CSFS Bits 4–0 . . . . . . . . . .14-1114.4.3.1.2 Select Register A (SRA[1:0])—CSFS Bits 6–5 . . . . .14-1114.4.3.1.3 Select Bit B (SBB[4:0])—CSFS Bits 12–8 . . . . . . . . .14-1114.4.3.1.4 Select Register B (SRB[1:0])—CSFS Bits 14–13 . . .14-1114.4.3.1.5 Select Bit C (SBC[4:0])—CSFS Bits 20–16 . . . . . . . .14-1214.4.3.1.6 Select Register C (SRC[1:0])—CSFS Bits 22–21 . . .14-1214.4.3.1.7 Reserved Bits—CSFS Bits 7, 15, 23 . . . . . . . . . . . . .14-1214.4.3.2 Step Function Table A (CSFTA). . . . . . . . . . . . . . . . . . .14-1214.4.3.3 Step Function Table B (CSFTB). . . . . . . . . . . . . . . . . . .14-1214.4.3.4 Input Enable bits (INE[3:0])—CSFTB Bits 19–16. . . . . .14-1314.4.3.5 Output Enable bits (OUTE[3:0])—CSFTB Bits 23–20 . .14-1414.4.4 CCOP Control Status Register (CCSR) . . . . . . . . . . . . . . .14-1414.4.4.1 Enable bit (CEN)—CCSR Bit 0 . . . . . . . . . . . . . . . . . . .14-1514.4.4.2 Processing Enable bit (PREN)—CCSR Bit 1 . . . . . . . . .14-1514.4.4.3 Operating Mode bits (OPM[1:0])—CCSR Bits 5–4. . . . .14-1514.4.4.4 Left-Right Connection bit (LRC)—CCSR Bit 8 . . . . . . . .14-1614.4.4.5 Halt On Zero Detect bit (HOZD)—CCSR Bit 9 . . . . . . . .14-1614.4.4.6 Force Shift bit (FOSH)—CCSR Bit 10 . . . . . . . . . . . . . .14-1714.4.4.7 Data In Interrupt Enable bit (DIIE)—CCSR Bit 12 . . . . .14-1714.4.4.8 Data Out Interrupt Enable bit (DOIE)—CCSR Bit 13 . . .14-17

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MOTOROLA DSP56305 User’s Manual xxiii

14.4.4.9 Cipher Done Interrupt Enable bit (CDIE)—CCSR Bit 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17

14.4.4.10 Parity Coding Done Interrupt Enable bit (PDIE)—CCSR Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17

14.4.4.11 Input Buffer Empty bit (INBE)—CCSR Bit 19 . . . . . . . . 14-1814.4.4.12 Input FIFO Empty bit (INFE)—CCSR Bit 20 . . . . . . . . . 14-1814.4.4.13 Output FIFO Not Empty bit (OFNE)—CCSR Bit 21 . . . 14-1814.4.4.14 Cipher Done bit (CIDN)—CCSR Bit 22 . . . . . . . . . . . . . 14-1814.4.4.15 Parity Coding Done bit (PCDN)—CCSR Bit 23. . . . . . . 14-1914.4.5 Cyclic Code Processing Registers. . . . . . . . . . . . . . . . . . . 14-1914.4.5.1 CCOP Linear Feedback Shift Register (CFSRz) . . . . . 14-2014.4.5.2 CCOP FeedBack Tap Register (CFBTz) . . . . . . . . . . . 14-2014.4.5.3 CCOP FeedForward Tap Register (CFFTz) . . . . . . . . . 14-2014.4.5.4 CCOP Bit Select Register (CBSRz) . . . . . . . . . . . . . . . 14-2014.4.5.5 CCOP Mask Register (CMSKz) . . . . . . . . . . . . . . . . . . 14-2014.5 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2114.5.1 Cipher Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2114.5.1.1 Normal Cipher Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2114.5.1.2 Step-by-step Cipher Mode . . . . . . . . . . . . . . . . . . . . . . 14-2114.5.2 Parity Coding Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2214.5.2.1 Parity Coding Mode Using One CFSR . . . . . . . . . . . . . 14-2214.5.2.2 Parity Coding Mode Using Two Concatenated

CFSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2214.6 PROGRAMMING CONSIDERATIONS . . . . . . . . . . . . . . . . . 14-2314.6.1 Input Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2314.6.2 Run Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2314.6.3 Output Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2414.6.4 Cipher Mode Processing . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2414.6.4.1 Cipher Mode Initialization . . . . . . . . . . . . . . . . . . . . . . . 14-2514.6.4.2 Cipher Mode Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2514.6.5 Parity Coding Processing . . . . . . . . . . . . . . . . . . . . . . . . . 14-2614.6.5.1 Parity Coding Mode Initialization. . . . . . . . . . . . . . . . . . 14-2714.6.5.2 Parity Coding Mode Output. . . . . . . . . . . . . . . . . . . . . . 14-2714.7 CONFIGURATION EXAMPLES. . . . . . . . . . . . . . . . . . . . . . . 14-2714.7.1 Programming a general circuit in Parity Coding mode . . . 14-2714.7.1.1 Case 1 - Polynomials of degree n £ 24 . . . . . . . . . . . . . 14-28

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xxiv DSP56305 User’s Manual MOTOROLA

14.7.1.2 Case 2 - Polynomials of degree n, such that 25 £ n £ 48 . . . . . . . . . . . . . . . . . . . . . . . . . . .14-28

14.7.2 GSM Fire Encode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-2914.7.3 GSM Fire Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-30

APPENDIX A BOOTSTRAP CODE. . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.1 BOOTSTRAP CODE FOR THE DSP56305 . . . . . . . . . . . . . . . A-2

APPENDIX B EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

B.1 INTERNAL I/O EQUATES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3B.2 INTERRUPT EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18

APPENDIX C JTAG BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

C.1 JTAG BSDL FILE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3

APPENDIX D PROGRAMMING REFERENCE . . . . . . . . . . . . . . . . . D-1

D.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3D.1.1 Peripheral Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3D.1.2 Interrupt Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3D.1.3 Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3D.1.4 DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3D.1.5 Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3D.1.6 HI32 Registers — Quick Reference Tables . . . . . . . . . . . . . D-3D.2 INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . D-4D.3 INTERRUPT ADDRESSES AND SOURCES . . . . . . . . . . . . . D-11D.4 INTERRUPT PRIORITIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . D-13D.5 DMA REQUEST SOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . D-15D.6 PROGRAMMING REFERENCE SHEETS . . . . . . . . . . . . . . . D-16D.7 QUICK REFERENCE TABLES . . . . . . . . . . . . . . . . . . . . . . . . D-42

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MOTOROLA DSP56305 User’s Manual xxv

LIST OF FIGURES

Figure 1-1 DSP56305 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Figure 2-1 Signals Identified by Functional Group . . . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 2-2 Host Interface/Port B Detail Signal Diagram . . . . . . . . . . . . . . . . . . . 2-5

Figure 3-1 Default Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Figure 3-2 Instruction Cache Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Figure 3-3 Memory Switch Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

Figure 3-4 Memory Switch Enabled, Instruction Cache Enabled . . . . . . . . . . . 3-15

Figure 3-5 Sixteen-Bit Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

Figure 3-6 Sixteen-Bit Compatibility Mode, Instruction Cache Enabled . . . . . . 3-17

Figure 3-7 Sixteen-Bit Compatibility Mode, Memory Switch Enabled. . . . . . . . 3-18

Figure 3-8 Sixteen-Bit Compatibility Mode, Memory Switch Enabled,Instruction Cache Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

Figure 4-1 Interrupt Priority Register C (IPR-C) (X:$FFFFFF) . . . . . . . . . . . . . 4-15

Figure 4-2 Interrupt Priority Register P (IPR-P) (X:$FFFFFE) . . . . . . . . . . . . . 4-16

Figure 4-3 DSP56305 Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . 4-22

Figure 4-4 PLL Control Register (PCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22

Figure 4-5 Identification Register Configuration (DSP56305 Revision 0) . . . . . 4-23

Figure 4-6 JTAG Identification Register Configuration (Revision 0) . . . . . . . . . 4-24

Figure 6-1 HI32 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

Figure 6-2 Host Side Registers (PCI Memory Address Space) . . . . . . . . . . . . 6-52

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Figure 6-3 Host Side Registers (PCI Configuration Address Space) . . . . . . . .6-52

Figure 6-4 Host Side Registers (Universal Bus Mode Address Space). . . . . . .6-53

Figure 6-5 Connection to PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-107

Figure 6-6 Connection to 16-Bit ISA/EISA Data Bus) . . . . . . . . . . . . . . . . . . .6-108

Figure 6-7 Example of Connection to DSP56300 Core Port A Bus. . . . . . . . .6-109

Figure 7-1 ESSI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5

Figure 7-2 SCKn Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6

Figure 7-3 SCn0 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8

Figure 7-4 SCn1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-11

Figure 7-5 SCn2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-12

Figure 7-6 ESSI Control Register A (CRA) (ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5) . . . . . . . . . . . . . . . . . . . . .7-13

Figure 7-7 ESSI Control Register B (CRB) (ESSI0 X:$FFFFB6, ESSI1 X:$FFFFA6) . . . . . . . . . . . . . . . . . . . .7-13

Figure 7-8 ESSI Status Register (SSISR) (ESSI0 X:$FFFFB7, ESSI1 X:$FFFFA7) . . . . . . . . . . . . . . . . . . . . .7-13

Figure 7-9 ESSI Transmit Slot Mask Register A (TSMA)(ESSI0 X:$FFFFB4, ESSI1 X:$FFFFA4) . . . . . . . . . . . . . . . . . . . . .7-14

Figure 7-10 ESSI Transmit Slot Mask Register B (TSMB) (ESSI0 X:$FFFFB3, ESSI1 X:$FFFFA3) . . . . . . . . . . . . . .7-14

Figure 7-11 ESSI Receive Slot Mask Register A(RSMA) (ESSI0 X:$FFFFB2, ESSI1 X:$FFFFA2) . . . . . . . . . . . . . .7-14

Figure 7-12 ESSI Receive Slot Mask Register B (RSMB) (ESSI0 X:$FFFFB1, ESSI1 X:$FFFFA1) . . . . . . . . . . . . . .7-14

Figure 7-13 ESSI Clock Generator Functional Block Diagram . . . . . . . . . . . . . .7-16

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Figure 7-14 ESSI Frame Sync Generator Functional Block Diagram. . . . . . . . . 7-18

Figure 7-15 ESSI Pin Configuration for Clocks, Frame Syncs, and Flags . . . . . 7-21

Figure 7-16 CRB FSL[1:0] Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25

Figure 7-17 CRB SYN Bit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26

Figure 7-18 Normal and Network Mode Operation . . . . . . . . . . . . . . . . . . . . . . . 7-27

Figure 7-19 ESSI Data Path Programming Model (SHFD = 0). . . . . . . . . . . . . . 7-37

Figure 7-20 ESSI Data Path Programming Model (SHFD = 1). . . . . . . . . . . . . . 7-38

Figure 7-21 ESSI Main Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47

Figure 7-22 GPIO/ESSI Port Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53

Figure 7-23 Port Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53

Figure 7-24 Port Direction Register (PRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54

Figure 7-25 Port Data Register (PDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-55

Figure 8-1 SCI Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

Figure 8-2 SCI Status Register (SSR

)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

Figure 8-3 SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

Figure 8-4 SCI Data Word Formats (SSFTD=0). . . . . . . . . . . . . . . . . . . . . . . . . 8-7

Figure 8-5 SCI Data Word Formats (SSFTD=1). . . . . . . . . . . . . . . . . . . . . . . . . 8-8

Figure 8-6 16 x Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

Figure 8-7 SCI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

Figure 8-8 SCI Programming Model - Data Registers . . . . . . . . . . . . . . . . . . . 8-20

Figure 8-9 Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30

Figure 8-10 Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30

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Figure 8-11 Port E Data Register (PDRE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-31

Figure 9-1 Timer/Event Counter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .9-4

Figure 9-2 Timer/Event Counter Programming Model. . . . . . . . . . . . . . . . . . . . .9-5

Figure 9-3 Timer Prescaler Load Register (TPLR) . . . . . . . . . . . . . . . . . . . . . . .9-5

Figure 9-4 Timer Prescaler Count Register (TPCR) . . . . . . . . . . . . . . . . . . . . . .9-7

Figure 9-5 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9

Figure 9-6 Timer Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10

Figure 10-1 OnCE Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3

Figure 10-2 OnCE Module Multiprocessor Configuration . . . . . . . . . . . . . . . . . .10-4

Figure 10-3 OnCE Controller Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5

Figure 10-4 OnCE Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5

Figure 10-5 OnCE Status and Control Register (OSCR). . . . . . . . . . . . . . . . . . .10-8

Figure 10-6 OnCE Memory Breakpoint Logic 0. . . . . . . . . . . . . . . . . . . . . . . . .10-10

Figure 10-7 OnCE Breakpoint Control Register (OBCR). . . . . . . . . . . . . . . . . .10-12

Figure 10-8 OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .10-15

Figure 10-9 OnCE Pipeline Information and GDB Registers . . . . . . . . . . . . . .10-19

Figure 10-10 OnCE Trace Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-22

Figure 11-1 TAP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-4

Figure 11-2 TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-6

Figure 11-3 JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-7

Figure 11-4 JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-10

Figure 11-5 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12

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Figure 12-1 Filter Co-Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 12-5

Figure 12-2 FCOP Control/Status Register (FCSR) . . . . . . . . . . . . . . . . . . . . . 12-10

Figure 12-3 Input and Output Stream for Real FIR Filter without Decimation . 12-18

Figure 12-4 Input and Output Stream for Real FIR Filter with Decimation by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20

Figure 12-5 Input and Output Stream for Complex FIR Filter Generating Real Outputs Only with Decimation by 21 . . . . . . . . . . . . . . . . . . . . . . . . 2-22

Figure 12-6 Input and Output Stream for Full Complex FIR Filterwithout Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24

Figure 12-7 Input and Output Stream for Full Complex Correlation Filterwithout Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26

Figure 12-8 Input and Output Stream for Full Complex Filter with Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28

Figure 12-9 Input and Output Stream for Complex FIR Filter Generating Pure Real or Pure Imaginary Outputs Alternately without Decimation1. . . . . . 2-30

Figure 12-10 Input and Output Stream for Complex FIR Filter Generating Pure Real and Pure Imaginary Outputs Alternately with Decimation by 21 . . . 2-33

Figure 12-11 Input and Output Stream for Complex Correlation of Non-Oversampled Data without Decimation1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36

Figure 12-12 Input and Output Stream for Complex Correlation of 2

×

Oversampled Data without Decimation1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39

Figure 13-1 Block Diagram of a Typical Data Communication System . . . . . . . 13-3

Figure 13-2 Ungerboeck Form of MLSE Channel Equalizer. . . . . . . . . . . . . . . . 13-4

Figure 13-3 VCOP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

Figure 13-4 Window Error Detection Function . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8

Figure 13-5 Bit Error Count Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9

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Figure 13-6 Viterbi Co-Processor in Equalization Mode . . . . . . . . . . . . . . . . . .13-11

Figure 13-7 Viterbi Co-Processor in Encoder Mode . . . . . . . . . . . . . . . . . . . . .13-12

Figure 13-8 Viterbi Co-Processor in Decoder Mode . . . . . . . . . . . . . . . . . . . . .13-13

Figure 13-9 Viterbi Control Register A (VCRA) . . . . . . . . . . . . . . . . . . . . . . . . .13-18

Figure 13-10 Viterbi Control Register B (VCRB) . . . . . . . . . . . . . . . . . . . . . . . . .13-21

Figure 13-11 Viterbi Status Register (VSTR). . . . . . . . . . . . . . . . . . . . . . . . . . . .13-23

Figure 13-12 Viterbi Tap A Register (VTPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-25

Figure 13-13 Viterbi Tap Register B (VTPB) . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-26

Figure 13-14 Viterbi Trellis Setup Register (VTSR). . . . . . . . . . . . . . . . . . . . . . .13-27

Figure 13-15 Viterbi WED Setup Register (VWES). . . . . . . . . . . . . . . . . . . . . . .13-28

Figure 13-16 Viterbi Butterfly Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-33

Figure 14-1 CCOP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-4

Figure 14-2 CFSR Configuration in the Cipher Modes . . . . . . . . . . . . . . . . . . . .14-5

Figure 14-3 CFSR Configuration in the Parity Coding Modes. . . . . . . . . . . . . . .14-6

Figure 14-4 CCOP Count Register (CCNT). . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-9

Figure 14-5 Step Function Select Register (CSFS). . . . . . . . . . . . . . . . . . . . . .14-11

Figure 14-6 Step Function Table A Register (CSFTA) . . . . . . . . . . . . . . . . . . .14-12

Figure 14-7 Step Function Table B Register (CSFTB) . . . . . . . . . . . . . . . . . . .14-13

Figure 14-8 CCOP Control Status Register (CCSR) . . . . . . . . . . . . . . . . . . . . .14-15

Figure 14-9 Shortened Cyclic Code Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-28

Figure 14-10 GSM Fire Encode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-29

Figure 14-11 GSM Fire Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-31

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LIST OF TABLES

Table 1-1 High True / Low True Signal Conventions. . . . . . . . . . . . . . . . . . . . . 1-5

Table 1-2 On Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

Table 2-1 DSP56305 Functional Signal Groupings . . . . . . . . . . . . . . . . . . . . . 2-3

Table 2-2 Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Table 2-3 Grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Table 2-4 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Table 2-5 Phase Lock Loop Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Table 2-6 External Address Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Table 2-7 External Data Bus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Table 2-8 External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Table 2-9 Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Table 2-10 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

Table 2-11 Enhanced Synchronous Serial Interface 0 (ESSI0) . . . . . . . . . . . . 2-29

Table 2-12 Enhanced Synchronous Serial Interface 1 (ESSI1) . . . . . . . . . . . . 2-32

Table 2-13 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . 2-35

Table 2-14 Triple Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

Table 2-15 JTAG/OnCE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

Table 3-1 Memory Space Configuration Bit Settings for the DSP56305 . . . . . . 3-6

Table 3-2 RAM Configuration Bit Settings for the DSP56305 . . . . . . . . . . . . . . 3-7

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Table 3-3 Memory Space Configurations for the DSP56305 . . . . . . . . . . . . . .3-10

Table 3-4 RAM Configurations for the DSP56305 . . . . . . . . . . . . . . . . . . . . . .3-10

Table 3-5 Memory Locations for Program RAM and Instruction Cache. . . . . .3-11

Table 3-6 Memory Locations for Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11

Table 4-1 DSP56305 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4

Table 4-2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-12

Table 4-3 Interrupt Priority Level Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-15

Table 4-4 Interrupt Source Priorities within an IPL. . . . . . . . . . . . . . . . . . . . . .4-17

Table 4-5 DMA Request Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-20

Table 6-1 HI32 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9

Table 6-2 HI32 Programming Model - DSP Side Registers . . . . . . . . . . . . . . .6-11

Table 6-3 DSP Control Register (DCTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12

Table 6-4 HI32 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-17

Table 6-5 Host Port Signal Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20

Table 6-6 DSP PCI Control Register (DPCR) . . . . . . . . . . . . . . . . . . . . . . . . .6-21

Table 6-7 DSP PCI Master Control Register (DPMC) . . . . . . . . . . . . . . . . . . .6-28

Table 6-8 HI32 (PCI Master) Data Transfer Formats . . . . . . . . . . . . . . . . . . . .6-29

Table 6-9 PCI Bus Commands Supported by the HI32 as PCI Master . . . . . .6-34

Table 6-10 DATH and DIRH Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-47

Table 6-11 HI32 Programming Model - Host Side Registers . . . . . . . . . . . . . . .6-48

Table 6-12 HI32 PCI Target Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-50

Table 6-13 HIRQ and HDRQ Signal Definition. . . . . . . . . . . . . . . . . . . . . . . . . .6-56

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MOTOROLA DSP56305 User’s Manual xxxiii

Table 6-14 DMAE Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57

Table 6-15 Transmit Data Transfer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-61

Table 6-16 Receive Data Transfer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-65

Table 6-17 Host Interface Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-91

Table 6-18 Host Port Signals - Detailed Description . . . . . . . . . . . . . . . . . . . . . 6-93

Table 6-19 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-106

Table 7-1 ESSI Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

Table 7-2 ESSI Word Length Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19

Table 7-3 FSL[1:0] Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23

Table 7-4 Mode and Signal Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . 7-31

Table 7-5 Port Control Register and Port Direction Register Bits Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54

Table 8-1 Word Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9

Table 8-2 TCM and RCM Bit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

Table 8-3 SCI Registers after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25

Table 8-4 Port Control Register and Port Direction Register Bits Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31

Table 9-1 Prescaler Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

Table 9-2 Timer/Event Counter Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

Table 9-3 Inverter (INV) Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13

Table 10-1 EX Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-2 GO Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-3 R/W Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

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Table 10-4 OnCE Register Select Encoding . . . . . . . . . . . . . . . . . . . . . . . . . .10-7

Table 10-5 Core Status Bits Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-9

Table 10-6 Memory Breakpoint 0 and 1 Select Table . . . . . . . . . . . . . . . . . . .10-12

Table 10-7 Breakpoint 0 Read/Write Select Table . . . . . . . . . . . . . . . . . . . . .10-13

Table 10-8 Breakpoint 0 Condition Select Table . . . . . . . . . . . . . . . . . . . . . . .10-13

Table 10-9 Breakpoint 1 Read/Write Select Table . . . . . . . . . . . . . . . . . . . . .10-13

Table 10-10 Breakpoint 1 Condition Select Table . . . . . . . . . . . . . . . . . . . . . . .10-14

Table 10-11 Breakpoint 0 and 1 Event Select Table . . . . . . . . . . . . . . . . . . . . .10-14

Table 10-12 TMS Sequencing for DEBUG_REQUEST . . . . . . . . . . . . . . . . . .10-30

Table 10-13 TMS Sequencing for ENABLE_ONCE. . . . . . . . . . . . . . . . . . . . . .10-31

Table 10-14 TMS Sequencing for Reading Pipeline Registers . . . . . . . . . . . .10-31

Table 11-1 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-8

Table 11-2 DSP56305 Boundary Scan Register (BSR) Bit Definitions . . . . . .11-13

Table 12-1 FCOP Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-7

Table 12-2 3 Types of 16-Bit FCOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . .12-7

Table 12-3 FCOP Register Read/Write Handling. . . . . . . . . . . . . . . . . . . . . . . .12-8

Table 12-4 FCOP Operation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-10

Table 12-5 Relationship of FDIIE and FDIBE. . . . . . . . . . . . . . . . . . . . . . . . . .12-11

Table 12-6 Relationship of FDOIE and FDOBF . . . . . . . . . . . . . . . . . . . . . . . .12-12

Table 12-7 FCOP Interrupt Vectors and DMA . . . . . . . . . . . . . . . . . . . . . . . . .12-14

Table 12-8 Non-Oversampled Data Sequence . . . . . . . . . . . . . . . . . . . . . . . .12-35

Table 12-9 2 ¥ Oversampled Data Sequence . . . . . . . . . . . . . . . . . . . . . . . . .12-37

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MOTOROLA DSP56305 User’s Manual xxxv

Table 12-10 FCOP Cycle Count in GSM Base Station . . . . . . . . . . . . . . . . . . . 12-40

Table 13-1 VCOP Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16

Table 13-2 Code Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20

Table 13-3 Trellis States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20

Table 13-4 Flush Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21

Table 13-5 Data Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22

Table 13-6 Memory Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28

Table 13-7 Memory modules usage and access. . . . . . . . . . . . . . . . . . . . . . . 13-30

Table 13-8 Interrupt and DMA Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31

Table 13-9 I/O Register Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31

Table 13-10 Soft Decision Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-32

Table 13-11 Performance of Various GSM Channels . . . . . . . . . . . . . . . . . . . . 13-34

Table 13-12 Variables for Calculating Processing Time . . . . . . . . . . . . . . . . . . 13-34

Table 14-1 CCOP Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

Table 14-2 Step Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13

Table 14-3 INE[3:0], OUTE[3:0] Bits and their Respective CFSRs . . . . . . . . . 14-14

Table 14-4 CCOP Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16

Table 14-5 LRC Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16

Table 14-6 CCOP Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19

Table 14-7 Operations During Cipher Mode Processing. . . . . . . . . . . . . . . . . 14-25

Table 14-8 Operations During Parity Coding Processing . . . . . . . . . . . . . . . . 14-26

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xxxvi DSP56305 User’s Manual MOTOROLA

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MOTOROLA DSP56305 User’s Manual 1-1

SECTION 1

DSP56305 OVERVIEW

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1-2 DSP56305 User’s Manual MOTOROLA

DSP56305 Overview

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-31.2 Manual Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-31.3 Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-51.4 DSP56305 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-61.5 DSP56305 Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-71.6 DSP56300 Core Functional Blocks . . . . . . . . . . . . . . . . . . . . . . .1-81.7 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-131.8 DSP56305 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-141.9 Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . .1-151.10 DSP56305 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . .1-15

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DSP56305 Overview

Introduction


1.1 INTRODUCTION

This manual describes the DSP56305 24-bit Digital Signal Processor (DSP), its memory, operating modes, and peripheral modules. The DSP56305 is an implementation of the DSP56300 core with a unique configuration of on-chip memory, cache, and peripherals.

This manual is intended to be used with the

DSP56300 Family Manual (DSP56300FM/AD),

which describes the Central Processing Unit (CPU), core programming models, and instruction set details. The

DSP56305 Technical Data Sheet (DSP56305/D)

provides electrical specifications, timing, pinout, and packaging descriptions.

These documents, as well as Motorola’s DSP development tools, can be obtained through a local Motorola Semiconductor Sales Office or authorized distributor.

To receive the latest information on this DSP, access the Motorola DSP home page at the address given on the back cover of this document.

1.2 MANUAL ORGANIZATION

This manual contains the following sections and appendices:

SECTION 1—DSP56305 OVERVIEW

– Provides a brief description of the DSP56305, a features list and block diagram, lists related documentation needed to use this chip, and describes the organization of this manual

SECTION 2—SECTION/CONNECTION DESCRIPTIONS

– Describes the DSP56305 signals and how these signals are grouped into interfaces

SECTION 3—MEMORY CONFIGURATION

– Describes the DSP56305 memory spaces, RAM and ROM configuration, memory configurations and bit settings, and memory maps

SECTION 4—CORE CONFIGURATION

– Describes the registers used to configure the DSP56300 core when programming the DSP56305, in particular the interrupt vector locations and the operation of the interrupt priority registers, explains the operating modes and how they affect the processor’s program and data memories

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DSP56305 Overview

Manual Organization

SECTION 5—GENERAL PURPOSE INPUT/OUTPUT (GPIO)

– Describes the DSP56305 General Purpose Input/Output (GPIO) capability and the programming model for the GPIO signals (operation, registers, and control)

SECTION 6—HOST INTERFACE (HI32)

– Describes the 32-bit Host Interface (HI32), including a quick reference to the HI32 programming model

SECTION 7—ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI)

– Describes the 24-bit Enhanced Synchronous Serial Interface (ESSI), which provides two identical full duplex UART-style serial ports for communications with devices such as codecs, DSPs, microprocessors, and peripherals implementing the Motorola Serial Peripheral Interface (SPI)

SECTION 8—SERIAL COMMUNICATIONS INTERFACE (SCI)

– Describes the 24-bit Serial Communications Interface (SCI), a full duplex serial port for serial communication to DSPs, microcontrollers, or other peripherals (such as modems or other RS-232 devices)

SECTION 9—TIMER/EVENT COUNTER MODULE

– Describes the three identical internal timer/event counter devices

SECTION 10—ON-CHIP EMULATION MODULE

– Describes the On-Chip Emulation (OnCE™) module, accessed through the JTAG port

SECTION 11—JTAG PORT

– Describes the specifics of the JTAG port on the DSP56305

APPENDIX A—BOOTSTRAP PROGRAM

– Lists the bootstrap code used for the DSP56305

APPENDIX B—EQUATES

– Lists the equates (I/O, HI32, SCI, ESSI, Exception Processing, TTM, DMA, PLL, BIU, and Interrupts) for the DSP56305

APPENDIX C—BSDL LISTING

– Provides the BSDL listing for the DSP56305

APPENDIX D—PROGRAMMING REFERENCE

– Lists peripheral addresses, interrupt addresses, and interrupt priorities for the DSP56305, and contains programming sheets listing the contents of the major DSP56305 registers for programmer’s reference

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DSP56305 Overview

Manual Conventions


1.3 MANUAL CONVENTIONS

The following conventions are used in this manual:

• Bits within registers are always listed from Most Significant Bit (MSB) to Least Significant Bit (LSB).

• Bits within a register are indicated AA[n:m], n>m, when more than one bit is involved in a description. For purposes of description, the bits are presented as if they are contiguous within a register. However, this is not always the case. Refer to the programming model diagrams or to the programmer’s sheets to see the exact location of bits within a register.

• When a bit is described as “set,” its value is 1. When a bit is described as “cleared,” its value is 0.

• The word “assert” means that a high true (active high) signal is pulled high to VCC or that a low true (active low) signal is pulled low to ground. The word “deassert” means that a high true signal is pulled low to ground or that a low true signal is pulled high to VCC. See Table 1-1.

• Pins or signals that are asserted low (made active when pulled to ground)

– In text, have an overbar: for example, RESET is asserted low.

– In code examples, have a tilde in front of their names. In the example on the following page, line 3 refers to the SS0 pin (shown as ~SS0).

• Sets of pins or signals are indicated by the first and last pins or signals in the set, for instance HA1–HA8.

Table 1-1 High True / Low True Signal Conventions

Signal/Symbol Logic State Signal State Voltage

PIN1 True Asserted Ground2

PIN False Deasserted VCC3

PIN True Asserted VCC

PIN False Deasserted Ground

Note: 1. PIN is a generic term for any pin on the chip.2. Ground is an acceptable low voltage level. See the appropriate data sheet

for the range of acceptable low voltage levels (typically a TTL logic low).3. VCC is an acceptable high voltage level. See the appropriate data sheet for

the range of acceptable high voltage levels (typically a TTL logic high).

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DSP56305 Overview

DSP56305 Features

• Code examples are displayed in a monospaced font, as shown in Example 1-1.

• Hex values are indicated with a dollar sign ($) preceding the hex value, as follows: $FFFFFF is the X memory address for the Core Interrupt Priority Register (IPR-C).

• The word ‘reset’ is used in four different contexts in this manual:

– the reset signal, written as RESET,

– the reset instruction, written as RESET,

– the reset operating state, written as Reset, and

– the reset function, written as reset.

1.4 DSP56305 FEATURES

The DSP56305 is a member of the DSP56300 family of programmable CMOS DSPs. The DSP56305 uses the DSP56300 core, a high performance, single clock cycle per instruction engine. It provides up to twice the performance of Motorola's popular DSP56000 core family, while retaining code compatibility with that family.

The DSP56300 core family’s rich instruction set and low power dissipation offer a new level of performance in speed and power, enabling a new generation of wireless, telecommunications, and multimedia products. The DSP56300 core is composed of the Data Arithmetic Logic Unit (Data ALU), Address Generation Unit (AGU), Program Control Unit (PCU), Instruction Cache Controller, Bus Interface Unit, Direct Memory Access (DMA) controller, On-Chip Emulation (OnCE) module, and a Phase Lock Loop (PLL)-based clock oscillator. Significant architectural enhancements to the DSP56300 core family include a barrel shifter, 24-bit addressing, an instruction cache, and DMA.

The DSP56300 core family members contain the DSP56300 core and additional modules. The modules are chosen from a library of standard pre-designed elements, such as memories and peripherals. New modules may be added to the library to meet customer specifications. A standard interface between the DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and peripheral configurations.

The DSP56305 may be used in GSM base stations and general digital signal processing.

Example 1-1 Sample Code Listing

BFSET #$0007,X:PCC; Configure: line 1

; MISO0, MOSI0, SCK0 for SPI master line 2

; ~SS0 as PC3 for GPIO line 3

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DSP56305 Overview

DSP56305 Core Description


1.5 DSP56305 CORE DESCRIPTION

Core features are described fully in the DSP56300 Family Manual. Pinout, memory, and peripheral features are described in this manual.

1.5.1 General Features

• 80 Million Instructions Per Second (MIPS) with an 80 MHz clock at 3.3 V

• Object code compatible with the DSP56000 core

• Highly parallel instruction set

1.5.2 Hardware Debugging Support

• On-Chip Emulation (OnCE) module

• Joint Action Test Group (JTAG) Test Access Port (TAP)

• Address Tracing mode reflects internal accesses at the external port

1.5.3 Reduced Power Dissipation

• Very low power CMOS design

• Wait and Stop low power standby modes

• Fully-static logic, operation frequency down to 0 Hz (dc)

• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent)

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DSP56305 Overview

DSP56300 Core Functional Blocks

1.6 DSP56300 CORE FUNCTIONAL BLOCKS

The DSP56300 core provides the following functional blocks:

• Data Arithmetic Logic Unit (Data ALU)

• Address Generation Unit (AGU)

• Program Control Unit (PCU)

• PLL and Clock Oscillator

• JTAG Test Access Port (TAP) and On-Chip Emulation (OnCE) module

• Memory

In addition, the DSP56305 provides a set of on-chip peripherals, described in Section 1.8.

1.6.1 Data ALU

The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core. The components of the Data ALU are as follows:

• Fully pipelined 24- × 24-bit parallel Multiplier-Accumulator (MAC)

• Bit Field Unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing)

• Conditional ALU instructions

• 24-bit or 16-bit arithmetic support under software control

• Four 24-bit input general purpose registers: X1, X0, Y1, and Y0

• Six Data ALU registers (A2, A1, A0, B2, B1, and B0) concatenated into two general purpose 56-bit accumulators, A and B accumulator shifters

• Two data bus shifter/limiter circuits

1.6.1.1 Data ALU RegistersThe Data ALU registers can be read or written over the X Data Bus (XDB) and the Y Data Bus (YDB) as 24- or 48-bit operands (or as 16- or 32-bit operands in 16-bit arithmetic mode). The source operands for the Data ALU, which can be 24, 48, or 56 bits (16, 32, or 40 bits in 16-bit arithmetic mode), always originate from Data ALU registers. The results of all Data ALU operations are stored in an accumulator.

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DSP56305 Overview



All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a new instruction can be initiated in every clock, yielding an effective execution rate of one instruction per clock cycle. The destination of every arithmetic operation can be used as a source operand for the immediately following arithmetic operation without a time penalty (i.e., without a pipeline stall).

1.6.1.2 Multiplier-Accumulator (MAC)The Multiplier-Accumulator (MAC) unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of the calculations on data operands. In the case of arithmetic instructions, the unit accepts as many as three input operands and outputs one 56-bit result of the following form, Extension:Most Significant Product:Least Significant Product (EXT:MSP:LSP).

The multiplier executes 24-bit × 24-bit, parallel, fractional multiplies, between two’s-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be stored as a 24-bit operand. The LSP can either be truncated or rounded into the MSP. Rounding is performed if specified.

1.6.2 Address Generation Unit (AGU)

The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry. The AGU operates in parallel with other chip resources to minimize address-generation overhead.

The AGU is divided into two halves, each with its own Address Arithmetic Logic Unit (Address ALU). Each Address ALU has four sets of register triplets, and each register triplet is composed of an address register, an offset register, and a modifier register. The two Address ALUs are identical. Each contains a 16-bit full adder (called an offset adder).

A second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register. A third full adder (called a reverse-carry adder) is also provided.

The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference between them is that the carry propagates in opposite directions. Test logic determines which of the three summed results of the full adders is output.

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DSP56305 Overview


Each Address ALU can update one address register from its respective address register file during one instruction cycle. The contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation. The modifier value is decoded in the Address ALU.

1.6.3 Program Control Unit (PCU)

The Program Control Unit (PCU) performs instruction prefetch, instruction decoding, hardware DO loop control, and exception processing. The PCU implements a seven-stage pipeline and controls the different processing states of the DSP56300 core. The PCU consists of three hardware blocks:

• Program Decode Controller (PDC)

• Program Address Generator (PAG)

• Program Interrupt Controller (PIC)

The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control. The PAG contains all the hardware needed for program address generation, system stack, and loop control. The PIC arbitrates among all interrupt requests (internal interrupts, as well as the five external requests IRQA, IRQB, IRQC, IRQD, and NMI), and generates the appropriate interrupt vector address.

PCU features include:

• Position Independent Code (PIC) support

• Addressing modes optimized for DSP applications (including immediate offsets)

• On-chip instruction cache controller

• On-chip memory-expandable hardware stack

• Nested hardware DO loops

• Fast auto-return interrupts

The PCU implements its functions using the following registers:

• PC—Program Counter register

• SR—Status Register

• LA—Loop Address register

• LC—Loop Counter register

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DSP56305 Overview



• VBA—Vector Base Address register

• SZ—Size register

• SP—Stack Pointer

• OMR—Operating Mode Register

• SC—Stack Counter register

The PCU also includes a hardware System Stack (SS).

1.6.4 PLL and Clock Oscillator

The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs clock input division, frequency multiplication, and skew elimination; and the Clock Generator (CLKGEN), which performs low power division and clock pulse generation.

• Allows change of low power Divide Factor (DF) without loss of lock

• Output clock with skew elimination

The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock input, offering two immediate benefits:

• A lower frequency clock input reduces the overall electromagnetic interference generated by a system.

• The ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system.

1.6.5 JTAG Test Access Port and On-Chip Emulation (OnCE) Module

The DSP56300 core provides a dedicated user-accessible Test Access Port (TAP) that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high density circuit boards have led to development of this standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The DSP56300 core implementation supports circuit-board test strategies based on this standard.

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DSP56305 Overview


The test logic includes a TAP consisting of four dedicated signals, a 16-state controller, and three test data registers. A boundary scan register links all device signals into a single shift register. The test logic, implemented utilizing static logic design, is independent of the device system logic. More information on the JTAG port is provided in Section 11, JTAG Port.

The On-Chip Emulation (OnCE) module provides a means of interacting with the DSP56300 core and its peripherals non-intrusively so that a user can examine registers, memory, or on-chip peripherals. This facilitates hardware and software development on the DSP56300 core processor. OnCE module functions are provided through the JTAG TAP signals. More information on the OnCE module is provided in Section 10, On-Chip Emulation Module.

1.6.6 On-Chip Memory

The memory space of the DSP56300 core is partitioned into program memory space, X data memory space, and Y data memory space. The data memory space is divided into X data memory and to Y data memory in order to work with the two Address ALUs and to feed two operands simultaneously to the Data ALU. Memory space includes internal RAM and ROM and can be expanded off-chip under software control. More information on the internal memory is provided in Section 3, Memory Configuration.

Program RAM, Instruction Cache, X data RAM, and Y data RAM size are programmable as described in Table 1-2, On Chip Memory, below:

Table 1-2 On Chip Memory

There are on-chip ROMs for program memory (6 K x 24-bit), bootstrap memory (192 words x 24-bit), and Y data memory (3 K x 24-bit).

Instruction Cache

Switch Mode

Program RAM Size

Instruction Cache Size

X Data RAM Size

Y Data RAM Size

disabled disabled 6.5 K × 24-bit 0 3.75 K × 24-bit 2 K × 24-bit

enabled disabled 5.5 K × 24-bit 1 K × 24-bit 3.75 K × 24-bit 2 K × 24-bit

disabled enabled 7.5 K × 24-bit 0 2.75 K × 24-bit 2 K× 24-bit

enabled enabled 6.5 K × 24-bit 1 K × 24-bit 2.75 K × 24-bit 2 K × 24-bit

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DSP56305 Overview

Internal Buses


1.6.7 Off-Chip Memory Expansion

Memory can be expanded off-chip as follows:

• Data memory can be expanded to two 16 M × 24-bit word memory spaces in 24-bit Address mode (64 K in 16-bit Address mode)

• Program memory can be expanded to one 16 M × 24-bit word memory space in 24-bit Address mode (64 K in 16-bit Address mode)

Other features of external memory expansion include the following:

• External memory expansion port

• Chip-select logic glueless interface to Static Random Access Memory (SRAM)

• On-Chip DRAM controller for glueless interface to Dynamic Random Access Memory (DRAM)

• Twenty-four external address lines

1.7 INTERNAL BUSES

To provide data exchange between blocks, the following buses are implemented:

• Peripheral I/O Expansion Bus (PIO_EB) to peripherals

• Program Memory Expansion Bus (PM_EB) to Program ROM

• X Memory Expansion Bus (XM_EB) to X memory

• Y Memory Expansion Bus (YM_EB) to Y memory

• Global Data Bus (GDB) between Program Control Unit and other core structures

• Program Data Bus (PDB) for carrying program data throughout the core

• X Memory Data Bus (XDB) for carrying X data throughout the core

• Y Memory Data Bus (YDB) for carrying Y data throughout the core

• Program Address Bus (PAB) for carrying program memory addresses throughout the core

• X Memory Address Bus (XAB) for carrying X memory addresses throughout the core

• Y Memory Address Bus (YAB) for carrying Y memory addresses throughout the core

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DSP56305 Overview

DSP56305 Block Diagram

With the exception of the Program Data Bus (PDB), all internal buses on the DSP56300 family members are 16-bit buses. The PDB is a 24-bit bus. Figure 1-1 provides a block diagram of the DSP56305.

1.8 DSP56305 BLOCK DIAGRAM

Note: Memory sizes in the block diagram are default sizes, except for the I-Cache, which is disabled by default. See Section 1.6.6 (On-Chip Memories) for more details about memory size.

Figure 1-1 DSP56305 Block Diagram

PLL

OnCE™

ClockGen-erator

Internal DataBus

Switch

YABXABPAB

YDBXDBPDBGDB

MODC/IRQBMODB/IRQC

ExternalData Bus

Switch

15

MODA/IRQD

DSP56300

651

24-Bit

24

24

DDB

DAB

Peripheral

CoreY

M_E

B

XM

_EB

PM

_EB

PIO

_EB

Expansion Area

6

SCIInter-face

JTAG5

3

RESET

MODD/IRQA

PINIT/NMI

2EXTALXTAL

Address

Control

Data

TimerHostInter-faceHI32

ESSIInter-face

AddressGeneration

UnitSix ChannelDMA Unit

ProgramInterrupt

Controller

ProgramDecode

Controller

ProgramAddress

Generator

Data ALU24 × 24+56→56-bit MACTwo 56-bit Accumulators

56-bit Barrel Shifter

PowerMngmnt.

ExternalBus

Interfaceand

I-CacheControl

AA1366

Memory Expansion Area

DE

P MemoryRAM

6.5 K × 24

(I-Cache1 K × 24)

ROM6 K × 24

X MemoryRAM

3.75 K × 24

X MemoryRAM

2 K × 24FCOP VCOP CCOP

ROM3 K × 24

ExternalAddress

BusSwitch

BootstrapROM

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DSP56305 Overview

Direct Memory Access (DMA)


1.9 DIRECT MEMORY ACCESS (DMA)

The Direct Memory Access (DMA) block has the following features:

• Six DMA channels supporting internal and external accesses

• One-, two-, and three-dimensional transfers (including circular buffering)

• End-of-block-transfer interrupts

• Triggering from interrupt lines and all peripherals

1.10 DSP56305 ARCHITECTURE OVERVIEW

The DSP56305 is designed to perform a wide variety of fixed-point digital signal processing functions. In addition to the core features previously discussed, the DSP56305 provides the following peripherals:

• Up to forty-two user-configurable General Purpose Input/Output (GPIO) signals

• 32-bit parallel Host Interface (HI32) to external hosts

• Dual Enhanced Synchronous Serial Interface (ESSI)

• Serial Communications Interface (SCI) with baud rate generator

• Timer/Event Counter Module (TEC)

• Memory Switch mode

• Four external interrupt/mode control lines

• Filter Co-Processor (FCOP)

• Viterbi Co-Processor (VCOP)

• Cyclic Code Co-Processor (CCOP)

1.10.1 General Purpose I/O (GPIO) Functionality

The General Purpose I/O (GPIO) port consists of as many as forty-two programmable signals, all of which are also used by the peripherals (HI32, ESSI, SCI, and TTM). There are no dedicated GPIO signals. The signals are configured GPIO after reset. The GPIO functionality for each peripheral is controlled by three memory-mapped registers per peripheral. The register programming techniques for GPIO functionality are very similar for each of the interfaces.

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DSP56305 Overview

DSP56305 Architecture Overview

1.10.2 Host Interface (HI32)

The Host Interface (HI32) is a thirty-two bit wide, full-duplex, double-buffered, parallel port that can be connected directly to the data bus of a host processor. The HI32 supports a variety of buses; it provides connection with a number of industry-standard DSPs, microcomputers, and microprocessors without requiring any additional logic.

The DSP core uses the HI32 as a memory-mapped peripheral, using either standard polled or interrupt programming techniques. Separate transmit and receive data registers are double-buffered to allow the DSP and host processor to efficiently transfer data at high speed. Memory mapping allows DSP core communication with the HI32 registers to be accomplished using standard instructions and addressing modes.

1.10.3 Enhanced Synchronous Serial Interface (ESSI)

The DSP56305 provides two independent and identical Enhanced Synchronous Serial Interfaces (ESSI0 and ESSI1). Each ESSI provides a full-duplex serial port for communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Motorola SPI. The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator.

The capabilities of the ESSI include:

• Independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs

• Normal mode operation using frame sync

• Network mode operation with up to 32 time slots

• Programmable word length (8, 12, or 16 bits)

• Program options for frame synchronization and clock generation

• One receiver and three transmitters per ESSI to allow six-channel home theater

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DSP56305 Overview



1.10.4 Serial Communications Interface (SCI)

The DSP56305’s Serial Communications Interface (SCI) provides a full-duplex port for serial communication to other DSPs, microprocessors, or peripherals such as modems. The SCI interfaces without additional logic to peripherals that use TTL-level signals. With a small amount of additional logic, the SCI can connect to peripheral interfaces that have non-TTL level signals, such as RS-232C, RS-422, etc.

This interface uses three dedicated signals: Transmit Data (TXD), Receive Data (RXD), and SCI Serial Clock (SCLK). It supports industry-standard asynchronous bit rates and protocols, as well as high-speed synchronous data transmission (up to 8.25 Mbps for a 66 MHz clock). The asynchronous protocols supported by the SCI include a Multidrop mode for master/slave operation with Wakeup On Idle Line and Wakeup On Address Bit capability. This mode allows the DSP56305 to share a single serial line efficiently with other peripherals.

The SCI consists of separate transmit and receive sections that can operate asynchronously with respect to each other. A programmable baud-rate generator provides the transmit and receive clocks. An enable vector and an interrupt vector have been included, allowing the baud-rate generator to function as a general purpose timer when it is not being used by the SCI, or when the interrupt timing is the same as that used by the SCI.

1.10.5 Timer/Event Counter (TEC)

The Timer/Event Counter is composed of a common 21-bit prescaler and three identical independent general purpose 24-bit timer/event counters. Each counters has its own memory-mapped register set.

Each timer has a single signal that can be used as a GPIO signal or as a timer signal. Each timer can use internal or external clocking; each timer can interrupt the DSP after a specified number of events (clocks) or can signal an external device after counting internal events. Each timer connects to the external world through one bidirectional signal. When this signal is configured as an input, the timer can function as an external event counter or measure external pulse width/signal period. When the signal is used as an output, the timer can function as a timer, a watchdog, or a Pulse Width Modulator (PWM).

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DSP56305 Overview


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SECTION 2

SIGNAL/CONNECTION DESCRIPTIONS

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Signal/Connection Descriptions

2.1 Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-32.2 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-62.3 Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-72.4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-82.5 Phase Lock Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-82.6 External Memory Expansion Port (Port A). . . . . . . . . . . . . . . . . .2-92.7 Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-152.8 Host Interface (HI32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-182.9 Enhanced Synchronous Serial Interface 0 (ESSI0). . . . . . . . . .2-282.10 Enhanced Synchronous Serial Interface 1 (ESSI1). . . . . . . . . .2-322.11 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . .2-352.12 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-362.13 JTAG/OnCE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-38

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Signal Groupings


2.1 SIGNAL GROUPINGS

The input and output signals of the DSP56305 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1.

The DSP56305 is operated from a 3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs.

Figure 2-1 is a diagram of DSP56305 signals by functional group.

Table 2-1 DSP56305 Functional Signal Groupings

Functional Group Number of Signals

Detailed Description

Power (VCC) 25 Table 2-2

Ground (GND) 26 Table 2-3

Clock 2 Table 2-4

PLL 3 Table 2-5

Address BusPort A1

24 Table 2-6

Data Bus 24 Table 2-7

Bus Control 15 Table 2-8

Interrupt and Mode Control 5 Table 2-9

Host Interface (HI32) Port B2 52 Table 2-10

Extended Synchronous Serial Interface (ESSI)

Ports C and D3

12 Table 2-11 and Table 2-12

Serial Communication Interface (SCI) Port E4 3 Table 2-13

Timer 3 Table 2-14

JTAG/OnCE Port 6 Table 2-15

Note: 1. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.

2. Port B signals are the HI32 port signals multiplexed with the GPIO signals. 3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. 4. Port E signals are the SCI port signals multiplexed with the GPIO signals.

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Signal Groupings

Figure 2-1 Signals Identified by Functional Group

DSP56305

24

24 ExternalAddress Bus

ExternalData Bus

ExternalBusControl

Extended SynchronousSerial Interface Port 0

(ESSI0)2

Timers3

PLL

JTAG/OnCE Port

Power Inputs:PLLInternal LogicAddress BusData BusBus ControlHI32ESSI/SCI/Timer

A0–A23

D0–D23

AA0–AA3/RAS0–RAS3

RDWRBSTABRBGBBBL

CASBCLKBCLK

TCKTDITDOTMSTRSTDE

CLKOUTPCAP

PINIT/NMI

VCCPVCCQVCCAVCCDVCCNVCCHVCCS

4

SerialCommunications

Interface (SCI) Port2

4

2

2

Grounds:PLLPLL Internal LogicAddress BusData BusBus ControlHI32ESSI/SCI/Timer

GNDPGND1PGNDQGNDAGNDDGNDNGNDHGNDS

464

2

Interrupt/Mode

Control

MODA/IRQAMODB/IRQBMODC/IRQCMODD/IRQDRESET

HostInterface

(HI32) Port1

PCI Bus

RXDTXDSCLK

SC00–SC02SCK0SRD0STD0

TIO0TIO1TIO2

52

3

6

2

EXTALXTAL CLOCK

ExtendedSynchronous Serial

Interface Port 1(ESSI1)2

SC10–SC12SCK1SRD1STD1

3

Universal Bus

Port B GPIO

Port E GPIO PE0PE1PE2

Port C GPIOPC0–PC2PC3PC4PC5

Port D GPIOPD0–PD2PD3PD4PD5

Timer GPIOTIO0TIO1TIO2

Port A

4

6

6

See Figure 2-2 for a listing of the Host Interface/Port B Signals

AA0355

Notes: 1. The HI32 port supports PCI and non-PCI bus configurations. Twenty-four of these HI32 signals can also be configured alternately as GPIO signals (PB0–PB23).

2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC0–PC5), Port D GPIO signals (PD0–PD5), and Port E GPIO signals (PE0–PE2), respectively.

3. TIO0–TIO2 can be configured as GPIO signals.

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Signal Groupings


Figure 2-2 Host Interface/Port B Detail Signal Diagram

DSP56305PCI Bus

HAD0HAD1HAD2HAD3HAD4HAD5HAD6HAD7HAD8HAD9HAD10HAD11HAD12HAD13HAD14HAD15HC0/HBE0HC1/HBE1HC2/HBE2HC3/HBE3HTRDYHIRDYHDEVSELHLOCKHPARHPERRHGNTHREQHSERRHSTOPHIDSELHFRAMEHCLKHAD16HAD17HAD18HAD19HAD20HAD21HAD22HAD23HAD24HAD25HAD26HAD27HAD28HAD29HAD30HAD31HRSTHINTAPVCL

Universal Bus

HA3HA4HA5HA6HA7HA8HA9HA10HD0HD1HD2HD3HD4HD5HD6HD7HA0HA1HA2Tie to pull-up or VCCHDBENHDBDRHSAKHBSHDAKHDRQHAENHTAHIRQHWR/HRWHRD/HDSTie to pull-up or VCCTie to pull-up or VCCHD8HD9HD10HD11HD12HD13HD14HD15HD16HD17HD18HD19HD20HD21HD22HD23HRSTHINTALeave unconnected

Port B GPIO

PB0PB1PB2PB3PB4PB5PB6PB7PB8PB9PB10PB11PB12PB13PB14PB15PB16PB17PB18PB19PB20PB21PB22PB23Internal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectInternal disconnectLeave unconnected

Port B Signals

Host Interface (HI32)/

HP Reference

HP0HP1HP2HP3HP4HP5HP6HP7HP8HP9HP10HP11HP12HP13HP14HP15HP16HP17HP18HP19HP20HP21HP22HP23HP24HP25HP26HP27HP28HP29HP30HP31HP32HP33HP34HP35HP36HP37HP38HP39HP40HP41HP42HP43HP44HP45HP46HP47HP48HP49HP50PVCL

Note: HPxx is a reference only and is not a signal name. GPIO references formerly designated as HIOxx have been renamed PBxx for consistency with other Motorola DSPs.

AA1407

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Power

2.2 POWER

Table 2-2 Power Inputs

Power Name (# of Pins) Description

VCCP PLL Power—VCCP provides isolated power for the Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail.

VCCQ (4) Quiet Power—VCCQ provides isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

VCCA (6) Address Bus Power—VCCA provides isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

VCCD (4) Data Bus Power—VCCD provides isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

VCCN (2) Bus Control Power—VCCN provides isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

VCCH (6) Host Power—VCCH provides isolated power for the HI32 I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

VCCS (2) ESSI, SCI, and Timer Power—VCCS provides isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

Note: These designations are package-dependent. Some packages connect all VCC inputs except VCCP to each other internally. On those packages, all power input, except VCCP, are labeled VCC. The number of connections indicated in this table are minimum values; the total VCC connections are package-dependent.

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Ground


2.3 GROUNDTable 2-3 Grounds

Ground Name (# of Pins) Description

GNDP PLL Ground—GNDP is ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 µF capacitor located as close as possible to the chip package.

GND1P PLL Ground 1—GND1P is ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground.

GNDQ (4) Quiet Ground—GNDQ provides isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

GNDA (6) Address Bus Ground—GNDA provides isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

GNDD (4) Data Bus Ground—GNDD provides isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

GNDN (2) Bus Control Ground—GNDN provides isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDN connections.

GNDH (6) Host Ground—GNDH provides isolated ground for the HI32 I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

GNDS (2) ESSI, SCI, and Timer Ground—GNDS provides isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

Note: These designations are package-dependent. Some packages connect all GND inputs except GNDP and GND1P to each other internally. On those packages, all power input, except GNDP and GND1P, are labeled GND. The number of connections indicated in this table are minimum values; the total GND connections are package-dependent.

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Clock

2.4 CLOCK

2.5 PHASE LOCK LOOP (PLL)

Table 2-4 Clock Signals

Signal Name Type

State During Reset

Signal Description

EXTAL Input Input External Clock/Crystal Input—EXTAL interfaces the internal crystal oscillator input to an external crystal or an external clock.

XTAL Output Chip-driven Crystal Output—XTAL connects the internal crystal oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected.

Table 2-5 Phase Lock Loop Signals

Signal Name Type State During

Reset Signal Description

PCAP Input Input PLL Capacitor—PCAP is an input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP.

If the PLL is not used, PCAP may be tied to VCC, GND, or left floating.

CLKOUT Output Chip-driven Clock Output—CLKOUT provides an output clock synchronized to the internal core clock phase.

If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL.

If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.

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External Memory Expansion Port (Port A)


2.6 EXTERNAL MEMORY EXPANSION PORT (PORT A)

Table 2-6, External Address Bus Signals, Table 2-7, External Data Bus Signals, and Table 2-8, External Bus Control Signals on the following pages detail the signals relevant to Port A, the external memory expansion port.

When the DSP56305 enters a low-power standby mode (Stop or Wait), it releases bus mastership and tri-states the relevant Port A signals: A0–A17, D0–D23, AA0/RAS0–AA3/RAS3, RD, WR, BS, CAS, BCLK, and BCLK.

If hardware refresh of external DRAM is enabled, Port A exits the Wait mode to allow the refresh to occur and then returns to the Wait mode.

PINIT/NMI

Input Input PLL Initial/Non-Maskable Interrupt—During assertion of RESET, PINIT/NMI is configured as PINIT and its value is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled.

After RESET deassertion and during normal instruction processing, PINIT/NMI is configured as NMI, which is a Schmitt-trigger input and negative-edge-triggered Non-Maskable Interrupt (NMI) request internally synchronized to CLKOUT.

PINIT/NMI can tolerate 5 V.

Table 2-5 Phase Lock Loop Signals (Continued)

Signal Name Type State During

Reset Signal Description

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2.6.1 External Address Bus

2.6.2 External Data Bus

Table 2-6 External Address Bus Signals

Signal Name Type

State During

Reset, Wait, or Stop

Signal Description

A0–A23 Output Tri-stated Address Bus—When the DSP is the bus master, A0–A23 specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A0–A23 do not change state when external memory spaces are not being accessed.

Table 2-7 External Data Bus Signals

Signal Name Type

State During

Reset, Wait, or Stop

Signal Description

D0–D23 Input/Output

Tri-stated Data Bus—When the DSP is the bus master, D0–D23 provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0–D23 are tri-stated.

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2.6.3 External Bus Control

Table 2-8 External Bus Control Signals

Signal Name Type

State During Reset, Wait,

or StopSignal Description

AA0–AA/RAS0–RAS3

Output Tri-stated Address Attribute or Row Address Strobe—When defined as AA, these signals can be used as chip selects or additional address lines.

When defined as RAS, these signals can be used as RAS for Dynamic Random Access Memory (DRAM) interface. These signals have programmable polarity.

RD Output Tri-stated Read Enable—When the DSP is the bus master, RD is asserted to read external memory on the data bus (D0–D23). Otherwise, RD is tri-stated.

WR Output Tri-stated Write Enable—When the DSP is the bus master, WR is asserted to write external memory on the data bus (D0–D23). Otherwise, the signals are tri-stated.

BS Output Tri-stated Bus Strobe—When the DSP is the bus master, BS is asserted for half a clock cycle at the start of a bus cycle to provide an “early bus start” signal for a bus controller. If the external bus is not used during an instruction cycle, BS remains deasserted until the next external bus cycle.

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TA Input Ignored Input

Transfer Acknowledge—If the DSP56305 is the bus master and there is no external bus activity, or if the DSP56305 is not the bus master, TA is ignored. TA is a Data Transfer Acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2,..., infinity) may be added to the wait states inserted by the Bus Control Register (BCR) by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to CLKOUT. The number of wait states is determined by the TA input or by the BCR, whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles.

In order to use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access can not be extended by TA deassertion, otherwise improper operation may result. TA can operate synchronously or asynchronously depending on the setting of the TAS bit in the Operating Mode Register (OMR).

TA functionality may not be used while performing DRAM type accesses, otherwise improper operation may result.

Table 2-8 External Bus Control Signals (Continued)

Signal Name Type



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BR Output Driven High(Deasserted)

Bus Request—BR is asserted when the DSP or the DMA requests bus mastership. BR is deasserted when the DSP or the DMA no longer needs the bus. BR may be asserted or deasserted independent of whether the DSP56305 is a bus master or a bus slave. Bus “parking” allows BR to be deasserted even though the DSP56305 is the bus master (see the description of bus “parking” in the BB signal description). The Bus Request Hole (BRH) bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. BR is only affected by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state. BR is never tri-stated.

BG Input Ignored Input

Bus Grant—BG is asserted by an external bus arbitration circuit when the DSP56305 becomes the next bus master. BG must be asserted/deasserted synchronous to CLKOUT for proper operation. When BG is asserted, the DSP56305 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution.


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BB Input/Output

Input Bus Busy—BB indicates that the bus is active. BB must be asserted and deasserted synchronous to CLKOUT. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master may keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted. This is called “bus parking” and allows the current bus master to reuse the bus without re-arbitration until another device requires the bus. The deassertion of BB is done by an “active pull-up” method (i.e., BB is driven high and then released and held high by an external pull-up resistor).

BB requires an external pull-up resistor.

BL Output Driven High (Deasserted)

Bus Lock—BL is asserted at the start of an external divisible Read-Modify-Write (RMW) bus cycle, remains asserted between the read and write cycles, and is deasserted at the end of the write bus cycle. This provides an “early bus start” signal for the bus controller. BL may be used to “resource lock” an external multi-port memory for secure semaphore updates. Early deassertion provides an “early bus end” signal useful for external bus control. If the external bus is not used during an instruction cycle, BL remains deasserted until the next external indivisible RMW cycle. The only instructions that assert BL automatically are the BSET, CLR, and BCHG instructions when they are used to modify external memory. An operation can also assert BL by setting the BLH bit in the Bus Control Register.

CAS Output Tri-stated Column Address Strobe—When the DSP is the bus master, CAS is used by DRAM to strobe the column address. Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM Control Register is cleared, the signal is tri-stated.


Signal Name Type



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Interrupt and Mode Control


2.7 INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.

BCLK Output Tri-stated Bus Clock—When the DSP is the bus master, BCLK is an active-high output used by Synchronous Static Random Access Memory (SSRAM) to sample address, data, and control signals. BCLK is active either during SSRAM accesses or as a sampling signal when the program Address Tracing mode is enabled (by setting the ATE bit in the OMR). When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. The BCLK rising edge may be used to sample the internal Program Memory access on the A0–A23 address lines.

BCLK Output Tri-stated Bus Clock Not—When the DSP is the bus master, BCLK is an active-low output that is the inverse of the BCLK signal. When the DSP is not the bus master, the signal is tri-stated.


Signal Name Type



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Table 2-9 Interrupt and Mode Control

Signal Name Type

State During Reset

Signal Description

RESET Input Input Reset—RESET is an active-low, Schmitt-trigger input. Deassertion of RESET is internally synchronized to the clock out (CLKOUT). When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. If RESET is deasserted synchronous to CLKOUT, exact start-up timing is guaranteed, allowing multiple processors to start synchronously and operate together in “lock-step.” When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted after power up.

This input is 5 V tolerant.

MODA

IRQA

Input

Input

Input Mode Select A—MODA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input IRQA during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted.

External Interrupt Request A—IRQA is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. If IRQA is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQA to exit the Wait state. If the processor is in the Stop standby state and IRQA is asserted, the processor will exit the Stop state.

These inputs are 5 V tolerant.

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MODB

IRQB

Input

Input

Input Mode Select B—MODB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input IRQB during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted.

External Interrupt Request B—IRQB is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. If IRQB is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQB to exit the Wait state. If the processor is in the Stop standby state and IRQC is asserted, the processor will exit the Stop state.


MODC

IRQC

Input

Input

Input Mode Select C—MODC selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input IRQC during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted.

External Interrupt Request C—IRQC is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. If IRQC is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQC to exit the Wait state. If the processor is in the Stop standby state and IRQC is asserted, the processor will exit the Stop state.


Table 2-9 Interrupt and Mode Control (Continued)

Signal Name Type

State During Reset

Signal Description

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Host Interface (HI32)

2.8 HOST INTERFACE (HI32)

The Host Interface (HI32) provides a fast parallel data to 32-bit port, which may be connected directly to the host bus.

The HI32 supports a variety of standard buses, and provides a glueless connection to a PCI bus and a number of industry-standard microcomputers, microprocessors, DSPs, and DMA hardware.

2.8.1 Host Port Configuration

The functions of the signals associated with the HI32 vary according to the programmed configuration of the interface as determined by the 24-bit DSP Control Register (DCTR). Refer to the DSP56305 User’s Manual for detailed descriptions of this and the other configuration registers used with the HI32.

MODD

IRQD

Input

Input

Input Mode Select D—MODD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input IRQD during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted.

External Interrupt Request D—IRQD is an active-low Schmitt-trigger input, internally synchronized to CLKOUT. If IRQD is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQD to exit the Wait state. If the processor is in the Stop standby state and IRQD is asserted, the processor will exit the Stop state.


Table 2-9 Interrupt and Mode Control (Continued)

Signal Name Type

State During Reset

Signal Description

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Table 2-10 Host Interface

Signal Name TypeState

During Reset

Signal Description

HAD0–HAD7

HA3–HA10

PB0–PB7

Input/Output

Input

Input or Output

Tri-stated Host Address/Data 0–7—When the HI32 is programmed to interface a PCI bus and the HI function is selected, these signals are lines 0–7 of the bidirectional, multiplexed Address/Data bus.

Host Address 3–10—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, these signals are lines 3–10 of the input Address bus.

Port B 0–7—When the HI32 is configured as GPIO through the DCTR, these signals are individually programmed as inputs or outputs through the HI32 Data Direction Register (DIRH).


HAD8–HAD15

HD0–HD7

PB8–PB15

Input/Output

Input/Output

Input or Output


Host Data 0–7—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, these signals are lines 0–7 of the bidirectional Data bus.

Port B 8–15—When the HI32 is configured as GPIO through the DCTR, these signals are individually programmed as inputs or outputs through the HI32 DIRH.


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HC0–HC3/HBE0–HBE3

HA0–HA2

PB16–PB19

Input/Output

Input

Input or Output

Tri-stated Host Command 0–3/Host Byte Enable 0–3—When the HI32 is programmed to interface a PCI bus and the HI function is selected, these signals are lines 0–7 of the bidirectional, multiplexed Address/Data bus.

Host Address 0–2—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, these signals are lines 0–2 of the input Address bus.

Note: The fourth signal in this set should be connected to a pull-up resistor or directly to VCC when using a non-PCI bus.

Port B 16–19—When the HI32 is configured as GPIO through the DCTR, these signals are individually programmed as inputs or outputs through the HI32 DIRH.


HTRDY

HDBEN

PB20

Input/Output

Output

Input or Output

Tri-stated Host Target Ready—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Host Target Ready signal.

Host Data Bus Enable—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal is Host Data Bus Enable output.

Port B 20—When the HI32 is configured as GPIO through the DCTR, this signal is individually programmed as an input or output through the HI32 DIRH.


Table 2-10 Host Interface (Continued)


During Reset

Signal Description

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HIRDY

HDBDR

PB21

Input/Output

Output

Input or Output

Tri-stated Host Initiator Ready—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Host Initiator Ready signal.

Host Data Bus Direction—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal is Host Data Bus Direction output.



HDEVSEL

HSAK

PB22

Input/Output

Output

Input or Output

Tri-stated Host Device Select—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Host Device Select signal.

Host Select Acknowledge—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal is Host Select Acknowledge output.





During Reset

Signal Description

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HLOCK

HBS

PB23

Input/Output

Input

Input or Output

Tri-stated Host Lock—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Host Lock signal.

Host Bus Strobe—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal is Host Bus Strobe Schmitt-trigger input.



HPAR

HDAK

Input/Output

Input

Tri-stated Host Parity—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Host Parity signal.

Host DMA Acknowledge—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal is Host DMA Acknowledge Schmitt-trigger input.

Port B—When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected.




During Reset

Signal Description

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HPERR

HDRQ

Input/Output

Output

Tri-stated Host Parity Error—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Host Parity Error signal.

Host DMA Request—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal is Host DMA Request output.



HGNT

HAEN

Input

Input

Input Host Bus Grant—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Host Bus Grant signal.

Host Address Enable—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal is Host Address Enable input.





During Reset

Signal Description

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HREQ

HTA

Output

Output

Tri-stated Host Bus Request—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Host Bus Request signal.

Host Transfer Acknowledge—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal is Host Transfer Acknowledge output.



HSERR

HIRQ

Output, open drain

Output, open drain

Tri-stated Host System Error—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Host System Error signal.

Host Interrupt Request—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal is Host Interrupt Request output.





During Reset

Signal Description

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HSTOP

HWR/HRW

Input/Output

Input

Tri-stated Host Stop—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Host Stop signal.

Host Write/Host Read-Write—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal is Host Write/Host Read-Write Schmitt-trigger input.



HIDSEL

HRD/HDS

Input

Input

Input Host Initialization Device Select—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Host Initialization Device Select signal.

Host Read/Host Data Strobe—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal is Host Data Read/Host Data Strobe Schmitt-trigger input.





During Reset

Signal Description

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HFRAME Input/Output

Tri-stated Host Frame—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Host cycle frame signal.

Non-PCI bus—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal must be connected to a pull-up resistor or directly to VCC.



HCLK Input Input Host Clock—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Host Bus Clock input.

Non-PCI bus—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal must be connected to a pull-up resistor or directly to VCC.





During Reset

Signal Description

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HAD16–HAD31

HD8–HD23

Input/Output

Input/Output


Host Data 8–23—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, these signals are lines 8–23 of the bidirectional Data bus.

Port B—When the HI32 is configured as GPIO through the DCTR, these signals are internally disconnected.


HRST

HRST

Input

Input

Tri-stated Hardware Reset—When the HI32 is programmed to interface a PCI bus and the HI function is selected, this is the Hardware Reset input.

Hardware Reset—When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal is the Hardware Reset Schmitt-trigger input.



HINTA Output, open drain

Tri-stated Host Interrupt A—When the HI function is selected, this signal is the Interrupt A open-drain output.





During Reset

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Enhanced Synchronous Serial Interface 0 (ESSI0)

2.9 ENHANCED SYNCHRONOUS SERIAL INTERFACE 0 (ESSI0)

There are two synchronous serial interfaces (ESSI0 and ESSI1) that provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals which implement the Motorola Serial Peripheral Interface (SPI).

PVCL Input Input PCI Voltage Clamp—When the HI32 is programmed to interface a PCI bus and the HI function is selected and the PCI bus uses a 3 V signal environment, connect this pin to VCC (3.3 V) to enable the high voltage clamping required by the PCI specifications. In all other cases, including a 5 V PCI signal environment, leave the input unconnected.



During Reset

Signal Description

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Table 2-11 Enhanced Synchronous Serial Interface 0 (ESSI0)

Signal Name Type

State During Signal Description

Reset Stop

SC00

PC0

Input or Output

Input Disconnected Serial Control 0—The function of SC00 is determined by the selection of either Synchronous or Asynchronous mode. In Asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). In Synchronous mode, this signal is used either for Transmitter 1 output or for Serial I/O Flag 0.

Port C 0—The default configuration following reset is GPIO input PC0. When configured as PC0, signal direction is controlled through the Port Directions Register (PRR0). The signal can be configured as ESSI signal SC00 through the Port Control Register (PCR0).


SC01

PC1

Input/Output

Input or Output

Input Disconnected Serial Control 1—The function of SC01 is determined by the selection of either Synchronous or Asynchronous mode. In Asynchronous mode, this signal is used for the receiver frame sync I/O. In Synchronous mode, this signal is used either for Transmitter 2 output or for Serial I/O Flag 1.

Port C 1—The default configuration following reset is GPIO input PC1. When configured as PC1, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC01 through PCR0.


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SC02

PC2

Input/Output

Input or Output

Input Disconnected Serial Control Signal 2—SC02 is used for frame sync I/O. SC02 is the frame sync for both the transmitter and receiver in Synchronous mode, and for the transmitter only in Asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation).

Port C 2—The default configuration following reset is GPIO input PC2. When configured as PC2, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC02 through PCR0.


Table 2-11 Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)

Signal Name Type


Reset Stop

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SCK0

PC3

Input/Output

Input or Output

Input Disconnected Serial Clock—SCK0 is a bidirectional Schmitt-trigger input signal providing the serial bit rate clock for the ESSI interface. The SCK0 is a clock input or output used by both the transmitter and receiver in Synchronous modes, or by the transmitter in Asynchronous modes.

Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6 T (i.e., the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock.

Port C 3—The default configuration following reset is GPIO input PC3. When configured as PC3, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SCK0 through PCR0.


SRD0

PC4

Input/Output

Input or Output

Input Disconnected Serial Receive Data—SRD0 receives serial data and transfers the data to the ESSI receive shift register. SRD0 is an input when data is being received.

Port C 4—The default configuration following reset is GPIO input PC4. When configured as PC4, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SRD0 through PCR0.



Signal Name Type


Reset Stop

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2.10 ENHANCED SYNCHRONOUS SERIAL INTERFACE 1 (ESSI1)

STD0

PC5

Input/Output

Input or Output

Input Disconnected Serial Transmit Data—STD0 is used for transmitting data from the serial transmit shift register. STD0 is an output when data is being transmitted.

Port C 5—The default configuration following reset is GPIO input PC5. When configured as PC5, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal STD0 through PCR0.


Table 2-12 Enhanced Synchronous Serial Interface 1 (ESSI1)

Signal Name Type

State DuringSignal Description

Reset Stop

SC10

PD0

Input or Output

Input Disconnected Serial Control 0—The function of SC10 is determined by the selection of either Synchronous or Asynchronous mode. In Asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). In Synchronous mode, this signal is used either for Transmitter 1 output or for Serial I/O Flag 0.

Port D 0—The default configuration following reset is GPIO input PD0. When configured as PD0, signal direction is controlled through the Port Directions Register (PRR1). The signal can be configured as an ESSI signal SC10 through the Port Control Register (PCR1).



Signal Name Type


Reset Stop

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SC11

PD1

Input/Output

Input or Output

Input Disconnected Serial Control 1—The function of SC11 is determined by the selection of either Synchronous or Asynchronous mode. In Asynchronous mode, this signal is used as the receiver frame sync I/O. In Synchronous mode, this signal is used either for Transmitter 2 output or for Serial I/O Flag 1.

Port D 1—The default configuration following reset is GPIO input PD1. When configured as PD1, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC11 through PCR1.


SC12

PD2

Input/Output

Input or Output

Input Disconnected Serial Control Signal 2—SC12 is used for frame sync I/O. SC12 is the frame sync for both the transmitter and receiver in Synchronous mode, and for the transmitter only in Asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in Synchronous operation).

Port D 2—The default configuration following reset is GPIO input PD2. When configured as PD2, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC12 through PCR1.



Signal Name Type


Reset Stop

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SCK1

PD3

Input/Output

Input or Output

Input Disconnected Serial Clock—SCK1 is a bidirectional Schmitt-trigger input signal providing the serial bit rate clock for the ESSI. The SCK1 is a clock input or output used by both the transmitter and receiver in Synchronous modes, or by the transmitter in Asynchronous modes.

Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6 T (i.e., the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock.

Port D 3—The default configuration following reset is GPIO input PD3. When configured as PD3, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SCK1 through PCR1.


SRD1

PD4

Input/Output

Input or Output

Input Disconnected Serial Receive Data—SRD1 receives serial data and transfers the data to the ESSI receive shift register. SRD1 is an input when data is being received.

Port D 4—The default configuration following reset is GPIO input PD4. When configured as PD4, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SRD1 through PCR1.



Signal Name Type


Reset Stop

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Serial Communication Interface (SCI)


2.11 SERIAL COMMUNICATION INTERFACE (SCI)

The Serial Communication Interface (SCI) provides a full duplex port for serial communication to other DSPs, microprocessors, or peripherals (such as modems).

STD1

PD5

Input/Output

Input or Output

Input Disconnected Serial Transmit Data—STD1 is used for transmitting data from the serial transmit shift register. STD1 is an output when data is being transmitted.

Port D 5—The default configuration following reset is GPIO input PD5. When configured as PD5, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal STD1 through PCR1.


Table 2-13 Serial Communication Interface (SCI)

Signal Name Type


Reset Stop

RXD

PE0

Input

Input or Output

Input Disconnected Serial Receive Data—This input receives byte oriented serial data and transfers it to the SCI Receive Shift Register.

Port E 0—The default configuration following reset is GPIO input PE0. When configured as PE0, signal direction is controlled through the SCI Port Directions Register (PRR). The signal can be configured as an SCI signal RXD through the SCI Port Control Register (PCR).



Signal Name Type


Reset Stop

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Timers

2.12 TIMERS

Three identical and independent timers are implemented in the DSP56305. Each timer can use internal or external clocking, and can interrupt the DSP56305 after a specified number of events (clocks), or can signal an external device after counting a specific number of internal events. Each timer connects has one bidirectional input or output signal dedicated to it.

TXD

PE1

Output

Input or Output

Input Disconnected Serial Transmit Data—This signal transmits data from SCI Transmit Data Register.

Port E 1—The default configuration following reset is GPIO input PE1. When configured as PE1, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal TXD through the SCI PCR.


SCLK

PE2

Input/Output

Input or Output

Input Disconnected Serial Clock—This bidirectional Schmitt-trigger input signal provides the input or output clock used by the transmitter and/or the receiver.

Port E 2—The default configuration following reset is GPIO input PE2. When configured as PE2, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal SCLK through the SCI PCR.


Table 2-13 Serial Communication Interface (SCI) (Continued)

Signal Name Type


Reset Stop

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Timers


Table 2-14 Triple Timer Signals

Signal Name Type


Reset Stop

TIO0 Input or Output

Input Disconnected Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions as an external event counter or in Measurement mode, TIO0 is used as input. When Timer 0 functions in Watchdog, Timer, or Pulse Modulation mode, TIO0 is used as output.

The default mode after reset is GPIO input. This can be changed to output or configured as a Timer Input/Output through the Timer 0 Control/Status Register (TCSR0).










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JTAG/OnCE Interface

2.13 JTAG/ONCE INTERFACE

Table 2-15 JTAG/OnCE Interface

Signal Name Type

State During Reset

Signal Description

TCK Input Input Test Clock—TCK is a test clock input signal used to synchronize the JTAG test logic.


TDI Input Input Test Data Input—TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor.


TDO Output Tri-stated Test Data Output—TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK.

TMS Input Input Test Mode Select—TMS is an input signal used to sequence the test controller’s state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor.


TRST Input Input Test Reset—TRST is an active-low Schmitt-trigger input signal used to asynchronously initialize the test controller. TRST has an internal pull-up resistor. TRST must be asserted after power up. Always assert TRST immediately after power-up.


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JTAG/OnCE Interface


DE Input/Output

Input Debug Event—DE is an open-drain bidirectional active-low signal. As an input, it provides a means of entering the Debug mode of operation from an external command controller. As an output, it provides a means of acknowledging that the chip has entered the Debug mode. When asserted as an input, DE causes the DSP56300 core to finish the current instruction being executed, save the instruction pipeline information, enter the Debug mode, and wait for commands to be entered from the debug serial input line. This signal is asserted as an output for 3 clock cycles when the chip enters the Debug mode as a result of a debug request or as a result of meeting a breakpoint condition. The DE has an internal pull-up resistor.

This is not a standard part of the JTAG Test Access Port (TAP) Controller. The signal connects directly to the OnCE module to initiate Debug mode directly or to provide a direct external indication that the chip has entered the Debug mode. All other interface with the OnCE module must occur through the JTAG port.


Table 2-15 JTAG/OnCE Interface (Continued)

Signal Name Type

State During Reset

Signal Description

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JTAG/OnCE Interface

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SECTION 3

MEMORY CONFIGURATION

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Memory Configuration

3.1 Memory Spaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-33.2 RAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-73.3 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-103.4 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-113.5 Internal and External I/O Memory Map . . . . . . . . . . . . . . . . . . .3-20

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Memory Spaces


3.1 MEMORY SPACES

The DSP56305 provides three independent memory spaces:

• Program

• X data

• Y data

Each memory space uses (by default) twenty-four external address lines for addressing, allowing access to 16 M of external memory. Program and data word length is 24 bits, and internal memory uses 24-bit addressing.

The DSP56305 provides a Sixteen-bit Compatibility mode that effectively uses 16-bit addressing for each memory space, allowing access to 64 K each of memory. This mode puts 0s in the most significant byte of the usual (24-bit) program and data word, and ignores the zeroed byte, thus effectively using 16-bit program and data words. The Sixteen-bit Compatibility mode allows the DSP56305 to use 56000 object code without change (thus minimizing system cost for applications that use the smaller address space). See the DSP56300 Family Manual, Section 6.4 for further information.

Internal memory is 24-bit wide, high-speed, Static RAM occupying the lowest parts of memory space.

3.1.1 Program Memory Space

Program memory space consists of:

• Internal program memory, consisting of:Program RAM, 6.5 K by defaultProgram ROM, 6 K x 24-bit

• Bootstrap Program ROM (192 x 24-bit)

• (Optionally) Off-chip memory expansion (as much as 16 M in 24-bit mode and 64 K in Sixteen-bit Compatibility mode)

• (Optionally) Instruction Cache (1 K) formed from the uppermost Program RAM

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Memory Spaces

The Program ROM usually contains the Real Time Operating System (RTOS), but may contain customer-supplied code. For further information on supplying code for a customized DSP56305 Program ROM, please contact your Motorola regional sales office.

Program memory space at locations $FF00C0–$FF07FF and $FF2000–$FFFFFF is reserved and should not be accessed.

3.1.1.1 Program RAMThe on-chip Program RAM consists of 24-bit wide, high-speed, internal Static RAM occupying the lowest 6.5 K (default), 5.5 K, or 7.5 K locations in the program memory space (depending on the settings of the MS and CE bits). The Program RAM default organization is four banks of 256 24-bit words (1 K). The upper four banks of X data RAM can be configured as Program RAM by setting the MS bit. When the CE bit is set, the upper 1 K of Program RAM is used as an internal Instruction Cache.

The Memory Switch bit (OMR Bit 7), when set, switches the uppermost 1 K of X data RAM to Program RAM.

3.1.1.2 Bootstrap ROMThe bootstrap code is accessed at addresses $FF0000–$FFF0BF (192 words) in Program memory space. The bootstrap ROM cannot be accessed in Sixteen-bit Compatibility mode. See Appendix A for a complete listing of the bootstrap code.

CAUTION

While the contents of Program RAM are unaffected by toggling theMS bit, the location of program data placed in the ProgramRAM/Instruction Cache area changes after the MS bit is toggled,since the cache always occupies the top-most 1 K Program RAMaddresses. To preserve program data integrity, do not set or clearthe MS bit when the CE bit is set. See Section 3.2 for the correctprocedure.

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Memory Spaces


3.1.2 Data Memory Spaces

Data memory space is divided into X data memory and Y data memory to match the natural partitioning of DSP algorithms. The data memory partitioning allows the DSP56305 to feed two operands to the Data ALU simultaneously, enabling it to perform a multiply-accumulate operation in one clock cycle.

X and Y data memory space are similar in structure and functionality. They each contain:

• Internal data RAM memory

• (Optionally) Off-chip memory expansion (up to 16 M in the 24-bit Address mode and 64 K in the 16-bit Address mode).

There are several differences between the two memory spaces.

1. The X data RAM size is 3.75 K by default, while Y data RAM size is 2 K.

2. The upper 128 words of each space are reserved for different uses. The upper 128 words of X data memory are reserved for internal I/O. The upper 64 words of Y data memory may be used for more internal and for external I/O space (for further information, see Section 3.1.2.1 and Section 3.1.2.2).

3. The Y memory space contains a ROM, which may be used for customer-supplied code.

For further information on supplying code for a customized DSP56305 ROM, please contact your Motorola regional sales office.

3.1.2.1 X Data Memory Space The on-chip X data RAM is 24-bit wide, high-speed, internal Static RAM occupying by default the lowest 3840 (3.75 K) locations ($000000–$000EFF) in X memory space. It is organized in 15 banks with 256 locations each.

When the Memory Switch (MS) bit (OMR Bit 7) is set, the 1024 (1 K, or four banks) uppermost locations ($000B00–$00000EFF) of X data RAM are switched to Program RAM. There is then 2.75 K of X data RAM, and the highest internal X data RAM location is then $000AFF. The default value of the MS bit is cleared.

The on-chip peripheral registers and some of the DSP56305 core registers occupy the top 128 locations of X data memory ($FFFF80–$FFFFFF in the 24-bit Address mode or $FF80–$FFFF in the 16-bit Address mode). This area is called X-I/O space, and it can be accessed by MOVE and MOVEP instructions and by bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET). For a listing of the contents of this area, see the Programming Sheets in Appendix D.

The X memory space at locations $FF0000–$FFEFFF is reserved and should not be accessed.

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Memory Spaces

3.1.2.2 Y Data Memory Space The on-chip Y data RAM is 24-bit wide, high-speed, internal Static RAM occupying the lowest 2048 (2 K) locations ($000000–$0007FF) in Y memory space. It is organized in 8 banks with 256 locations each.

The on-chip Y data ROM is a 24-bit wide, internal, read-only, static memory occupying 3072 (3 K) locations ($FF0000–$FF0BFF) in Y memory space. It is organized in 12 banks with 256 locations each.

Some of the on-chip peripheral registers occupy 64 locations ($FFFF80–$FFFFBF) in Y data memory. This area is called internal Y-I/O space and it can be accessed by the MOVE or MOVEP instructions and by bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR and JSSET).

The off-chip peripheral registers should be mapped into the top 64 locations ($FFFFC0–$FFFFFF) to take advantage of the move peripheral data (MOVEP) instruction and the bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR and JSSET). This area is called external Y-I/O space.

For a listing of the contents of internal and external Y-I/O space, see the Programming Sheets in Appendix D.

The Y memory space at locations $FF0C00–$FFEFFF is reserved and should not be accessed.

3.1.3 Memory Space Configuration

Memory space addressing is for 24-bit words by default. The DSP56305 switches to Sixteen-bit Address Compatibility mode by setting the Sixteen-bit Compatibility (SC) bit in the Status Register (SR).

Memory maps for the different configurations are shown in Figure 3-1 to Figure 3-8.

Table 3-1 Memory Space Configuration Bit Settings for the DSP56305

Bit Abbreviation Bit Name Bit Location Cleared = 0

Effect (Default) Set = 1 Effect

SC Sixteen-bit Compatibility

SR 13 16 M word address space (24-bit word)

64 K word address space (16-bit word)

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RAM Configuration


3.2 RAM CONFIGURATION

The DSP56305 contains 12.25 K of RAM, divided by default into:

• Program RAM (6.5 K)

• X data RAM (3.75 K)

• Y data RAM (2.0 K)

RAM configuration depends on two bits: the Cache Enable (CE) of the SR and the Memory Select (MS) of the OMR.

Memory maps for the different configurations are shown in Figure 3-1 to Figure 3-8.

Note: The MS bit may not be changed when CE is set. The Instruction Cache occupies the top 1 K of what would otherwise be Program RAM, and to switch memory into or out of Program RAM when the cache is enabled will cause conflicts. To change the MS bit when CE is set:

1. clear CE

2. change MS

3. set CE

Table 3-2 RAM Configuration Bit Settings for the DSP56305

Bit Abbreviation Bit Name Bit

LocationCleared = 0 Effect

(Default) Set = 1 Effect

CE Cache Enable

SR 19 Cache Disabled Cache Enabled1 K

MS Memory Switch

OMR 7 Program RAM 6.5 KX data RAM 3.75 KY data RAM 2.0 K

Program RAM 7.5 KX data RAM 2.75 KY data RAM 2.0 K

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RAM Configuration

3.2.1 DSP56300 RAM Patch Mechanism

The 56300 series patch mechanism is intended for use when certain ROM code locations need to be replaced by RAM. The replacements are generally intended for lines of code, rather than whole blocks of code. For example, a call to a certain subroutine could be replaced by a call to a subroutine at a different location.The patch mechanism is implemented using the cache circuitry — the cache must be activated for the patch to work, and using the patch will affect the availability of cache space.

To use the patch, do the following:

1. activate cache (set sr bit 19)

2. activate patch (set omr bit 23)

3. initialize all cache tags to different values (required for proper functioning)

4. lock the desired patch location

5. write the desired replacement data to the (virtual) patch locations

6. reading (or fetching) the location to be replaced will then return the replacement data instead of the ROM data

3.2.1.1 Sample Code for DSP56305 Patch Mechanism

M_PROMS EQU $ff0800 ; ROM area StartM_PROME EQU $ff08ff ; ROM area EndPATCH_OFSET equ 64 ; patch offset

move #M_PROMS,r0

; 3 - regular write (activate patch)

bset #M_CE,sr ; CacheEnable = 1 bset #M_PAE,omr ; PatchEnable = 1 move #$800000,r1 ; any external address move #128,n1 ; 128/256 for 1/2K RAM, sector size move #(M_PROMS+PATCH_OFSET),r2

rep #8 punlock (r1)+n1 ; initialize TAGs to different values

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RAM Configuration


plock (r2) ; lock patch's sector (start/mid/end) nop nop nop move #PATCH_DATA_START,r1 do #(PATCH_DATA_END-PATCH_DATA_START),PATCH_LOOP ; replace ROM by PATCH movem p:(r1)+,x0 movem x0,p:(r2)+ nop ; Do-loop restrictionPATCH_LOOP

; 1 - regular read; 5 - read with hit

rep #(M_PROME-M_PROMS+1) move p:(r0)+,x0

; 2 - fetch; 6 - fetch with hit

move #M_PROMS,r0 nop nop nop

jsr r0 ; ROM: rts (to the ENDTEST)

ENDTEST jmp ENDTEST nop nop nop nop

; patch data

PATCH_DATA_START

move #5,m0 move #6,m1 move #7,m2

PATCH_DATA_END

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Memory Configurations

3.3 MEMORY CONFIGURATIONS

Memory configuration determines the size and address range for addressable memory, and the amount of memory allocated to Program RAM, data RAM, and the Instruction Cache.

3.3.1 Memory Space Configurations

The memory space configurations are listed in Table 3-3.

3.3.2 RAM Configurations

The RAM configurations for the DSP56305 are listed in Table 3-4.

The actual memory locations for Program RAM and the Instruction Cache in the program memory space are determined by the MS and CE bits, and their addresses are given in Table 3-5.

Table 3-3 Memory Space Configurations for the DSP56305

SC Bit Setting

Addressable Memory Size Address Range Bits per Word

0 16 M words $000000–$FFFFFF 24

1 64 K words $0000–$FFFF 16

Table 3-4 RAM Configurations for the DSP56305

Bit Settings Memory Sizes (in K)

MS CE Program RAM

X data RAM

Y data RAM Cache

0 0 6.5 3.75 2.0 0

0 1 5.5 3.75 2.0 1

1 0 7.5 2.75 2.0 0

1 1 6.5 2.75 2.0 1

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Memory Maps


The actual memory locations for both X and Y data RAM in their own memory space are determined by the MS bit, and their addresses are listed in Table 3-6.

3.4 MEMORY MAPS

The following figures describe each of the memory space and RAM configurations defined by the settings of the SC, MS, and CE bits. The figures show the configuration and the table describes the bit settings, memory sizes, and memory locations.

Table 3-5 Memory Locations for Program RAM and Instruction Cache

MS CE Program RAM Location Cache Location

0 0 $000000–$0019FF N/A

0 1 $000000–$0015FF $001600–$0019FF

1 0 $000000–$001DFF N/A

1 1 $000000–$0019FF $001A00–$001DFF

Table 3-6 Memory Locations for Data RAM

MS X data RAM Location Y data RAM Location

0 $000000–$000EFF $000000–$0007FF

1 $000000–$000AFF $000000–$0007FF

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Memory Maps

Figure 3-1 Default Memory Configuration

Note: This column gives the maximum memory addressable in the memory space.

SC = 0, MS = 0, CE = 0Program X Data Y Data

$FFFFFF Internal Reserved

$FFFFFF

$FFFF80

Internal I/O128 words

$FFFFFF$FFFFC0

External I/O64 words

$FF2000 $FFFF80Internal I/O64 words

$FF0800

Internal Program ROM 6 K $FFF000

External

$FFF000

External

$FF00C0Internal

ReservedInternal

Reserved $FF0C00Internal

Reserved

$FF0000

Bootstrap ROM 192 words

$FF0000 $FF0000

Internal Y data ROM

3 K

$001A00External

$000F00External

$000800External

$000000

Internal Program RAM 6.5 K $000000

InternalX data RAM

3.75 K $000000

InternalY data RAM

2 K


Program X Data Y Data CacheMax.

Mem.*

RAM: 6.5 K$000000–$0019FF

RAM: 3.75 K$000000–$000EFF

RAM: 2 K$000000–$0007FF

None 16 M

ROM: 6 K$FF0800–$FF1FFF

N/AROM

ROM: 3 K$FF0000–$FF0BFF

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Memory Maps


Figure 3-2 Instruction Cache Enabled




$FFFFFF

$FFFF80


$FFFFFF$FFFFC0



$FF0800


External

$FFF000

External

$FF00C0Internal

ReservedInternal


Reserved

$FF0000


$FF0000 $FF0000

Internal Y data ROM

3 K

$001A00External

$000F00External

$000800External

$001600

Instruction Cache

1 K

InternalX data RAM

3.75 K

InternalY data RAM

2 K

$000000

Internal Program RAM 5.5 K $000000 $000000



Mem.*

RAM: 5.5 K$000000–$0015FF

RAM: 3.75 K$000000–$000EFF

RAM: 2 K$000000–$0007FF

1 K$001600–$0019FF

16 M


N/AROM


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Memory Maps

Figure 3-3 Memory Switch Enabled




$FFFFFF

$FFFF80


$FFFFFF$FFFFC0



$FF0800


External

$FFF000

External

$FF00C0Internal

ReservedInternal


Reserved

$FF0000


$FF0000 $FF0000

Internal Y data ROM

3 K

$001E00External

$000B00External

$000800External

$000000


InternalX data RAM

2.75 K $000000

InternalY data RAM

2 K



Mem.*

RAM: 7.5 K$000000–$001DFF

RAM: 2.75 K$000000–$000AFF

RAM: 2 K$000000–$0007FF

None 16 M


N/AROM


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Memory Maps


Figure 3-4 Memory Switch Enabled, Instruction Cache Enabled




$FFFFFF

$FFFF80


$FFFFFF$FFFFC0



$FF0800


External

$FFF000

External

$FF00C0Internal

ReservedInternal


Reserved

$FF0000


$FF0000 $FF0000

Internal Y data ROM

3 K

$001E00External

$000B00External

$000800External

$001A00

Instruction Cache

1 K

InternalX data RAM

2.75 K

InternalY data RAM

2 K

$000000

Internal Program RAM 6.5 K $000000 $000000



Mem.*

RAM: 6.5 K$000000–$0019FF

RAM: 2.75 K$000000–$000AFF

RAM: 2 K$000000–$0007FF

1 K$001A00–$001DFF

16 M


N/AROM


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Memory Maps

Figure 3-5 Sixteen-Bit Compatibility Mode



$FFFF External $FFFF$FF80


$FFFF$FFC0


External$FF80


$1A00 $0F00 $0800External

$0000


Internal X data RAM

3.75 K $0000

InternalY data RAM

2 K



Mem.*

RAM: 6.5 K$0000–$19FF

RAM: 3.75 K$0000–$0EFF

RAM: 2 K$0000–$07FF

None 64 K

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Memory Maps


Figure 3-6 Sixteen-Bit Compatibility Mode, Instruction Cache Enabled





$FFFF$FFC0


$1A00External

$FF80Internal I/O64 words

$1600

Instruction Cache

1 K $0F00 $0800

External

$0000

Internal Program RAM5.5 K $0000

Internal X data RAM

3.75 K $0000

InternalY data RAM

2 K



Mem.*

RAM: 5.5 K$0000–$15FF

RAM: 3.75 K$0000–$0EFF

RAM: 2 K$0000–$07FF

1 K$1600–$19FF

64 K

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Memory Maps

Figure 3-7 Sixteen-Bit Compatibility Mode, Memory Switch Enabled





$FFFF$FFC0


External$FF80


$1E00 $0B00 $0800External

$0000


Internal X data RAM

2.75 K $0000

InternalY data RAM

2 K



Mem.*

RAM: 7.5 K$0000–$1DFF

RAM: 2.75 K$0000–$0AFF

RAM: 2 K$0000–$07FF

None 64 K

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Memory Maps


Figure 3-8 Sixteen-Bit Compatibility Mode, Memory Switch Enabled, Instruction Cache Enabled





$FFFF$FFC0


$1E00External

$FF80Internal I/O64 words

$1A00

Instruction Cache

1 K $0B00 $0800

External

$0000

Internal Program RAM6.5 K $0000

Internal X data RAM

2.75 K $0000

InternalY data RAM

2 K



Mem.*

RAM: 6.5 K$0000–$19FF

RAM: 2.75 K$0000–$0AFF

RAM: 2 K$0000–$07FF

1 K$1A00–$1DFF

64 K

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Internal and External I/O Memory Map

3.5 INTERNAL AND EXTERNAL I/O MEMORY MAP

The DSP56305 internal I/O space (the top 128 locations of the X data memory space and 64 high Y data memory space locations) and external I/O space (the top 64 locations of Y data memory space) are listed in Appendix D, Table D-2.

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SECTION 4

CORE CONFIGURATION

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Core Configuration

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-34.2 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-34.3 BOOTSTRAP PROGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-54.5 INTERRUPT SOURCES AND PRIORITIES . . . . . . . . . . . . . . .4-104.6 DMA REQUEST SOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . .4-194.7 OPERATING MODE REGISTER (OMR). . . . . . . . . . . . . . . . . .4-214.8 PLL CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . .4-224.9 DEVICE IDENTIFICATION REGISTER . . . . . . . . . . . . . . . . . .4-234.10 JTAG IDENTIFICATION (ID) REGISTER . . . . . . . . . . . . . . . . .4-234.11 JTAG BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . . . .4-24

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Core Configuration

Introduction


4.1 INTRODUCTION

This chapter contains DSP56300 core configuration details specific to the DSP56305. These configuration details include:

• Operating modes

• Bootstrap program

• Interrupt sources and priorities

• DMA request sources

• Operating Mode Register (OMR)

• PLL control register (PCTL)

• Device Identification Register (IDR)

• JTAG Device Identification Register (ID)

• JTAG Boundary Scan Register (BSR)

For more information on specific registers or modules in the DSP56300 core, refer to the DSP56300 Family Manual (DSP56300FM/AD).

4.2 OPERATING MODES

The DSP56305 begins operations by leaving Reset and going into one of eight operating modes. As the DSP56305 exits the Reset state it loads the values of MODA, MODB, MODC, and MODD into bits MA, MB, MC, and MD of the Operating Mode Register (OMR). These bit settings determine the chip’s operating mode, which determines what bootstrap program option the chip uses to start up.

The MA–MD bits of the OMR can also be set directly by software. Jumping directly to the bootstrap program entry point ($FF0000) after setting the OMR bits causes the DSP56305 to execute the specified bootstrap program option (except modes 0 and 8).

Table 4-1 shows the DSP56305 bootstrap operation modes, the corresponding settings of the external operational mode signal lines (the mode bits MA–MD in the OMR), and the reset vector address to which the DSP56305 jumps once it leaves the Reset state.

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Core Configuration

Operating Modes

Table 4-1 DSP56305 Operating Modes

Mode MODD MODC MODB MODA Reset Vector Description

0 0 0 0 0 $C00000 Expanded mode

1 0 0 0 1 $FF0000 RTOS Mode

2 0 0 1 0 $FF0000 RTOS Mode

3 0 0 1 1 $FF0000 RTOS Mode

4 0 1 0 0 $FF0000 Reserved

5 0 1 0 1 $FF0000 Reserved

6 0 1 1 0 $FF0000 Reserved

7 0 1 1 1 $FF0000 Reserved

8 1 0 0 0 $008000 Expanded mode

9 1 0 0 1 $FF0000 Bootstrap from byte-wide memory

A 1 0 1 0 $FF0000 Bootstrap through SCI

B 1 0 1 1 $FF0000 Host Bootstrap 24-bit-wide UB Mode (from Port A of a DSP563xx device)

C 1 1 0 0 $FF0000 Host Bootstrap PCI Mode (32-bit-wide)

D 1 1 0 1 $FF0000 Host Bootstrap 16-bit-wide UB Mode (ISA)

E 1 1 1 0 $FF0000 Host Bootstrap 8-bit-wide UB Mode in double-strobe pin configuration

F 1 1 1 1 $FF0000 Host Bootstrap 8-bit-wide UB Mode in single-strobe pin configuration

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Core Configuration

Bootstrap Program


4.3 BOOTSTRAP PROGRAM

The bootstrap program is factory-programmed in an internal 192 word by 24-bit bootstrap ROM located in Program memory space at locations $FF0000–$FF00BF. The bootstrap program can load any Program RAM segment from an external DSP56305 port. The bootstrap material described here, and listed in Appendix A , is a default, which may be modified or replaced by the customer.

On exiting the Reset state, the DSP56305

1. samples the MODA, MODB, MODC and MODD signal lines, to determine the reset vector location, and

2. loads their values into bits MA, MB, MC, and MD in the OMR

The contents of the MA, MB, MC, and MD bits determine which bootstrap mode the DSP56305 enters.

1. If MA, MB, MC, and MD are all cleared (Bootstrap mode 0), the program bypasses the bootstrap ROM and the DSP56305 starts loading instructions from external program memory location $C00000.

2. If MA, MB, and MC are cleared and MD is set (Bootstrap mode 8), the program bypasses the bootstrap ROM and the DSP56305 starts loading in instruction values from external program memory location $008000.

3. Otherwise, the DSP56305 jumps to the bootstrap program entry point at $FF0000.

If the bootstrap program is loading via the Host Interface (HI32), setting the HF0 bit in the HSR causes the DSP56305 to stop loading and begin execution of the loaded program at the specified start address.

See Table 4-1 for a tabular description of the mode bit settings for the operating modes.

The bootstrap program options (except modes 0 and 8) can be invoked at any time by setting the appropriate MA, MB, MC, and MD bits in the OMR and jumping to the bootstrap program entry point, $FF0000. The mode selection bits in the OMR can be set directly by software.

Bootstrap modes 0 and 8 are the normal functioning modes for the DSP56305. The other bootstrap modes are bootstrap modes proper.

In the proper bootstrap modes, the bootstrap program expects the following data sequence when downloading the user program through an external port:

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Core Configuration

Bootstrap Program

1. Three bytes defining the number of (24-bit) program words to be loaded

2. Three bytes defining the (24-bit) start address to which the user program loads in the DSP56305 program memory

3. The user program (three bytes for each 24-bit program word)

The three bytes for each data sequence must be loaded with the least significant byte first.

Once the bootstrap program completes loading the specified number of words, it jumps to the specified starting address and executes the loaded program.

4.3.1 Mode 0: Expanded Mode

The bootstrap ROM is bypassed and the DSP56305 starts fetching instructions beginning at address $C00000. Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected.

4.3.2 Modes 1–3: Bootstrap according to RTOS mode

The program stored in this location, after testing MODD, jumps to the head of the RTOS ROM (address $FF0800). Then the program stored in the RTOS ROM is executed according to the result from testing MODA, MODB, and MODC.


0 0 0 0 0 $C00000 Expanded mode


1 0 0 0 1 $FF0000 RTOS Mode

2 0 0 1 0 $FF0000 RTOS Mode

3 0 0 1 1 $FF0000 RTOS Mode

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Core Configuration

Bootstrap Program


4.3.3 Modes 4–7: Reserved

These modes are reserved for future use.

4.3.4 Mode 8: Expanded Mode

The bootstrap ROM is bypassed and the DSP56305 starts fetching instructions beginning at address $008000. Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected.

4.3.5 Mode 9: Bootstrap from Byte-Wide External Memory

The bootstrap program loads instructions through Port A from external byte-wide memory, starting at P:$D00000 (bits 7–0). The SRAM memory access type is selected by the values in Address Attribute Register 1 (AAR1). Thirty-one (31) wait states are


4 0 1 0 0 — Reserved





8 1 0 0 0 $008000 Expanded mode


9 1 0 0 1 $FF0000 Bootstrap from byte-wide memory (at $D00000)

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Core Configuration

Bootstrap Program

inserted between each memory access. Address $D00000 is reflected as address $00000 on Port A signals HA0–HA17.

4.3.6 Mode A: Bootstrap Through SCI

Instructions are loaded through the SCI. The bootstrap program sets the SCI to operate in 10-bit Asynchronous mode, with 1 start bit, 8 data bits, 1 stop bit, and no parity. Data is received in this order; start bit, 8 data bits (Least Significant Bit first), and one stop bit. Data is aligned in the SCI Receive Data Register with the Least Significant Bit of the least significant byte of the received data appearing at bit 0.The user must provide an external clock source with a frequency at least 16 times the transmission data rate. Each byte received by the SCI is echoed back through the SCI transmitter to the external transmitter.

4.3.7 Mode B: Bootstrap through HI32 in 24-bit-wide UB mode (from 563xx Port A)

The program stored at the hardware reset vector, after testing MODA, MODB, MODC, and MODD, bootstraps through HI32 in 24-bit wide UB slave mode, in a configuration that allows glueless connection to Port A of a DSP563xx device. The DSP56305 is written with 24-bit wide words reflecting the 24-bit wide host bus transfers. This mode may be used for booting a slave DSP56305 from Port A of a master DSP563xx device with glueless connection.


A 1 0 1 0 $FF0000 Bootstrap through SCI


B 1 0 1 1 $FF0000 Bootstrap through HI32 in 24-bit-wide UB mode (from 563xx Port A)

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Core Configuration

Bootstrap Program


4.3.8 Mode C: Bootstrap through HI32 in PCI mode

The program stored at the hardware reset vector, after testing MODA, MODB, MODC, and MODD, bootstraps through HI32 in standard PCI slave configuration. The DSP56305 is written with 24-bit wide words encapsulated in 32-bit wide PCI transfers.

4.3.9 Mode D: Bootstrap through HI32 in 16-bit-wide UB mode (ISA)

The program stored at the hardware reset vector, after testing MODA, MODB, MODC, and MODD, bootstraps through HI32 in ISA slave configuration. The DSP56305 is written with 24-bit wide words broken into 16-bit wide ISA transfers.

4.3.10 Mode E: Bootstrap through HI32 in 8-bit-wide UB mode in double-strobe pin configuration

The program stored at the hardware reset vector, after testing MODA, MODB, MODC, and MODD, bootstraps through HI32 in UB slave double-strobe (HWR, HRD)


A 1 0 1 0 $FF0000 Bootstrap through HI32 in PCI mode


D 1 1 0 1 $FF0000 Bootstrap through HI32 in 16-bit-wide UB mode (ISA)


E 1 1 1 0 $FF0000 Bootstrap through HI32 in 8-bit-wide UB mode in double-strobe pin configuration

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Core Configuration

RTOS Program

configuration. The DSP56305 is written with 24-bit wide words broken into 8-bit wide host bus transfers. This mode may be used for booting from various microprocessors or microcontrollers, as for booting a slave DSP56305 from Port A of a master DSP563xx device.

4.3.11 Mode F: Bootstrap through HI32 in 8-bit-wide UB mode in single-strobe pin configuration

The program stored at the hardware reset vector, after testing MODA, MODB, MODC, and MODD, bootstraps through HI32 in UB slave single-strobe (HRW, HDS) configuration. The DSP56305 is written with 24-bit wide words broken into 8-bit wide host bus transfers. This mode may be used for booting from various microprocessors or microcontrollers.

4.4 RTOS PROGRAM

The RTOS program is factory-programmed in an internal 6144-words by 24-bit RTOS ROM located in P memory space at locations $FF0800–$FF1FFF. When exiting reset, the DSP56305 samples MODA, MODB, MODC, and MODD to determine the reset vector location. Except for modes 0 and 8, program execution begins from the internal P memory location $FF0000, which is the bootstrap ROM location. The bootstrap program first tests the MD bit in the Operating Mode Register (OMR), and if it is cleared, jumps to the RTOS ROM location $FF0800. The RTOS Program then tests the MA, MB, and MC bits in the OMR to determine the program flow.

4.5 INTERRUPT SOURCES AND PRIORITIES

Interrupt handling by the DSP56305, like that of all DSP56300 family members, has been optimized for DSP applications. Refer to Section 7 of the DSP56300 Family Manual. The


F 1 1 1 1 $FF0000 Bootstrap through HI32 in 8-bit-wide UB mode in single-strobe pin configuration

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Core Configuration

Interrupt Sources and Priorities


interrupt table is located in the 256 locations of program memory pointed to by the Vector Base Address (VBA) register in the Program Control Unit.

4.5.1 Interrupt Sources

Each interrupt is allocated two instructions in the table, so there are 128 table entries for interrupt handling. Table 4-2 shows the table entry address for each interrupt source. The DSP56305 initialization program loads the table entry for each interrupt serviced with two interrupt servicing instructions.

In the DSP56305,not all of the 128 vector addresses are used for specific interrupt sources. The remaining addresses are reserved. If it is known that certain interrupts will not be used, those interrupt vector locations may be used for program or data storage.

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Core Configuration


Table 4-2 Interrupt Sources

Interrupt Starting Address

Interrupt Priority

Level Range

Interrupt Source

VBA:$00 3 Hardware RESET

VBA:$02 3 Stack Error

VBA:$04 3 Illegal Instruction

VBA:$06 3 Debug Request Interrupt

VBA:$08 3 Trap

VBA:$0A 3 Non-Maskable Interrupt (NMI)

VBA:$0C 3 Reserved For Future Level-3 Interrupt Source

VBA:$0E 3 Reserved For Future Level-3 Interrupt Source

VBA:$10 0–2 IRQA

VBA:$12 0–2 IRQB

VBA:$14 0–2 IRQC

VBA:$16 0–2 IRQD

VBA:$18 0–2 DMA Channel 0

VBA:$1A 0–2 DMA Channel 1

VBA:$1C 0–2 DMA Channel 2

VBA:$1E 0–2 DMA Channel 3



VBA:$24 0–2 TIMER 0 Compare

VBA:$26 0–2 TIMER 0 Overflow


VBA:$2A 0–2 TIMER 1 Overflow

VBA:$2C 0–2 TIMER 2 Compare

VBA:$2E 0–2 TIMER 2 Overflow

VBA:$30 0–2 ESSI0 Receive Data

VBA:$32 0–2 ESSI0 Receive Data With Exception Status

VBA:$34 0–2 ESSI0 Receive last slot

VBA:$36 0–2 ESSI0 Transmit Data

VBA:$38 0–2 ESSI0 Transmit Data with Exception Status

VBA:$3A 0–2 ESSI0 Transmit last slot

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Core Configuration



VBA:$3C 0–2 Reserved

VBA:$3E 0–2 Reserved



VBA:$44 0–2 ESSI1 Receive last slot


VBA:$48 0–2 ESSI1 Transmit Data with Exception Status

VBA:$4A 0–2 ESSI1 Transmit last slot



VBA:$50 0–2 SCI Receive Data

VBA:$52 0–2 SCI Receive Data with Exception Status

VBA:$54 0–2 SCI Transmit Data

VBA:$56 0–2 SCI idle Line

VBA:$58 0–2 SCI Timer

VBA:$5A 0–2 Reserved



VBA:$60 0–2 Host PCI Transaction Termination

VBA:$62 0–2 Host PCI Transaction Abort

VBA:$64 0–2 Host PCI Parity Error

VBA:$66 0–2 Host PCI Transfer Complete

VBA:$68 0–2 Host PCI Master Receive Request

VBA:$6A 0–2 Host Slave Receive Request

VBA:$6C 0–2 Host PCI Master Transmit Request

VBA:$6E 0–2 Host Slave Transmit Request

VBA:$70 0–2 Host PCI Master Address Request

VBA:$72 0–2 / 3 Host Command / Host NMI (Default)

VBA:$74 0–2 Reserved


VBA:$78 0–2 FCOP Data Input Buffer Empty


Interrupt Priority

Level Range

Interrupt Source

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Core Configuration


Note: Any Interrupt starting address (including reserved addresses) may be used for Host NMI (IPL = 3) and for Host command interrupt (IPL = 0–2).

4.5.2 Interrupt Priority Levels

The DSP56305 has a four level interrupt priority structure. Each interrupt has two Interrupt Priority Level bits (IPL[1:0]) that determine its interrupt priority level. Level 0 is the lowest priority level. Level 3 is the highest level priority and is non-maskable. Table 4-3 defines the IPL bits.

VBA:$7A 0–2 FCOP Data Output Buffer Full



VBA:$80 0–2 VCOP Data In Request

VBA:$82 0–2 VCOP Output Buffer Full

VBA:$84 0–2 VCOP Data Out Request

VBA:$86 0–2 VCOP Processing Done

VBA:$88 0–2 VCOP Operation Complete




VBA:$90 0–2 CCOP Input FIFO Empty

VBA:$92 0–2 CCOP Output FIFO Not Empty

VBA:$94 0–2 CCOP Cipher Processing Done

VBA:$96 0–2 CCOP Parity Code Processing Done


: : :

VBA:$FE 0–2 Reserved


Interrupt Priority

Level Range

Interrupt Source

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Core Configuration



There are two interrupt priority registers in the DSP56305. The IPR-C is dedicated to DSP56300 core interrupt sources and IPR-P is dedicated to DSP56305 peripheral interrupt sources. IPR-C is shown on Figure 4-1 on page 4-15 and IPR-P is shown in Figure 4-2 on page 4-16.

Table 4-3 Interrupt Priority Level Bits

IPL bitsInterrupts Enabled

Interrupts Masked

Interrupt Priority

LevelxxL1 xxL0

0 0 No — 0

0 1 Yes 0 1

1 0 Yes 0, 1 2

1 1 Yes 0, 1, 2 3

Figure 4-1 Interrupt Priority Register C (IPR-C) (X:$FFFFFF)

IAL0IAL1IAL2IBL0IBL1IBL2ICL0ICL1ICL2

01234567891011

IRQA IPLIRQA modeIRQB IPLIRQB modeIRQC IPLIRQC modeIRQD IPL

D0L0D0L1D1L0D1L1

23 22 21 20 19 18 17 16 15 14 13 12

DMA0 IPLDMA1 IPL

D2L0D2L1D3L0D3L1D4L0D4L1D5L0D5L1

DMA2 IPLDMA3 IPLDMA4 IPLDMA5 IPL

IDL2 IDL1 IDL0

IRQD mode

AA1410

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Core Configuration


4.5.3 Interrupt Source Priorities within an IPL

If more than one interrupt request is pending when an instruction is executed, the interrupt source with the highest IPL is serviced first. When several interrupt requests having the same IPL are pending, another fixed-priority structure within that IPL determines which interrupt source is serviced first. The fixed priority of interrupt sources within an IPL is listed in Table 4-4.

Figure 4-2 Interrupt Priority Register P (IPR-P) (X:$FFFFFE)

HPL0HPL1S0L0S0L1S1L0S1L1

23 22 21 20 19 18 17 16 15 14 13 12

01234567891011

HI32 IPLESSI0 IPLESSI1 IPLSCI IPLTriple Timer IPL

T0L0T0L1 SCL0SCL1

Reserved

FCOP IPL

FIL1 FIL0

VIL0VIL1CIL0CIL1

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Core Configuration



Table 4-4 Interrupt Source Priorities within an IPL

Priority Interrupt Source

Level 3 (Nonmaskable)

Highest Hardware RESET

Stack Error

Illegal Instruction

Debug Request Interrupt

Trap

Non-Maskable Interrupt

Lowest Non-Maskable Host Command Interrupt

Levels 0, 1, 2 (Maskable)

Highest IRQA (External Interrupt)

IRQB (External Interrupt)

IRQC (External Interrupt)

IRQD (External Interrupt)

DMA Channel 0 Interrupt






Host Command Interrupt

Host PCI Transaction Termination

Host PCI Transaction Abort

Host PCI Parity Error

Host PCI Transfer Complete

Host PCI Master Receive Request

Host Slave Receive Request

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Core Configuration


Host PCI Master Transmit Request

Host Slave Transmit Request

Host PCI Master Address Request

ESSI0 RX Data with Exception Interrupt

ESSI0 RX Data Interrupt

ESSI0 Receive Last Slot Interrupt

ESSI0 TX Data with Exception Interrupt

ESSI0 Transmit Last Slot Interrupt

ESSI0 TX Data Interrupt




ESSI1 TX Data with Exception Interrupt



SCI Receive Data with Exception Interrupt

SCI Receive Data

SCI Transmit Data

SCI Idle Line

SCI Timer

TIMER0 Overflow Interrupt

TIMER0 Compare Interrupt





FCOP Data Input Buffer Empty


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Core Configuration

DMA Request Sources


4.6 DMA REQUEST SOURCES

The DMA Request Source bits (DRS[4:0]) in the DMA Control/Status registers) encode the source of DMA requests used to trigger DMA transfers. DMA request sources may be internal peripherals or external devices requesting service through the IRQA, IRQB, IRQC, or IRQD signals. Table 4-5 describes the meanings of the DRS bits.

FCOP Data Output Buffer Full

VCOP Data In Request

VCOP Output Buffer Full

VCOP Data Out Request

VCOP Processing Done

VCOP Operation Complete

CCOP Input FIFO Empty

CCOP Output FIFO Not Empty

CCOP Cipher Processing Done

Lowest CCOP Parity Code Processing Done


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Core Configuration

DMA Request Sources

Table 4-5 DMA Request Sources

DMA Request Source Bits DRS4...DRS0 Requesting Device

00000 External (IRQA pin)

00001 External (IRQB pin)

00010 External (IRQC pin)

00011 External (IRQD pin)

00100 Transfer Done from DMA channel 0






01010 ESSI0 Receive Data (RDF0=1)

01011 ESSI0 Transmit Data (TDE0=1)



01110 SCI Receive Data (RDRF=1)

01111 SCI Transmit Data (TDRE=1)

10000 Timer0 (TCF0=1)

10001 Timer1 (TCF1=1)

10010 Timer2 (TCF2=1)

10011 FCOP Data Input Buffer Empty (FDIBE=1)

10100 FCOP Data Output Buffer Full (FDOBF=1)

10101 VCOP Input Data (DREQ=1)

10110 VCOP Output Buffer Full (DOBF=1)

10111 VCOP Output Data (DRDY=1)

11000 VCOP Processing Done (DONE=1)

11001 CCOP Input FIFO Empty (INFE=1)

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Core Configuration

Operating Mode Register (OMR)


4.7 OPERATING MODE REGISTER (OMR)

The Operating Mode Register (OMR) is a 24-bit read/write register divided into three byte-sized units. The first two bytes (COM and EOM) are used to control the chip’s operating mode. The third byte (SCS) is used to control and monitor the stack extension. The OMR control bits are shown in Figure 4-3. Refer to the DSP56300 Family Manual for a description of the OMR.

4.7.1 Address Tracing Enable (ATE)—OMR Bit 15

The Address Tracing Enable bit (ATE) is used to enable the Address Tracing mode, which allows the core to reflect the addresses of internal fetches and program space moves to the Address bus, providing assistance in software development.

11010 CCOP Cipher Processing Done (CIDN=1)

11011 Reserved

11100 Host Slave Receive Data (SRRQ=1)

11101 Host Master Receive Data (MRRQ=1)

11110 Host Slave Transmit Data (STRQ=1)

11111 Host Master Transmit Data (MTRQ=1)


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Core Configuration

PLL Control Register

4.8 PLL CONTROL REGISTER

The PLL Control register (PCTL) is an X-I/O mapped, 24-bit read/write register used to direct the operation of the on-chip PLL. The PCTL control bits are shown in Figure 4-4. Refer to the DSP56300 Family Manual for a full description of the PCTL.

4.8.1 PLL Multiplication Factor (MF11:0)—PCTL Bits 0–11

The Multiplication Factor bits (MF[11:0]) define the Multiplication Factor (MF) that is applied to the PLL input frequency. The MF bits are cleared during DSP56305 hardware reset, which corresponds to an MF of one.

4.8.2 Crystal Range (XTLR)—PCTL Bit 15

The Crystal Range bit (XTLR) controls the on-chip crystal oscillator transconductance. It is cleared during hardware reset.

SCS EOM COM

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEN WRP EOV EUN XYS ATE BRT TAS BE CDP1:0 MS SD EBD MD MC MB MA

SEN—Stack Extension Enable BRT—Bus Release Timing SD—Stop Delay

WRP—Extended Stack Wrap Flag TAS—TA Synchronize Select EBD—External Bus Disable

EOV—Extended Stack Overflow Flag BE—Burst Mode Enable MD—Operating Mode D

EUN—Extended Stack Underflow Flag CDP1—Core-DMA Priority 1 MC—Operating Mode C

XYS—Stack Extension Space Select CDP0—Core-DMA Priority 0 MB—Operating Mode B

ATE—Address Tracing Enable MS—Memory Switch Mode MA—Operating Mode A

Reserved bit. Read as zero, should be written with zero for future compatibility.

AA0851

Figure 4-3 DSP56305 Operating Mode Register (OMR)

11 10 9 8 7 6 5 4 3 2 1 0

MF11 MF10 MF9 MF8 MF7 MF6 MF5 MF4 MF3 MF2 MF1 MF0

23 22 21 20 19 18 17 16 15 14 13 12

PD3 PD2 PD1 PD0 COD PEN PSTP XTLD XTLR DF2 DF1 DF0

AA0852

Figure 4-4 PLL Control Register (PCTL)

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Core Configuration

Device Identification Register


4.8.3 XTAL Disable (XTLD)—PCTL Bit 16

The XTAL Disable bit (XTLD) controls the on-chip crystal oscillator XTAL output. The XTLD bit is cleared during DSP56305 hardware reset, which means that the XTAL output signal is active, permitting normal operation of the crystal oscillator.

4.8.4 PreDivider Factor Bits (PD3:0)—PCTL Bits 20–23

The PreDivider Factor bits (PD3:0) define the Predivider Factor (PDF) applied to the PLL input frequency. The PD bits are cleared during DSP56305 hardware reset, which corresponds to a PDF of one.

4.9 DEVICE IDENTIFICATION REGISTER

The Device Identification Register (IDR) is a 24-bit, read-only factory programmed register which identifies DSP56300 family members. It specifies the derivative number and revision number of the device. This information may be used in testing or by software. Figure 4-5 gives the contents of the IDR for the DSP56305 Revision 0.

The IDR for a specific mask can be found on the silicon errata sheet on the Motorola DSP Web page. Revision numbers are assigned as follows: $0 is revision 0, $1 is revision A, $2 is revision B, and so on. The derivative number is $305.

4.10 JTAG IDENTIFICATION (ID) REGISTER

The JTAG Identification (ID) register is a 32-bit, read-only through JTAG, factory programmed register used to distinguish the component on a board according to the IEEE 1149.1 standard. Figure 4-6 shows the JTAG ID register configuration.

Figure 4-5 Identification Register Configuration (DSP56305 Revision 0)

23 16 15 12 11 0

Reserved Revision Number Derivative Number

00000000 0000 001100000101AA1412

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Core Configuration

JTAG Boundary Scan Register (BSR)

The ID register has five parts:

1. Reserved bit 0, which is defined as 1 by the JTAG standard.

2. The manufacturer identity, in bits 11–1, which for Motorola is $E (00000001110).

3. The customer part number, in bits 27–12, which is divided into two parts:

a. The sequence number, in bits 21–12, which for the DSP56305 is $5 (0000000101)

b. The design center number, in bits 27–22, which for MSIL is $6 (000110)

4. The revision number, in bits 28–31, which for the DSP56305 Revision 0 is $0 (0000).

The JTAG ID register value for the DSP56305 Revision 0 is $0180501D.

4.11 JTAG BOUNDARY SCAN REGISTER (BSR)

The Boundary Scan Register (BSR) in the DSP56305 JTAG implementation contains bits for all device signal and clock pins and associated control signals. All DSP56305 bidirectional pins have a corresponding register bit in the BSR for pin data, and are controlled by an associated control bit in the BSR. The BSR is listed in Section 11 . The JTAG code listing is in Appendix C .

Figure 4-6 JTAG Identification Register Configuration (Revision 0)

31 28 27 22 21 12 11 1 0

Revision Number Customer Part Number

Sequence Number

Manufacturer Identity

1

0000 000110 0000000101 00000001110 1

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SECTION 5

GENERAL PURPOSE I/O

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General Purpose I/O

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-35.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3

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General Purpose I/O

Introduction


5.1 INTRODUCTION

The DSP56305 provides forty-two bidirectional signals that can be configured as General Purpose Input/Output (GPIO) signals or as peripheral dedicated signals. No dedicated GPIO signals are provided. All of these signals are GPIO by default after reset. The control register settings of the DSP56305’s peripherals determine whether these signals are used as GPIO or as peripheral dedicated signals. This section describes how signals may be used as GPIO.

5.2 PROGRAMMING MODEL

The Signals Description section (Section 2) of this manual describes the special uses of these signals in detail. There are five groups of these signals. They can be controlled separately or as groups. The groups are:

• Port B: twenty-four GPIO signals (shared with the HI32 signals)

• Port C: six GPIO signals (shared with the ESSI0 signals)

• Port D: six GPIO signals (shared with the ESSI1 signals)

• Port E: three GPIO signals (shared with the SCI signals)

• Timers: three GPIO signals (shared with the Triple Timer signals)

5.2.1 Port B Signals and Registers

Twenty-four Port B signals when not used as HI32 signals can be configured as GPIO signals. The GPIO functionality of Port B is controlled by three registers: DSP Control Register (DCTR), DSP Host Port GPIO Direction register (DIRH), and DSP Host Port GPIO Data register (DATH). These registers are described in Section 6 of this document.

5.2.2 Port C Signals and Registers

Each of the six Port C signals not used as an ESSI0 signal can be configured individually as a GPIO signal. The GPIO functionality of Port C is controlled by three registers: Port C Control Register (PCRC), Port C Direction Register (PRRC), and Port C Data Register (PDRC). These registers are described in Section 7 of this document.

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General Purpose I/O

Programming Model

5.2.3 Port D Signals and Registers

Each of the six Port D signals not used as a ESSI1 signal can be configured individually as a GPIO signal. The GPIO functionality of Port D is controlled by three registers: Port D Control Register (PCRD), Port D Direction Register (PRRD) and Port D Data Register (PDRD). These registers are described in Section 7 of this document.

5.2.4 Port E Signals and Registers

Each of the three Port E signals not used as a SCI signal can be configured individually as a GPIO signal. The GPIO functionality of Port E is controlled by three registers: Port E Control Register (PCRE), Port E Direction Register (PRRE) and Port E Data Register (PDRE). These registers are described in Section 8 of this document.

5.2.5 Triple Timer Signals

Each of the three Triple Timer Interface signals (TIO0–TIO2) not used as a timer signal can be configured individually as a GPIO signal. Each signal is controlled by the appropriate Timer Control Status register (TCSR0–TCSR2). These registers are described in Section 9 of this document.

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HOST INTERFACE (HI32)


SECTION 6


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Introduction to the Host Interface (HI32)


6.1 INTRODUCTION TO THE HOST INTERFACE (HI32)

The Host Interface (HI32) provides a fast parallel host port up to 32 bits wide that can be connected directly to the data bus of the host processor. It supports a variety of standard buses, and provides glueless connection with a number of industry standard microcomputers, microprocessors, DSPs, and DMA controllers.

The host bus can operate asynchronously to the DSP core clock, so the HI32 registers are divided into two banks. The Host side register bank is accessible to the external host, and the DSP side register bank is accessible to the DSP56300 core. Figure is a block diagram showing the registers in the HI32.

The HI32 supports three classes of interfaces:

• Peripheral Component Interconnect (PCI) bus (PCI Specification Revision 2.1)

• Universal Bus (UB)

• General Purpose I/O (GPIO) port

In the PCI mode, the HI32 is a dedicated, bidirectional, target (slave)/initiator (master) parallel port, with a 32-bit wide data path up to eight words deep. In this mode, the HI32 may be connected directly to the PCI bus.

In the Universal Bus (UB) modes, the HI32 is a dedicated, bidirectional, slave-only parallel port, with a data path up to 24 bits wide and six words deep. In this mode, the HI32 may be connected directly to 8-bit data buses, 16-bit data buses (e.g. ISA/EISA or Micro Channel), and 24-bit data buses (e.g. the DSP56300 core based DSP Port A bus).

In the General Purpose I/O (GPIO) mode, 24 of the HI32 signals may be programmed as GPIO signals.

Host port signal functionality and polarity are controlled by the DSP56300 core programming the DSP Control Register (DCTR).

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HI32 Features

6.2 HI32 FEATURES

The DSP56305 host interface features are discussed below as they apply to the Core Interface, the Host Interface, the PCI mode, and the UB mode.

6.2.1 Interface - DSP56300 Core Side

• Mapping — 11 internal I/O data space memory locations

• Word Sizes— 24-bit (DSP56305 native) data words— 16-bit— 8-bit

• Data Format Conversions

– PCI Mode

• Output data alignment of 16-bit words to 32-bit words


– left aligned and zero filled

– right aligned and zero extended

– right aligned and sign extended

• Input data alignment of 32-bit words to 24-bit words

– three most significant bytes

– three least significant bytes

• True 32-bit word input and output data transfers

– 32-bit PCI bus data to two DSP56300 core 16-bit words, and vice versa

– UB Mode


– two most significant bytes

– two least significant bytes

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HI32 Features


– UB Mode (cont.)

• Input data alignment of 16-bit words to 24-bit words




• Data Buffers: FIFOs up to eight words deep, on both transmit and receive data paths

• Handshaking Protocols

– Software polled

– Interrupt driven (fast or long)

– Direct Memory Access (up to four DSP56300 core DMA channels)

• GPIO

– 24 I/O signals (data and signal direction are programmable)

• Self Configuration

– DSP56300 core can indirectly access the CCMR, CLAT, and CBMA HI32 configuration registers

• Instructions

– Memory mapped registers allow standard MOVE instruction for data transfer between DSP56305 and external hosts

– Special MOVEP instruction provides for I/O service capability using fast interrupts, and provides faster execution with fewer instruction words

– Bit addressing instructions (e.g., BCHG, BCLR, BSET, BTST, JCLR, JSCLR, JSET, JSSET) simplify I/O service routines.

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HI32 Features

6.2.2 Interface - Host Side

• Mapping

– PCI Mode

• Memory Space — 16 K 32-bit wide locations

– 3 32-bit read/write registers (control, status, and host command)

– 16377 32-bit read/write locations corresponding toone 32-bit input data FIFOone 32-bit output data FIFO

– 4 32-bit reserved locations (read-only)

• Configuration Space — 64 32-bit locations

– Universal Bus Mode: 8 locations up to 24-bits wide (of which 4 locations are reserved)

• Address Decoding

– PCI Mode — 32 bit internal address decoding

– Universal Bus Mode — 11 bit (12 with HAEN) internal address decoding

• Word Size — 8–, 16–, 24–, or 32–bits

• Data Buffers: FIFOs six or eight words deep, on transmit and receive data paths, five deep in Universal Bus Mode (UBM)

• Data Fetch Types in HI32 (slave) to Host Data Transfers

– Fetch

– Pre-fetch

• Semaphores: flags supplied for HI32 allocation in a multi-host system

• Handshaking Protocols

– PCI Mode Handshaking Protocols

• Software Polled

• PCI Interrupt (HINTA signal)

• Data Acknowledge (HTRDY and HIRDY signals)

• Bus Arbitration (HREQ and HGNT signals)

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HI32 Features


– Universal Bus Mode Handshaking Protocols

• Software Polled

• Interrupt Driven - Data Request (HIRQ signal) and Interrupt A (HINTA signal)

• Data Acknowledge (HTA signal)

• Direct Memory Access (External DMA - HDRQ and HDAK signals)

6.2.3 HI32 Features in PCI Mode

• Operates as an initiator (master) or target (slave)

• Up to 33 Mword/sec zero-wait-state data transfers (with a 33MHz PCI clock and a DSP clock frequency of 66MHz or more)

• Supports words of 8–,16–, 24–, and 32–bits (as defined by the HBE[3:0] lines)

• Supports output data alignment of 24-bit words to 32-bit words




• Supports input data transfer of 32-bit words to 24-bit words

– three most significant bytes

– three least significant bytes

• Supports true 32-bit input and output data transfers (32-bit PCI bus data to two DSP56300 core 16-bit words, and vice versa)

• Supports bursts of up to 16384 32-bit words when accessed as a memory space mapped target

• Generates bursts of up to 64 32-bit words or unlimited length (as master)

• Supports high speed (fast peripheral) DSP56300 core DMA transfers (two core clock cycles per DMA transfer)

• Supports memory-space and configuration transactions as a target

• Supports memory-space, I/O-space and configuration transactions as an initiator

• Supports exclusive (locked) accesses

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HI32 Features

• Supports a self configuration mode, for initialization of the configuration registers in a system without an external system configurator

• Supports software driven PCI Interrupt Requests (Interrupt A).

• Generates vectored DSP56300 core interrupts — separately for receive, transmit, transaction termination, error events and host commands

• Supports both 3.3 V and 5 V PCI signaling environments

• Supports address insertion in the data written to the HI32 by the host

• Supports parity generation, detection and reporting

• Supports system error generation and reporting

• Supports PCI Plug and Play

6.2.4 HI32 Features in Universal Bus Modes

• Operates as a slave in many standard bus environments (e.g. ISA bus or DSP56300 core based DSP Port A bus)

• Transfers data at three clock cycles per transfer (i.e. 22 Mword/sec for a 66 MHz DSP clock), when operating synchronously with a DSP56300 core–based DSP host (two wait states per access)

• Supports high speed (fast peripheral) DSP56300 core DMA transfers (two core clock cycles per DMA transfer)

• Supports words of 8,16, and 24 bits

• Supports output data alignment of 24-bit words to 16-bit words (two most significant bytes, two least significant bytes)

• Supports input data alignment of 16-bit words to 24-bit words (left aligned and zero filled, right aligned and zero extended, right aligned and sign extended)

• Supports an external data buffer for drive and voltage level compatibility with the external bus (e.g. ISA bus)

• Generates interrupt requests: hardware driven (HIRQ) and software driven (HINTA)

• Generates vectored DSP56300 core interrupts separately for receive and transmit events and host commands

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HI32 Resets


6.3 HI32 RESETS

The following table lists and describes the resets available in the HI32.

Table 6-1 HI32 Resets

Type Initiated when Description

Init

iate

d b

y th

e D

SP56

300

core

Hardware Reset

HS The DSP56300 core RESET signal is asserted.

These resets force the HI32 DSP side state machines, control and status registers to their initial states.

These resets also activate the Personal Software (PS) reset (see below).

Software Reset

The RESET instruction is executed.

Personal Software Reset

PS The DSP56300 core writes zeros to the HI32 mode bits HM[2:0] in the DSP Control Register or the HS reset is executed

The HI32 terminates the current PCI transaction (if it is an active PCI agent), clears the HACT bit in the DSP Status Register (DSR) and enters the personal software (PS) reset state. All data paths are cleared, as are some status register bits.

In the personal software reset state, the HI32 is a PCI agent and will respond to all memory space transactions with a retry event. If connected to other buses (e.g., the ISA bus, DSP56300 core based DSP Port A bus, etc.) all outputs are high impedance.

STOP Reset

ST The STOP instruction is executed.

This reset forces all host port signals to the disconnected state: all outputs are high impedance, all inputs are electrically disconnected.

The host port signals are affected immediately.

Note: This reset may be executed only when the HACT bit in the DSP Status Register (DSR) is zero.

Init

iate

d b

y th

e H

ost

Personal Hardware Reset

PH The HI32 HRST/HRST signal is asserted.

This reset forces the HI32 host side state machines, control registers, FIFOs, and configuration registers to their initial states. All host port signals, except HRST/HRST, are forced to the disconnected state: all outputs are high impedance, inputs are electrically disconnected. The DSP side state machines are not affected.

The HRST/HRST signal is ignored in the self configuration mode.

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HI32 Block Diagram

6.4 HI32 BLOCK DIAGRAM

Figure is a block diagram showing the HI32 registers. They are divided into two banks, DSP side and Host side.The DSP side registers can be accessed by the DSP56300 core. They are listed in Table 6-2. Host side registers, accessed by the host bus, are listed in Table 6-11.

Figure 6-1 HI32 Block Diagram

24

DSP DMA Data Bus

DSP Global Data Bus

HOST Bus

32 32

24 24

DPCR

24

DPMC

24

DPAR

24

DCTR

24 24 24 24 24 24

CDID

CCMR

CVID

CSTR

CCCR CRID

CBMA

32 323232

HCTRHCVR

DSR DTXM DTXS

PCI Configuration Space

DPSR

CHTY CLAT

HSTR HTXR HRXS

data transfer format converter

24

DRXR

HRXM

24 24

6 w

ords

dee

p

8 w

ords

dee

p

6 w

ords

dee

p

24 24

DATHDIRH

24

CILP

Note: Five words in UBM

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DSP SIDE Programming Model


6.5 DSP SIDE PROGRAMMING MODEL

The DSP56300 core views the HI32 as a memory-mapped peripheral occupying 11 24-bit words in data memory space. The HI32 DSP side programming model is shown in Table 6-2.

Table 6-2 HI32 Programming Model - DSP Side Registers

The separate host-to-DSP and DSP-to-host data paths FIFOs allow the HI32 and the host processor to transfer data efficiently at high speeds.

Memory mapping allows DSP56300 core data transfers with the HI32 registers using standard instructions and addressing modes. In addition, the MOVEP instruction allows HI32-to-memory and memory-to-HI32 data transfers without going through an intermediate register.

The on-chip general purpose DMA channels in the DSP56300 core can be programmed to transfer data between the HI32 data FIFOs and other DMA accessible resources at maximum throughput, without DSP56300 core intervention.

The DSP56300 core accesses the HI32 using standard polling, interrupt, or DMA techniques. The following paragraphs describe the purpose and operation of each bit in each register of the HI32 visible to the DSP56300 core. The effects of different reset types on these registers are shown.

The HI32 host side programming model is described in Section 6.6.

Address (HI32 via programmed base

address)

Register Acronym Register Name Register Type

$5 DCTR DSP Control Register Internal I/O space registers$6 DPCR DSP PCI Control Register

$7 DPMC DSP PCI Master Control Register

$8 DPAR DSP PCI Address Register

$9 DSR DSP Status Register

$A DPSR DSP PCI Status Register

$B DTXM DSP Master Transmit Data FIFO

$C DRXR DSP Receive Data FIFO

$D DTXS DSP Slave Transmit Data FIFO

$E DIRH DSP GPIO Direction Register GPIO registers

$F DATH DSP GPIO Data Register

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6.5.1 DSP Control Register (DCTR)

The DCTR is a 24-bit read/write control register used by the DSP56300 core to control the HI32 interrupts, flags, and the host port signal functionality. The DCTR cannot be accessed by the host processor. All reserved bits are read as zeros and should be programmed as zeros for future compatibility. The bit manipulation instructions are useful for accessing individual bits in the DCTR. The DCTR bits are described in the following paragraphs.

Table 6-3 DSP Control Register (DCTR)

11 10 9 8 7 6 5 4 3 2 1 0

HINT HF5 HF4 HF3 SRIE STIE HCIE

23 22 21 20 19 18 17 16 15 14 13 12

HM2 HM1 HM0 HIRD HIRH HRSP HDRP HTAP HRWP HDSM

* - Reserved, read as zero and should be written with zero.

Bit Name Function

0 HCIE Host Command Interrupt Enable

1 STIE Slave Transmit Interrupt Enable

2 SRIE Slave Receive Interrupt Enable

3-5 HF[5:3] Host Flags

6 HINT Host Interrupt A

13 HDSM Host Data Strobe Mode

14 HRWP Host RD/WR Polarity

15 HTAP Host Transfer Acknowledge Polarity

16 HDRP Host DMA Request Polarity

17 HRSP Host Reset Polarity

18 HIRH Host Interrupt Request Handshake Mode

19 HIRD Host Interrupt Request Drive Control

20-22 HM[2:0] HI32 Mode

23,12-7 reserved

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6.5.1.1 Host Command Interrupt Enable (HCIE) Bit 0Setting the HCIE bit enables a vectored DSP56300 core interrupt request if the host command pending (HCP) status bit in the DSR is set. If HCIE is cleared, HCP interrupt requests are disabled. The starting address of this interrupt is determined by the host vector HV[6:0] in the host command vector register (HCVR).

If the host non-maskable interrupt (HNMI) bit is set in the host command vector register (HCVR), HCIE is ignored, and an interrupt is generated if HCP is set regardless of HCIE.

Hardware and software resets clear HCIE.

6.5.1.2 Slave Transmit Interrupt Enable (STIE) Bit 1The STIE bit, when set, enables an DSP56300 core interrupt request when the slave transmit data request (STRQ) status bit in the DSR is set. If STIE is cleared, STRQ interrupt requests are disabled.

Hardware and software resets clear STIE.

6.5.1.3 Slave Receive Interrupt Enable (SRIE) Bit 2The SRIE bit, when set, enables a DSP56300 core interrupt request when the slave receive data request (SRRQ) status bit in the DSR is set. If SRIE is cleared, SRRQ interrupt requests are disabled.

Hardware and software resets clear SRIE.

6.5.1.4 Host Flags (HF[5:3]) Bits 5-3The Host Flag (HF[5:3]) bits are used as general purpose flags for DSP-to-host communication. HF[5:3] may be set or cleared by the DSP56300 core. HF[5:3] are visible to the external host in the HSTR.

Hardware and software resets clear host flags.

Note: There are six host flags: three used by the host to signal the DSP56300 core (HF[2:0]) and three used by the DSP56300 core to signal the host processor (HF[5:3]). These are general purpose flags. The host flags do not cause interrupts; they must be polled to see if they have changed. These flags can be used individually or as encoded triads.

6.5.1.5 Host Interrupt A (HINT) Bit 6The HINT bit controls the HINTA signal. When HINT is set by the DSP56300 core, the HINTA signal is driven low. When HINT is cleared by the DSP56300 core, the HINTA signal is released.

Hardware and software resets clear HINT.

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6.5.1.6 Host Data Strobe Mode (HDSM) Bit 13The HDSM bit controls the data strobe mode of the host port signals when in a Universal Bus mode (HM[2:0] is 010 or 011). If HDSM is cleared, the double-strobe signal mode is selected: HWR/HRW signal (HP29) functions as host write strobe HWR and HRD/HDS (HP30) functions as host read strobe HRD. If HDSM is set, the single-strobe signal mode is selected: HWR/HRW signal functions as host read/write HRW and HRD/HDS functions as host data strobe HDS.

The value of HDSM may be changed only when HACT (DSR Bit 23) is cleared.

HDSM is ignored when not in a Universal Bus mode (HM[2:0] is 010 or 011).

Hardware and software resets clear HDSM.

6.5.1.7 Host Read/Write Polarity (HRWP) Bit 14The HRWP bit controls the polarity of HWR/HRW signal, when in single-strobe Universal Bus modes (HM[2:0] is 010 or 011 and HDSM = 1), that is, when HWR/HRW signal (HP29) functions as the host read/write (HRW) signal.

If HRWP is cleared, the host-to-DSP data transfer direction corresponds to low level of HRW signal, and DSP-to-host data transfer direction corresponds to high level of HRW signal.

If HRWP is set, the host-to-DSP data transfer direction corresponds to high level of HRW signal, and DSP-to-host data transfer direction corresponds to low level of HRW signal.

The value of HRWP may be changed only when HACT = 0.

HRWP is ignored when not in a Universal Bus mode or double-strobe host port mode is selected (HM ≠ $2 or $3, or HDSM = 0).

Hardware and software resets clear HRWP.

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6.5.1.8 Host Transfer Acknowledge Polarity (HTAP) Bit 15The HTAP bit controls the polarity of the HTA signal when the HI32 is in a Universal Bus mode (HM = $2 or $3). If HTAP is cleared, the HTA signal is active high and the HI32 will request to extend the access by driving the HTA signal low (i.e. deasserted). If HTAP is set, the HTA signal is active low and the HI32 will request to extend the access by driving the HTA signal high (i.e. deasserted).

Note: HTA is driven in the Universal Bus modes (HM = $2 or $3) while the HI32 is being accessed by an external host. If the HI32 is not being accessed, the HTA signal is high impedance.

The value of HTAP may be changed only when HACT = 0.

HTAP is ignored when not in a Universal Bus mode (HM ≠ $2 or $3).

Hardware and software resets clear HTAP.

6.5.1.9 Host DMA Request Polarity (HDRP) Bit 16The HDRP bit controls the polarity of the HDRQ signal when the HI32 is in a Universal Bus mode (HM = $2 or $3). If HDRP is cleared, the HDRQ signal is active high and the HI32 will request DMA service by driving the HDRQ signal high (i.e. asserted). If HDRP is set, the HDRQ signal is active low and the HI32 will request DMA service by driving the HDRQ signal low (i.e. asserted).

The value of HDRP may be changed only when HACT = 0.

HDRP is ignored when not in a Universal Bus mode (HM ≠ $2 or $3).

Hardware and software resets clear HDRP.

6.5.1.10 Host Reset Polarity (HRSP) Bit 17The HRSP bit controls the polarity of the HRST signal when the HI32 is in a Universal Bus or the GPIO mode (HM = $2, $3 or $4). If HRSP is cleared, the HRST signal is active high and the HI32 will be reset if the HRST signal is high (i.e. asserted). If HRSP is set, the HRST signal is active low and the HI32 will be reset if HRST signal is low (i.e. asserted).

The value of HRSP may be changed only when HACT = 0.

HRSP is ignored in the PCI mode (HM = $1).

Hardware and software resets clear HRSP.

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6.5.1.11 Host Interrupt Request Handshake Mode(HIRH) Bit 18The HIRH bit controls the handshake mode of the HIRQ signal when the HI32 is in a Universal Bus mode (HM = $2 or $3). HIRQ is asserted by the HI32 when a host interrupt request (receive and/or transmit) is generated in the HI32. With HIRH cleared, when a host interrupt request is generated, HIRQ is asserted for the number of DSP56300 core clock cycles specified by the LT7-LT0 bits in the CLAT and then deasserted. The duration of the HIRQ pulse is given by the following equation:

HIRQ_PULSE_WIDTH = (LT[7:0]_Value + 1) • DSP56300_Core_clock_cycle

If HIRH is set: HIRQ is deasserted when the interrupt request source is cleared (by the corresponding host data access), masked (by TREQ = 0 or RREQ = 0) or disabled by the DMA enable bit (DMAE) in the HCTR.

The value of HIRH may be changed only when HACT = 0.

HIRH is ignored when not in a Universal Bus mode (HM ≠ $2 or $3).

Hardware and software resets clear HIRH.

6.5.1.12 Host Interrupt Request Drive Control (HIRD) Bit 19The HIRD bit controls the output drive of HIRQ signal when the HI32 is in a Universal Bus mode (HM = $2 or $3). With HIRD cleared, the HIRQ signal is an open drain output (i.e. driven low when asserted, released (high impedance) when deasserted). With HIRD set, the HIRQ signal is always driven.

The value of HIRD may be changed only when HACT = 0.

HIRD is ignored when not in a Universal Bus mode (HM ≠ $2 or $3).

Hardware and software resets clear HIRD.

Note: Each of the bits HDSM, HRWP, HTAP, HDRP, HRSP, HIRH, and HIRD affect the host port signals directly. To assure proper operation, these signals may be changed only when HACT = 0. The HM2-HM0 bits must not be changed together with these bits (i.e. in the same core write).

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6.5.1.13 HI32 Mode (HM2-HM0) Bits 22-20The HM bits control the operation modes and signal functionality of the HI32 (see Table 6-4). The host port signals in the different modes are shown in Table 6-5.

Table 6-4 HI32 Modes

6.5.1.13.1 Terminate and Reset (HM[2:0] = 000) If the HI32 was in the PCI mode (HM[2:0] = 001), as an active PCI master: the HI32 generates a master initiated termination; if a selected target in a memory space transaction, the HI32 generates a target-disconnect-C/retry event, thus completing the PCI transaction. When the PCI idle state is subsequently detected, the HI32 clears HACT in the DSR and enters the personal software (PS) reset state. In the personal software reset state all data paths are cleared, and the HI32 will respond to all memory space transactions with a retry event.

If the HI32 was not an active target in the PCI mode (HM[2:0]≠001) memory space transaction, the HI32 immediately clears HACT in the DSR and enters the personal software (PS) reset state.

Configuration space transactions are affected by clearing the HM bits. CSID must be loaded, due to self configuration mode before the host can configure the DSP56305.

In the personal software reset the HI32 consumes very little current. This is a low-power state. For even greater power saving, the HI32 may be programmed to the GPIO mode.

HM[2:0] HI32 Mode

000 Terminate and Reset

001 PCI

010 Universal Bus

011 Enhanced Universal Bus

100 GPIO

101 Self Configuration

110 reserved

111 reserved

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6.5.1.13.2 PCI Mode (HM = $1)The HI32 supports:

• Glueless connection to the standard PCI bus.

• Operation as an initiator (master) or target (slave).

• 24- to 32-bit, 32- to 24-bit data formatting and true 32-bit (Dword) data transfers.

• Memory-space and configuration transactions as a target.

• Memory-space, I/O-space and configuration transactions as an initiator.

6.5.1.13.3 Universal Bus Mode (HM = $2)The HI32 supports:

• Slave-only glueless connection to various external buses (e.g. ISA/EISA, DSP56300 core based DSP Port A bus).

• 24-, 16- (with data alignment), and 8-bit buses.

• ISA/EISA bus DMA-type accesses.

• Pins HP22-HP20 are general purpose I/O.

• HP19, HP31 and HP32 are unused and must be forced or pulled up to Vcc.

• When operating with a host bus less than 24 bits wide, the data signals that are not used for transferring data must be forced or pulled up or down to Vcc or to GND respectively. For example: when operating with a 16-bit bus (e.g. ISA bus), HP48-HP41 must be forced or pulled up to Vcc or pulled down to GND.

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6.5.1.13.4 Enhanced Universal Bus Mode (HM = $3):The HI32 supports:

• Slave-only glueless connection to various external buses (e.g. ISA/EISA, DSP56300 core based DSP Port A bus).

• 24-, 16- (with data alignment), and 8-bit buses.

• ISA/EISA bus DMA-type accesses.

• Output of two control signals (data direction and data output enable) to an optional external data buffer.

• Host select acknowledge output.

• HP19, HP31 and HP32 are unused and must be forced or pulled up to Vcc.


6.5.1.13.5 GPIO Mode (HM = $4):The HI32 supports:

• General purpose I/O (GPIO) port.

• Pins HP23-HP0 are GPIO.

• Pins HP48-HP33, HP30-24 are disconnected.

• HP31 and HP32 are unused and must be forced or pulled up to Vcc.

• Minimum current consumption.

6.5.1.13.6 Self Configuration Mode (HM = $5):The HI32 supports:

• Indirect DSP56300 core access to the CCMR, CLAT and CBMA HI32 configuration registers.

• All the host port signals are in the disconnected state.

The value of the HM bits may be changed to a non zero value by the DSP56300 core only when the HI32 is in the personal software reset state (HM = $0, HACT = 0), they must not be changed together (i.e. in the same core write) with any of the following bits: HDSM, HRWP, HTAP, HDRP, HRSP, HIRH, or HIRD.

The combinations HM = $6, HM = $7 are reserved for future expansion and should not be used.

Hardware and software resets clear the HM bits.

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6.5.1.14 DCTR Reserved Control Bits 23, 12-7These bits are reserved for future expansion, they are read as zeros and should be written with zeros for upward compatibility.

Table 6-5 Host Port Signal Functionality

HI32 Port Pin

PCI Bus Mode

Universal Bus Mode a

a. When operating with a host bus less than 24 bits wide, the data signals that are not used for transferring data must be forced or pulled to Vcc or to GND.

GPIO ModeEnhanced Universal

Bus Mode Universal Bus Mode

HM = $1 HM = $3 HM = $2 HM = $4

7-0 HAD15-HAD0 HA10-HA3 7-0

15-8 HD7-HD0 15-8

19-16 HC3/HBE3-HC0/HBE0

HA2-HA0 HIO18-16

UNUSEDb

b. Must be forced or pulled to Vcc or GND.

HIO19

20 HTRDY HDBEN 20

21 HIRDY H DBDR 21

22 HDEVSEL HSAK 22

23 HLOCK HBS c

c. HBS/HDAK should be forced or pulled up to Vcc if not used.

HIO23

24 HPAR HDAK c disconnected

25 HPERR HDRQ

26 HGNT HAEN

27 HREQ HTA

28 HSERR HIRQ

29 HSTOP HWR/HRW

30 HIDSEL HRD/HDS

31 HFRAME UNUSEDd

d. Must be forced or pulled up to Vcc.

32 HCLK UNUSEDd

40-33 HAD23-HAD16 HD15-8 disconnected

48-41 HAD31-HAD24 HD23-16Output is high impedance if HRFπ$0.

Input is disconnected if HTFπ$0.

49 HRST HRST

50 HINTA

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6.5.2 DSP PCI Control Register (DPCR)

The DPCR is a 24-bit read/write control register used by the DSP56300 core to control the HI32 PCI interrupts, and interface logic. The DPCR cannot be accessed by the host processor. All reserved bits are read as zeros and should be programmed as zeros for future compatibility. The bit manipulation instructions are useful for accessing individual bits in the DPCR. The DPCR bits are described in the following paragraphs.

Table 6-6 DSP PCI Control Register (DPCR)

11 10 9 8 7 6 5 4 3 2 1 0

TTIE TAIE PEIE MAIE MRIE MTIE

23 22 21 20 19 18 17 16 15 14 13 12

IAE RBLE MWSD MACE SERF MTT CLRT TCIE

* - Reserved, read as zero and should be written with zero.

Bit Name Function

1 MTIE Master Transmit Interrupt Enable

2 MRIE Master Receive Interrupt Enable

4 MAIE Master Address Interrupt Enable

5 PEIE Parity Error Interrupt Enable

7 TAIE Transaction Abort Interrupt Enable

9 TTIE Transaction Termination Interrupt Enable

12 TCIE Transfer Complete Interrupt Enable

14 CLRT Clear Transmitter

15 MTT Master Transfer Terminate

16 SERF HSERR Force

18 MACE Master Access Counter Enable

19 MWSD Master Wait State Disable

20 RBLE Receive Buffer Lock Enable

21 IAE Insert Address Enable

23-22,17,13,11-10,8,6,3,0

reserved

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6.5.2.1 Master Transmit Interrupt Enable (MTIE) Bit 1The MTIE bit is used to enable a DSP56300 core interrupt request when the master transmit data request (MTRQ) status bit in the DPSR is set. If MTIE is cleared, MTRQ interrupt requests are disabled. If MTIE is set a master transmit data interrupt request will be generated if MTRQ is set.

Hardware and software resets clear MTIE.

6.5.2.2 Master Receive Interrupt Enable (MRIE) Bit 2The MRIE bit is used to enable a DSP56300 core interrupt request when the master receive data request (MRRQ) status bit in the DSP status register (DPSR) is set. If MRIE is cleared, master receive data interrupt requests are disabled. If MRIE is set, a master receive data interrupt request will be generated if MRRQ is set.

Hardware and software resets clear MRIE.

6.5.2.3 Master Address Interrupt Enable (MAIE) Bit 4The MAIE bit is used to enable a DSP56300 core interrupt request when the HI32 is currently not the PCI transaction initiator, when in the PCI mode (HM=$1). If MAIE is cleared, master address interrupt requests are disabled. If MAIE is set, a master address interrupt request will be generated if the master address request (MARQ) status bit in the DPSR register is set.

Hardware and software resets clear MAIE.

6.5.2.4 Parity Error Interrupt Enable (PEIE) Bit 5The PEIE bit is used to enable a DSP56300 core interrupt request when a parity error is detected, when in the PCI mode (HM=$1). If PEIE is cleared, parity error interrupt requests are disabled. If PEIE is set, a parity error interrupt request will be generated if a parity error (address or data) is detected and the address parity error (APER) status bit or the data parity error (DPER) status bit in the DPSR register is set.

Hardware and software resets clear PEIE.

6.5.2.5 Transaction Abort Interrupt Enable (TAIE) Bit 7The TAIE bit is used to enable a DSP56300 core interrupt request when in the PCI mode (HM=$1) and the HI32, as a PCI master, has executed a master-abort termination, or received a target initiated target-abort termination. If TAIE is cleared, transaction abort interrupt requests are disabled. If TAIE is set, a transaction abort interrupt request will be generated if a transaction was terminated due to master-abort (MAB is set in the DPSR) or target-abort (TAB is set).

Hardware and software resets clear TAIE.

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6.5.2.6 Transaction Termination Interrupt Enable (TTIE) Bit 9The TTIE bit is used to enable a DSP56300 core interrupt request when in the PCI mode (HM=$1) and the HI32, as a PCI master, has executed a time-out termination, or a target initiated disconnect or retry termination. If TTIE is cleared, transaction termination interrupt requests are disabled. If TTIE is set, a transaction termination interrupt request will be generated if a transaction was terminated due to a disconnect (TDIS is set in the DPSR), retry (TRTY is set) or time-out (TO is set). This bit is used for non-fatal transaction terminations (i. e., not an abort or priority error).

Hardware and software resets clear TTIE.

6.5.2.7 Transfer Complete Interrupt Enable (TCIE) Bit 12The TCIE bit is used to enable a DSP56300 core interrupt request when in the PCI mode (HM = $1) and the host data transfer complete (HDTC) status bit in the DSP PCI status register (DPSR) is set. If TCIE is cleared, transfer complete interrupt requests are disabled. If TCIE is set, a transfer complete interrupt request will be generated if HDTC is set.

Hardware and software resets clear TCIE.

6.5.2.8 Clear Transmitter (CLRT) Bit 14The CLRT bit is used to clear the HI32 master-to-host bus data path in the PCI mode (HM = $1). This bit is used after a transaction is ended prematurely.When CLRT is set by the DSP56300 core, the HI32 hardware clears the master DSP-to-host bus data path (i.e. the DTXM-HRXM FIFO is forced empty) - thus setting the PCI Master Transmit Data Request bit (MTRQ) in the DPSR, and then clears CLRT. CLRT cannot be written zero by the DSP56300 core.

To assure operation, CLRT may be set by the DSP56300 core, only if

• MARQ is set in the DPSR (i.e. the DSP56300 core is not currently performing a PCI transaction); and

• No DSP56300 core DMA channel is enabled to service HI32 master transmit data DMA requests.

CLRT is ignored when the HI32 is not in the PCI mode (HM≠$1).

Hardware and software resets clear CLRT.

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6.5.2.9 Master Transaction Termination (MTT) Bit 15The MTT bit is used for the generation of a PCI master initiated transaction termination. When the HI32, in the PCI mode (HM=$1), is the active PCI master, if MTT is set, by the DSP56300 core, a master initiated transaction termination (not master-abort) is generated. MTT is cleared by the HI32 hardware when the PCI bus is in the idle state. MTT cannot be written zero by the DSP56300 core. This bit is used to end an unlimited length burst.

MTT is ignored when the HI32 is not in the PCI mode (HM≠$1).

Hardware and software resets clear MTT.

6.5.2.10 System Error Force (SERF) Bit 16The SERF bit controls HSERR signal state in the PCI mode (HM=$1). When SERF is set by the DSP56300 core and the HI32 is the current PCI bus master or a selected target, the HSERR signal is pulsed one PCI clock cycle, if the system error enable (SERE) bit is set in the status/command configuration register (CSTR/CCMR); the signalled system error (SSE) bit is set in the CSTR/CCMR. SERF is cleared by the HI32 hardware after HSERR is asserted. If SERF is cleared, the HSERR signal is controlled by the HI32 hardware (see HSERR signal definition in Table 6-5). SERF cannot be written zero by the DSP56300 core.

SERF is ignored when the SERE bit is cleared or when the HI32 is not an active PCI agent (i.e. HM≠$1 or the HI32 is not the current PCI bus master or a selected target).

Hardware and software resets clear SERF.

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6.5.2.11 Master Access Counter Enable (MACE) Bit 18The MACE bit is used to enable the master access counter.

If MACE is set, the master access counter is enabled and the HI32 as the active PCI master (HM=$1) will terminate the current PCI transaction when the burst length counter reaches the terminal count. This is called a limited length burst. The initial value is loaded from the Burst Length bits (Bl[5:0]).

If MACE is cleared, the counter is disabled, and the burst length of transactions initiated by the HI32 are unlimited.

The DSP56300 core can terminate a transaction initiated by the HI32 by writing one to the MTT bit in the DPCR.

MACE is ignored when the HI32 is not in the PCI mode (HM≠$1).

The value of MACE may be changed only if MARQ = 1, or HACT = 0.

Hardware and software resets clear MACE.

6.5.2.12 Master Wait State Disable (MWSD) Bit 19The MWSD bit is used to disable PCI wait states (inserted by negating HIRDY), during a data phase.

If MWSD is cleared, the HI32 as the active PCI master (HM=$1) will insert wait states to extend the current data phase if it cannot guarantee the completion of the next data phase. This is a consequence of the PCI requirement that the Initiator Ready (HINTA) signal be asserted by the master at the end of every data phase.The HI32 will assert HIRDY and complete the current data phase if:

• it can complete the next data phase, or

• it has determined to terminate the transaction due to time-out or completion.

If MWSD is set, the HI32, as the active PCI master (HM=$1) will not insert wait states. If it cannot guarantee the completion of the next data phase, the HI32 will complete the current data phase and terminate the transaction.

MWSD is ignored when the HI32 is not in the PCI mode (HM≠$1).

The value of MWSD may be changed only when HACT = 0.

Hardware and software resets clear MWSD.

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6.5.2.13 Receive Buffer Lock Enable (RBLE) Bit 20The RBLE bit is used, in the PCI mode (HM = $1), to ensure that the host-to-DSP data path contains data from only one external master at any time. This is accomplished by inhibiting the HI32 from responding to new PCI write transactions to the HTXR until the DSP56300 core has read all the data written to the HTXR in the last access.

With RBLE set: After a non-exclusive write transaction to the HTXR, or upon HLOCK negation after completion of an exclusive write access to the HTXR; or after the completion of a read transaction initiated by the HI32:

– Forthcoming PCI write accesses to the HTXR will be disconnected (retry or disconnect-C) until the DSP56300 core writes one to the host data transfer complete (HDTC) bit in the DPSR.

– If the host-to-DSP data path is empty (SRRQ = 0 and MRRQ = 0), due to DSP56300 core reads from the DRXR, the HDTC bit will be set. The HI32 will disconnect (retry or disconnect-C) all PCI write accesses to the HTXR until the DSP56300 core writes one to the HDTC bit to clear it.

If RBLE is cleared the HI32 will not set the HDTC bit.

If the HDTC bit is cleared the HI32 will respond to write PCI transactions according to the status of the host-to-DSP data path.

RBLE is ignored when the HI32 is not in the PCI mode (HM≠$1).

The value of RBLE may be changed only when HACT = 0 or HDTC = 1.

Hardware and software resets clear RBLE.

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6.5.2.14 Insert Address Enable (IAE) Bit 21The IAE bit is used, in the PCI mode (HM = $1), to insert the PCI transaction address at the head of the incoming data stream from the host in accordance with the value of the host data transfer format (HTF) bits in the HCTR.

If the HI32 is being accessed in a write transaction, and if IAE is set, the HI32 writes the PCI transaction address to the HTXR before the data written by the host.

If HTF = $0 (32-bit mode): first, the two least significant bytes of the PCI transaction address are written to the two least significant bytes of the HTXR, then the two most significant bytes of the PCI transaction address (the address is inserted as $00HHHH, $00LLLL, where HHHH = HAD[31:16] and LLLL = HAD[15:0]).

If HTF≠$0: only the two least significant bytes of the PCI transaction address are written to the two least significant bytes of the HTXR (the address is inserted as $00LLLL, where LLLL = HAD[15:0]).

The incoming data is written to the HTXR after the address.

IAE is ignored when the HI32 is not in the PCI mode (HM≠$1).

The value of IAE may be changed only when HACT = 0 or HDTC = 1.

Hardware and software resets clear IAE.

6.5.2.15 DPCR Reserved Control Bits 23, 22,17,13,11,10, 8, 6, 3, 0These bits are reserved for future expansion, they are read as zeros and should be written with zeros for upward compatibility.

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6.5.3 DSP PCI Master Control Register(DPMC)

The DPMC is a 24-bit read/write register used by the DSP56300 core to generate the two most significant bytes of the 32-bit PCI transaction address, and to control the burst length and the data transfer format. The DPMC cannot be accessed by the host processor.

The DPMC may be written only if MARQ is set or in the Self Configuration mode. (See Section 6.5).

The DPMC bits are described in the following paragraphs.

6.5.3.1 DSP PCI Transaction Address (AR31-AR16) Bits 15-0The AR31-AR16 bits are the two most significant bytes of the 32-bit PCI transaction address. The two least significant bytes of the PCI transaction address are located in the DPAR register (see Section 6.5.4). When the DPAR is written by the DSP56300 core, while in the PCI mode (HM = $1), the PCI ownership is requested and, when granted, the HI32 will initiate a PCI transaction. The full 32-bit address (AR31-AR16 from the DPMC and AR15-AR0 from the DPAR) is driven to the HAD31-HAD0 signals during the PCI address phase.

Hardware and software resets clear AR31-AR16.

Table 6-7 DSP PCI Master Control Register (DPMC)

11 10 9 8 7 6 5 4 3 2 1 0

AR27 AR26 AR25 AR24 AR23 AR22 AR21 AR20 AR19 AR18 AR17 AR16

23 22 21 20 19 18 17 16 15 14 13 12

FC1 FC0 BL5 BL4 BL3 BL2 BL1 BL0 AR31 AR30 AR29 AR28

Bit Name Function

15-0 AR[31:16] DSP PCI Transaction Address (High)

21-16 BL[5:0] PCI Data Burst Length

23-22 FC[1:0] Data Transfer Format Control

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6.5.3.2 DSP PCI Data Burst Length (BL5-BL0) Bits 21-16The BL5-BL0 bits control the PCI data burst length, the value of the BL5-BL0 bits being the desired number of accesses in the burst, minus one. When the DPAR is written by the DSP56300 core, while in the PCI mode (HM=$1), the master access counter is initialized with the value of BL5-BL0. The burst length may be programmed from 1 (BL = $00) to 64 (BL = $3F) accesses.

If the master access counter is enabled (MACE = 1 in the DPCR) and the HI32 is the active PCI master, the value of the counter is decremented after each data cycle in which data is transferred (i.e. a data phase), until a value of $00 is reached. When the counter value reaches $00, the HI32 PCI master will execute one more data phase and terminate the transaction. A transaction may be terminated before the counter reaches $00 (e.g. a target initiated transaction termination, or the bus grant was taken, or the DSP56300 core wrote one to MTT). Note that the burst length (BL) is not changed. The value of the counter at the end of a transaction is indicated by the RDC5-RDC0 bits in the DSP PCI status register (DPSR).

Hardware and software resets clear BL5-BL0.

6.5.3.3 DSP Data Transfer Format Control (FC1-FC0) Bits 23 and 22The FC1-FC0 bits define data transfer formats between the HI32 and a PCI agent when in the PCI mode (HM=$1) and the HI32 is a bus master. The data transfer format converter (see Figure ) operates according to the specified FC1-FC0 (see Table 6-5).

Table 6-8 HI32 (PCI Master) Data Transfer Formats

FC1 FC0 DSP to PCI Host Data Transfer Format

PCI Host to DSP Data Transfer Format

0 0 The two least significant bytes of two HRXM locations are output.

All 32 PCI data bits are written to the HTXR as two zero-extended 16-bit words.

HDTFC

PCI bus

DTXM

HI32GDB/MDDB

HRXM

X

X

X

$0

HDTFC

PCI bus

DRXR

HI32GDB/MDDB

HTXR

$0

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0 1 The three least significant HRXM bytes are output right aligned and zero extended.

The three least significant PCI data bytes are written to the HTXR.

1 0 The three least significant HRXM bytes are output right aligned and sign extended.

The three least significant PCI data bytes are written to the HTXR.

1 1 The three least significant HRXM bytes are output left aligned and zero filled.

The three most significant PCI data bytes are written to the HTXR.

Table 6-8 HI32 (PCI Master) Data Transfer Formats

FC1 FC0 DSP to PCI Host Data Transfer Format

PCI Host to DSP Data Transfer Format

HDTFC

PCI bus

DTXM

HI32GDB/MDDB

$0

$0

HRXM

HDTFC

PCI bus

DRXR

HI32GDB/MDDB

X

HTXR

HDTFC

PCI bus

DTXM

HI32GDB/MDDB

S

S

HRXM

HDTFC

PCI bus

DRXR

HI32GDB/MDDB

X

HTXR

HDTFC

PCI bus

DTXM

HI32GDB/MDDB

$0

$0

HRXM

HDTFC

PCI bus

DRXR

HI32GDB/MDDB

X

HTXR

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6.5.3.4 In a PCI DSP-to-Host Transaction:

6.5.3.4.1 If FC = $0 (32-bit data mode):The two least significant bytes of the first word written to the DTXM and the two least significant bytes of the second word written to the DTXM are output to the HAD31-HAD0 signals. HAD[31:0] = $HHHHLLLL, where LLLL are the two least significant bytes of the first word written to the DTXM, and HHHH are the two least significant bytes of the second word written to the DTXM.

6.5.3.4.2 If FC = $1:The data written to the DTXM is output to the HAD31-HAD0 signals as right aligned and zero extended in the most significant byte.

6.5.3.4.3 If FC = $2:The data written to the DTXM is output to the HAD31-HAD0 signals as right aligned and sign extended in the most significant byte.

6.5.3.4.4 If FC = $3:The data written to the DTXM is output to the HAD31-HAD0 signals as left aligned and zero filled in the least significant byte.

6.5.3.5 In a PCI Host-to-DSP Transaction:

6.5.3.5.1 If FC = $0 (32-bit data mode):The two least significant bytes PCI data bytes from the HAD15-HAD0 signals are transferred to the two least significant bytes of the DRXR after which the two most significant bytes, from the HAD32-HAD16 signals, are transferred to the two least significant bytes of the DRXR. Thus, when the DSP56300 core reads two words from the DRXR, the two least significant bytes of the first word read contain the two least significant bytes of the 32-bit word written to the HTXR, the two least significant bytes of the second word read contain the two most significant bytes of the 32-bit word.

6.5.3.5.2 If FC = $1 or $2:The three least significant PCI data bytes from the HAD23-HAD0 signals are transferred to the DRXR to be read by the DSP56300 core.

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6.5.3.5.3 If FC = $3:The three most significant PCI data bytes from the HAD31-HAD8 signals are transferred to the DRXR to be read by the DSP56300 core.

To assure proper operation: FC1-FC0 may be changed only if both the host-to-DSP and the DSP-to-host master data paths are empty. In addition, switching between 32-bit data modes and non-32-bit data modes may be done only in the personal software reset state (HM = $0 and HACT = 0).

FC1-FC0 are ignored when not in the PCI mode (HMπ$1).

The DPMC bits are ignored when not in the PCI mode (HMπ$1).

Hardware and software resets clear FC1-FC0.

6.5.4 DSP PCI Address Register (DPAR)

The DPAR is a 24-bit read/write register used by the DSP56300 core to generate the two least significant bytes of the 32-bit PCI transaction address, the PCI bus command, and the PCI bus byte enables. The DPAR cannot be accessed by the host processor. The two most significant bytes of the PCI transaction address are located in the DSP PCI master control register (DPMC, see Section 6.5.3).

11 10 9 8 7 6 5 4 3 2 1 0

AR11 AR10 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

23 22 21 20 19 18 17 16 15 14 13 12

BE3 BE2 BE1 BE0 C3 C2 C1 C0 AR15 AR14 AR13 AR12

Bit Name Function

15-0 AR[15:0] DSP PCI Transaction Address (Low)

19-16 C[3:0] PCI Bus Command

23-20 BE{3:0] PCI Byte Enables

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When the DPAR is written by the DSP56300 core, while in the PCI mode (HM=$1),

• MARQ is cleared

• when the HI32 can complete the first data phase (i.e. in a write transaction, the DSP-to-host data path is not empty; in a read transaction, the host-to-DSP data path is not full) ownership of the PCI bus is requested and when granted

• the address (from the DPMC and the DPAR) is driven to the HAD31-HAD0 signals and the bus command is driven to the HC3/HBE3-HC0/HBE0 signals during the PCI address phase.

The DPAR may be written only if MARQ is set.

In memory space accesses, the AR1-AR0 bits have the following meaning:

The DPAR bits are ignored when not in the PCI mode (HM≠$1).

Hardware and software resets clear A15-A0.

6.5.4.1 PCI Bus Command (C3-C0) Bits 11-8The C3-C0 define the PCI bus command. PCI bus commands supported by the HI32 as a PCI master are listed in Table 6-9. When the DPAR is written by the DSP56300 core, while the HI32 is in the PCI mode (HM=$1), ownership of the PCI bus is requested and, when granted, the address is driven to the HAD31-HAD0 signals and the bus command is driven to the HC3/HBE3-HC0/HBE0 signals during the PCI address phase.

AR1 AR0 Burst Order

0 0 Linear incrementing

0 1 PCI Cache line toggle mode (the data must be arranged by the DSP software)

1 X Reserved

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Table 6-9 PCI Bus Commands Supported by the HI32 as PCI Master

Illegal C3-C0 values are not supported by the HI32 and should not be used.

Hardware and software resets clear C3-C0.

6.5.4.2 PCI Byte Enables (BE3 -BE0) Bits 15-12The BE3-BE0 determine which byte lanes carry meaningful data when in the PCI mode (HM=$1) and the HI32 is a PCI master. BE3 applies to byte 3, and BE0 to byte 0. Byte enables are driven to HC3/HBE3-HC0/HBE0 signals during the PCI data phases.

The HI32, as master, drives all the HRXM data to the HAD31-HAD0 signals during write transactions, and writes the HAD31-HAD0 signals to the HTXR (in accordance with the FC1-FC0 bits) in read transactions, regardless of the BE3-BE0 value.

Hardware and software resets clear BE3-BE0.

C3-C0 Command Type

0000 illegal

0001 illegal

0010 I/O read

0011 I/O Write

0100 illegal

0101 illegal

0110 Memory Read

0111 Memory Write

1000 illegal

1001 illegal

1010 Configuration Read

1011 Configuration Write

1100 Memory Read Multiple

1101 illegal

1110 Memory Read Line

1111 illegal

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6.5.5 DSP Status Register (DSR)

The DSR is a 24-bit read-only status register used by the DSP56300 core to examine the status and flags of the HI32. The DSR cannot be accessed by the host processor. The DSR bits are described in the following paragraphs.

6.5.5.1 Host Command Pending (HCP) Bit 0The HCP bit indicates that the host has set the HC bit and that a host command interrupt is pending. The HCP bit reflects the status of the HC bit in the HCVR. If HCP is set and HCIE is set, a host command interrupt request is generated. HC and HCP are cleared by the HI32 interrupt logic hardware when the HC interrupt request is serviced. The host cannot clear HC.

The personal software reset clears HCP.

6.5.5.2 Slave Transmit Data Request (STRQ) Bit 1The STRQ bit indicates that the slave transmit data FIFO (DTXS) is not full and may be written by the DSP56300 core. STRQ functions in accordance with the value of the slave fetch type (SFT) bit in the host control register (HCTR).

In the Fetch mode: the HI32 requests data from the DSP56300 core (by enabling the STRQ status bit and generating core interrupt requests or DMA requests if enabled), only after the host has begun a read transaction from the HI32.

In the Pre-Fetch mode: the HI32 requests data from the DSP56300 core (by enabling the STRQ status bit and generating core interrupt requests or DMA requests if enabled) whenever the DTXS is not full.

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HACT HF2 HF1 HF0 SRRQ STRQ HCP

Reserved, read as zero

Bit Name Function

0 HCP Host Command Pending

1 STRQ Slave Transmit Data Request

2 SRRQ Slave Receive Data Request

3-5 HF2-HF0 Host Flags

23 HACT HI32 Active

22-6 reserved

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In the PCI mode (HM = $1):

• Fetch (SFT = 1): The DSP-to-host data path is a six word deep (three word deep in the 32-bit data format mode, HRF = $0) FIFO buffer. During a read transaction from the DTXS-HRXS FIFO, STRQ reflects the status of the DTXS: STRQ is set if the DTXS is not full. STRQ is cleared when the DSP56300 core fills the DTXS. If the host is not executing a read transaction from the HRXS, the DSP-to-host data path is forced to the reset state and STRQ is cleared.

In a Universal Bus mode (HM = $2 or $3):

• Fetch (SFT = 1): There is no FIFO buffering of the DSP-to-host data path. At the beginning of a read data transfer from the HRXS, STRQ is set. STRQ is cleared when the DSP56300 core writes to the DTXS. If the host is not reading from the HRXS, the DSP-to-host data path is forced to the reset and STRQ is cleared.

In both the PCI and Universal Bus modes (HM = $1, $2 or $3):

• Pre-fetch (SFT = 0): The DSP-to-host data path is a six word deep (three word deep in the 32-bit data format mode, HM = $1 and HRF = $0) FIFO buffer. STRQ reflects the status of the DTXS: STRQ is set if the DTXS is not full. STRQ is cleared when the DSP56300 core fills the DTXS.

If STRQ is set

• if STIE is set, a slave transmit data interrupt request is generated

• if enabled by an DSP56300 core DMA channel, a slave transmit data DMA request will be generated.

Hardware, software and personal software resets set STRQ. In the personal software reset state STRQ = 0.

6.5.5.3 Slave Receive Data Request (SRRQ) Bit 2The SRRQ bit indicates that the receive data FIFO (DRXR) contains data written by the host processor to the HI32 slave. When an external host writes data to the host-to-DSP FIFO (HTXR-DRXR), SRRQ is set. SRRQ is cleared if the DRXR is emptied by DSP56300 core reads; or the data to be read from the DRXR is master data.

If SRRQ is set

• if SRIE is set, a slave receive data interrupt request is generated

• if enabled by an DSP56300 core DMA channel, a slave receive data DMA request will be generated.

Hardware, software and personal software resets clear SRRQ.

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6.5.5.4 Host Flags (HF2-HF0) Bits 5-3The HF2-HF0 bits in the DSR indicate the state of host flags HF2-HF0 respectively, in the host control register (HCTR) on the host side. HF2-HF0 can only be changed, albeit indirectly, by the host processor.

In the PCI mode (HM = $1) the HF2-HF0 bits are updated at the end of a transaction.

Note: A potential problem exists when reading the status bits HF2-HF0 as an encoded triad. During personal hardware reset these bits are cleared asynchronously. For example: If HF2-HF0 change from 111 to 000, there is a small probability the DSP56300 core could read the bits during transition and receive 001 or 110 or other combinations instead of 000. This problem can be avoided if the DSP56300 core reads these bits twice and checks for consensus.

The personal hardware reset clears HF2-HF0.

6.5.5.5 HI32 Active (HACT) Bit 23The HACT bit indicates the activity of the HI32. The HACT is cleared in response to HM=$0 (Terminate and Reset) and set by HM = $1, $2, $3, $5.

HACT is cleared in response to Terminate and Reset (HM = $0):

• If HM = $0 is written (Terminate and Reset), while the HI32 is an active PCI bus master or selected target in a memory space transaction, a master initiated termination or target disconnect, respectively, is generated. When the PCI idle state is detected, the HACT status bit in the DSR is cleared.

• If HM = $0 is written (Terminate and Reset), while the HI32 is in a Universal Bus or Self Configuration mode (HM = $2, $3 or $5), the HACT status bit in the DSR is cleared immediately.

When HACT is set, the HI32 is active, and the DCTR mode and polarity bits must NOT be changed.

Hardware and software resets clear HACT.

6.5.5.6 DSR Reserved Status Bits 22-6These bits are reserved for future expansion and read as zeros.

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6.5.6 DSP PCI Status Register (DPSR)

The DPSR is a 24-bit read-only status register used by the DSP56300 core to examine the status and flags of the HI32, when in the PCI mode (HM=$1). The DPSR cannot be accessed by the host processor. The DPSR bits are described in the following paragraphs.

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RDC5

RDC4

RDC3

RDC2

RDC1

RDC0

HDTC TO TRTY TDIS TAB MAB DPER APER MARQ MRRQ MTRQ MWS

Reserved, read as zero

Bit Name Function

0 MWS PCI Master Wait States

1 MTRQ PCI Master Transmit Data Request

2 MRRQ PCI Master Receive Data Request

4 MARQ PCI Master Address Request

5 APER PCI Address Parity Error

6 DPER PCI Data Parity Error

7 MAB PCI Master Abort

8 TAB PCI Target Abort

9 TDIS PCI Target Disconnect

10 TRTY PCI Target Retry

11 TO PCI Time Out Termination

12 HDTC PCI Host Data Transfer Complete

21-16 RDC5-RDC0 Remaining Data Count

23,22,15-13,3 reserved

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6.5.6.1 PCI Master Wait State (MWS) Bit 0The MWS bit indicates that the HI32, as master in a PCI transaction, will insert wait states (if enabled, i.e. the MWSD bit in the DPCR is cleared) to extend the current data phase (or the first data phase if the transaction has not been initiated yet) by deasserted HIRDY as it cannot guarantee completion of the next data phase.

MWS is set:

• In a PCI write transaction, if there is only one word in the HI32-to-host data path.

• In a PCI read transaction, if there is only one empty location in the host-to-DSP data path.

This has many applications. For example, the DSP56300 core can set MTT, when MWS is set, to terminate a transaction after the transfer of a specific number of words. After MTT is set the HI32 will complete the data phase and terminate the transaction.

Hardware, software and personal software resets clear MWS.

6.5.6.2 PCI Master Transmit Data Request (MTRQ) Bit 1The MTRQ bit indicates that the DSP master transmit data FIFO (DTXM) is not full and can be written by the DSP56300 core. MTRQ is cleared if the DTXM is filled by DSP56300 core writes. MTRQ is set when data is output from the DTXM-HRXM FIFO to the host bus.

If MTRQ is set

• if MTIE is set, a master transmit data interrupt request is generated

• if enabled by an DSP56300 core DMA channel, a master transmit data DMA request will be generated.

Hardware, software and personal software resets set MTRQ. In the personal software reset state MTRQ = 0.

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6.5.6.3 PCI Master Receive Data Request (MRRQ) Bit 2The MRRQ bit indicates that the DSP receive data FIFO (DRXR) contains data read from the host bus by the HI32 master. When the HI32, as master, reads data from the host bus to the host-to-DSP FIFO (HTXR-DRXR), MRRQ is set. MRRQ is cleared if the DRXR is emptied by DSP56300 core reads; or the data to be read from the DRXR is slave data.

If MRRQ is set

• if MRIE is set, a master receive data interrupt request is generated

• if enabled by an DSP56300 core DMA channel, a master receive data DMA request will be generated.

Hardware, software and personal software resets clear MRRQ.

6.5.6.4 Master Address Request (MARQ) Bit 4The MARQ bit indicates that the HI32 is currently not the initiator of a PCI transaction and the DPAR can be written with the address of the next transaction. When the HI32 with the PCI bus master enable bit (BM) set in the CCMR, is first programmed to the PCI mode (HM=$1) or completes a PCI transaction as a master, MARQ is set and, if MAIE is set, a master address interrupt request is generated. MARQ is cleared by any of the following:

• the DSP56300 core writes the DPAR

• the PCI bus master enable bit (BM) is cleared in the CCMR

Hardware, software, personal hardware and personal software resets clear MARQ.

6.5.6.5 Address Parity Error (APER) Bit 5The APER bit indicates that an address parity error has been detected by the HI32 hardware, when in the PCI mode (HM=$1) and the HI32 is a PCI target. At the end of a transaction, if an address parity error has been detected, APER is set and, if PEIE is set, a parity error interrupt request is generated.

If an address parity error has been detected:

• the HI32 target claims the cycles and terminates as though the address was correct.

• if the system error enable (SERE) bit in the status/command configuration register (CSTR/CCMR) is set, the HSERR signal is pulsed one PCI clock cycle, and the signalled system error (SSE) bit is set in the CSTR/CCMR.

• the detected parity error bit (DPE) in the CSTR is set.

APER is cleared when it is written one by the DSP56300 core.

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In personal software reset APER does not reflect new address parity errors.

Hardware and software resets clear APER.

6.5.6.6 Data Parity Error (DPER) Bit 6The DPER bit indicates that a data parity error has been detected (by the HI32 hardware, or reported by the external host (HPERR asserted)), when in the PCI mode (HM = $1) and the HI32 is a PCI master or selected target. At the end of a transaction, if a data parity error has been detected, DPER is set and, if PEIE is set, a parity error interrupt request is generated. DPER is cleared when it is written one by the DSP56300 core.

In personal software reset DPER does not reflect new data parity errors.

Hardware and software resets clear DPER.

6.5.6.7 Master Abort (MAB) Bit 7The MAB bit indicates that a PCI transaction, initiated by the HI32, was terminated with master abort. When a PCI transaction initiated by the HI32 is terminated with master abort, MAB is set and, if TAIE is set, a transaction abort interrupt request is generated. MAB is cleared when written one by the DSP56300 core. If a PCI transaction, initiated by the HI32, was terminated with master abort, the received master abort bit (RMA) in the CSTR is also set.

Hardware and software resets clear MAB.

6.5.6.8 Target Abort (TAB) Bit 8The TAB bit indicates that a PCI transaction, initiated by the HI32, was terminated with target abort. When a PCI transaction initiated by the HI32 is terminated with target abort, TAB is set and, if TAIE is set, a transaction abort interrupt request is generated. TAB is cleared when written one by the DSP56300 core. If a PCI transaction, initiated by the HI32, was terminated with target abort, the received target abort bit (RTA) in the CSTR is also set.

Hardware and software resets clear TAB.

6.5.6.9 Target Disconnect (TDIS) Bit 9The TDIS bit indicates that a PCI transaction, initiated by the HI32, was terminated with a target initiated disconnect. When a PCI transaction initiated by the HI32 is terminated with disconnect, TDIS is set and, if TTIE is set, a transaction termination interrupt request is generated. TDIS is cleared when written one by the DSP56300 core.

Hardware and software resets clear TDIS.

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6.5.6.10 Target Retry (TRTY) Bit 10The TRTY bit indicates that a PCI transaction, initiated by the HI32, was terminated with a target initiated retry. When a PCI transaction initiated by the HI32 is terminated with retry, TRTY is set and, if TTIE is set, a transaction termination interrupt request is generated. TRTY is cleared when written one by the DSP56300 core.

Hardware and software resets clear TRTY.

6.5.6.11 PCI Time Out (TO) Bit 11The TO bit indicates that a PCI transaction, initiated by the HI32, was terminated due to the negation of the bus grant after the latency timer had expired. When a PCI transaction initiated by the HI32 is terminated due to time-out, TO is set and, if TTIE is set, a transaction termination interrupt request is generated. TO is cleared when written one by the DSP56300 core.

Hardware and software resets clear TO.

6.5.6.12 Host Data Transfer Complete (HDTC) Bit 12With the receive buffer lock enable (RBLE) bit in the DSP PCI control register (DPCR) set: the HDTC bit indicates that the host-to-DSP data path is empty. HDTC is set if SRRQ and MRRQ are cleared (i.e. the host-to-DSP data path is emptied by DSP56300 core reads) after the termination or completion a non-exclusive PCI write transaction to the HTXR, or the negation of HLOCK after the completion of an exclusive write access to the HTXR, or after a read transaction initiated by the HI32. The HI32 will disconnect (retry or disconnect-C) forthcoming write accesses to the HTXR as long as HDTC is set. HDTC is cleared when written one by the DSP56300 core. HDTC may be written one by the DSP56300 core only if it is set.If the HDTC bit is cleared the HI32 will respond to write PCI transactions according to the status of the host-to-DSP data path.

Hardware, software and personal software resets clear HDTC.

Note: Each of the bits APER, DPER, MAB, TAB, TDIS, TRTY, TO and HDTC are cleared by writing one to the specific bit. In order to assure that only the desired bit is cleared, the programmer should not use the BSET command. The proper way to clear these bits is to write (MOVE(P) instruction) ones to the bits to be cleared and zeros to all the others.

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6.5.6.13 Remaining Data Count (RDC5-RDC0) Bits 21-16The read-only bits, RDC5-RDC0, indicate the PCI data phases remaining to complete a PCI burst after the HI32 has completed a transaction as a PCI master. The RDC5-RDC0 bits are updated each time a transaction is terminated with the HI32 as a PCI master (MARQ = 1). If the transaction terminated normally, the value of RDC5-RDC0 will be $00 and TO = 0, TRTY = 0, TDIS = 0, TAB = 0, MAB = 0. If the master access counter was enabled and the burst was not completed for any reason (typical examples being: the target initiated transaction termination or the HI32 was required to generate a master initiated time-out transaction termination), the value of RDC5-RDC0 will be the remaining number of data phases remaining to complete the burst minus one (i.e. RDC = $2 signifies that there remain three more words to be transferred to complete the burst). The length of the burst is limited by BL5-BL0 in the DPMC.

6.5.6.14 DPSR Reserved Bits 23-22, 15-12 and 3 These bits are reserved for future expansion and are read as zeros.

6.5.7 Host To DSP Data Path

In PCI master data transfers (HM = $1) with FC≠$0, the host-to-DSP data path is a six word deep, 24-bit wide FIFO. The host data is read into the host side of the FIFO (HTXR) as 24-bit words, and the DSP56300 core reads 24-bit words from the DSP side (DRXR).

In PCI master data transfers (HM = $1) with FC = $0, and PCI target data transfers (HM = $1) with HTF = $0, the host-to-DSP data path operates as a three word deep, 32-bit wide FIFO. The host data is read into the HTXR as 32-bit words, and the DSP56300 core reads from the DRXR 24-bit words. Each word read by the DSP56300 core contains 16-bits of data, right aligned and zero extended. The first word read by the DSP56300 core contains the two least significant bytes of the 32-bit word read into the HTXR. The second word read by the DSP56300 core contains the two most significant bytes of the 32-bit word read into the HTXR.

In PCI target data transfers (HM = $1) with HTF≠$0 the host-to-DSP data path is a six word deep, 24-bit wide FIFO. The host writes 24-bit words to the HTXR, and the DSP56300 core reads 24-bit words from the DRXR.

In Universal Bus mode data transfers, the host-to-DSP data path is a five word deep, 24-bit wide FIFO. The host writes 24-bit words to the HTXR, and the DSP56300 core reads 24-bit words from the DRXR.

The DSP side of the host-to-DSP data FIFO is described below. For a detailed description of the host side see Section 6.2.2.

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6.5.8 DSP Receive Data FIFO (DRXR)

The 24-bit wide DSP receive data register (DRXR) is the output stage of the host-to-DSP data path FIFO used for host-to-DSP data transfers.

The DRXR contains master data (i.e. data read by the HI32 as PCI master from an external target) to be read if MRRQ is set in the DPSR. MRRQ is cleared if the data in the DRXR is slave data or when the host-to-DSP data path FIFO is emptied by DSP56300 core reads. The DSP56300 core may set the MRIE bit to cause a host receive data interrupt when MRRQ is set.

The DRXR contains slave data (i.e. data written to the HI32 from the host bus) to be read if SRRQ is set in the DSR. SRRQ is cleared if the data in the DRXR is master data or when the host-to-DSP data path FIFO is emptied by DSP56300 core reads. The DSP56300 core may set the SRIE bit to cause a host receive data interrupt when SRRQ is set.

In the 32-bit mode (HM = $1 with FC = $0 or HTF = $0), only the two least significant bytes contain data, the most significant byte is read as zeroes. (See Table 6-5 and Table 6-15).

Hardware, software and personal software resets empty the host-to-DSP data path FIFO (SRRQ and MRRQ are cleared).

6.5.9 DSP To Host Data Path

In PCI master data transfers (HM = $1) with FC≠$0, the master DSP-to-host data path (DTXM-HRXM) is an eight word deep FIFO. The DSP56300 core writes to the DSP side of the FIFO (DTXM). The data is output to the bus from the host side (HRXM).

In PCI master data transfers (HM = $1) with FC = $0, the master DSP-to-host data path is a four word deep, 32-bit wide FIFO. The DSP56300 core writes 24-bit words to the DTXM. Each word written by the DSP56300 core contains 16-bits of significant data, right aligned, the most significant byte is not transmitted. The first word written by the DSP56300 core contains the two least significant bytes of the 32-bit word to be output from the HRXM. The second word written by the DSP56300 core contains the two most significant bytes of the 32-bit word be output from the HRXM. Each time a 32-bit word is output from the HRXM, the 32-bits of significant data located in two words written to the DTXM are output.

In PCI target data transfers (HM = $1) with HRF≠$0 and in Universal Bus mode data transfers, the slave DSP-to-host data path (DTXS-HRXS) is a six word deep FIFO. The

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DSP56300 core writes 24-bit words to the DTXS. The data is output, a word at a time, to the bus from the HRXS.

In PCI target data transfers (HM = $1) with HRF = $0, the slave DSP-to-host data path is a three word deep, 32-bit wide FIFO. The DSP56300 core writes 24-bit words to the DTXS. Each word written by the DSP56300 core contains 16-bits of significant data, right aligned, the most significant byte is not transmitted. The first word written by the DSP56300 core contains the two least significant bytes of the 32-bit word to be output from the HRXS. The second word written by the DSP56300 core contains the two most significant bytes of the 32-bit word be output from the HRXS. Each time the host reads a 32-bit word from the HRXS, the 32-bits of significant data located in two locations of the slave DSP-to-host data path (DTXS and HRXS) are output.

The DSP side of the DSP-to-host data FIFOs are described in the following pages. For a detailed description of the host side see Section 6.6.4 and Section 6.6.5.

6.5.10 DSP Master Transmit Data Register (DTXM)

The 24-bit wide DSP master transmit data register (DTXM) is the input stage of the master DSP-to-host data path FIFO used for DSP-to-host master data transfers in the PCI mode (HM = $1).

The DTXM may be written if the MTRQ bit is set in the DPSR. Data should not be written to the DTXM until MTRQ is set to prevent previous data from being overwritten. Filling the DTXM by DSP56300 core writes (MOVE(P) instructions or DMA transfers) clears MTRQ. The DSP56300 core may set the MTIE bit to cause a host receive data interrupt when MTRQ is set.

In the PCI mode (HM = $1) the DSP56300 core can clear the HI32 master-to-host bus data path and empty DTXM by setting the CLRT bit in the DPCR.

In the 32-bit mode (HM = $1 with FC = $0), only the two least significant bytes of the DTXM are transferred. (See Section 6.5.9, above, and Table 6-5).

Hardware, software and personal software resets empty the DTXM.

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6.5.11 DSP Slave Transmit Data Register (DTXS)

The 24-bit wide DSP slave transmit data register (DTXS) is the input stage of the slave DSP-to-host data path FIFO used for DSP-to-host slave data transfers in the PCI mode (HM = $1).

The DTXS may be written if the STRQ bit is set in the DSR. Data should not be written to the DTXS until STRQ is set to prevent previous data from being overwritten. Filling the DTXS by DSP56300 core writes (MOVE(P) instructions or DMA transfers) clears STRQ. The DSP56300 core may set the STIE bit to cause a host receive data interrupt when STRQ is set.

In the 32-bit mode (HM = $1 with HRF = $0), only the two least significant bytes of the DTXS are transferred. (See Section 6.5.9, above,Table 6-5, and Section 6-16)

Hardware, software and personal software resets empty the DTXS.

6.5.12 DSP Host Port GPIO Data Register (DATH)

The DATH is a 24-bit read/write data register used by the DSP56300 core to read or write data to/from host port signals configured as GPIO. The DATH cannot be accessed by the host processor.

DAT23-DAT0 are used to read or write data from/to the corresponding GPIO signal. The functionality of the DAT23-DAT0 bits is defined in Table 6-10.

Hardware and software resets clear all DATH bits.

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DAT23

DAT22

DAT21

DAT20

DAT19

DAT18

DAT17

DAT16

DAT15

DAT14

DAT13

DAT12

DAT11

DAT10

DAT9

DAT8

DAT7

DAT6

DAT5

DAT4

DAT3

DAT2

DAT1

DAT0

Bit Name Function

23-0 DAT23-DAT0 GPIO Signal Data

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6.5.13 DSP Host Port GPIO Direction Register (DIRH)

The DIRH is a 24-bit read/write register used by the DSP56300 core to control the direction of the host port signals in GPIO mode. The DIRH cannot be accessed by the host processor.

DIR23-DIR0 are used to define the corresponding GPIO signals as input or output. The functionality of the DIR23-DIR0 bits is defined in Table 6-10.

Hardware and software resets clear all DIRH bits.

Table 6-10 DATH and DIRH Functionality

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DIR23

DIR22

DIR21

DIR20

DIR19

DIR18

DIR17

DIR16

DIR15

DIR14

DIR13

DIR12

DIR11

DIR10

DIR9

DIR8

DIR7

DIR6

DIR5

DIR4

DIR3

DIR2

DIR1

DIR0

Bit Name Function

23-0 DIR23-DIR0 GPIO Signal Direction

DIRx

DATx

GPIO signala

a. defined by the selected mode

non-GPIO signala

0 Read only bit. The value read is the binary value of the signal.The corresponding signal is configured as an input.

Read only bit. Does not contain significant data.

1 Read/write bit. The value written is the value read. The corresponding signal is configured as an output, and is driven with the data written to DATx.

Read/write bit. The value written is the value read.

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HOST SIDE Programming Model

6.6 HOST SIDE PROGRAMMING MODEL

The HI32 appears to the host processor as a bank of registers.

Table 6-11 HI32 Programming Model - Host Side Registers

In the Universal Bus modes:

• The HI32 occupies eight words in the host processor address space (see Figure 6-4). The PCI configuration registers (CDID/CVID, CSTR/CCMR, CCCR/CRID, CHTY/CLAT, CBMA and CILP) cannot be accessed by the host processor in the Universal Bus modes.

• Due to the fast DSP56300 core interrupt response, most host microprocessors can read or write data at their maximum programmed non-DMA instruction rate without testing the handshake flags for each transfer. If the full interrupt driven handshake is not needed, the high speed data transfer between the host and the HI32 may be supported with only host data strobe/acknowledge handshake mechanism. DMA hardware may be used with the handshake flags to transfer data without host processor intervention.


Register Acronym Register Name Register Type

HCTR Host Interface Control Register Control, status, vector and data registers, and FIFOs

HSTR Host Interface Status Register

HCVR Host Command Vector Register

HRXM Host Master Receive Data FIFO

HRXS Host Slave Receive Data FIFO

HTXR Host Transmit Data FIFO

CDID/CVID Device ID/Vendor ID Configuration Register PCI configuration registersCSTR/CCMR Status/Command Configuration Register

CCCR/CRID Class Code/Revision ID Configuration Register

CHTY/CLAT Header Type/Latency Timer Configuration Register

CBMA Memory Space Base Address Configuration Register

CILP Interrupt Line -Interrupt Signal Configuration RegisterNote: The HRXM is used by the HI32, as the PCI master, to output data, and cannot actually be

accessed by the host bus.

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In the PCI mode:

• In memory space read/write transactions, the HI32 occupies 16384 Dwords (see Figure 6-2). The HTXR FIFO and HRXS FIFO can be accessed by the host at 16377 Dword locations. These FIFOs appear to the external host as 16377 Dwords of read/write memory. Registers are accessed as 32-bit Dwords.

• HAD1 and HAD0 should be zero during the address phase of a transaction. The HI32 will respond with a target-disconnect transaction termination with the first data phase if HAD1-HAD0≠$0 during the address phase.

• In configuration space read/write transactions, the HI32 occupies 64 Dwords (see Figure 6-3). The configuration registers are accessed as 32-bit Dwords, thus HAD1 ad HAD0 must be zero during the address phase. The HI32 will ignore the transaction if HAD1-HAD0≠$0 during the address phase of a configuration transaction.

• In PCI host-to-DSP data transfers to the HI32 registers (HCTR, HSTR, HCVR and all configuration space registers): disabled byte lanes (i.e. the corresponding byte enable line is deasserted) are not written and the corresponding bytes do not contain significant data.

• In HI32 to PCI agent data transfers, all four byte lanes are driven with data, regardless of the value of the byte enables.

• In HCTR, HSTR, HCVR and configuration space register accesses: if all four byte lanes are disabled the HI32 completes the data phase without affecting any flags or data.

• In PCI DSP-to-host data transfers via the HRXS or HRXM, all four byte lanes are driven with data, in accordance with FC1-FC0 or HRF1-HRF0 bits, regardless of the value of the byte enable signals (HC3/HBE3-HC0/HBE0).

• In PCI host-to-DSP data transfers, data is written to the HTXR FIFO, in accordance with FC1-FC0 or HTF1-HTF0 bits, regardless of the value of the byte enable signals (HC3/HBE3-HC0/HBE0).

• The HI32 will not reach dead-lock due to illegal PCI events. Illegal PCI events bring the HI32 Master and Target state machines to the IDLE state.

• As a PCI target the HI32 executes the PCI bus command as described in Table 6-12:

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Table 6-12 HI32 PCI Target Execution

The master data transfer format control bits (FC1-FC0 in the DPMC) affect the HTXR-DRXR and DTXM-HRXM data paths only. The target data transfer format control bits (HTF1-HTF0 and HRF1-HRF0 in the HCTR) affect the HTXR-DRXR and DTXS-HRXS data paths only. The data paths to the other host registers (HCTR, HSTR, HCVR, CDID/CVID, CSTR/CCMR, CCCR/CRID, CHTY/CLAT, CBMA and CILP) are not affected by the data transfer format control bits.

The host side registers can be accessed by the host processor. The CCMR, CLAT and CBMA HI32 configuration registers can also be accessed, indirectly, by the DSP56300 core in the Self Configuration mode (HM = $5 - see Section 6.5.1.13).

Reserved addresses are read as zeros, and should be written with zeroes for future compatibility.

HC3/HBE3-HC0/HBE0 Executed as Command Type

0000 ignoreda

a. All internal address decoding is ignored and DEVSEL is not asserted.

0001 ignored(a)

0010 ignored(a)

0011 ignored(a)

0100 ignored(a)

0101 ignored(a)

0110 Memory Read

0111 Memory Write

1000 ignored(a)

1001 ignored(a)

1010 Configuration Read

1011 Configuration Write

1100 Memory Read

1101 ignored(a)

1110 Memory Read

1111 Memory Write

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Host processors may use standard host processor instructions and addressing modes to communicate with the HI32 registers. The host processor may be any of a number of industry standard microcomputers or microprocessors, DMA controllers or standard peripheral bus (e.g. ISA/EISA), because this interface appears to the host like static RAM.

With the host command feature, the host processor can issue vectored interrupt requests to the DSP56300 core. The host may select any one of 128 DSP56300 core interrupt routines to be executed by writing a vector address register in the HI32. This flexibility allows the host programmer to execute up to 128 pre-programmed functions inside the DSP. For example, host exceptions can allow the host processor to read or write DSP registers, X-, Y-, or program memory locations, force exception handlers (e.g., SSI, Timer, IRQA, IRQB exception routines), and perform control and debugging operations if exception routines are implemented in the DSP to perform these tasks. The host processor can also generate non-maskable interrupt requests to the DSP56300 core using the host commands.

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Figure 6-2 Host Side Registers (PCI Memory Address Space1)

Figure 6-3 Host Side Registers (PCI Configuration Address Space2)

Base Address: $0000

Base Address: $000C

Reserved (4 Dwords)

Base Address: $0010 HI32 Control Register (HCTR)

Base Address: $0014 HI32 Status Register (HSTR)

Base Address: $0018 Host Command Vector Register (HCVR)

Base Address: $001C

Base Address: $FFFC

Host Transmit/Slave Receive Data Register (HTXR/HRXS)(16377 Dwords)

1. Addresses shown are in bytes. The base address is defined by the CBMA register

$00(CDID/CVID) Device ID (CDID) Vendor ID (CVID)

$04(CSTR/CCMR) Status (CSTR) Command (CCMR)

$08(CCCR/CRID) Class Code (CCCR) Revision ID (CRID)

$0C(CLAT) Header Type (CHTY) Latency Timer (CLAT)

$10(CBMA) Memory Space Base Address (CBMA)

$14

$F8

Reserved(58 Dwords)

$FC(CILP) MAX_LAT MIN_GNT Interrupt Line Interrupt Signal

2. Addresses shown are in bytes.

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Figure 6-4 Host Side Registers (Universal Bus Mode Address Space1)

Base Address: $0

Base Address: $3

Reserved(4 Locations)

Base Address: $4 HI32 Control Register (HCTR)

Base Address: $5 HI32 Status Register (HSTR)

Base Address: $6 Host Command Vector Register (HCVR)

Base Address: $7 Host Transmit/Slave Receive Data FIFO (HTXR/HRXS)

1. Addresses shown are in words (locations). The base address is defined by eight bits of the CBMA register.

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6.6.1 HI32 Control Register (HCTR)

The HCTR is a 32-bit read/write control register used by the host processor to control the HI32 interrupts, flags, semaphores, data transfer formats and operation modes.

In the PCI mode (HM=$1), the HAD31-HAD0 signals are driven with HCTR data during a read access; and the signals are written to the HCTR in a write access.

In a 24-bit data Universal Bus mode (HM=$2 or $3 and HTF = $0 or HRF = $0), the HD23-HD0 signals are driven with the three least significant HCTR bytes during a read access; HD23-HD0 are written to the three least significant HCTR bytes in a write access.

In a 16-bit data Universal Bus mode (HM=$2 or $3 and HTF≠$0 or HRF≠$0), the HD15-HD0 signals are driven with the two least significant bytes of the HCTR in a read access; HD15-HD0 are written to the two least significant bytes of the HCTR, the most significant portion is zero filled during the HCTR write.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TWSD HS2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HS1 HS0 HRF1 HRF0 HTF1 HTF0 SFT DMAE HF2 HF1 HF0 RREQ TREQ

Reserved, read as zero and should be written zero

Bit Name Function

1 TREQ Transmit Request Enable

2 RREQ Receive Request Enable


6 DMAE DMA Enable (ISA/EISA)

7 SFT Slave Fetch Type

9-8 HTF1-HTF0 Host Transmit Data Transfer Format

12-11 HRF1-HRF0 Host Receive Data Transfer Format

16-14 HS2-HS0 Host Semaphores

19 TWSD Target Wait State Disable

31-20,18-17,13,10,0 reserved

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In PCI mode (HM = $1) memory space transactions, the HCTR is accessed if the PCI address is HI32_base_address: $010.

The HCTR is written in accordance with the byte enables (HC3/HBE3-HC0/HBE0 signals). Byte lanes that are not enabled are not written and the corresponding bits remain unchanged.

The HCTR bits affect the HI32 logic upon the completion of the transaction in they were written.

When in a Universal Bus mode (HM=$2 or $3), the HCTR is accessed if the HA10-HA3 value matches the HI32 base address (CBMA, see Section 6.6.11) and the HA2-HA0 value is $4.

The control bits are described in the following paragraphs.

6.6.1.1 Transmit Request Enable (TREQ) Bit 1The TREQ bit is used to control the HIRQ and HDRQ signals for host transmit data transfers (see Table 6-13), when in a Universal Bus mode (HM=$2 or $3).

If DMA enable bit (DMAE) is cleared, TREQ enables the host interrupt request HIRQ signal when the host transmit data request (HTRQ) status bit in the HI32 status register (HSTR) is set. If TREQ is cleared, HTRQ host interrupt requests are disabled. If TREQ is set, the host interrupt request HIRQ signal will be asserted if HTRQ is set. HDRQ is deasserted.

If DMAE is set, TREQ enables the host DMA request (HDRQ) signal when the host transmit data request (HTRQ) status bit in the HSTR is set. If TREQ is cleared, HTRQ external DMA requests are disabled. If TREQ is set, the host DMA request HDRQ signal will be asserted if HTRQ is set. HIRQ is deasserted (high impedance if HIRD = 0 in the DCTR).

The personal hardware reset clears TREQ.

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6.6.1.2 Receive Request Enable (RREQ) Bit 2The RREQ bit is used to control the HIRQ and HDRQ signals for DSP-to-host data transfers (see Table 6-13), when in a Universal Bus mode (HM=$2 or $3).

If DMAE is cleared, RREQ enables the host interrupt request (HIRQ) signal when the host receive data request (HRRQ) status bit in the HSTR is set. If RREQ is cleared, HRRQ host interrupt requests are disabled. If RREQ is set, the host interrupt request HIRQ signal will be asserted if HRRQ is set. HDRQ is deasserted.

If DMAE is set, RREQ enables the host DMA request (HDRQ) signal when the host receive data request (HRRQ) status bit in the HSTR is set. If RREQ is cleared, HRRQ host DMA requests are disabled. If RREQ is set, the host DMA request HDRQ signal will be asserted if HRRQ is set. HIRQ is deasserted (high impedance if HIRD = 0 in the DCTR).

The personal hardware reset clears RREQ.

Note: In a Universal Bus mode (HM = $2 or $3), when both the TREQ and RREQ control bits (in the HCTR) are cleared, host interrupt request / strobe / acknowledge hardware handshake (using the HIRQ / Data Strobe / HTA signals) is disabled. The host may poll the HTRQ, HRRQ status bits or use the host data strobe/acknowledge hardware handshake (using the Data Strobe / HTA signals) (see Table 6-5).

Table 6-13 HIRQ and HDRQ Signal Definition

DMAE TREQ RREQ HIRQ Signal HDRQ signal

0 0 0 deasserted a (HRRQ, HTRQ polling)

a. high impedance if HIRD = 0 in the DCTR

high impedance

0 0 1 HRRQ Host Interrupt Requests Enabled

high impedance

0 1 0 HTRQ Host Interrupt Request Enabled high impedance

0 1 1 HRRQ, HTRQ Interrupt Requests Enabled

high impedance

1 0 0 deasserteda high impedance

1 0 1 deasserteda HRRQ DMA Request Enabled

1 1 0 deasserteda HTRQ DMA Request Enabled

1 1 1 deasserteda HRRQ, HTRQ Host DMA Requests Enabled

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6.6.1.3 Host Flags (HF2-HF0) Bits 5 and 3The HF2-HF0 bits are used as general purpose flags for host-to-DSP communication. HF2-HF0 may be set or cleared by the host processor.

The personal hardware reset clears HF2-HF0.

6.6.1.4 DMA Enable (DMAE) Bit 6The DMAE is used by the host processor to enable the HI32 ISA/EISA DMA-type accesses, when in a Universal Bus mode (HM=$2 or $3) (see Table 6-14)

.

If the HAEN signal is driven low by the host, the HI32 responds when it identifies its address (i.e. ISA/EISA I/O-type accesses). The HI32 will not respond to ISA/EISA DMA-type accesses.

If the HAEN signal is high:

• If DMAE is cleared the HI32 cannot be accessed.

• If DMAE is set, the HI32 responds to ISA/EISA DMA-type accesses.

If DMAE is cleared, the HDRQ signal is deasserted, HIRQ is active.

Table 6-14 DMAE Definition

DMAE HAEN ISA/EISA Access Type HIRQ and HDRQ functionality

0 0 The HI32 responds when it identifies its address (i.e. ISA/EISA I/O-type access)

HIRQ is active, HDRQ is deasserted

0 1 The HI32 will not respond to any access HIRQ is active, HDRQ is deasserted

1 0 The HI32 responds when it identifies its address (i.e. ISA/EISA I/O-type access)

HDRQ is active, HIRQ is deasserteda

a. High impedance if HIRD = 0 in the DCTR

1 1 The HI32 responds when HDAK is asserted(i.e. ISA/EISA DMA-type access)

HDRQ is active, HIRQ is deasserteda

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If DMAE is set, the HIRQ signal is deasserted, HDRQ is active. This allows the HI32 to generate host DMA requests during ISA/EISA I/O-type accesses. A typical application would be that the external host writes to the HI32 using a polling procedure, and the external DMA reads from the HI32. An external bus controller arbitrates between the two and sets or clears HAEN accordingly.

If both DMAE and HAEN are set, HTA is released (high impedance), as DMA devices cannot extend DMA cycles (ISA/EISA).

The personal hardware reset clears DMAE.

6.6.1.5 Slave Fetch Type (SFT) Bit 7The SFT bit defines the fetch mode (data fetch or pre-fetch) as described below.

In the Fetch mode: the HI32 requests data from the DSP56300 core (by enabling the STRQ status bit and generating core interrupt requests or DMA requests if enabled), only after the host has begun a read transaction from the HI32.

In the Pre-Fetch mode: the HI32 requests data from the DSP56300 core (by enabling the STRQ status bit and generating core interrupt requests or DMA requests if enabled) whenever the DTXS is not full.

In the PCI mode (HM = $1):

• Fetch (SFT = 1):The DSP-to-host data path (DTXS-HRXS) is a six word deep (three word deep if HRF = $0) FIFO buffer. Writing SFT = 1 resets the DSP-to-host data path and clears STRQ and HRRQ. During a read transaction from the HRXS, STRQ is set if the DTXS-HRXS FIFO is not full, and cleared when the DSP56300 core fills the DTXS; HRRQ is cleared if the HRXS is empty, and set if it contains data to be read by an external host. If the host is not executing a read transaction from the HRXS, the DSP-to-host data path is forced to the reset state and STRQ and HRRQ are cleared.

SFT Slave Fetch Type

1 Fetch0 Pre-fetch

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In a Universal Bus mode (HM= $2 or $3):

• Fetch (SFT = 1): There is no FIFO buffering of the DSP-to-host data path. Writing SFT = 1 resets the DSP-to-host data path and clears the STRQ and the HRRQ. At the beginning of a read data transfer from the HRXS, STRQ is set. STRQ is cleared when the DSP56300 core writes to the DTXS; HRRQ is cleared if the HRXS is empty, and set if it contains data to be read by an external host. If the host is not reading from the HRXS, the DSP-to-host data path is forced to the reset and STRQ and HRRQ are cleared.

Note: Any data remaining in the DSP-to-host data path when entering the reset state, is lost.

In both the PCI and Universal Bus modes (HM=$1, $2 or $3):

• Pre-fetch (SFT = 0):The DSP-to-host data path is a six word deep (three word deep in the 32-bit data format mode, HM = $1 and HRF = $0) FIFO buffer. STRQ reflects the status of the DTXS and HRRQ reflects the status of the HRXS. STRQ is set if the DTXS is not full, and cleared when the DSP56300 core fills the DTXS. HRRQ is cleared if the HRXS is empty, and set when it contains data to be read by an external host.

The value of SFT may be changed only if the DTXS-HRXS data path is empty.

The personal hardware reset clears SFT.

6.6.1.6 Host Transmit Data Transfer Format (HTF1-HTF0) Bits 9 and 8The HTF1-HTF0 bits define data transfer formats for host-to-DSP communication. The data transfer format converter (HDTFC) operates according to the specified HTF1-HTF0 (see Table 6-15).

PCI host to DSP data transfer formats (HM = $1):

• If HTF = $0 (32-bit data mode):All four PCI data bytes from HAD31-HAD0 signals are written to the 32-bit HTXR. The two least significant bytes are transferred to the two least significant bytes of the DRXR FIFO after which the two most significant bytes are transferred to the two least significant bytes of the DRXR FIFO. Thus, when the DSP56300 core reads two words from the DRXR, the two least significant bytes of the first word read contain the two least significant bytes of the 32-bit word written to the HTXR, the two least significant bytes of the second word read contain the two most significant bytes of the 32-bit word.

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• If HTF = $1 or $2:The three least significant PCI data bytes from the HAD23-HAD0 signals are transferred to the three least significant HTXR bytes and transferred to the DRXR to be read by the DSP56300 core.

• If HTF = $3:The three most significant PCI data bytes from the HAD31-HAD8 signals are transferred to the three least significant HTXR bytes and transferred to the DRXR to be read by the DSP56300 core.

Universal Bus mode host to DSP data transfer formats (HM = $2 or $3):

• If HTF = $0:The 24-bit data from HD23-HD0 data signals is transferred to the three least significant HTXR bytes and transferred to the DRXR to be read by the DSP56300 core.

• If HTF = $1:The 16-bit data from HD15-HD0 data signals is transferred to the three least significant HTXR bytes as right aligned and zero extended and transferred to the DRXR to be read by the DSP56300 core.

• If HTF = $2:The 16-bit data from HD15-HD0 data signals is transferred to the three least significant HTXR bytes as right aligned and sign extended and transferred to the DRXR to be read by the DSP56300 core.

• If HTF = $3:The 16-bit data from HD15-HD0 data signals is transferred to the three least significant bytes of the HTXR, as left aligned, the least significant byte is zero filled and transferred to the DRXR to be read by the DSP56300 core.

To assure proper operation:

• HTF1-HTF0 may be changed only if the host-to-DSP data path is empty.

• Switching between 32-bit data modes and non-32-bit data modes may be done only in the personal software reset state (HM = $0 and HACT = 0).

• If the HTF1-HTF0 value is not equal to the value of the FC1-FC0 bits in the DPMC: PCI transactions that start in the non-data address space (i.e. the PCI address is less than HI32_base_address:$007) should not extend into the data address space.

The personal hardware reset clears HTF1-HTF0.

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Table 6-15 Transmit Data Transfer Format

HTF1

HTF0

Host to DSP Data Transfer Format

PCI mode Universal Bus mode

0 0 All 32 PCI data bits are written to the HTXR astwo zero-extended 16-bit words.

All HD23-HD0 data are written to the HTXR.

$0

HDTFC

PCI bus

DRXR

HI32GDB/MDDB

HTXR

$0

HDTFC

Host bus

DRXR

HI32GDB/MDDB

HTXR

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0 1 The three least significant PCI data bytes arewritten to the HTXR.

HD15-HD0 is written to the HTXR, rightaligned and zero extended.

1 0 The three least significant PCI data bytes arewritten to the HTXR.

HD15-HD0 are written to the HTXR, rightaligned and sign extended.

1 1 The three most significant PCI data bytes arewritten to the HTXR.

HD15-HD0 are written to the HTXR, leftaligned, and zero filled.

Table 6-15 Transmit Data Transfer Format

HTF1

HTF0

Host to DSP Data Transfer Format


HDTFC

PCI bus

DRXR

HI32GDB/MDDB

X

HTXR

HDTFC

Host bus

DRXR

HI32GDB/MDDB$0

$0

HTXR

$0

$0

HDTFC

PCI bus

DRXR

HI32GDB/MDDB

X

HTXR

HDTFC

Host bus

DRXR

HI32GDB/MDDBS

S

HTXR

S

S

HDTFC

PCI bus

DRXR

HI32GDB/MDDB

X

HTXR

HDTFC

Host bus

DRXR

HI32GDB/MDDB$0

$0

HTXR

$0

$0

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6.6.1.7 Host Receive Data Transfer Format (HRF1-HRF0) Bits 12 and 11The HRF1-HRF0 bits define data transfer formats for DSP-to-host communication. The data transfer format converter (HDTFC) operates according to the specified HRF1-HRF0 (See Table 6-16).

DSP to PCI host data transfer formats (HM = $1):

• If HRF = $0 (32-bit data mode):The two least significant bytes of two words written to the DTXS are transferred to the HRXS. The two least significant bytes of the first word written to the DTXS are transferred to the two least significant bytes of the HRXS. The two least significant bytes of the second word written to the DTXS are transferred to the two most significant bytes of the HRXS. All four HRXS bytes are output to the HAD31-HAD0 signals.

• If HRF = $1:The data written to the DTXS is transferred to the three least significant HRXS bytes and output to the HAD31-HAD0 signals as right aligned and zero extended in the most significant byte.

• If HRF = $2:The data written to the DTXS is transferred to the three least significant HRXS bytes and output to the HAD31-HAD0 signals as left aligned and zero filled in the least significant byte.

• If HRF = $3:The data written to the DTXS is transferred to the three least significant HRXS bytes and output to the HAD31-HAD0 signals as right aligned and sign extended in the most significant byte.

Universal Bus mode DSP to host data transfer formats (HM = $2 or $3):

• If HRF = $0:The data written to the DTXS is transferred to the HRXS and output to the HI32 data signals HD23-HD0.

• If HRF = $1 or $2:The two least significant bytes of the data written to the DTXS is transferred to the HRXS and output to the HI32 data signals HD15-HD0.

• If HRF = $3:The two most significant bytes of the data written to the DTXS is transferred to the HRXS and output to the HI32 data signals HD15-HD0.

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To assure proper operation, HRF1-HRF0 may be changed only if the DSP-to-host slave data path is empty. In addition, switching between 32-bit data modes and non-32-bit data modes may be done only in the personal software reset state (HM = $0 and HACT = 0).

The personal hardware reset clears HRF1-HRF0.

6.6.1.8 Host Semaphores (HS2-HS0) Bits 16 and 14 The HS2-HS0 bits may be used by the host processors for software arbitration of mastership over the HI32. These bits do not affect the HI32 operation and only serve as a read/write semaphore repository. These bits may be used as a mailbox between the external hosts. For example: the semaphores may be used to assist HI32 bus arbitration among several external hosts.

All external host processors that compete for mastership over the HI32 should work according to the same software protocol for handling over the HI32 from one host processor to another.

The personal hardware reset clears HS2-HS0.

6.6.1.9 Target Wait State Disable (TWSD) Bit 19The TWSD bit is used to disable PCI wait states (which are inserted by negating HTRDY), during a data phase.

If TWSD is cleared and the HI32 is in the PCI mode (HM=$1):

• the HI32 as the selected target in a read data phase from the HRXS, will insert PCI wait states if the HRXS is empty (HRRQ = 0). Wait states will be inserted until the data is transferred from the DSP side to the HRXS. Up to eight wait states may be inserted before a target initiated transaction termination (disconnect-C/Retry) will be generated.

• the HI32 as the selected target in a write data phase to the HTXR, will insert PCI wait states if the HTXR is full (HTRQ = 0). Wait states will be inserted until the data is transferred from the HTXR to the DSP side. Up to eight wait states may be inserted before a target initiated transaction termination (disconnect-C/Retry) will be generated.

• the HI32 as the selected target in a write data phase to the HCVR, will insert PCI wait states if a host command is pending (HC = 1). Wait states will be inserted until the pending host command is serviced. Up to eight wait states may be inserted before a target initiated transaction termination (disconnect-C/Retry) will be generated.

If TWSD is set and the HI32 is in the PCI mode (HM=$1):

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Table 6-16 Receive Data Transfer Format

HRF1

HRF0

DSP to Host Data Transfer Format


0 0 The two least significant bytes of two HRXS locations are output.

The three least significant HRXS bytes are output to HD23-HD0.

HDTFC

PCI bus

DTXS

HI32GDB/MDDB

HRXS

X

X

X

HDTFC

Host bus

DTXS

HI32GDB/MDDB

HRXS

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0 1 The three least significant HRXS bytes are output right aligned and zero extended.

The two least significant HRXS bytes are output to HD15-HD0.

1 0 The three least significant HRXS bytes are output right aligned and sign extended.

The two least significant HRXS bytes are output to HD15-HD0.

1 1 The three least significant HRXS bytes are output left aligned and zero filled.

The two middle HRXS bytes are output to HD15-HD0.

Table 6-16 Receive Data Transfer Format

HRF1

HRF0

DSP to Host Data Transfer Format


HDTFC

PCI bus

DTXS

HI32GDB/MDDB

$0

$0

HRXS

HDTFC

Host bus

DTXS

HI32GDB/MDDBX

HRXS

X

X

HDTFC

PCI bus

DTXS

HI32GDB/MDDB

S

S

HRXS

HDTFC

Host bus

DTXS

HI32GDB/MDDBX

HRXS

X

X

HDTFC

PCI bus

DTXS

HI32GDB/MDDB

$0

$0

HRXS

HDTFC

Host bus

DTXS

HI32GDB/MDDBX

HRXS

X

X

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• the HI32 as the selected target in a read transaction from the HRXS, will generate a target initiated transaction termination (disconnect-C) if the HRXS is empty (HRRQ = 0).

• the HI32 as the selected target in a write transaction to the HTXR, will generate a target initiated transaction termination (disconnect-C) if the HTXR is full (HTXR = 0).

• the HI32 as the selected target in a write transaction to the HCVR, will generate a target initiated transaction termination (disconnect-C) if a host command is pending (HC = 1).

TWSD is ignored when the HI32 is not in the PCI mode (HM≠$1).

The personal hardware reset clears TWSD.

6.6.1.10 HCTR Reserved Control Bits 31-20, 18-17, 13, 10, and 0These bits are reserved for future expansion, they are read as zeros and should be written with zeros for upward compatibility.

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6.6.2 HI32 Status Register (HSTR)

The HSTR is a 32-bit read-only status register used by the host processor to examine the status and flags of the HI32.

When the HSTR is read to the PCI bus (HM=$1), the HAD31-HAD0 signals are driven with the HSTR data during a read access.

In a 24-bit data Universal Bus mode (HM=$2 or $3 and HRF = $0), the HD23-HD0 signals are driven with the three least significant HSTR bytes during a read access.

In a 16-bit data Universal Bus mode (HM=$2 or $3 and HRF≠$0), the HD15-HD0 signals are driven with the two least significant bytes of the HSTR in a read access.

In PCI mode (HM = $1) memory space transactions, the HSTR is accessed if the PCI address is HI32_base_address: $014.

When in a Universal Bus mode (HM=$2 or $3), the HSTR is accessed if the HA10-HA3 value matches the HI32 base address (CBMA, see Section 6.6.11) and the HA2-HA0 value is $5.

The status bits are described in the following paragraphs.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HREQ HINT HF5 HF4 HF3 HRRQ HTRQ TRDY


Bit Name Function

0 TRDY Transmitter Ready

1 HTRQ Host Transmit Data Request

1 HRRQ Host Receive Data Request


6 HINT Host Interrupt A

7 HREQ Host Request

31-8 reserved

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6.6.2.1 Transmitter Ready (TRDY) Bit 0The TRDY status bit indicates that both the HTXR and the DRXR registers are empty. If TRDY is set to one, the data that the host processor writes to the HTXR will be immediately transferred to the DSP side of the HI32. This has many applications. For example: if the host processor issues a host command which causes the DSP56300 core to read the DRXR, the host processor can be guaranteed that the data it just transferred to the HI32 is what is being received by the DSP56300 core.

In order to support high speed data transfers, the HI32 host-to-DSP data path is a six word deep FIFO (five word deep in the Universal Bus modes, three word deep in the 32-bit mode, HM = $1 and HTF = $0). In PCI data transfers with HM = $1 and HTFπ$0, if TRDY is set, the HI32 will not insert wait states in the next six data transfers written by the host to the HTXR. In PCI data transfers with HM = $1 and HTF = $0 (i.e. 32-bit mode), if TRDY is set, the HI32 will not insert wait states in the next three data phases written by the host to the HTXR. In Universal bus mode data transfers, if TRDY is set, the HI32 will not insert wait states in the next five data transfers written by the host to the HTXR.

TRDY is cleared when the HTXR is written by the host processor.

Hardware, software and personal software resets set TRDY.

6.6.2.2 Host Transmit Data Request (HTRQ) Bit 1The HTRQ bit indicates that the host transmit data FIFO (HTXR) is not full and can be written by the host processor. HTRQ is set when the HTXR data is transferred to the DRXR. HTRQ is cleared when the HTXR is filled by host processor writes.

In the PCI mode: The HI32 as target in a write data phase to the HTXR, will deassert HTRDY, and insert up to eight PCI wait cycles, if HTRQ is cleared.

In a Universal Bus mode write to the HTXR, the HI32 slave will deassert HTA as long as HTRQ is cleared. HTRQ may be used to assert the external HIRQ signal if the TREQ bit is set. Regardless of whether the HTRQ host interrupt request is enabled, HTRQ provides valid status so that polling techniques may be used by the host processor.

Hardware, software and personal software resets set HTRQ.

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6.6.2.3 Host Receive Data Request (HRRQ) Bit 2The HRRQ bit indicates that the host slave receive data FIFO (HRXS) contains data from the DSP56300 core and may be read by the host processor.

In the PCI mode: The HI32 as a target in a read data phase from the HRXS, will deassert HTRDY, and insert up to eight PCI wait cycles, if HRRQ is cleared.

In a Universal Bus mode read from the HRXS, the HI32 slave will deassert HTA as long as HRRQ is cleared. HRRQ may be used to assert the HIRQ signal if the RREQ bit is set. Regardless of whether the HRRQ host interrupt request is enabled, HRRQ provides valid status so that polling techniques may be used by the host processor.

HRRQ functions in accordance with the value of the slave fetch type (SFT) bit in the HCTR.

Fetch (SFT = 1): HRRQ is always read as zero.

Pre-fetch (SFT = 0):The DSP-to-host data path is FIFO buffered. HRRQ reflects the status of the HRXS. HRRQ is cleared if the HRXS is empty, and set when data is transferred from the DTXS.

Hardware, software and personal software resets clear HRRQ.

6.6.2.4 Host Flags (HF5-HF3) Bits 5, 4 and 3 The HF5-HF3 bits in the HSTR indicate the state of host flags HF5-HF3 respectively, in the DSP Control Register (DCTR) on the DSP side. HF5-HF3 can be changed, albeit indirectly, only by the DSP56300 core.

HF5-HF3 are cleared by a hardware or software reset.

6.6.2.5 Host Interrupt A (HINT) Bit 6 The HINT bit reflects the status of the HINT bit in the DSP Control Register (DCTR) and the HINTA signal. HINT is set if the host interrupt A bit is set in the DCTR, and the HINTA signal is driven low. HINT is cleared if the host interrupt A is cleared in the DCTR, and the HINTA signal is driven low.

HINT is cleared by a hardware or software reset.

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6.6.2.6 Host Request (HREQ) Bit 7HREQ is set and cleared in accordance with the following table:

The personal hardware reset clears HREQ.

6.6.2.7 HSTR Reserved Status Bits 31-8These status bits are reserved for future expansion and read as zeros during host read operations.

TREQ RREQ HREQ

0 0 cleared

0 1 set if HRRQ = 1otherwise cleared

1 0 set if HTRQ = 1otherwise cleared

1 1 set if HTRQ = 1 or HRRQ = 1otherwise cleared

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6.6.3 Host Command Vector Register (HCVR)

The HCVR is a 32-bit read/write register used by the host processor to cause the DSP56300 core to execute a vectored interrupt. The host command feature is independent of any of the data transfer mechanisms in the HI32. It can be used to cause any of the 128 possible interrupt routines in the DSP to be executed.

When the HCVR is read to the PCI bus (HM=$1), the HAD31-HAD0 signals are driven with the HCVR data during a read access; and these signals are written to the HCVR in a write access.

In a 24-bit data Universal Bus mode (HM=$2 or $3 and HTF = $0 or HRF = $0), the HD23-HD0 signals are driven with the three least significant bytes of the HCVR in a read access; HD23-HD0 are written to the three least significant bytes of the HCVR, the most significant portion is zero filled during the HCVR write.

In a 16-bit data Universal Bus mode (HM=$2 or $3 and HTF≠$0 or HRF≠$0), the HD15-HD0 signals are driven with the two least significant bytes of the HCVR in a read access; HD15-HD0 are written to the two least significant bytes of the HCVR, the most significant portion is zero filled during the HCVR write.

In PCI mode (HM = $1) memory space transactions, the HCVR is accessed if the PCI address is HI32_base_address: $018.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HNMI HV6 HV5 HV4 HV3 HV2 HV1 HV0 HC


Bit Name Function

0 HC Host Command

7-1 HV6-HV0 Host Command Vector

15 HNMI Host Non Maskable Interrupt

31-16,14-8 reserved

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The HCVR is written in accordance with the byte enables (HC3/HBE3-HC0/HBE0 signals). Byte lanes that are not enabled are not written and the corresponding bits remain unchanged.

When in a Universal Bus mode (HM=$2 or $3), the HCVR is accessed if the HA10-HA3 value matches the HI32 base address (CBMA, see Section 6.6.11) and the HA2-HA0 value is $6.

If TWSD is cleared, the HI32 as the selected PCI target (HM=$1) in a write data phase to the HCVR will insert PCI wait states if a host command is pending (HC = 1). Wait states will be inserted until the pending host command is serviced. Up to eight wait states may be inserted before a target initiated transaction termination (disconnect-C/Retry) will be generated.

In a Universal Bus mode write to the HCVR, the HI32 will insert wait states if a host command is pending (HC = 1). Wait states will be inserted until the pending host command is serviced.

The HCVR bits are described in the following paragraphs.

6.6.3.1 Host Command (HC) Bit 0The HC bit is used by the host processor to handshake the execution of host command interrupt requests. Normally, the host processor sets HC to request a host command interrupt from the DSP56300 core. When the host command interrupt request is acknowledged by the DSP56300 core, the HC bit is cleared by the HI32 hardware. The host processor can read the state of HC to determine when the host command request has been serviced. The host processor cannot clear HC.

Setting HC causes host command pending (HCP) to be set in the DSR. The host can write HC and HV in the same write cycle if desired.

If HC is set:

• In the PCI mode: The HI32 as a target in a write data phase to the HCVR, will deassert HTRDY, and insert up to eight PCI wait cycles, until HC is cleared.

• In a Universal Bus mode: In a write transaction to the HCVR, the HI32 slave will deassert HTA, until HC is cleared.

The personal software reset clears HC.

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6.6.3.2 Host Vector (HV6-HV0) Bits 7-1The seven HV bits select the host command interrupt address. When the host command interrupt is recognized by the DSP56300 core interrupt control logic, the starting address of the interrupt executed is 2 × (HV6-HV0).

The host processor can select any of the 128 possible interrupt routine starting addresses in the DSP by writing the interrupt routine starting address divided by two into HV. This means that the host processor can force any of the existing interrupt routines (SSI, Timer, IRQA, IRQB, etc.) and can use any of the reserved or otherwise unused starting addresses provided they have been pre-programmed in the DSP. Non-maskable interrupts of DSP56300 core can be forced by the host processor by setting the host non-maskable interrupt (HNMI) bit in the HCVR. When HNMI set is recognized by the HI32 command interrupt logic, the host command interrupt is processed with the highest priority regardless of the current HI32 interrupt priority (as written in the DSP56300 core peripheral priority register (IPRP)).

CAUTIONMV6-HV0 should not be used with a value of zero - the reset location, as thislocation is normally programmed with a JMP instruction. Doing so willcause an improper short interrupt.

The personal hardware reset sets HV to the default host command vector, which is via programmable (see Section 6.10).

6.6.3.3 Host Non-Maskable Interrupt (HNMI) Bit 15The HNMI bit is used by the host processor to force the generation of the host command as non-maskable interrupt request. If HNMI and HC are set, the host command interrupt is processed with the highest priority regardless of the current HI32 interrupt priority (as written in the DSP56300 core peripheral priority register (IPRP)). If HNMI is cleared and HC is set, the host command interrupt is processed in accordance with the priority programmed in the IPRP register, and can be disabled by clearing HCIE in the DCTR.

The personal hardware reset clears HNMI.

6.6.3.4 HCVR Reserved Bits 31-16, 14-8These unused bits are reserved for future expansion and should be written with zeros for upward compatibility. They are read by the host processor as zeros.

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6.6.4 Host Slave Receive Data Register (HRXS)

The HRXS is the output stage of the slave DSP-to-host data path FIFO used for DSP-to-host data transfers. The HRXS cannot be accessed by the DSP56300 core.

The HRXS contains valid data when the HRRQ bit is set. Emptying the HRXS by host processor reads clears HRRQ.

The HRXS transfers the data to the HI32 data signals via the data transfer format converter (HDTFC). The value of the HRF bits in the HCTR define which bytes of the HRXS are output to the signals and their alignment. (See Section 6.5.9 and Section 6-16).

In PCI mode (HM = $1) memory space read transaction, the HRXS is accessed if the PCI address is between HI32_base_address: $01C and HI32_base_address: $FFFC.

In the PCI mode (HM = $1), HRXS is viewed by the host processor as a 16377 Dword read-only memory.

In PCI DSP-to-host data transfers via the HRXS, all four byte lanes are driven with data, in accordance with HRF1-HRF0 bits, regardless of the value of the byte enable signals (HC3/HBE3-HC0/HBE0).

When in a Universal Bus mode (HM = $2 or $3), the HRXS is accessed if the HA10-HA3 value matches the HI32 base address (CBMA, see Section 6.6.11) and the HA2-HA0 value is $7.

In a 24-bit data Universal Bus mode (HM = $2 or $3 and HRF = $0), the HRXS is viewed by the host processor as a 24-bit read-only register. HD23-HD0 signals are driven with all three bytes of the HRXS in a read access.

In a 16-bit data Universal Bus mode (HM = $2 or $3 and HRF≠$0), the HRXS is viewed by the host processor as a 16-bit read-only register. In a read access, the HD15-HD0 signals are driven with data from the two most significant bytes or two least significant bytes of the HRXS, as defined by the HRF bits in the HCTR.

When HRRQ is set and RREQ in the HCTR is set:

• the HREQ status bit will be set in the HSTR.

• the HIRQ signal will be asserted - if DMAE is cleared (in the Universal Bus modes)

• the HDRQ signal will be asserted - if DMAE is set (in the Universal Bus modes)

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If TWSD is cleared, the HI32 as the selected PCI target (HM = $1) in a read data phase from the HRXS will insert PCI wait states if the HRXS is empty (HRRQ = 0). Wait states will be inserted until the data is transferred from the DSP side to the HRXS. Up to eight wait states may be inserted before a target initiated transaction termination (disconnect-C/Retry) will be generated.

In a Universal Bus mode read from the HRXS the HI32 will insert wait states if the HRXS is empty (HRRQ = 0). Wait states will be inserted until the data is transferred from the DSP side to the HRXS.

Hardware, software and personal software resets empty the HRXS (HRRQ is cleared).

6.6.5 Host Master Receive Data Register (HRXM)

The HRXM is the output stage of the master DSP-to-host data path FIFO used for DSP-to-host data transfers. The HRXM cannot be accessed by the DSP56300 core or the host.

The HRXM transfers the data to the HI32 data signals via the data transfer format converter (HDTFC). The value of the FC bits in the DPMC define which bytes of the HRXM are output to the signals and their alignment. (See Section 6.5.9 and Table 6-5).

In the PCI mode (HM = $1) the DSP56300 core can clear the HI32 master-to-host bus data path and empty HRXM by setting the CLRT bit in the DPCR.

In PCI DSP-to-host data transfers via the HRXM, all four byte lanes are driven with data, in accordance with FC1-FC0 bits, regardless of the value of the byte enable signals (HC3/HBE3-HC0/HBE0).

Hardware, software and personal software resets empty the HRXM.

6.6.6 Host Transmit Data Register (HTXR)

The HTXR is the input stage of the host-to-DSP data path FIFO used for host-to-DSP data transfers. The HTXR cannot be accessed by the DSP56300 core.

The HTXR may be written if the HTRQ bit in the HSTR is set. Data should not be written to the HTXR until HTRQ is set to prevent previous data from being overwritten. Filling the HTXR by host processor writes, clears HTRQ.

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The HTXR receives data from the HI32 data signals via the data transfer format converter (HDTFC). The value of the FC bits in the HCTR or the HTF bits in the HCTR define which bytes of the PCI bus are written to the HTXR and their alignment. (See Table 6-5, Section 6.5.7, and Table 6-15).

In the PCI mode (HM = $1):As the active target, in a memory space write transaction, the HTXR is accessed if the PCI address is between HI32_base_address: $01C and HI32_base_address: $FFFC (i.e. the HTXR is viewed by the host processor as a 16377 Dword write-only memory).As the active master, all data read from the target being accessed is written to the HTXR.

In PCI host-to-DSP data transfers, data is written to the HTXR FIFO, in accordance with FC1-FC0 or HTF1-HTF0 bits, regardless of the value of the byte enable signals (HC3/HBE3-HC0/HBE0).

In a Universal Bus mode (HM=$2 or $3), the HTXR is accessed if the HA10-HA3 value matches the HI32 base address (CBMA, see Section 6.6.11) and the HA2-HA0 value is $7.

In a 24-bit data Universal Bus mode (HM=$2 or $3 and HTF = $0), the HTXR is viewed by the host processor as a 24-bit write-only register. HD23-HD0 signals are written to all three bytes of the HTXR in a write access.

In a 16-bit data Universal Bus mode (HM=$2 or $3 and HTF≠$0), the HTXR is viewed by the host processor as a 16-bit write-only register. In a write access, the HD15-HD0 signals are written to the two most significant bytes or least significant bytes of the HTXR, as defined by the HTF bits in the HCTR.

When HTRQ is set and TREQ in the HCTR is set:

• the HREQ status bit will be set in the HSTR.

• the HIRQ signal will be asserted - if DMAE is cleared (in the Universal Bus modes)

• the HDRQ signal will be asserted - if DMAE is set (in the Universal Bus modes)

If TWSD is cleared, the HI32 as the selected PCI target (HM=$1) in a write data phase to the HTXR will insert PCI wait states if the HTXR is full (HTRQ = 0). Wait states will be inserted until the data is transferred from the HTXR to the DSP side. Up to eight wait states may be inserted before a target initiated transaction termination (disconnect-C/Retry) will be generated.

In a Universal Bus mode write to the HTXR the HI32 will insert wait states if the HTXR is full (HTRQ = 0). Wait states will be inserted until the data is transferred from the HTXR to the DSP side.

Hardware, software and personal software resets empty the HTXR (HTRQ is set).

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6.6.7 Device/Vendor ID Configuration Register (CDID/CVID)

The CDID/CVID is a PCI standard 32-bit read-only register mapped into the PCI configuration space, when in the PCI mode or in mode 0 (HM=$1 or $0). CDID/CVID is accessed if a configuration read command is in progress and the PCI address is $00.

The DID15-DID0 bits identify the DSP. The VID15-VID0 bits identify the manufacturer of the DSP. The contents of CDID/CVID are hardwired and cannot be affected by any type of reset.

The CDID/CVID cannot be accessed by the host when not in the PCI mode (HM≠$1).

6.6.8 Status/Command Configuration Register (CSTR/CCMR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DID15 DID14 DID13 DID12 DID11 DID10 DID9 DID8 DID7 DID6 DID5 DID4 DID3 DID2 DID1 DID0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VID15 VID14 VID13 VID12 VID11 VID10 VID9 VID8 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

Bit Name Value(hardwired) Function

CVID 15-0 VID15-VID0 $1057 Vendor ID

CDID 31-16 DID15-DID0 via programmablesee Section 6.10

Device ID

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DPE SSE RMA RTA STA DST1 DST0 DPR FBBC

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SERE WCC PERR BM MSE

Not implemented, read as zero, should be written zero Reserved, read as zero and should be written zero

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Bit Name Function

CC

MR

1 MSE Memory Space Enable

2 BM Bus Master Enable

6 PERR Parity Error Response

7 WCC Wait Cycle Control (hardwired to zero)

8 SERE System Error Enable

9,5-3, 0 not implemented

15-10 reserved

CS

TR

23 FBBC Fast Back-to-Back Capable (hardwired to one)

24 DPR Data Parity Reported

26-25 DST1-DST0 DEVSEL Timing (hardwired to $1)

27 STA Signaled Target Abort

28 RTA Received Target Abort

29 RMA Received Master Abort

30 SSE Signaled System Error

31 DPE Detected Parity Error

22-16 reserved

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The CSTR/CCMR is a PCI standard 32-bit read/write register mapped into the PCI configuration space, when in the PCI mode or in mode 0 (HM=$1 or $0). CSTR/CCMR is accessed if a configuration read/write command is in progress and the PCI address is $04. In the Self Configuration mode (HM = $5): the DSP56300 core can indirectly access the CCMR. (see Section 6.7)

The CSTR/CCMR is written by the host in accordance with the byte enables. Byte lanes that are not enabled are not written and the corresponding bits remain unchanged.

The CSTR/CCMR cannot be accessed by the host when not in the PCI mode (HM≠$1).

The CSTR/CCMR bits are described in the following paragraphs.

6.6.8.1 Memory Space Enable (MSE) Bit 1The MSE bit is used to control the HI32 response to the PCI memory space accesses, when in the PCI mode (HM=$1). The HI32 memory space response is disabled if MSE is cleared and enabled if MSE is set.

The personal hardware reset clears MSE.

6.6.8.2 Bus Master Enable (BM) Bit 2The BM bit is used to control the HI32 ability to act as a master on the PCI bus, when in the PCI mode (HM=$1). If BM is cleared, the HI32 is disabled from acting as a bus master. If BM is set, the HI32 can function as a bus master. This bit affects the MARQ bit in the DSP side status register (DPSR): if BM is cleared, MARQ is also cleared.

The personal hardware reset clears BM.

6.6.8.3 Parity Error Response (PERR) Bit 6The PERR bit is used to control the HI32 response to parity errors, when in the PCI mode (HM=$1). If PERR is cleared: the HI32 does not drive HPERR. If PERR is set: if a parity error is detected the HI32 pulses the HPERR signal. If a parity error or HPERR low is detected, the HI32 sets the DPR bit in the CSTR/CCMR

In both cases the HI32 sets bit 15 (DPE) in the CSTR/CCMR, sets DPER in the DPSR, and generates a parity error interrupt request if PEIE, in the DPCR, is set.

The personal hardware reset clears PERE.

6.6.8.4 Wait Cycle Control (WCC) Bit 7The WCC bit is hardwired to zero, as the HI32 never executes address stepping.

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6.6.8.5 System Error Enable (SERE) Bit 8The SERE bit is used to enable the HSERR signal driving by the HI32, when in the PCI mode (HM = $1). If SERE is cleared, the HSERR signal disabled (i.e. high impedance). If SERE is set: if the force system error (SERF) bit in the DPCR is set and the HI32 is an active PCI agent, or an address parity error was detected, the HI32 pulses the HSERR signal and sets the signalled system error (SSE) bit in the CSTR.

The personal hardware reset clears SERE.

6.6.8.6 Fast Back-to-Back Capable (FBBC) Bit 23The FBBC indicates the HI32 supports fast back-to-back transactions as a target, when in the PCI mode (HM=$1). This bit is hardwired to one.

6.6.8.7 Data Parity Reported (DPR) Bit 24The DPR indicates the data parity error detected, when in the PCI mode (HM=$1). The DPR is set if the HI32 acts as a bus master and detects a data parity error or samples HPERR asserted while PERR bit is set in CCMR. The DPR bit is cleared when it is written with one by the host processor.

The personal hardware reset clears DPR.

6.6.8.8 DEVSEL Timing (DST1-DST0) Bits 26 and 25The DST1-DST0 bits encode the timing of the HDEVSEL signal, when in the PCI mode (HM=$1). These bits are hardwired to DST = $1, indicating that the HI32 belongs to the ‘medium DEVSEL timing’ class of the PCI devices.

6.6.8.9 Signaled Target Abort (STA) Bit 27The STA indicates a target-abort PCI bus event has been generated. When in the PCI mode (HM=$1) and the HI32, as a target device, terminates a transaction with target-abort, the STA is set. The STA bit is cleared when it is written with one by the host processor.

The personal hardware reset clears STA.

6.6.8.10 Received Target Abort (RTA) Bit 28The RTA indicates a target-abort PCI bus event has been generated. When in the PCI mode (HM=$1) and the HI32, as a master device, detects that its transaction is terminated with target-abort, the RTA is set. The RTA bit is cleared when it is written with one by the host processor.

The personal hardware reset clears RTA.

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6.6.8.11 Received Master Abort (RMA) Bit 29The RMA indicates a master-abort PCI bus state has been generated. When in the PCI mode (HM=$1) and the HI32, as a master device, terminates its transaction with master-abort, the RMA is set. The RMA bit is cleared when it is written with one by the host processor.

The personal hardware reset clears RMA.

6.6.8.12 Signaled System Error (SSE) Bit 30The SSE indicates a system error has occurred. When in the PCI mode (HM=$1) and the HI32 asserts HSERR signal, the SSE is set. The SSE bit is cleared when it is written with one by the host processor.

The personal hardware reset clears SSE.

6.6.8.13 Detected Parity Error (DPE) Bit 31The DPE indicates a parity error has been detected by the HI32 hardware. When in the PCI mode (HM=$1) and the HI32 detects either address or data parity error, the DPE is set. The DPE bit is cleared when it is written with one by the host processor.

The personal hardware reset clears DPE.

6.6.8.14 CSTR Reserved Bits 23-16These unused bits are reserved for future PCI expansion and read by the host processor as zeros.

6.6.8.15 CCMR Reserved Bits 15-10These bits are reserved for future PCI expansion and should be written with zeros for upward compatibility. They are read by the host processor as zeros.

6.6.8.16 CCMR Not Implemented Bits 9, 5-3These not implemented bits are reserved for future expansion and should be written with zeros for upward compatibility. They are read by the host processor as zeros.

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6.6.9 Class Code/Revision ID Configuration Register (CCCR/CRID)

The CCCR/CRID is a PCI standard 32-bit read-only register mapped into the PCI configuration space, when in the PCI mode or in mode 0 (HM=$1 or $0). CCCR/CRID is accessed if a configuration read command is in progress and the PCI address is $08.

The RID7-RID0 bits specify the DSP specific identifier (as an extension of Device ID).

The CCCR/CRID cannot be accessed by the host when not in the PCI mode (HM≠$1)

The contents of CCCR/CRID are hardwired and not affected by any type of reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0

Bit Name Value(hardwired) Function

CR

ID 7-0 RID7-RID0 via programmablesee Section 6.10

Revision ID

CC

CR

15-8 PI7-PI0 PCI Device Program Interface

23-16 SC7-SC0 PCI Device Sub-Class

31-24 BC7-BC0 PCI Device Base Class

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6.6.10 Header Type/Latency Timer Configuration Register (CHTY/CLAT)

The CHTY/CLAT is a PCI standard 32-bit read/write register mapped into the PCI configuration space, when in the PCI mode or in mode 0 (HM=$1 or $0). The CHTY/CLAT is accessed if a configuration read/write command is in progress and the PCI address is $0C. In the Self Configuration mode (HM = $5): the DSP56300 core can indirectly access the CLAT (Section 6.7).

The CHTY/CLAT is written in accordance with the byte enables. Byte lanes that are not enabled are not written and the corresponding bits remain unchanged.

The CHTY/CLAT cannot be accessed by the host when not in the PCI mode (HM≠$1).

The CHTY/CLAT bits are described in the following paragraphs.

6.6.10.1 Header Type (HT7-HT0) Bits 23-16The read-only bits HT7-HT0 identify the layout of bytes $10-$3F in the configuration space and also whether or not the device contains multiple functions. This byte is hardwired to the value $00.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

HT7 HT6 HT5 HT4 HT3 HT2 HT1 HT0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LT7 LT6 LT5 LT4 LT3 LT2 LT1 LT0

Not implemented, read as zero and should be written zero

Bit Name Function

7-0 not implemented

CLAT 15-8 LT7-LT0 Latency Timer (High)

CHTY 23-16 HT7-HT0 Header Type (hardwired to $00)

31-24 not implemented

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6.6.10.2 Latency Timer (LT7-LT0) Bits 15-8The read/write bits LT7-LT0 have two functions:

In the PCI mode (HM = $1): LT7-LT0 specify, in units of PCI bus clock cycles, the value of the latency timer for this PCI bus master.

In the Universal Bus modes (HM = $2,$3) with HIRH cleared: LT7-LT0 specify, in units of DSP56300 core clock cycles, the duration of the HIRQ pulse. The duration of the HIRQ pulse is given by the following equation:

HIRQ_PULSE_WIDTH = (LT[7:0]_Value+ 1) • DSP56300_Core_clock_cycle

This bits can be written by the DSP56300 core in the Self Configuration mode (see Section 6.7.2).

The personal hardware reset clears LT7-LT0.

6.6.10.3 CHTY/CLAT Not Implemented Bits 31-24,7-0These not implemented bits are reserved for future expansion and should be written with zeros for upward compatibility. They are read by the host processor as zeros.

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6.6.11 Memory Space Base Address Configuration Register (CBMA)

The CBMA is a PCI standard 32-bit read/write register mapped into the PCI configuration space, when in the PCI mode or in mode 0 (HM=$1 or $0). The CBMA is accessed if a configuration read/write command is in progress and the PCI address is $10. The CBMA controls the HI32 mapping into the PCI memory space and the Universal Bus mode space. In the Self Configuration mode (HM = $5): the DSP56300 core can indirectly access the CBMA (Section 6.7).

The CBMA is written in accordance with the byte enables. Byte lanes that are not enabled are not written and the corresponding bits remain unchanged.

The CBMA cannot be accessed by the host when not in the PCI mode (HM≠$1).

The CBMA bits are described in the following paragraphs.

6.6.11.1 Memory Space Indicator (MSI) Bit 0The MSI determines that CBMA register maps the HI32 into the PCI memory space. The MSI bit is hardwired to zero and is not affected by any type of reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PM31 PM30 PM29 PM28 PM27 PM26 PM25 PM24PM23/GB10

PM22/GB9

PM21/GB98

PM20/GB7

PM19/GB6

PM18/GB5

PM17/GB4

PM16/GB3

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PM15 PM14 PM13 PM12 PM11 PM10 PM9 PM8 PM7 PM6 PM5 PM4 PF MS1 MS0 MSI

Hardwired to zero

Bit Name Function

0 MSI Memory Space Indicator (Hardwired to zero)

2-1 MS1-MS0 Memory Space (Hardwired to zeros)

3 PF Pre-fetch (Hardwired to zero)

15-4 PM15-PM4 Memory Base Address Low (Hardwired to zeros)

31-16 PM31-PM16 Memory Base Address High

23-16 GB10-GB3 Universal Bus mode Base Address

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6.6.11.2 Memory Space (MS1-MS0) Bits 2 and 1The MS1 and MS0 bits encode that CBMA register is 32 bits wide and mapping can be done anywhere in the 32 bit memory space. The MS1 and MS0 are hardwired to zeros and is not affected by any type of reset.

6.6.11.3 Pre-fetch (PF) Bit 3The PF bit indicates that the data is pre-fetchable or not. PF is hardwired to zero and is not affected by any type of reset.

6.6.11.4 Memory Base Address (PM31-PM16) Bits 31-4The PM31-PM4 bits define the HI32 base address when it is mapped into the PCI memory space. The PM15-PM4 are hardwired to zero, while PM31-PM16 can be written by the PCI master during system configuration.

The HI32 target occupies 16384 Dwords of the PCI memory space. The HI32 is selected by the 20 most significant PCI address signals HAD31-HAD12, and the twelve least significant address signals HAD11-HAD0 are used to select the HI32 registers on the host side (see Figure 6-2).

The personal hardware reset clears PM31-PM16.

6.6.11.5 Universal Bus Mode Base Address (GB10-GB3) Bits 23-16The GB10-GB3 bits define the HI32 base address when it is mapped into the Universal Bus mode space. The remaining CBMA bits are ignored in Universal Bus modes.

The HI32 slave occupies eight locations in the Universal Bus mode space. The HI32 is selected by the eight most significant address signals HA10-HA3, and the three least significant address signals HA2-HA0 are used to select the HI32 registers on the host side.

All reserved register addresses are read as zeros and should be written with zeros for upward compatibility (see Figure 6-4).

The personal hardware reset clears GB10-GB3.

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6.6.12 Interrupt Line - Interrupt Signal Configuration Register (CILP)

The CILP is a PCI standard 32-bit read-only register mapped into the PCI configuration space, when in the PCI mode or in mode 0 (HM=$1 or $0). CILP is accessed if a configuration read command is in progress and the PCI address is $FC. The CILP register cannot be accessed by the DSP56300 core.

ML7-ML0: MAX_LAT is used for specifying how often the device needs to gain access to the PCI bus. As the HI32 has no major requirements for the settings of Latency Timers, these bits are hardwired to zero.

MG7-MG0: MIN_GNT is used for specifying how long a burst the device needs. As the HI32 has no major requirements for the settings of Latency Timers, these bits are hardwired to zero.

IP7-IP0: The Interrupt Signal bits specify which interrupt the device uses. A value of 1 corresponds to PCI INTA.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 MG7 MG6 MG5 MG4 MG3 MG2 MG1 MG0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 IL7 IL6 IL5 IL4 IL3 IL2 IL1 IL0

Hardwired to zero Hardwired to one

Bit Name Value(hardwired)

Interrupt Line 7-0 IL7-IL0 ---

Interrupt Signal 15-8 IP7-IP0 $01

MIN_GNT 23-16 MG7-MG0 $00

MAX_LAT 31-24 ML7-ML0 $00

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SELF CONFIGURATION MODE


IL7-IL0: These read/write bits are used to communicate PCI interrupt line routing information. POST software will write the routing information into these bits as it initializes and configures the PCI system.

The CILP cannot be accessed by the host when not in the PCI mode (HM≠$1).

The 24 most significant bits of the CILP register are hardwired and are not affected by any type of reset. The personal hardware reset clears IL7-IL0.

6.7 SELF CONFIGURATION MODE

The Self Configuration mode is used to program the HI32 base address and HIRQ pulse width, for operation in the Universal Bus mode; and for programming the configuration registers for operation in a PCI environment without an external system configurator.

In the Self Configuration mode (HM = $5), the DSP56300 core can indirectly write to all the writable HI32 configuration registers. The DSP56300 core writes the Dword data to the AR bits of the DPMC and DPAR registers (the remaining bits in these registers are ignored). The two most significant bytes of the Dword are written to the DPMC, the two least significant, to the DPAR. The data is transferred to the configuration register by the HI32 hardware. The registers are written sequentially beginning with the CSTR/CCMR register (location $04). After each write to the DPAR, the data is transferred to the accessed register and an internal pointer is advanced to point to the next Dword location in the configuration space.

Note: At least one DSP instruction must appear between writing the Self Configuration mode (HM2-HM0 = $5) and first write to the DPAR if the first write is a one DSP clock cycle instruction. (e.g. move immediate and move from external memory are more than one clock cycle)

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SELF CONFIGURATION MODE

6.7.1 Self Configuration Procedure for the PCI Mode

Example 6-1 Self Configuration Procedure for the PCI Mode

6.7.2 Self Configuration Procedure for the Universal Bus Mode

Example 6-2 Self Configuration Procedure for the Universal Bus Mode

M_DCTR equ DCTR_ADDR ; HI32 via programmed address :$5M_DPMC equ DPMC_ADDR ; HI32 via programmed address :$6M_DPAR equ DPAR_ADDR ; HI32 via programmed address :$8movep #$500000, x: M_DCTR ; enter self configuration modemovep #BASE_ADDRESS, x: M_DPMC ; CBMA Data (location $10)movep #CCMR_DATA, x: M_DPAR ; write CSTR & CCMR (location $04)movep #$0, x: M_DPAR ; dummy write to location $08movep #CLAT_DATA, x: M_DPAR ; write CLAT (location $0C)movep #$0, x: M_DPAR ; write CBMA (location $10)movep #$0, x: M_DCTR ; return to personal software reset

M_DCTR equ DCTR_ADDR ; HI32 via programmed address :$5M_DPMC equ DPMC_ADDR ; HI32 via programmed address :$6M_DPAR equ DPAR_ADDR ; HI32 via programmed address :$8movep #$500000, x: M_DCTR ; enter self configuration modemovep #BASE_ADDRESS, x: M_DPMC ; CBMA Data (location $10)movep #$0, x: M_DPAR ; dummy write to location $04movep #$0, x: M_DPAR ; dummy write to location $08movep #HIRQ__DURATION, x: M_DPAR ; write CLAT (location $0C)movep #$0, x: M_DPAR ; write CBMA (location $10)

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HOST PORT SIGNALS


6.8 HOST PORT SIGNALS Table 6-17 Host Interface Port Signals

HI32 Port Signal PCI Mode Enhanced General Bus

Mode General Bus Mode GPIO Mode

HP0 HAD0 HA3 HIO0HP1 HAD1 HA4 HIO1HP2 HAD2 HA5 HIO2HP3 HAD3 HA6 HIO3HP4 HAD4 HA7 HIO4HP5 HAD5 HA8 HIO5HP6 HAD6 HA9 HIO6HP7 HAD7 HA10 HIO7HP8 HAD8 HD0 HIO8HP9 HAD9 HD1 HIO9HP10 HAD10 HD2 HIO10HP11 HAD11 HD3 HIO11HP12 HAD12 HD4 HIO12HP13 HAD13 HD5 HIO13HP14 HAD14 HD6 HIO14HP15 HAD15 HD7 HIO15HP16 HC0/HBE0 HA0 HIO16HP17 HC1/HBE1 HA1 HIO17HP18 HC2/HBE2 HA2 HIO18HP19 HC3/HBE3 UNUSED1 HIO19HP20 HTRDY HDBEN HIO20HP21 HIRDY HDBDR HIO21HP22 HDEVSEL HSAK HIO22HP23 HLOCK HBS2 HIO23HP24 HPAR HDAK2 disconnectedHP25 HPERR HDRQ disconnectedHP26 HGNT HAEN disconnectedHP27 HREQ HTA disconnectedHP28 HSERR HIRQ disconnectedHP29 HSTOP HWR/HRW3 disconnectedHP30 HIDSEL HRD/HDS3 disconnectedHP31 HFRAME UNUSED4

HP32 HCLK UNUSED4

HP33 HAD HD85 disconnectedHP34 HAD HD95 disconnectedHP35 HAD HD105 disconnectedHP36 HAD HD115 disconnected

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HOST PORT SIGNALS

HP37 HAD HD125 disconnectedHP38 HAD HD135 disconnectedHP39 HAD HD145 disconnectedHP40 HAD HD155 disconnectedHP41 HAD HD166, 7 disconnectedHP42 HAD HD176, 7 disconnectedHP43 HAD HD186, 7 disconnectedHP44 HAD HD196, 7 disconnectedHP45 HAD HD206, 7 disconnectedHP46 HAD HD216, 7 disconnectedHP47 HAD HD226, 7 disconnectedHP48 HAD HD236, 7 disconnectedHP49 HRST HRST3

HP50 HINTANote: 1. Must be forced or pulled to Vcc or GND

2. Schmitt trigger buffer on input - should be forced or pulled to Vcc if not used3. Schmitt trigger buffer on input4. Must be forced or pulled up to Vcc5. Should be pulled to Vcc or GND if not used6. Should be forced or pulled to Vcc or GND if not used7. Output is high impedance if HRF ≠ $0. Input is disconnected if HTF ≠ $0.

HI32 Port Signal PCI Mode Enhanced General Bus

Mode General Bus Mode GPIO Mode

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Table 6-18 Host Port Signals - Detailed Description (Sheet 1 of 13)HI32Port Pina

HI32 Mode

PCI Enhanced Universal Universal GPIO

HP7-HP0 HAD15-HAD0Address/Data Multiplexed BusTri-state, bidirectional bus.

During the first clock cycle of a transaction HAD31-HAD0 contain the physical byte address (32 bits). During subsequent clock cycles, HAD31-HAD0 contain data.

HA10-HA3Address BusInput signal.

This bus selects the HI32 register to be accessed. HA10-HA3 select the HI32 and HA2-HA0 select the particular register of the HI32 to be accessed.

PB15-PB0

HP15-HP8 HD7-HD0Data BusTri-state, bidirectional bus.

Used to transfer data between the host processor and the HI32. This bus is released (disconnected) when the HI32 is not selected by HA10-HA0. The HD23-HD0 signals are driven by the HI32 during a read access, and are inputs to the HI32 during a write access. HD23-HD16 outputs are high impedance if HRF≠$0. HD23-HD16 inputs are disconnected if HTF≠$0.

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HP18-HP16 HC3/HBE3-HC0/HBE0 Bus Command/Byte EnablesTri-state, bidirectional bus.

During the address phase of a transaction, HC3/HBE3- HC0/HBE0 define the bus command. During the data phase HC3/HBE3-HC0/HBE0 are used as byte enables. The byte enables determine which byte lanes carry meaningful data.

HA2-HA0Address BusInput signal.

This bus selects the HI32 register to be accessed. HA10-HA3 select the HI32 and HA2-HA0 select the particular register of the HI32 to be accessed.

PB18-PB16

UNUSED

Must be forced or pulled to Vcc or GND.

PB20


HI32 Mode


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HTRDY Target ReadySustained tri-state bidirectional signal.d

Indicates the target agent’s ability to complete the current data phase of the transaction. HTRDY is used in conjunction with HIRDY. A data phase is completed on any clock both HIRDY and HTRDY are sampled asserted. HTRDY is asserted if:

• during a data read valid data is present on HAD31-HAD0 (HRRQ = 1 in the HSTR).

• during a data write it indicates the HI32 is ready to accept data (HTRQ = 1 in the HSTR).

• during a vector write it indicates the HI32 is ready to accept a new host command (HC = 0 in the HCVR).

Wait cycles are inserted until both HIRDY and HTRDY are asserted together.

HDBENHost Data Bus EnableOutput signal.

Asserted during HI32 accesses.When asserted the external (optional) data transceiver outputs are enabled. When deasserted the external transceiver outputs are high impedance.

PB20


HI32 Mode


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HIRDYInitiator Ready Sustained tri-state bidirectional signal.c

Indicates the initiating agent’s ability to complete the current data phase of the transaction. HIRDY is used in conjunction with HTRDY. A data phase is completed on any clock both HIRDY and HTRDY are sampled asserted. Wait cycles are inserted until both HIRDY and HTRDY are asserted together. The HI32 deasserts HIRDY if it cannot complete the next data phase.

HDBDRHost Data Bus DirectionOutput signal.HDBDR is driven high on write data transfers and driven low on read data transfers. This signal is normally high.

HDEVSELDevice SelectSustained tri-state bidirectional

signal.c

When actively driven, indicates the driving device has decoded its address as a target of the current access. As an input it indicates whether any device on the bus has been selected.

HSAKHost Select AcknowledgeActive low output signal.Used to acknowledge the host processor that the HI32 has identified its address as a slave. HSAK is asserted when the HI32 is the selected slave; otherwise HSAK is released.


HI32 Mode


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HLOCKLockSustained tri-state bidirectional

signal.c

HLOCK indicates an atomic operation that may require multiple transactions to complete. When HLOCK is asserted, non-exclusive transactions to the HI32 will be ‘retried’ (i.e. this is an entire resource lock).

HBS(Bus Strobe)Schmitt trigger input signal.Asserted at the start of a bus cycle (for half of a clock cycle) providing an “early bus start” signal. This enables the HI32 to respond (HTA valid) earlier.HBS should be forced or pulled up to Vcc if not used (e.g. ISA bus).

HPARParityTri-state, bidirectional signal.Even parity across HAD31-HAD0 and HC3/HBE3-HC0/HBE0. The master drives HPAR during address and write data phases; the target drives HPAR during read data phases.

HDAKHost DMA AcknowledgeSchmitt trigger input signal.HDAK indicates that the external DMA channel is accessing the HI32. The HI32 is selected as a DMA device if HDAK and HWR or HRD (in the double-strobe mode) or HDAK and HDS (in the single-strobe mode) are asserted. HDAK should be forced or pulled up to Vcc if not used.

Disconnected


HI32 Mode


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HPERRParity ErrorSustained tri-state bidirectional

signal.c

Used for reporting of data parity errors. HPERR must be driven active (by the agent receiving data) two clocks following the data (i.e. one clock following the HPAR signal) when a data parity error is detected.

HDRQDMA RequestOutput Signal.Used to support ISA/EISA-type DMA data transfers.HDRQ is asserted by the HI32 when a DMA request (receive and/or transmit) is generated in the HI32. HDRQ is deasserted when the DMA request source is cleared (HDAK is asserted), masked (by RREQ = 0 or TREQ = 0) or disabled (DMAE = 0).The polarity of HDRQ signal is controlled by HDRP bit in the DCTR.

Disconnected

HGNT Bus GrantInput signal.Indicates to the HI32 that it has been granted mastership of the bus.If not used this signal should be forced or pulled up to Vcc.

HAENHost Address EnableInput signal.Enables ISA/EISA DMA / I/O type accesses.When high, the HI32 will respond to DMA cycles only (if DMAE = 1 in the DCTR, if DMAE = 0 the HI32 will ignore the access).When low, the HI32 responds when it identifies its address (i.e. ISA/EISA DMA / I/O type-space accesses).

Disconnected


HI32 Mode


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HREQ Bus RequestTri-state, Output signal.Indicates to the arbiter that the HI32 desires use of the bus.HREQ is deasserted in the same PCI clock that the HI32 asserts HFRAME.As during the STOP reset HREQ is high impedance, an external pull-up should be connected if it is connected to the PCI bus arbiter.

HTAHost Transfer Acknowledge Tri-state, Output signal.Used for high speed data transfer between the HI32 and an external host, when the host uses a non-interrupt driven handshake mechanism. If the HI32 deasserts HTA at the beginning of the host access, the host should extend the access as long as HTA is deasserted. The polarity of the HTA signal is controlled by HTAP in the DCTR.The HTA signal is asserted if:during a data read valid data is present on HD23-HD0 (HRRQ = 1 in the HSTR). during a data write it indicates the HI32 is ready to accept data (HTRQ = 1 in the HSTR). during a vector write it indicates the HI32 is ready to accept a new host command (HC = 0 in the HCVR).

Disconnected


HI32 Mode


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HSERRSystem ErrorActive low, open drain output signalb.Used for reporting address parity errors and other errors where the result will be catastrophic. Asserted for a single PCI clock by the HI32.

HIRQ Host Interrupt RequestActive low, output signalb.Used by the HI32 to request service from the host processor. HIRQ may be connected to an interrupt request signal of a host processor, a transfer request of a DMA controller or a control input of external circuitry. HIRQ is initially asserted by the HI32 when an interrupt request is enabled (TREQ = 1 or RREQ = 1) and the corresponding data path is ready for a data transfer.If the HIRH bit in the DCTR is cleared: HIRQ assertion is a pulse who’s width is controlled by the CLAT register.If HIRH is set: HIRQ is deasserted at the beginning of a corresponding host data access (read or write), or masked (by TREQ = 0 or RREQ = 0) or disabled (DMAE = 1).HIRQ will be asserted again, after the host access (regardless of the HIRH value), if enabled and the corresponding data path is ready for a data transfer.The HIRQ drive (driven or open drain) is controlled by the HIRD bit in the DCTR.

Disconnected


HI32 Mode


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HSTOP StopSustained tri-state bidirectional signal.b

Indicates the current target is requesting the master to stop the current transaction.

HWR/HRWHost Write/Read-WriteSchmitt trigger input signal.When in the double-strobe mode of the HI32 (HDSM = 0), this signal functions as host write input strobe (HWR). The host processor initiates a write access by asserting HWR. Data input is latched with the rising edge of HWR. When in the single-strobe mode of the HI32 (HDSM = 1), this signal functions as host read-write (HRW) input. It selects the direction of data transfer for each host processor access: from the HI32 to the host processor when HRW is asserted and from the host processor to the HI32 when HRW is deasserted. The polarity of the HRW signal is controlled by HRWP bit in the DCTR. NOTE: The simultaneous assertion of HRD and HWR is illegal.

Disconnected


HI32 Mode


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HIDSEL Initialization Device SelectInput signal.Used as a chip select in lieu of the upper 21 address lines during configuration read and write transactions.

HRD/HDS Host Read/Data Strobe Schmitt trigger input signal.When in the double-strobe mode of the HI32 (HDSM = 0), this signal functions as the host read strobe (HRD). The host processor initiates a read access by asserting HRD. Data output may be latched with the rising edge of HRD. When in the single-strobe mode of the HI32 (HDSM = 1), this signal functions as the host data strobe (HDS). The host processor initiates a read access by asserting HDS with HRW asserted. Data output may be latched with the rising edge of HDS. The host processor initiates a write access by asserting HDS with HRW deasserted. Data input is latched by the HI32 with the rising edge of HDS.NOTE: The simultaneous assertion of HRD and HWR is illegal.

Disconnected

HFRAME Cycle FrameSustained tri-state bidirectional signal.c

Driven By the current master to indicate the beginning and duration of an access. HFRAME is deasserted in the final data phase of the transaction.

UNUSEDMust be forced or pulled up to Vcc.


HI32 Mode


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HCLKBus ClockInput signal.Provides timing for all transactions on PCI. All other PCI signals are sampled on the HCLK rising edge.

UNUSEDMust be forced or pulled up to Vcc.

HP40-HP33 HAD31-HAD16Address/Data Multiplexed BusTri-state, bidirectional bus.During the first clock of a transaction HAD31-HAD0 contain the physical byte address (32 bits). During subsequent clock HAD31-HAD0 contain data.

HD15-HD8Data BusTri-state, bidirectional bus.Used to transfer data between the host processor and the HI32. This bus is released (disconnected) when the HI32 is not selected by HA10-HA0. The HD15-HD0 signals are driven by the HI32 during a read access, and are inputs to the HI32 during a write access. When operating with a host bus less than 16 bits wide, the HD15-HD8 signals that are not used for transferring data must be pulled to Vcc or to GND. For example: when operating with a 8-bit bus, HP40-HP33 must be pulled up to Vcc or pulled down to GND.NOTE: It is recommended to pull these unused data lines to GND, as pulling these lines to Vcc will set the corresponding bits in the HCTR, when the external host writes to this register.

Disconnected


HI32 Mode


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HP48-HP41 HD23-HD16Data BusTri-state, bidirectional bus.Used to transfer data between the host processor and the HI32. This bus is released (disconnected) when the HI32 is not selected by HA10-HA0. The HD23-HD16 signals are driven by the HI32 during a read access, and are inputs to the HI32 during a write access. HD23-HD16 outputs are high impedance if HRF≠$0. HD23-HD16 inputs are disconnected if HTF≠$0. When operating with a host bus less than 24 bits wide, the data signals that are not used for transferring data must be forced or pulled to Vcc or to GND. For example: when operating with a 16-bit bus (e.g. ISA bus), HP48-HP41 must be forced or pulled up to Vcc or pulled down to GND.NOTE: It is recommended to force or pull these unused data lines to GND, as forcing or pulling these lines to Vcc will set the corresponding bits in the HCTR, when the external host writes to this register.

Disconnected

HRSTHardware ResetInput signal.Forces the HI32 PCI sequencer to the initial state. All signals are forced to the disconnected state.HRST is asynchronous to HCLK.

HRSTHardware ResetSchmitt trigger input signal.Forces the HI32 to its initial state. All signals are forced to the disconnected state. The polarity of the HRST signal is controlled by HRSP bit in the DCTR.


HI32 Mode


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HINTAHost Interrupt AActive low, open drain output signalb.Used by the HI32 to request service from the host processor. HINTA may be connected to an interrupt request signal of a host processor, a control input of external circuitry, or be used as a general purpose open-drain output. HINTA is asserted by the HI32 when HINT, in the DCTR, is set by the DSP56300 core.HINTA is released (high impedance) when HINT, in the DCTR, is cleared by the DSP56300 core.HINTA is asynchronous to HCLK.

a. This list does not include Vcc and Ground supply signals.The GPIO pin is controlled by the corresponding bits in the port data and port direction registers.

b. Open Drain output signal is driven, when asserted, by the HI32. When deasserted the signal is released (high impedance). This enables using a multi-slave configuration. An external pull-up, must be connected externally for proper operation.

c.


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INTERRUPT VECTORS

6.9 INTERRUPT VECTORS

Table 6-19 Interrupt Vectors

6.10 VIA PROGRAMMING

Below is a table of the DSP56305 via-programmable registers:

Vector / 2 Interrupt Activated by Priority

Via Programmable Host Command (default) HC (HCVR) Highest

Lowest

PCI Transaction Termination TO, TRTY, TDIS (DPSR)

Via Programmable Base + 1 PCI Transaction Abort TAB, MAB (DPSR)

Via Programmable Base + 2 PCI Parity Error DPER, APER (DPSR)

Via Programmable Base + 3 PCI Transfer Complete HDTC (DPSR)

Via Programmable Base + 4 PCI Master Receive MRRQ (DPSR)

Via Programmable Base + 5 Slave Receive SRRQ (DSR)

Via Programmable Base + 6 PCI Master Transmit MTRQ (DPSR)

Via Programmable Base + 7 Slave Transmit STRQ (DSR)

Via Programmable Base + 8 PCI Master Address MARQ (DPSR)

Register Bits Value Meaning

CDID CDID15-CDID0 $1802 DSP56305

CCCR CCCR23-CCCR0 $048000 $04:(Multimedia Device)$80:(Other Multimedia Device)$00:(Default Program Interface)

CRID CRID7-CRID0 $00 Rev 0

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EXAMPLES OF HOST TO HI32 CONNECTIONS


6.11 EXAMPLES OF HOST TO HI32 CONNECTIONS

Figure 6-5 Connection to PCI Bus

AD31-AD0

C3/BE3-C0/BE0

FRAME

IRDY

TRDY

STOP

PAR

DEVSEL

PERR

SERR

REQ

GNT

IDSEL

RST

CLK

HAD31-HAD0

HC3/HBE3-HC0/HBE0

HFRAME

HIRDY

HTRDY

HSTOP

HPAR

HDEVSEL

HPERR

HSERR

HREQ

HGNT

HIDSEL

HRST

HCLK

HI32

DSP56305PCI Bus(initiator/target) (target/initiator)

LOCK HLOCK

INTA HINTA

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Figure 6-6 Connection to 16-Bit ISA/EISA Data Bus)

Note: HI32 may be externally buffered to drive the current required by the ISA/EISA standard. HI32 inputs should be externally buffered if the other ISA/EISA agents are not “3 Volt friendly” as defined in the PCI specifications.

HDBEN

HDBDR

BUF

HA[10]

HAEN

HD[15:0]

HTA

HWR

HRD

HSAK

HIRQ

HDRQ

HDAK

DSP56305

HRST

HI32

D[15:0]

SBHE

CHRDY

DRQ

IOWC

IORC

IO16

AEN

IRQ

DAK

RESDRV

ISA

Host(master) (slave)

HA[9]SA[0]

HA[8:3]SA[9:4]

HA[2:0]SA[3:1]

HBSVcc

*

*

*

* Open Collector

HD[23:16]

HP31Vcc

HP32Vcc

HP19Vcc

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Figure 6-7 Example of Connection to DSP56300 Core Port A Bus

Note: If the HI32’s DSP and the host DSP use the same EXTAL clock, the HI32 can operate synchronously at its maximum throughput of three clock cycles/word (e.g. for a 66MHz clock the HI32 throughput is 22 Mwords/sec = 66 Mbytes/sec)

D[23:0]

A[10:0]

TA

WR

RD

AA0

IRQA

HA[10:0]

HAEN

HD[23:0]

HTA

HWR

HRD

HIRQ

Port A

DSP56301

(master)HI32

DSP56301

(slave)

(master) (slave)

HBSBS

HDAKVcc

HP31Vcc

HP32Vcc

HP19Vcc

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SECTION 7

ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI)

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Enhanced Synchronous Serial Interface (ESSI)

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-37.2 ESSI Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-37.3 ESSI Data and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . .7-47.4 ESSI Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-137.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-427.6 GPIO/ESSI Selection and GPIO Usage . . . . . . . . . . . . . . . . . .7-52

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Introduction


7.1 INTRODUCTION

The Enhanced Synchronous Serial Interface (ESSI) provides a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Motorola Serial Peripheral Interface (SPI). The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator.

There are two independent and identical Enhanced Synchronous Serial Interfaces in the DSP56305: ESSI0 and ESSI1. For the sake of simplicity, a single generic ESSI is described. Each ESSI can be accessed through a port, as indicated in Figure 7-2. Any unused ESSI pins may be used as GPIO pins.

The ESSI has three principal modes of operation, as shown in Figure 7-21. The Normal mode of operation is used to transfer data at a periodic rate, one word per period. The Network mode is similar in that it is also intended for periodic transfers; however, it supports up to 32 words (time slots) per period. The Network mode can be used to build Time Division Multiplexed (TDM) networks. In contrast, the On-demand mode is intended for non-periodic transfers of data. This mode can be used to transfer data serially at high speed when the data become available. This mode offers a subset of the SPI protocol. The On-demand mode is programmed as a submode of Network mode.

The ESSI block diagram is shown in Figure 7-1. This interface is synchronous because all serial transfers are synchronized to a clock.

Note: This should not be confused with what is known as the Asynchronous channels mode of the ESSI, in which separate clocks and frame sync signals are used for the receiver and transmitter. In this mode, the ESSI is still a synchronous device, because all transfers are synchronized to these clocks.

Since each ESSI unit can be configured with one receiver and three transmitters, the two units can be used together for surround sound applications (which need two digital input channels and six digital output channels). The ESSI can operate with more than one active transmitter only in Synchronous mode.

7.2 ESSI ENHANCEMENTS

The Synchronous Serial Interface (SSI) used in the DSP56000 family has been enhanced in the following ways to make the Enhanced Synchronous Serial Interface (ESSI):

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ESSI Data and Control Signals

• Network Enhancements

– Time Slot Mask Registers (receive and transmit) added, typically obviating the need for software time slot counters

– End-of-frame interrupt added

– Drive Enable signal added (to be used with transmitter 0)

• Audio Enhancements

– Three transmitters per ESSI (Both ESSIs may be used together for six-channel surround sound.)

• General Enhancements

– DMA transfers can be triggered by receive or transmit events

– Separate exception enable bits

• Other Changes

– One divide-by-2 removed from the internal clock source chain

– CRA(PSR) bit definition is reversed

– Gated Clock mode not available

7.3 ESSI DATA AND CONTROL SIGNALS

Three to six signals are required for ESSI operation, depending on the operating mode selected. The Serial Transmit Data (STD) signal and Serial Control (SC0 and SC1) signals are fully synchronized to the clock if they are programmed as transmit-data signals.

7.3.1 Serial Transmit Data Signal (STD)

The STD signal is used for transmitting data from the TX0 Serial Transmit Shift Register. STD is an output when data is being transmitted from TX0 Shift Register. With an internally generated bit clock, the STD signal becomes a high impedance output signal for a full clock period after the last data bit has been transmitted. If sequential data words are being transmitted, the STD signal does not assume a high-impedance state. The STD signal may be programmed as a General Purpose Input/Output (GPIO) signal (P5) when the ESSI STD function is not being used.

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7.3.2 Serial Receive Data Signal (SRD)

The SRD signal receives serial data and transfers the data to the ESSI Receive Shift Register. SRD may be programmed as a GPIO signal (P4) when the ESSI SRD function is not being used.

Figure 7-1 ESSI Block Diagram

RSMA

RSMB

TSMA

TSMB

SSISR

RX

RX SHIFT REG

TX0 SHIFT REG

TSR

RCLK

TX0

CRB

CRA

SRD

STDTCLK

SC2SCK

Clock/Frame Sync Generators and Control LogicInterrupts

GDB DDB

TX1 SHIFT REG

TX1

SC0

TX2 SHIFT REG

TX2

SC1

AA0678

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7.3.3 Serial Clock (SCK)

The SCK signal is a bidirectional signal providing the serial bit rate clock for the ESSI interface. The SCK signal is a clock input or output used by all the enabled transmitters and receivers in Synchronous modes or by all the enabled transmitters in Asynchronous modes (see Figure 7-2, Table 7-1, and Figure 7-13).

SCK may be programmed as a GPIO signal (P3) when the ESSI SCK function is not being used.

Notes: 1. Although an external serial clock can be independent of and asynchronous to the DSP system clock, the external ESSI clock frequency must not exceed Fcore/3, and each ESSI phase must exceed the minimum of 1.5 CLKOUT cycles.

2. The internally sourced ESSI clock frequency must not exceed Fcore/4.

Figure 7-2 SCKn Pin ConfigurationAA1458

TX Clock

CRB

10SYN

SCKn Pin

CRB

10SCKD

Input Output

Async

Mode

Sync

Mode

CRB

SCKD10

Note: “n” in SCKn is ESSI (0 or 1)

Input Output

TX ClockTX/RXClock

TX/RXClock

Pindirection?

SCKnpin is...

Synchronousoperation?

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Table 7-1 ESSI Clock Sources

SYN SCKD SCD0 R Clock Source

RX Clock Out

T Clock Source TX Clock Out

Asynchronous

0 0 0 EXT, SC0 — EXT, SCK —

0 0 1 INT SC0 EXT, SCK —

0 1 0 EXT, SC0 — INT SCK

0 1 1 INT SC0 INT SCK

Synchronous

1 0 0/1 EXT, SCK — EXT, SCK —

1 1 0/1 INT SCK INT SCK

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7.3.4 Serial Control Signal (SC0)

In ESSI0: SC00; In ESSI1: SC10

The function of this signal is determined by selecting either Synchronous or Asynchronous mode (see Figure 7-3, Table 7-4, and Figure 7-15). In Asynchronous mode, this signal is used for the receive clock I/O. In Synchronous mode, this signal is used as the transmitter data out signal for Transmit Shift Register 1 or for serial flag I/O. A typical application of serial flag I/O would be multiple device selection for addressing in codec systems.

If SC0 is configured as a serial flag signal, its direction is determined by the Serial Control Direction 0 (SCD0) bit in the ESSI Control Register B (CRB). When configured as an output, its direction is determined by the value of the serial Output Flag 0 (OF0) bit in the CRB.

Figure 7-3 SCn0 Pin ConfigurationAA1457

CRB

10SYN

SCn0 Pin

CRB

10SCD0

Input Output

Async

Mode

Sync

Mode

CRB

TE1

CRB

SCD010

Note: 1. “n” in SCn0 is ESSI (0 or 1)2. TD1 = Transmit Data Signal 1

Input Output

10

Pindirection?

SCn0pin is...


Usetransmitter

#1?

RX ClockFlag 0

InFlag 0

OutTD1Out

RX Clock

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If SC0 is an output, this signal can be configured as either serial output flag 0 or a Receive Shift Register clock output. If SC0 is an input, this signal may be used either as serial input flag 0 or as a Receive Shift Register clock input. If SC0 is used as serial input flag 0, it controls the state of serial Input Flag 0 (IF0) bit in the ESSI Status Register (SSISR).

When SC0 is configured as a transmit data signal, it is always an output signal regardless of the SCD0 bit value. SC0 is fully synchronized with the other transmit data signals (STD and SC1).

SC0 may be programmed as a GPIO signal (P0) when the ESSI SC0 function is not being used.

Note: The ESSI can operate with more than one active transmitter only in Synchronous mode.

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In ESSI0:SC01; In ESSI1: SCI11

The function of this signal is determined by selecting either Synchronous or Asynchronous mode (see Figure 7-4, Table 7-4, and Figure 7-15). In Asynchronous mode (such as a single codec with asynchronous transmit and receive), SC1 is the receiver frame sync I/O. In Synchronous mode, SC1 is used for the transmitter data out signal of Transmit Shift Register TX2, for the drive enable transmitter 0 signal, or for serial flag SC1.

When used as SC1, it operates like the previously described SC0. SC0 and SC1 are independent flags, but may be used together for multiple serial device selection. SC0 and SC1 can be used unencoded to select up to two codecs or may be decoded externally to select up to four codecs. If SC1 is configured as a serial flag signal, its direction is determined by the SCD1 bit in the CRB.

When configured as an output, SC1 functionality is determined by control bit OF1 in the SSISR. The SC1 signal can be used as a serial output flag, the transmitter 0 drive enable signal, or the receive frame sync signal output. When configured as an input, this signal can be used as to receive frame sync signals from an external source or it can be used as a serial input flag. When SC1 is a serial input flag, it controls status bit IF1 in the SSISR.

When this signal is configured as a transmit data signal, it is always an output signal regardless of the SCD1 bit value. As an output, it is fully synchronized with the other ESSI transmit data signals (STD and SC0). SC1 may be programmed as a GPIO signal (P1) when the ESSI SC1 function is not being used.

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Figure 7-4 SCn1 Pin Configuration

AA1456

CRB

10SYN

SCn1 Pin

CRB

10SCD1

Input Output

Async

Mode

Sync

Mode

CRB

TE2

CRB

SCD110

Note: 1. “n” in SCn1 is ESSI (0 or 1)2. TDm = Transmit Data Signal m

CRA

SSC110

Input Output

10

Pindirection?

SCn1pin is...


Usetransmitter

#2?

Use driveenable for

transmitter #0(STD pin)?

Flag 1In

Flag 1Out

TD0 DriveEnable Out

TD2Out

RXFrame Sync

RXFrame Sync

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In ESSI0:SC02; In ESSI1:SC12

This signal is used for frame sync I/O. SC2 is the frame sync for both the transmitter and receiver in Synchronous mode and for the transmitter only in Asynchronous mode (see Figure 7-5, Table 7-4, and Figure 7-15). The direction of this signal is determined by the SCD2 bit in the CRB. When configured as an output, this signal outputs the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter in Asynchronous mode and for the receiver when in Synchronous mode. SC2 may be programmed as a GPIO signal (P2) when the ESSI SC2 function is not being used.

Figure 7-5 SCn2 Pin Configuration

Pindirection?

SCn2pin is...


AA1459

CRB

10SYN

SCn2 Pin

CRB

10SCD2

Input Output

Async

Mode

Sync

Mode

CRB

SCD210

Note: “n” in SCn2 is ESSI (0 or 1)

Input Output

TX/RXFrame Sync

TXFrame Sync

TXFrame Sync

TX/RXFrame Sync

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ESSI Programming Model


7.4 ESSI PROGRAMMING MODEL

The ESSI is composed of:

• Two control registers (CRA, CRB)

• One status register (SSISR)

• Three transmit data registers (TX0, TX1, TX2)

• One receive data register (RX)

• Two transmit slot mask registers (TSMA, TSMB)

• Two receive slot mask registers (RSMA, RSMB)

• One special-purpose time slot register (TSR)

The following paragraphs give detailed descriptions and operations of each of the bits in the ESSI registers. The GPIO functionality of the ESSI is described in Section 7.6 of this manual.

11 10 9 8 7 6 5 4 3 2 1 0PSR PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

23 22 21 20 19 18 17 16 15 14 13 12SSC1 WL2 WL1 WL0 ALC DC4 DC3 DC2 DC1 DC0

AA0857

Figure 7-6 ESSI Control Register A (CRA) (ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5)

11 10 9 8 7 6 5 4 3 2 1 0CKP FSP FSR FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0 OF1 OF0

23 22 21 20 19 18 17 16 15 14 13 12REIE TEIE RLIE TLIE RIE TIE RE TE0 TE1 TE2 MOD SYN

AA0858

Figure 7-7 ESSI Control Register B (CRB) (ESSI0 X:$FFFFB6, ESSI1 X:$FFFFA6)

11 10 9 8 7 6 5 4 3 2 1 0RDF TDE ROE TUE RFS TFS IF1 IF0

23 22 21 20 19 18 17 16 15 14 13 12

AA0859

Figure 7-8 ESSI Status Register (SSISR) (ESSI0 X:$FFFFB7, ESSI1 X:$FFFFA7)

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Note: The Transmit and Receive Slot Mask registers are each 24-bit, of which only the lower 16 bits are significant, so TSMA/TSMB and RSMA/RSMB can function as the bottom and top halves of a 32-bit register.

11 10 9 8 7 6 5 4 3 2 1 0TS11 TS10 TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0

23 22 21 20 19 18 17 16 15 14 13 12TS15 TS14 TS13 TS12

AA0860

Figure 7-9 ESSI Transmit Slot Mask Register A (TSMA) (ESSI0 X:$FFFFB4, ESSI1 X:$FFFFA4)

11 10 9 8 7 6 5 4 3 2 1 0TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16

23 22 21 20 19 18 17 16 15 14 13 12TS31 TS30 TS29 TS28

AA0861

Figure 7-10 ESSI Transmit Slot Mask Register B (TSMB) (ESSI0 X:$FFFFB3, ESSI1 X:$FFFFA3)

11 10 9 8 7 6 5 4 3 2 1 0RS11 RS10 RS9 RS8 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0

23 22 21 20 19 18 17 16 15 14 13 12RS15 RS14 RS13 RS12

AA0862

Figure 7-11 ESSI Receive Slot Mask Register A (RSMA) (ESSI0 X:$FFFFB2, ESSI1 X:$FFFFA2)

11 10 9 8 7 6 5 4 3 2 1 0RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16

23 22 21 20 19 18 17 16 15 14 13 12RS31 RS30 RS29 RS28

– Reserved bit - read as zero should be written with zero for future compatibilityAA0863

Figure 7-12 ESSI Receive Slot Mask Register B (RSMB) (ESSI0 X:$FFFFB1, ESSI1 X:$FFFFA1)

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7.4.1 ESSI Control Register A (CRA)

The ESSI Control Register A (CRA) is one of two 24-bit read/write control registers used to direct the operation of the ESSI. The CRA controls the ESSI clock generator bit and frame sync rates, word length, and number of words per frame for the serial data. The CRA control bits are described in the following paragraphs (see Figure 7-6 ).

7.4.1.1 Prescale Modulus Select (PM[7:0]) CRA Bits 7-0The PM[7:0] bits specify the divide ratio of the prescale divider in the ESSI clock generator. A divide ratio from 1 to 256 (PM = $0 to $FF) may be selected. The bit clock output is available at the transmit clock signal (SCK) and/or the receive clock (SC0) signal of the DSP. The bit clock output is also available internally for use as the bit clock to shift the Transmit and Receive Shift Registers. The ESSI clock generator functional diagram is shown in Figure 7-13. Fcore is the DSP56305 core clock frequency (the same frequency as the CLKOUT signal, when that signal is enabled). Careful choice of the crystal oscillator frequency and the prescaler modulus will allow the industry-standard codec master clock frequencies of 2.048 MHz, 1.544 MHz, and 1.536 MHz to be generated. Both the hardware reset signal and the software reset instruction clear PM[7:0].

7.4.1.2 Reserved CRA Bits 8-10These bits are reserved. They are read as 0 and should be written with 0.

7.4.1.3 Prescaler Range (PSR) CRA Bit 11The PSR controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired. When PSR is set, the fixed prescaler is bypassed. When PSR is cleared, the fixed divide-by-eight prescaler is operational (see Figure 7-13).

Note: This definition is reversed from that of the 560xx SSI.

The maximum allowed internally generated bit clock frequency is the DSP56305 internal clock frequency divided by 4 (Fcore/4); the minimum possible internally generated bit clock frequency is the DSP56305 internal clock frequency divided by 4096 (Fcore/4096). Both the hardware reset signal and the software reset instruction clear PSR.

Note: The combination PSR = 1 and PM[7:0] = $00 (dividing Fcore by 2) may cause synchronization problems and should not be used.

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7.4.1.4 Frame Rate Divider Control DC[4:0] CRA Bits 16-12The DC[4:0] bits determine the division factor used by a frame rate divider to generate an RX or TX frame sync signal from its respective word clock, when that frame sync is configured as internally sourced (an output). This is depicted in Figure 7-14. For a divide-by-N, the value (N-1) must be loaded into DC[4:0].

Note that although the RX and TX word widths will always be the same (according to CRA(WL[2:0])), the RX and TX word clock rates will differ if their respective bit clock rates are not the same. This can occur if one or both of these clocks are externally sourced. If this is the case, then the RX and TX frame clock rates will differ accordingly.

DC[4:0] are cleared by hardware and software reset.

Figure 7-13 ESSI Clock Generator Functional Block Diagram

SCn0

SCKn

CRB(SCD0)

CRB(SCKD)

CRB(SYN) = 1SCD0 = 0

RCLOCK

TCLOCK

Internal Bit Clock

SYN = 1

CRA(WL2:0)

RX Shift Register

TX Shift Registers

/1 or /8 /1 to /256

FCORE

RXWordClock

SYN = 0 SCD0 = 1

Note: 1. Fcore is the DSP56300 core internal clock frequency.

2. ESSI internal clock range: min = Fcore/4096, max = Fcore/4

3. ‘n’ in signal name is ESSI (0 or 1)

AA0679

Sync:TD1, or

Async:RX clk

Sync:TX/RX clk

Async:TX clk

0

0 0 255

CRA(PSR) CRA(PM7:0)

/8, /12, /16, /24, /32

1 2 3 4,5

Flag0 Out

(Sync Mode)CRB(OF0)CRB(TE1)

TD1 Flag0 In

(Sync Mode)SSISR(IF0)

1

SYN = 0

0

/8, /12, /16, /24, /32

1 2 3 4,5

/2

CRA(WL2:0) TXWordClock

Flag0

(Oppositefrom SSI)

or

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7.4.1.4.1 Normal Mode (MOD = 0)When an internal frame sync is used, DC[4:0] determine the word transfer rate. In other words, these bits control how many word periods elapse per frame (although a word is transferred only during the first period in the frame). The number of word periods per frame may range from 1 to 32 (DC = 00000 to 11111).

For an external RX or TX frame sync, DC[4:0] define the minimum frame window. Once the external frame sync triggering edge is received, commencing a new frame, any additional triggering edges on the same frame sync signal will be ignored, until the number of word periods defined by DC[4:0] has elapsed during that frame.

7.4.1.4.2 Network Mode (MOD = 1; DC ≠ 00000)When an internal frame sync is used, DC[4:0] determine the number of time slots per frame (a separate word will be transferred in each time slot enabled using the appropriate slot mask register). The number of time slots per frame may range from 2 to 32 (DC = 00001 to 11111). For overview information about Network mode, see Section 7.5.3.2.

For an external RX or TX frame sync, DC[4:0] define the minimum frame window. Once the external frame sync triggering edge is received, commencing a new frame, any additional triggering edges on the same frame sync signal will be ignored, until the number of word periods defined by DC[4:0] has elapsed during that frame.

7.4.1.4.3 On-Demand Mode (MOD = 1; DC = 00000)In On-demand mode, the frame rate dividers are not used, and periodic frame syncs are not generated. Instead, a transmit frame sync is output from the DSP as a result of the core writing a word to an active ESSI transmit register, and one word is shifted in (width set by CRA(WL[2:0])) on the ESSI serial input pin as a result of a receive frame sync being input to the DSP. For overview information about On-demand mode, see Section 7.5.3.3.

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7.4.1.5 Reserved CRA Bit 17This bit is reserved. It is read as 0 and should be written with 0.

7.4.1.6 Alignment Control (ALC) CRA Bit 18The ESSI is designed for 24-bit fractional data. Shorter data words are left aligned to the Most Significant Bit (MSB), Bit 23. For applications that use 16 bit fractional data, shorter data words are left aligned to Bit 15. The ALC bit supports these shorter data words. If ALC is set, received words are left aligned to Bit 15 in the Receive Shift Register. Transmitted words must be left aligned to Bit 15 in the Transmit Shift Register. If the ALC bit is cleared, received words are left aligned to Bit 23 in the Receive Shift Register. Transmitted words must be left aligned to Bit 23 in the Transmit Shift Register. The ALC bit is cleared by either a hardware reset signal or a software reset instruction.

Note: If the ALC bit is set, only 8-, 12-, or 16-bit words should be used. The use of 24- or 32-bit words leads to unpredictable results.

Figure 7-14 ESSI Frame Sync Generator Functional Block Diagram

Frame Sync

Transmit

Frame Sync

Receive

RX WordClock

TX WordClock

CRA(DC4:0)

ReceiveControl Logic

TransmitControl Logic

SyncType

SyncType

CRB(SYN) = 0

SYN = 1

Internal Rx Frame Sync

CRB(SCD1) = 1

SYN = 1SCD1 = 0

SYN = 0CRB(SCD1)

Internal TX Frame Sync

AA0680

SCn1

/1 to /32

310

CRB(FSL1:0)

CRB(FSL1:0)

CRA(DC4:0)

/1 to /32

310

SCn2

CRB(SCD2)

Flag1 Out,

(Sync Mode)CRB(OF1)CRB(TE2)

TD2, or drive enb.CRA(SSC1)

Flag1 InSSISR (IF1)

(Sync Mode)

CRB(FSR)

Sync:TD2,

Async:RX F.S.

Flag1, ordrive enb.

Sync:TX/RX F.S.

Async:TX F.S.

CRB(FSR)

These signals areidentical in sync mode.

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7.4.1.7 Word Length Control (WL[2:0]) CRA Bits 21-19The WL[2:0] bits are used to select the length of the data words being transferred via the ESSI. Word lengths of 8-, 12-, 16-, 24-, or 32- bits may be selected (see Table 7-2). The ESSI data path programming model in Figure 7-19 and Figure 7-20 has additional information on selecting different length data words. The ESSI data registers are 24 bits long. The ESSI transmits 32-bit words either by duplicating the last bit 8 times when WL[2:0] = 100, or by duplicating the first bit 8 times when WL[2:0] = 101. The WL[2:0] bits are cleared by a hardware reset signal or by a software reset instruction.

7.4.1.8 Select SC1 as Transmitter 0 Drive Enable (SSC1) CRA Bit 22The SSC1 bit controls SC1 signal functionality (see Figure 7-4). If SSC1 = 1, and the following three conditions hold: the ESSI is configured in Synchronous mode (SYN = 1), transmitter 2 is disabled (TE2 = 0), and the SC1 signal is configured as output (SCD1 = 1), then the SC1 signal is the driver enable for transmitter 0. This enables the use of an external buffer for the transmitter 0 output. If SSC1 = 0, and the same three conditions hold: the ESSI is configured in Synchronous mode (SYN = 1), transmitter 2 is disabled (TE2 = 0), and the SC1 signal is configured as output (SCD1 = 1), then the SC1 signal is the serial I/O flag. The reset value is cleared.

7.4.1.9 Reserved CRA Bit 23This bit is reserved. It is read as 0 and should be written with 0.

Table 7-2 ESSI Word Length Selection

WL2 WL1 WL0 Number of Bits/Word

0 0 0 8

0 0 1 12

0 1 0 16

0 1 1 24

1 0 0 32 (valid data in the first 24 bits)

1 0 1 32 (valid data in the last 24 bits)

1 1 0 Reserved

1 1 1 Reserved

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7.4.2 ESSI Control Register B (CRB)

The CRB is one of two 24-bit read/write control registers used to direct the operation of the ESSI (see Figure 7-7). CRB controls the ESSI multifunction signals, SC[2:0], which can be used as clock inputs or outputs, frame synchronization signals, transmit data signals, or serial I/O flag signals.

The serial output flag control bits and the direction control bits for the serial control signals are in the ESSI CRB. Interrupt enable bits for the receiver and the transmitter are also in the CRB. The bit setting of the CRB also determines how many transmitters are enabled (0, 1, 2, or 3 transmitters can be enabled). The CRB settings also determine the ESSI operating mode.

Either a hardware reset signal or a software reset instruction clear all the bits in the CRB.

The relationship between the ESSI signals SC[2:0], SCK, and the CRB bits is summarized in Table 7-4. See also Figure 7-3, Figure 7-4, Figure 7-5, and Figure 7-15. The ESSI CRB bits are described in the following paragraphs.

7.4.2.1 Serial Output Flags (OF[1:0]) CRB Bits 1-0The ESSI has two serial output flag bits, OF1 and OF0. The normal sequence for setting output flags when transmitting data (by transmitter 0 through the STD signal only) is:

1. Wait for TDE (TX0 empty) to be set.

2. Write the flags.

3. Write the transmit data to the TX register.

Bits OF0 and OF1 are double-buffered so that the flag states appear on the signals when the TX data is transferred to the Transmit Shift Register. The flag bits values are synchronized with the data transfer.

Note: The timing of the optional serial output signals SC[2:0] is controlled by the frame timing and is not affected by the settings of TE2, TE1, TE0, or the Receive Enable (RE) bit of the CRB.

7.4.2.1.1 Serial Output Flag 0 (OF0) CRB Bit 0When the ESSI is in Synchronous mode and transmitter 1 is disabled (TE1 = 0), the SC0 signal is configured as ESSI flag 0. If the serial control direction bit (SCD0) is set, the SC0 signal is an output. Data present in bit OF0 is written to SC0 at the beginning of the frame in Normal mode or at the beginning of the next time slot in Network mode.

Bit OF0 is cleared by a hardware reset signal or by a software reset instruction.

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7.4.2.1.2 Serial Output Flag 1 (OF1) CRB Bit 1When the ESSI is in Synchronous mode and transmitter 2 is disabled (TE2 = 0), the SC1 signal is configured as ESSI flag 1. If the serial control direction bit (SCD1) is set, the SC1 signal is an output. Data present in bit OF1 is written to SC1 at the beginning of the frame in Normal mode or at the beginning of the next time slot in Network mode.

Bit OF1 is cleared by a hardware reset signal or by a software reset instruction.

7.4.2.2 Serial Control Direction 0 (SCD0) CRB Bit 2In Synchronous mode (SYN = 1) when transmitter 1 is disabled (TE1 = 0), or in Asynchronous mode (SYN = 0), SCD0 controls the direction of the SC0 I/O signal. When SCD0 is set, SC0 is an output; when SCD0 is cleared, SC0 is an input.

When TE1 is set, the value of SCD0 is ignored and the SC0 signal is always an output.

Bit SCD0 is cleared by a hardware reset signal or by a software reset instruction.

Figure 7-15 ESSI Pin Configuration for Clocks, Frame Syncs, and Flags

AA0849Asynchronous Mode (SYN = 0)

Synchronous Mode (SYN = 1)

0 = Input 1 = Output

Pin

CRB

Bit Number

SCKD

SCKn

SCD2 SCD1 SCD0

SCn2 SCn1 SCn0

Clock F.S. F.S. Clock

Tx Rx

Clock F.S. Flag 1 Flag 05 4 3 2

Tx/Rx

Bit Value

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7.4.2.3 Serial Control Direction 1 (SCD1) CRB Bit 3In Synchronous mode (SYN = 1) when transmitter 2 is disabled (TE2 = 0), or in Asynchronous mode (SYN = 0), SCD1 controls the direction of the SC1 I/O signal. When SCD1 is set, SC1 is an output; when SCD1 is cleared, SC1 is an input. See Figure 7-11 for more information about the use of this pin in ESSI configuration.

When TE2 is set, the value of SCD1 is ignored and the SC1 signal is always an output.

Bit SCD1 is cleared by a hardware reset signal or by a software reset instruction.

7.4.2.4 Serial Control Direction 2 (SCD2) CRB Bit 4SCD2 controls the direction of the SC2 I/O signal. When SCD2 is set, SC2 is an output; when SCD2 is cleared, SC2 is an input. SCD2 is cleared by a hardware reset signal or by a software reset instruction. See Figure 7-11 for more information about the use of this pin in ESSI configuration.

7.4.2.5 Clock Source Direction (SCKD) CRB Bit 5SCKD selects the source of the clock signal used to clock the Transmit Shift Register in Asynchronous mode and all the Transmit and Receive Shift Registers in Synchronous mode. If SCKD is set and the ESSI is in Synchronous mode, the internal clock is the source of the clock signal used for all the Transmit Shift Registers and the Receive Shift Register. If SCKD is set and the ESSI is in Asynchronous mode, the internal clock source becomes the bit clock for the Transmit Shift Register and word length divider. The internal clock is output on the SCK signal.

When SCKD is cleared, the external clock source is selected. The internal clock generator is disconnected from the SCK signal, and an external clock source may drive this signal. See Figure 7-11 for more information about the use of this pin in ESSI configuration.

Either a hardware reset signal or a software reset instruction clears SCKD.

7.4.2.6 Shift Direction (SHFD) CRB Bit 6The setting of the SHFD bit determines the shift direction of the Transmit or Receive Shift Register. If SHFD is set, data is shifted out with the Least Significant Bit (LSB) first. If SHFD is cleared, data is shifted out MSB first (see Figure 7-19 and Figure 7-20). Received data is shifted in LSB first when SHFD is set or MSB first when SHFD is cleared.

Either a hardware reset signal or a software reset instruction clears SHFD.

7.4.2.7 Frame Sync Length FSL[1:0] CRB Bits 8-7These bits select the length of frame sync to be generated or recognized (see Figure 7-16). The meaning of the FSL[1:0] values is described in Table 7-3.

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Note: In Synchronous Mode, it is recommended that FSL[1:0] not be assigned the values of 01 or 11, as this may cause the receive frame sync position to be shifted one bit from the normally expected position.

The word length is defined by WL[2:0].

Either a hardware reset signal or a software reset instruction clears FSL[1:0].

7.4.2.8 Frame Sync Relative Timing (FSR) CRB Bit 9The FSR bit determines the relative timing of the receive and transmit frame sync signal in reference to the serial data lines, for word length frame sync only. When FSR is cleared, the word length frame sync occurs together with the first bit of the data word of the first slot. When FSR is set, the word length frame sync begins one serial clock cycle earlier (i.e., simultaneously with the last bit of the previous data word).

Either a hardware reset signal or a software reset instruction clears FSR.

7.4.2.9 Frame Sync Polarity (FSP) CRB Bit 10The FSP bit determines the polarity of the receive and transmit frame sync signals. When FSP is cleared, the frame sync signal polarity is positive (i.e., the frame start is indicated by the frame sync signal going high). When FSP is set, the frame sync signal polarity is negative (i.e., the frame start is indicated by the frame sync signal going low).

Either a hardware reset signal or a software reset instruction clears FRB.

Table 7-3 FSL[1:0] Encoding

FSL[1:0]Asynchronous Modes Synchronous

Mode

RX TX RX/TX

00 word word word

01 word bit -

10 bit bit bit

11 bit word -

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7.4.2.10 Clock Polarity (CKP) CRB Bit 11The CKP bit controls on which bit clock edge data and frame sync are clocked out and latched in. If CKP is cleared, the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the receive bit clock. If CKP is set, the data and the frame sync are clocked out on the falling edge of the transmit bit clock and latched in on the rising edge of the receive bit clock.

Either a hardware reset signal or a software reset instruction will clear CKP.

7.4.2.11 Synchronous /Asynchronous (SYN) CRB Bit 12SYN controls whether the receive and transmit functions of the ESSI occur synchronously or asynchronously with respect to each other (see Figure 7-17). When SYN is cleared, the ESSI is in Asynchronous mode, and separate clock and frame sync signals are used for the transmit and receive sections. When SYN is set, the ESSI is in Synchronous mode and the transmit and receive sections use common clock and frame sync signals. Only in the Synchronous mode can more than one transmitter can be enabled.

Either a hardware reset signal or a software reset instruction clears SYN.

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Figure 7-16 CRB FSL[1:0] Bit Operation

Serial Clock

RX, TX Frame SYNC

Word Length: FSL[1:0] = 00, (SYN = 1)

RX, TX Serial Data

NOTE: Frame sync occurs while data is valid.

Data Data

Serial Clock

RX, TX Frame SYNC

One Bit Length: FSL[1:0] = 10, (SYN = 1)

RX, TX Serial Data

NOTE: Frame sync occurs for one bit time preceding the data.

Serial Clock

TX Frame SYNC

Mixed Frame Length: FSL[1:0] = 01, (SYN = 0)

RX Frame Sync,(FSR = 0)

Serial Clock

TX Frame SYNC

Mixed Frame Length: FSL[1:0] = 11, (SYN = 0)

TX Serial Data

RX Frame SYNC

Data Data

Data Data

Data Data

Data Data

Data Data

RXSerial Data

TX Serial Data

RX Serial Data

AA0681

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7.4.2.12 ESSI Mode Select (MOD) CRB Bit 13MOD selects the operational mode of the ESSI (see Figure 7-18). When MOD is cleared, the Normal mode is selected; when MOD is set, the Network mode is selected. In the Normal mode, the frame rate divider determines the word transfer rate: one word is transferred per frame sync during the frame sync time slot. In Network mode, a word may be transferred every time slot. For more details, see Section 7.5 . Either a hardware reset signal or a software reset instruction will clear MOD.

Figure 7-17 CRB SYN Bit Operation

External Frame SYNC

SC1

Asynchronous (SYN = 0)

Transmitter

ClockFrameSYNC

RECEIVER

Clock FrameSYNC

SRD

STD

SC2External Transmit Frame SYNC

External Receive Frame SYNC

Internal Frame SYNC

SC0

SCKExternal Transmit Clock

External Receive Clock

Internal ClockESSI BitClock

NOTE: Transmitter and receiver may have different clocks and frame syncs.

SYNCHRONOUS (SYN = 1)

Transmitter

Clock

FrameSYNC

Receiver

Clock FrameSYNC

SRD

STD

SC2

Internal Frame SYNC

SCKExternal Clock

Internal ClockESSI BitClock

NOTE: Transmitter and receiver may have the same clock frame syncs.AA0682

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Enhanced S

ynchronous Serial Interface (E

SS

I)

ES

SI P

rogramm

ing Model

MO

TO

RO

LAD

SP

56305 User’s M

anual7-27

Figure 7-18 Normal and Network Mode Operation

Normal Mode (MOD = 0)

Serial Clock

Frame SYNC(Word Length,

FSR = 0)

Serial Data Data Data

Transmitter Interrupt (or DMA Request) and Flags Set

Receiver Interrupt (or DMA Request) and Flags Set

NOTE: Interrupts occur and data is transferred once per frame sync.

Network Mode (MOD = 1)

Serial Clock

Frame SYNC,(Word Length,

FSR = 0) Transmitter Interrupts (or DMA Request) and Flags Set

Slot 1 Slot 2 Slot 3 Slot 1 Slot 2Serial Data

Receiver Interrupt (or DMA Request) and Flags Set

NOTE: Interrupts occur every time slot and a word may be transferred.AA0683

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7.4.2.13 Enabling and Disabling Data Transmission from the ESSIThe ESSI has three Transmit Enable bits (TE[2:0]), one for each data transmitter. The process of transmitting data from TX1 and TX2 is the same. TX0 can also operate in Asynchronous mode. The normal transmit enable sequence is to write data to one or more Transmit Data Registers (or the Time Slot Register (TSR) before setting the TE bit. The normal transmit disable sequence is to set the Transmit Data Empty (TDE) bit, then clear the TE, Transmit Interrupt Enable (TIE), and Transmit Exception Interrupt Enable (TEIE) bits. In the Network mode, clearing the appropriate TE bit and setting it again disables the corresponding transmitter (0, 1, or 2) after transmission of the current data word. The transmitter remains disabled until the beginning of the next frame. During that time period, the corresponding SC (or STD in the case of TX0) signal remains in the high-impedance state.

7.4.2.14 ESSI Transmit 2 Enable (TE2) CRB Bit 14The TE2 bit enables the transfer of data from TX2 to Transmit Shift Register 2. TE2 is functional only when the ESSI is in Synchronous mode and is ignored when the ESSI is in Asynchronous mode.

When TE2 is set and a frame sync is detected, the transmitter 2 is enabled for that frame.

When TE2 is cleared, transmitter 2 is disabled after completing transmission of data currently in the ESSI Transmit Shift Register. Any data present in TX2 is not transmitted. If TE2 is cleared, data can be written to TX2; the TDE bit will be cleared, but data will not be transferred to Transmit Shift Register 2.

Keeping the TE2 bit cleared until the start of the next frame causes the SC1 signal to act as serial I/O flag from the start of the frame, in both Normal and Network mode. The On-demand mode transmit enable sequence can be the same as the Normal mode, or the TE2 bit can be left enabled.

The TE2 bit is cleared by either a hardware reset signal or a software reset instruction.

Note: The setting of the TE2 bit does not affect the generation of frame sync or output flags.

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7.4.2.15 ESSI Transmit 1 Enable (TE1) CRB Bit 15The TE1 bit enables the transfer of data from TX1 to Transmit Shift Register 1. TE1 is functional only when the ESSI is in Synchronous mode and is ignored when the ESSI is in Asynchronous mode.


When TE1 is cleared, transmitter 1 is disabled after completing transmission of data currently in the ESSI Transmit Shift Register. Any data present in TX1 is not transmitted. If TE1 is cleared, data can be written to TX1; the TDE bit will be cleared, but data will not be transferred to Transmit Shift Register 1.

Keeping the TE1 bit cleared until the start of the next frame causes the SC0 signal to act as serial I/O flag from the start of the frame, in both Normal and Network mode. The On-demand mode transmit enable sequence can be the same as the Normal mode, or the TE1 bit can be left enabled.


Note: The setting of the TE1 bit does not affect the generation of frame sync or output flags.

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7.4.2.16 ESSI Transmit 0 Enable (TE0) CRB Bit 16The TE0 bit enables the transfer of data from TX1 to Transmit Shift Register 0. TE0 is functional when the ESSI is in either Synchronous or Asynchronous mode.


When TE0 is cleared, transmitter 0 is disabled after completing transmission of data currently in the ESSI Transmit Shift Register. The STD output is tri-stated, and any data present in TX0 will not be transmitted (i.e., data can be written to TX0 with TE0 cleared; the TDE bit is cleared, but data will not be transferred to the Transmit Shift Register 0).


The On-demand mode transmit enable sequence can be the same as the Normal mode, or TE0 can be left enabled.

Note: Transmitter 0 is the only transmitter that can operate in Asynchronous mode (SYN = 0). TE0 does not affect the generation of frame sync or output flags.

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Table 7-4 Mode and Signal Definition Table

Control Bits ESSI Signals

SYN TE0 TE1 TE2 RE SC0 SC1 SC2 SCK STD SRD

0 0 X X 0 U U U U U U

0 0 X X 1 CLKR FSR U U U RD

0 1 X X 0 U U FST CLKT TD0 U

0 1 X X 1 CLKR FSR FST CLKT CLKTTD0

RD

1 0 0 0 0 F0/U F1/U U U U U

1 0 0 0 1 F0/U F1/U FS CLK U RD

1 0 0 1 0 F0/U TD2 FS CLK U U

1 0 0 1 1 F0/U TD2 FS CLK U RD

1 0 1 0 0 TD1 F1/T0DE/U FS CLK U U

1 0 1 0 1 TD1 F1/T0DE/U FS CLK U RD

1 0 1 1 0 TD1 TD2 FS CLK U U

1 0 1 1 1 TD1 TD2 FS CLK U RD

1 1 0 0 0 F0/U F1/T0DE/U FS CLK TD0 U

1 1 0 0 1 F0/U F1/T0DE/U FS CLK TD0 RD

1 1 0 1 0 F0/U TD2 FS CLK TD0 U

1 1 0 1 1 F0/U TD2 FS CLK TD0 RD

1 1 1 0 0 TD1 F1/T0DE/U FS CLK TD0 U

1 1 1 0 1 TD1 F1/T0DE/U FS CLK TD0 RD

1 1 1 1 0 TD1 TD2 FS CLK TD0 U

1 1 1 1 1 TD1 TD2 FS CLK TD0 RD

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7.4.2.17 ESSI Receive Enable (RE) CRB Bit 17When the RE bit is set, the receive portion of the ESSI is enabled. When this bit is cleared, the receiver is disabled by inhibiting data transfer into RX. If data is being received while this bit is cleared, the remainder of the word is shifted in and transferred to the ESSI Receive Data Register.

RE must be set in both the Normal and On-demand modes for the ESSI to receive data. In Network mode, clearing RE and setting it again disables the receiver after reception of the current data word. The receiver remains disabled until the beginning of the next data frame.

RE is cleared by either a hardware reset signal or a software reset instruction.

Note: The RE bit value does not affect frame sync generation.

Note:CLK= Transmitter/Receiver Clock (Synchronous Operation)CLKR= Receiver ClockCLKT= Transmitter ClockFS= Transmitter/Receiver Frame Sync (Synchronous Operation)FSR= Receiver Frame SyncFST= Transmitter Frame SyncF0= Flag 0F1= Flag 1 if SSC1 = 0RD= Receive Data TD0= Transmit Data signal 0TD1= Transmit Data signal 1TD2= Transmit Data signal 2T0DE= Transmitter 0 drive enable if SYN = 1, TE2 = 0, SSC1 = 1, and SCD1 = 1U= Unused (may be used as GPIO signal)X=Don’t Care

Table 7-4 Mode and Signal Definition Table (Continued)

Control Bits ESSI Signals

SYN TE0 TE1 TE2 RE SC0 SC1 SC2 SCK STD SRD

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7.4.2.18 ESSI Transmit Interrupt Enable (TIE) CRB Bit 18Setting the TIE bit enables a DSP transmit interrupt, which is generated when both the TIE and the TDE bits in the ESSI Status Register are set. When TIE is cleared, the transmit interrupt is disabled. The use of the transmit interrupt is described in Section 7.5.2 . Writing data to the data registers of the enabled transmitters or to the TSR clears TDE and also clears the interrupt. Transmit interrupts with exception conditions have higher priority than normal transmit data interrupts. If the Transmit Underrun Run (TUE) bit is set, signaling that an exception has occurred, and the TEIE bit is set, the ESSI requests an SSI transmit data with exception interrupt from the interrupt controller.

TIE is cleared by either a hardware reset signal or a software reset instruction.

7.4.2.19 ESSI Receive Interrupt Enable (RIE) CRB Bit 19Setting the RIE enables a DSP receive data interrupt, which is generated when both the RIE and Receive Data Register Full (RDF) bit (in the SSISR) are set. When RIE is cleared, this interrupt is disabled. The use of the receive interrupt is described in Section 7.5.2 . Reading the Receive Data Register clears RDF and the pending interrupt. Receive interrupts with exception have higher priority than normal receive data interrupts. If the Receiver Overrun Error (ROE) bit is set, signaling that an exception has occurred, and the REIE bit is set, the ESSI requests an SSI receive data with exception interrupt from the interrupt controller.

RIE is cleared by either a hardware reset signal or a software reset instruction.

7.4.2.20 ESSI Transmit Last Slot Interrupt Enable (TLIE) CRB Bit 20Setting the TLIE bit enables an interrupt at the beginning of the last slot of a frame when the ESSI is in Network mode. When TLIE is set, the DSP is interrupted at the start of the last slot in a frame regardless of the Transmit Mask Register setting. When TLIE is cleared, the transmit last slot interrupt is disabled. The use of the transmit last slot interrupt is described in Section 7.5.2 .

TLIE is cleared by either a hardware reset signal or a software reset instruction. TLIE is disabled when the ESSI is in On-demand mode (DC [4:0]= 00000, in CRA Bits 16-12).

7.4.2.21 ESSI Receive Last Slot Interrupt Enable (RLIE) CRB Bit 21Setting the RLIE bit enables an interrupt after the last slot of a frame ends when the ESSI is in Network mode. When RLIE is set, the DSP is interrupted after the last slot in a frame ends regardless of the Receive Mask Register setting. When RLIE is cleared, the receive last slot interrupt is disabled. The use of the receive last slot interrupt is described in Section 7.5.2 .

RLIE is cleared by either a hardware reset signal or a software reset instruction. RLIE is disabled when the ESSI is in On-demand mode (DC [4:0]= 00000, in CRA Bits 16-12).

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7.4.2.22 ESSI Transmit Exception Interrupt Enable (TEIE) CRB Bit 22When the TEIE bit is set, the DSP is interrupted when both TDE and TUE in the ESSI Status Register are set. When TEIE is cleared, this interrupt is disabled. The use of the transmit interrupt is described in Section 7.5.2 . Reading the Status Register followed by writing to all the data registers of the enabled transmitters clears both TUE and the pending interrupt.

TEIE is cleared by either a hardware reset signal or a software reset instruction.

7.4.2.23 ESSI Receive Exception Interrupt Enable (REIE) CRB Bit 23When the REIE bit is set, the DSP is interrupted when both RDF and ROE in the ESSI Status Register are set. When REIE is cleared, this interrupt is disabled. The use of the receive interrupt is described in Section 7.5.2 . Reading the Status Register followed by reading the Receive Data Register clears both ROE and the pending interrupt.

REIE is cleared by either a hardware reset signal or a software reset instruction.

7.4.3 ESSI Status Register (SSISR)

The SSISR (see Figure 7-8 on page 7-13) is a 24-bit read-only Status Register used by the DSP to read the status and serial input flags of the ESSI. The meaning of the SSISR bits is described in the following paragraphs. When the SSISR is read to the internal data bus, the register contents occupy the low-order byte of the data bus and the remaining bus bits are read as zeros.

7.4.3.1 Serial Input Flag 0 (IF0) SSISR Bit 0The IF0 bit is enabled only when SC0 is an input flag and the Synchronous mode is selected (i.e., when SC0 is programmed as ESSI in the Port Control Register (PCR), the SYN bit is set, and the TE1 and SCD0 bits are cleared). See Figure 7-3.

The ESSI latches data present on the SC0 signal during reception of the first received bit after the frame sync is detected. The IF0 bit is updated with this data when the data in the Receive Shift Register is transferred into the Receive Data Register.

If it is not enabled, the IF0 bit is cleared.

Hardware, software, ESSI individual, and stop reset clear the IF0 bit.

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7.4.3.2 Serial Input Flag 1 (IF1) SSISR Bit 1The IF1 bit is enabled only when SC1 is an input flag and the Synchronous mode is selected (i.e., when SC1 is programmed as ESSI in the Port Control Register (PCR), the SYN bit is set, and the TE2 and SCD1 bits are cleared). See Figure 7-4.

The ESSI latches data present on the SC1 signal during reception of the first received bit after the frame sync is detected. The IF1 bit is updated with this data when the data in the Receive Shift Register is transferred into the Receive Data Register.

If it is not enabled, the IF1 bit is cleared.

Hardware, software, ESSI individual, and stop reset clear the IF1 bit.

7.4.3.3 Transmit Frame Sync Flag (TFS) SSISR Bit 2When set, TFS indicates that a transmit frame sync occurred in the current time slot. TFS is set at the start of the first time slot in the frame and cleared during all other time slots. If the transmitter is enabled, data written to a Transmit Data Register during the time slot when TFS is set will be transmitted (in Network mode) during the second time slot in the frame. TFS is useful in Network mode to identify the start of a frame. TFS is valid only if at least one transmitter is enabled (TE0, TE1, or TE2 are set).

TFS is cleared by hardware, software, ESSI individual, or stop reset.

Note: In Normal mode, TFS is always read as 1 when transmitting data because there is only one time slot per frame, the ‘frame sync’ time slot.

7.4.3.4 Receive Frame Sync Flag (RFS) SSISR Bit 3When set, the RFS bit indicates that a receive frame sync occurred during the reception of a word in the serial Receive Data Register. This means that the data word is from the first time slot in the frame. When the RFS bit is cleared and a word is received, it indicates (only in the Network mode) that the frame sync did not occur during reception of that word. RFS is valid only if the receiver is enabled (i.e., the RE bit is set).

RFS is cleared by hardware, software, ESSI individual, or stop reset.

Note: In Normal mode, RFS is always read as 1 when reading data because there is only one time slot per frame, the ‘frame sync’ time slot.

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7.4.3.5 Transmitter Underrun Error Flag (TUE) SSISR Bit 4The TUE bit is set when at least one of the enabled Serial Transmit Shift Registers is empty (no new data to be transmitted) and a transmit time slot occurs. When a transmit underrun error occurs, the previous data (which is still present in the TX registers that were not written) will be retransmitted. In the Normal mode, there is only one transmit time slot per frame. In the Network mode, there can be up to thirty-two transmit time slots per frame. If the TEIE bit is set, a DSP transmit underrun error interrupt request is issued when the TUE bit is set.

Hardware, software, ESSI individual, and stop reset clear TUE. TUE can also be cleared by first reading the SSISR with the TUE bit set, then writing to all the enabled Transmit Data Registers or to the TSR.

7.4.3.6 Receiver Overrun Error Flag (ROE) SSISR Bit 5The ROE bit is set when the Serial Receive Shift Register is filled and ready to transfer to the Receive Data Register (RX) but the RX is already full (i.e., when the RDF bit is set). If the REIE bit is set, a DSP receiver overrun error interrupt request is issued when the ROE bit is set.

Hardware, software, ESSI individual, and stop reset clear ROE. ROE can also be cleared by reading the SSISR with the ROE bit set and then reading the RX.

7.4.3.7 ESSI Transmit Data Register Empty (TDE) SSISR Bit 6The TDE bit is set when the contents of the Transmit Data Register of every enabled transmitter are transferred to the Transmit Shift Register. It is also set for a TSR disabled time slot period in Network mode (as if data were being transmitted after the TSR was written). When set, the TDE bit indicates that data should be written to all the TX registers of the enabled transmitters or to the TSR. The TDE bit is cleared when the DSP56304 writes to all the Transmit Data Registers of the enabled transmitters, or when the DSP writes to the TSR to disable transmission of the next time slot. If the TIE bit is set, a DSP transmit data interrupt request is issued when TDE is set.

Hardware, software, ESSI individual, and stop reset clear the TDE bit.

7.4.3.8 ESSI Receive Data Register Full (RDF) SSISR Bit 7The RDF bit is set when the contents of the Receive Shift Register are transferred to the Receive Data Register. The RDF bit is cleared when the DSP reads the Receive Data Register. If RIE is set, a DSP receive data interrupt request is issued when RDF is set.

Hardware, software, ESSI individual, and stop reset clear the RDF bit.

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Figure 7-19 ESSI Data Path Programming Model (SHFD = 0)

SRD

ESSI Receive Data Register(Read Only)

SerialReceive

ShiftRegister

24 Bit

WL1, WL0

24-bit Data

000

16-bit Data

12-bit Data

8-bit Data

LSB

LSB

LSB

LSBMSBLeast SignificantZero Fill

NOTES:•Data is received MSB first if SHFD = 0•24-bit fractional format (ALC = 0)•32-bit mode is not shown

16 Bit12 Bit8 Bit

(a) Receive Registers

STD

ESSI Transmit Data Register(Write Only)

ESSI Transmit Shift Register

24-bit Data

000

16-bit Data

12-bit Data

8-bit Data

LSB

LSB

LSB

LSBLeast SignificantZero Fill

(b) Transmit Registers

Transmit High Byte Transmit Middle Byte Transmit Low Byte


23 16 15 8 7 0

23 16 15

8

7 0

7 0 7

0

7 0

7 0 7 0 7 0

MSB

MSB

MSB

NOTES:•Data is transmitted MSB first ifSHFD = 0•24-bit fractional format (ALC = 0)•32-bit mode is not shown

Receive High Byte Receive Middle Byte Receive Low Byte


23 16 15 8 7 0

23 16 15 7 0

7 0 7 7 0

7 0 7 0 7 0

MSB

MSB

MSB

MSB

AA0686

0

8

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Figure 7-20 ESSI Data Path Programming Model (SHFD = 1)

SRD

ESSI Receive Data Register (Read Only)

ESSI ReceiveShift Register

24-bit Data

000

16-bit Data

12-bit Data

8-bit Data

LSB

LSB

LSB

LSBMSB

MSB

MSB

MSB

Least SignificantZero Fill

(a) Receive Registers

STD

ESSI Transmit Data Register (Write Only)

ESSI Transmit Shift Register

24 Bit

WL1, WL0

24-bit Data

000

16-bit Data

12-bit Data

8-bit Data

LSB

LSB

LSB

LSBMSB

MSB

MSB

MSB

Least SignificantZero Fill

16 Bit12 Bit8 Bit

(b) Transmit Registers



23 16 15 8 7 0

23 16 15 7 0

7 0 7 7 0

7 0 7 0 7 0




23 16 15 8 7 0

23 16 15 7 0

7 0 7 7 0

7 0 7 0 7 0


8

8

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0

0

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7.4.4 ESSI Receive Shift Register

The 24-bit Receive Shift Register (see Figure 7-19 and Figure 7-20) receives the incoming data from the Serial Receive Data signal. Data is shifted in by the selected (internal or external) bit clock when the associated frame sync I/O is asserted. It is assumed that data is received Most Significant Bit (MSB) first if SHFD is cleared and Least Significant Bit (LSB) first if SHFD is set. Data is transferred to the ESSI Receive Data Register after 8, 12, 16, 24, or 32 serial clock cycles are counted, depending on the word-length control bits in the CRA.

7.4.5 ESSI Receive Data Register (RX)

The Receive Data Register (RX) is a 24-bit read-only register that accepts data from the Receive Shift Register as it becomes full (see Figure 7-19 and Figure 7-20). The data read is aligned according to the value of the ALC bit. When the ALC bit is cleared, the MSB is bit 23 and the least significant byte is unused. When the ALC bit is set, the MSB is Bit 15 and the most significant byte is unused. Unused bits are read as 0s. If the associated interrupt is enabled, the DSP is interrupted whenever the RX register becomes full.

7.4.6 ESSI Transmit Shift Registers

The three 24-bit Transmit Shift Registers contain the data being transmitted (see Figure 7-19 and Figure 7-20). Data is shifted out to the Serial Transmit Data signals by the selected (internal or external) bit clock when the associated frame sync I/O is asserted. The word-length control bits in the CRA determine the number of bits that must be shifted out before the shift registers are considered empty and may be written to again. Depending on the setting of the CRA, the number of bits to be shifted out can be 8, 12, 16, 24, or 32 bits.

The data transmitted is aligned according to the value of the ALC bit. When the ALC bit is cleared, the MSB is Bit 23 and the least significant byte is unused. When ALC is set, the MSB is Bit 15 and the most significant byte is unused. Unused bits are read as 0s. Data is shifted out of these registers MSB first if the SHFD bit is cleared and LSB first if the SHFD bit is set.

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7.4.7 ESSI Transmit Data Registers

ESSI0:TX02, TX01, TX00; ESSI1:TX12, TX11, TX10

TX2, TX1, and TX0 are 24-bit write-only registers. Data to be transmitted is written into these registers and automatically transferred to the Transmit Shift Registers (see Figure 7-19 and Figure 7-20). The data transmitted (8, 12, 16, or 24 bits) is aligned according to the value of the ALC bit. When the ALC bit is cleared, the MSB is Bit 23. When ALC is set, the MSB is Bit 15. If the transmit data register empty interrupt has been enabled, the DSP is interrupted whenever a Transmit Data Register becomes empty.

Note: When writing data to a peripheral device there is a two core clock cycle pipeline delay until any status bits affected by this operation are updated. If the user reads any of those status bits within the next two cycles, the bit will not reflect its current status. See the DSP56300 Family Manual, Appendix B, Polling a Peripheral Device for Write for further details.

7.4.8 ESSI Time Slot Register (TSR)

TSR is effectively a write-only null data register that is used to prevent data reception in the current receive time slot. For the purposes of timing, TSR is a write-only register that behaves like an alternative Receive Data Register except that rather than receiving data, the receive data signals of all the enabled receivers are in the high-impedance state for the current time slot.

7.4.9 Transmit Slot Mask Registers (TSMA, TSMB)

The Transmit Slot Mask Registers are two 16-bit read/write registers. When the TSMA or TSMB is read to the internal data bus, the register contents occupy the two low-order bytes of the data bus, and the high-order byte is zero-filled. In Network mode, these registers are used by the transmitter(s) to determine what action to take in the current transmission slot. Depending on the setting of the bits, the transmitter(s) either tri-state their data signal(s) or transmit a data word and generate a transmitter empty condition (TDE = 1).

TSMA and TSMB (see Figure 7-19 and Figure 7-20) can be seen as a single 32-bit register, TSM. Bit k in TSM (TSMk) is an enable/disable control bit for transmission in slot number K. When TSMk is cleared, all the transmit data signals of the enabled transmitters are tri-stated during transmit time slot number K. The data is still

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transferred from the enabled Transmit Data Register(s) to the Transmit Shift Register. However, the TDE and the TUE flags are not set. This means that during a disabled slot, no transmitter empty interrupt is generated. The DSP is interrupted only for enabled slots. Data written to the Transmit Data Register when servicing the transmitter empty interrupt request is transmitted in the next enabled transmit time slot.

When TSMk is set, the transmit sequence proceeds normally. Data is transferred from the TX register to the Shift Register during slot number K and the TDE flag is set.

Changing the bits in the TSM affects the next frame transmission. The frame currently being transmitted is not affected by the new TSM value. If the TSM is read, it shows the current value.

Using the TSM slot mask does not conflict with using the TSR. Even if a slot is enabled in the TSM, the user may choose to write to the TSR to tri-state the transmit data signals of the enabled transmitters during the next transmission slot.

After a hardware or software reset instruction, the TSM register is reset to $FFFFFFFF, which enables all thirty-two slots for data transmission.

7.4.10 Receive Slot Mask Registers (RSMA, RSMB)

The Receive Slot Mask Registers are two 16-bit read/write registers. In Network mode, these registers are used by the receiver(s) to determine what action to take in the current time slot. Depending on the setting of the bits, the receiver(s) either tri-state their data signal(s) or receive a data word and generate a receiver full condition (RDF = 1).

RSMA and RSMB (see Figure 7-19 and Figure 7-20) can be seen as one 32-bit register, RSM. Bit k in RSM (RSMk) is an enable/disable control bit for time slot number K. When RSMk is cleared, all the data signals of the enabled receivers are tri-stated during time slot number K. Data is not transferred from the Receive Data Register(s) to the Receive Shift Register(s) and the RDF and ROE flags are not set. During a disabled slot, no receiver full interrupt is generated. The DSP is interrupted only for enabled slots.

When RSMk is set, the receive sequence proceeds normally. Data shifted into the Receive Shift Register is transferred into the Receive Data Register during slot number K, and the RDF flag is set.

Changing the bits in the RSM affects the next frame transmission. The frame currently being received is not affected by the new RSM value. If the RSM is read, it shows the current value.

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Operating Modes

When the RSMA or RSMB register are read by the internal data bus, the register contents occupy the two low-order bytes of the data bus, and the high-order byte is zero-filled.

After a hardware reset or a software reset instruction, the RSM register is reset to $FFFFFFFF. This enables all thirty-two time slots for data reception.

7.5 OPERATING MODES

The ESSI operating modes are selected by the ESSI Control Registers (CRA and CRB). The operating modes are described in the following paragraphs.

7.5.1 ESSI Initialization

A hardware reset signal or software reset instruction clears the Port Control Register and the Port Direction Control Register. This configures all the ESSI signal signals as GPIO. The ESSI is in the reset state while all ESSI signals are programmed as GPIO and is active only if at least one of the ESSI I/O signals is programmed as an ESSI signal.

To initialize the ESSI do the following:

1. Send a reset: hardware, software, ESSI individual, or STOP instruction reset.

2. Program the ESSI control and time slot registers.

3. Write data to all the enabled transmitters.

4. Configure at least one signal as ESSI signal.

5. If an external frame sync will be used, from the moment the ESSI is activated, at least five (5) serial clocks are needed before the first external frame sync is supplied. Otherwise, improper operation may result.

Clearing the PC[5:0] bits in the GPIO Port Control Register (PCR) during program execution causes the ESSI to stop serial activity and enter the individual reset state. All status bits of the interface are set to their reset state, but the contents of CRA and CRB are not affected. The ESSI individual reset allows a program to reset each interface separately from the other internal peripherals. During ESSI individual reset, internal DMA accesses to the data registers of the ESSI are not valid and data read is undefined.

To ensure proper operation of the ESSI, use an ESSI individual reset when changing the ESSI Control Registers (except for bits TEIE, REIE, TLIE, RLIE, TIE, RIE, TE2, TE1, TE0, and RE).

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Operating Modes


Here is an example of initializing the ESSI.

1. Put the ESSI in its individual reset state by clearing the PCR bits.

2. Configure the Control Registers (CRA, CRB) to set the operating mode. Disable the transmitters and receiver by clearing the TE[2:0] and RE bits. Set the interrupt enable bits for the operating mode chosen.

3. Enable the ESSI by setting the PCR bits to activate the input/output signals to be used.

4. Write initial data to the transmitters which will be in use during operation. This step is needed even if DMA is used to service the transmitters.

5. Enable the transmitters and receiver to be used.

Now the ESSI can be serviced by polling, interrupts, or DMA.

Once the ESSI has been enabled (Step 3), operation will start as follows:

• For internally generated clock and frame sync, these signals will start activity immediate after the ESSI is enabled.

• Data will be received by the ESSI after the occurrence of a frame sync signal (either internally or externally generated) only when the Receive Enable (RE) bit is set.

• Data will be transmitted after the occurrence of a frame sync signal (either internally or externally generated) only when the Transmitter Enable (TE[2:0]) bit is set.

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Operating Modes

7.5.2 ESSI Exceptions

The ESSI can generate six different exceptions.

7.5.2.1 ESSI Exception TypesThe ESSI exception types are discussed in the following paragraphs (ordered from the highest to the lowest exception priority):

1. ESSI Receive Data with Exception StatusOccurs when the receive exception interrupt is enabled, the Receive Data Register is full, and a receiver overrun error has occurred. This exception sets the ROE bit. The ROE bit is cleared by first reading the SSISR and then reading RX.

2. ESSI Receive DataOccurs when the receive interrupt is enabled, the Receive Data Register is full, and no receive error conditions exist. Reading RX clears the pending interrupt. This error-free interrupt can use a fast interrupt service routine for minimum overhead.

3. ESSI Receive Last Slot InterruptOccurs when the ESSI is in Network mode and the last slot of the frame has ended. This interrupt is generated regardless of the Receive Mask Register setting. The receive last slot interrupt may be used to signal that the Receive Mask Slot Register can be reset, the DMA channels may be reconfigured, and data memory pointers may be reassigned. Using the receive last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame will be serviced with the new setting without synchronization problems.

Note: The maximum time it takes to service a receive last slot interrupt should not exceed W – 1 ESSI bits service time (where W is the word length in bits).

4. ESSI Transmit Data with Exception StatusOccurs when the transmit exception interrupt is enabled, at least one Transmit Data Register of the enabled transmitters is empty, and a transmitter underrun error has occurred. This exception sets the TUE bit. The TUE bit is cleared by first reading the SSISR and then writing to all the Transmit Data Registers of the enabled transmitters, or by writing to the TSR to clear the pending interrupt.

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Operating Modes


5. ESSI Transmit Last Slot InterruptOccurs when the ESSI is in Network mode at the start of the last slot of the frame. This exception occurs regardless of the Transmit Mask Register setting. The transmit last slot interrupt may be used to signal that the Transmit Mask Slot Register can be reset, the DMA channels can be reconfigured, and data memory pointers can be reassigned. Using the transmit last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame will be serviced with the new setting without synchronization problems.

Note: The maximum transmit last slot interrupt service time should not exceed W – 1 ESSI bits service time (where W is the word length in bits).

6. ESSI Transmit DataOccurs when the transmit interrupt is enabled, at least one of the enabled Transmit Data Registers is empty, and no transmitter error conditions exist. Writing to all the enabled TX registers or to the TSR clears this interrupt. This error-free interrupt may use a fast interrupt service routine for minimum overhead (if no more than two transmitters are used).

7.5.2.2 Exception ConfigurationTo configure an ESSI exception, perform the steps listed below. The register examples to the right of the steps show register settings for configuring an ESSI0 transmit interrupt using transmitter 0. The format used is REGISTER (BITFIELD).

1. Configure Interrupt Service Routine (ISR)

a. Load Vector Base Address Register VBA(23:8)

b. Define I_VEC to be equal to the VBA value (if that isnonzero). If it is defined, I_VEC must be defined for theassembler before the interrupt equate file is included.

c. Load the exception vector table entry: two-word fastinterrupt, or jump/branch to subroutine (long interrupt). p:I_SI0TD

2. Configure interrupt trigger/Preload transmit data

a. Enable and prioritize overall peripheral interruptfunctionality IPRP(S0L1:0)

b. Write data to all enabled transmit registers. TX00

c. Enable peripheral interrupt-generating function. CRB(TE0)

d. Enable specific peripheral interrupt. CRB0(TIE)

e. Enable peripheral and associated signals. PCRC(PC5:0)

f. Unmask interrupts at global level. SR(I1:0)

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Operating Modes

Notes: 1. The order of the steps is optional except that the interrupt trigger configuration must not be completed until the ISR configuration has been completed. Since 2c may cause an immediate transmit without generating an interrupt, the transmit data preload in 2b should be performed before 2c to ensure valid data is sent in the first transmission.

2. After the first transmit, subsequent transmit values are typically loaded into TXnn by the ISR (one value per register per interrupt). Therefore, if N items are to be sent from a particular TXnn, the ISR will need to load the transmit register (N – 1) times.

3. Steps 2c and 2d may be performed using a single instruction.

4. If an interrupt trigger event occurs at a time when not all interrupt trigger configuration steps have been performed, the event will be ignored forever (the event will not be queued in this case).

5. If interrupts derived from the core or other peripherals need to be enabled at the same time as ESSI interrupts, step 2f should be done last.

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Operating Modes


7.5.3 Operating Modes

The ESSI has three basic operating modes and several data/operation formats. These modes can be programmed using the ESSI Control Registers. The data/operation formats available to the ESSI are selected by setting or clearing control bits in the CRA and CRB. These control bits are WL[2:1], MOD, SYN, FSL[1:0], FSR, FSP, CKP, and SHFD.

7.5.3.1 Normal Mode (CRB(MOD) = 0)Normal mode is typically used to transfer data to or from a single device. Selecting the Normal mode is accomplished by clearing the MOD bit in the CRB. In Normal mode, the ESSI sends or receives one data word per frame (per enabled receiver or transmitter). The transfers are periodic.

7.5.3.2 Network Mode (CRB(MOD) = 1; CRA(DC) ≠ 00000)The ESSI's Network mode is well-suited for using the DSP in Time Division Multiplexing (TDM) networks, or in parallel processing networks.

In Network mode, the ESSI may be programmed for two to thirty-two time slots per frame (always the same number for receive and transmit). A single data word may be received or transmitted (from each enabled receiver or transmitter) during each time slot. The duration of a receive or transmit time slot equals the time needed to shift one word in or out of the ESSI, respectively. In other words, if the word size is 24 bits, one time slot consists of exactly 24 ESSI clock periods (“bit times”). An edge on the receive or transmit frame sync signal (rising or falling edge, but never both) indicates the beginning of a new data frame.

Figure 7-21 ESSI Main Modes

AA1427

ESSI

NormalMode

NetworkMode

On-DemandMode

10

01-31CRB

MOD

CRA

DC[4:0]

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Operating Modes

Time slots are contiguous – with one exception, the last bit time in time slot K is always immediately followed by the first bit time in time slot K+1. The exception involves the last time slot in the frame, in conjunction with an external frame sync. If an internal frame sync is used, the last time slot in the frame will be contiguous with the first time slot in the next frame. The same situation is possible, but not required, if an external frame sync is used. In summary, it is possible for an ESSI receive or transmit channel to transfer a new data bit during every bit time in the frame.

Each ESSI in the network is assigned zero, one, or more receive time slots, and zero, one, or more transmit time slots. The time slot assignment scheme used is dependent on the network topology and software multiprocessing algorithm which is used. The receive and transmit time slots of a given ESSI may be assigned independently of each other if its receive and transmit pins are on different network nodes, and the multiprocessing algorithm does not cause them to be interdependent.

An ESSI must receive or transmit only during its assigned receive or transmit time slots, respectively. For the case in which transmitters from more than one ESSI are connected to a given network node, this will prevent network collisions. The core code must also take into account the inherent delays which occur in the ESSI due to double buffering and serial/parallel conversion. Data written to the transmit register(s) in time slot K will be shifted out of the ESSI in time slot K+1; data read from the receive register in time slot K was shifted into the ESSI in time slot K-1. For the purposes of this discussion, any reference to a “time slot” is from the core point of view. In other words, this is the time slot in which the appropriate ESSI data register is read or written, as opposed to when the serial data is actually transferred.

Time slot mask registers may be used to constrain an ESSI to transferring data only during its assigned time slots. These registers are used to disable the receiver or transmitter(s), along with the associated status flags, during all but the assigned time slots. The result is that actions triggered by an ESSI's status flags or interrupts will only occur during that ESSI's designated receive or transmit time slots. Masking out unneeded time slots saves core MIPS because the ISRs are only called during the assigned time slots. Time slot assignment may be predesignated or changed dynamically (mask register changes take effect in the following frame).

If an ESSI needs to receive during more than one time slot per frame, or transmit during more than one time slot per frame, then a system must be employed for tracking the assigned slots within a given frame. Various solutions are possible, such as multiple DMA channels, software counters, or input/output buffers with a known data interleaving scheme.

Details on programming the ESSI in network mode are given in subsequent sections.

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Operating Modes


7.5.3.3 On-Demand Mode (CRB(MOD) = 1, DC = 00000)Network mode has a sub-mode called On-demand mode. Setting the MOD bit in the CRB for Network mode, and setting the frame rate divider to 0 (DC[4:0] = 00000) selects the On-demand mode.This sub-mode does not generate a periodic frame sync. A frame sync pulse is generated only when data is available to transmit. The frame sync signal indicates the beginning of the frame.

The On-demand mode requires that the transmit frame sync be internal (output) and the receive frame sync be external (input). For simplex operation, the Synchronous mode could be used; however, for full-duplex operation, the Asynchronous mode must be used. Data transmission of a word is enabled by writing data into each TX. Although the ESSI is double-buffered, only one word can be written to a transmit register, even if the Transmit Shift Register is empty. Note that if full duplex is used, the ESSI must be in synchronous mode, so that only one transmit signal, and thus one transmit register, will be available for use. The receive and transmit interrupts function normally, using TDE and RDF; however, transmit underruns are impossible in On-demand transmission and are disabled.

On-demand mode is useful for interfacing to codecs requiring a continuous clock.

7.5.3.4 Synchronous/Asynchronous Operating ModesThe transmit and receive sections of the ESSI interface may be synchronous or asynchronous. The transmitter and receiver use common clock and synchronization signals in the Synchronous mode; they use separate clock and sync signals in the Asynchronous mode. The SYN bit in CRB selects synchronous or asynchronous operation. When the SYN bit is cleared, the ESSI TX and RX clocks and frame sync sources are independent. If the SYN bit is set, the ESSI TX and RX clocks and frame sync are driven by the same source (either external or internal). Since the ESSI is designed to operate either synchronously or asynchronously, separate receive and transmit interrupts are provided.

Transmitter 1 and transmitter 2 operate only in Synchronous mode. Data clock and frame sync signals can be generated internally by the DSP or may be obtained from external sources. If clocks are internally generated, the ESSI clock generator derives bit clock and frame sync signals from the DSP internal system clock. The ESSI clock generator consists of a selectable fixed prescaler with a programmable prescaler for bit rate clock generation and a programmable frame-rate divider with a word-length divider for frame-rate sync-signal generation.

The ESSI receive timing may be independent of the transmit timing. In the Normal and Network modes, the receive channel may be asynchronous with respect to the transmit channel(s); i.e., the receive clock rate may not match the transmit clock rate. As a result,

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Operating Modes

in these modes, receive and transmit may have different word and frame rates (but the receive and transmit word size is always the same number of bits).

On the other hand, the transmit timing is always the same for all transmit channels, in all modes of operation. All enabled ESSI transmitters (one in Synchronous mode, and up to three in Asynchronous mode) will have the same bit, word, and frame timing.

7.5.3.5 Frame Sync SettingsThe transmitter and receiver can operate independently. The transmitter can have either a bit-long or word-long frame-sync signal format, and the receiver can have the same or another format. The selection is made by programming FSL[1:0], FSR, and FSP bits in the CRB.

7.5.3.5.1 Frame Sync Signal FormatFSL1 controls the frame-sync signal format.

• If the FSL1 bit is cleared, the RX frame sync is asserted during the entire data transfer period. This frame sync length is compatible with Motorola codecs, serial peripherals that conform to the Motorola SPI, serial A/D and D/A converters, shift registers, and telecommunication Pulse Code Modulation (PCM) serial I/O.

• If the FSL1 bit is set, the RX frame sync pulses active for one bit clock immediately before the data transfer period. This frame sync length is compatible with Intel and National components, codecs, and telecommunication PCM serial I/O.

7.5.3.5.2 Frame Sync Length for Multiple DevicesThe ability to mix frame sync lengths is useful in configuring systems in which data is received from one type of device (e.g., codec) and transmitted to a different type of device. FSL0 controls whether RX and TX have the same frame sync length.

• If the FSL0 bit is cleared, both RX and TX have the same frame sync length.

• If the FSL0 bit is set, RX and TX have different frame sync lengths.

FSL0 is ignored when the SYN bit is set.

7.5.3.5.3 Word Length Frame Sync PositionThe FSR bit controls the relative timing of the word length frame sync relative to the data word timing.

• When the FSR bit is cleared, the word length frame sync is generated (or expected) with the first bit of the data word.

• When the FSR bit is set, the word length frame sync is generated (or expected) with the last bit of the previous word.

FSR is ignored when a bit length frame sync is selected.

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Operating Modes


7.5.3.5.4 Frame Sync PolarityThe FSP bit controls the polarity of the frame sync.

• When the FSP bit is cleared, the polarity of the frame sync is positive (i.e., the frame sync signal is asserted high). The ESSI synchronizes on the leading edge of the frame sync signal.

• When the FSP bit is set, the polarity of the frame sync is negative (i.e., the frame sync is asserted low). The ESSI synchronizes on the trailing edge of the frame sync signal.

The ESSI receiver looks for a receive frame sync edge (leading edge if FSP is cleared, trailing edge if FSP is set) only when the previous frame is completed. If the frame sync is asserted before the frame is completed (or before the last bit of the frame is received in the case of a bit frame sync or a word length frame sync with FSR set), the current frame sync is not recognized, and the receiver is internally disabled until the next frame sync.

Frames do not have to be adjacent, that is, a new frame sync does not have to follow immediately the previous frame. Gaps of arbitrary periods can occur between frames. All the enabled transmitters will be tri-stated during these gaps.

7.5.3.6 Selecting the Bit Shift Order for the TransmitterSome devices, such as codecs, require a MSB-first data format. Other devices, such as those that use the AES-EBU digital audio format, require the LSB first. To be compatible with all formats, the shift registers in the ESSI are bidirectional. The MSB/LSB selection is made by programming the SHFD bit in the CRB.

• If the SHFD bit is cleared, data is shifted into the Receive Shift Register MSB first and shifted out of the Transmit Shift Register MSB first.

• If the SHFD bit is set, data is shifted into the Receive Shift Register LSB first and shifted out of the Transmit Shift Register LSB first.

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GPIO/ESSI Selection and GPIO Usage

7.5.4 ESSI Flag Usage

Two ESSI signals (SC[1:0]) are available for use as serial I/O flags. Their operation is controlled by the SYN, SCD[1:0], SSC1, and TE[2:1] bits in the CRB/CRA.The control bits OF[1:0] and status bits IF[1:0] are double-buffered to/from SC[1:0]. Double-buffering the flags keeps the flags in sync with TX and RX.

The SC[1:0] flags are available in the Synchronous mode only. Each flag can be separately programmed.

Flag SC0 is enabled when transmitter 1 is disabled (TE1 = 0). The flag’s direction is selected by the SCD0 bit. When SCD0 is set, SC0 is configured as output. When SCD0 is cleared, SC0 is configured as input.

Similarly, the SC1 flag is enabled when transmitter 2 is disabled (TE2 = 0) and the SC1 signal is not configured as transmitter drive enable (Bit SSC1 = 0). SC1’s direction is selected by the SCD1 bit. When SCD1 is set, SC1 is an output flag. When SCD1 is cleared, SC1 is an input flag.

When programmed as input flags, the value of the SC[1:0] bits are latched at the same time as the first bit of the receive data word is sampled. Once the input has been latched, the signal on the input flag signal (SC0 and SC1) can change without affecting the input flag. The value of SC[1:0] does not change until the first bit of the next data word is received. When the received data word is latched by RX, the latched values of SC[1:0] are latched by the SSISR IF[1:0] bits respectively, and can be read by software.

When programed as output flags, the value of the SC[1:0] bits is taken from the value of the OF[1:0] bits. The value of the OF[1:0] bits is latched when the contents of TX are transferred to the Transmit Shift Register. The value of SC[1:0] is stable from the time the first bit of the transmit data word is transmitted until the first bit of the next transmit data word is transmitted. The OF[1:0] values can be set directly by software. This allows the DSP56305 to control data transmission by indirectly controlling the value of the SC[1:0] flags.

7.6 GPIO/ESSI SELECTION AND GPIO USAGE

The GPIO functionality of an ESSI port (ESSI0 is Port C, ESSI1 is Port D) is controlled by three registers: Port Control Register (PCRC, PCRD), Port Direction Register (PRRC, PRRD) and Port Data Register (PDRC, PDRD). After a hardware reset, all Port C and Port D pins are configured as GPIO inputs.

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7.6.1 Port Control Register (PCR)

The read/write twenty-four-bit Port Control Register(PCR) controls the functionality of the ESSI/GPIO signals. Each of the PC[5:0] bits controls the functionality of the corresponding port signal. When a PC[i] bit is set, the corresponding port signal is configured as a ESSI signal. When a PC[i] bit is cleared, the corresponding port signal is configured as a GPIO signal. Either a hardware reset signal or a software reset instruction clear all PCR bits.

Figure 7-22 GPIO/ESSI Port Organization

Figure 7-23 Port Control Register (PCR)

AA1426

Port C

GPIO ESSI0

Port D

GPIO ESSI1

6 6

DSP56305

per pin per pin

PC0PC1PC2PC3PC4PC5

Reserved Bit, Read As Zero, Should Be Written With Zero For Future Compatibility

01234567

89101112131415

1617181920212223

AA0688

STDn SRDn SCKn SCKn2 SCKn1 SCKn0 PCRC: ESSI0, X:$FFFFBF

0 = GPIO, 1 = ESSI

PCRD: ESSI1, X:$FFFFAF

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7.6.2 Port Direction Register (PRR)

The read/write twenty-four-bit Port Direction Register (PRR) controls the data direction of the ESSI GPIO signals. When PRR[i] is set, the corresponding signal is an output signal. When PRR[i] is cleared, the corresponding signal is an input signal.

Note: Either a hardware reset signal or a software reset instruction clear all PRR bits.

The following table describes the port signal configurations.

Figure 7-24 Port Direction Register (PRR)

Table 7-5 Port Control Register and Port Direction Register Bits Functionality

PC[i] PDC[i] Port Signal[i] Function

1 X ESSI

0 0 GPIO input

0 1 GPIO output

Note: X: The signal setting is irrelevant to Port Signal[i] function.

01234567

PDC0PDC1PDC2PDC3PDC4PDC5


89101112131415

1617181920212223

AA0689

STDn SRDn SCKn SCKn2 SCKn1 SCKn0 PRRC: ESSI0, X:$FFFFBE

0 = Input, 1 = Output

PRRD: ESSI1, X:$FFFFAE

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7.6.3 Port Data Register (PDR)

The read/write twenty-four-bit Port Data Register (PDR) is used to read or write data to and from the ESSI GPIO signals. The PD[5:0] bits are used to read or write data from and to the corresponding port signals if they are configured as GPIO signals. If a port signal [i] is configured as a GPIO input, then the corresponding PD[i] bit reflects the value present on this signal. If a port signal [i] is configured as a GPIO output, then the value written into the corresponding PD[i] bit is reflected on the this signal.

Note: Either a hardware reset signal or a software reset instruction clear all PDR bits.Figure 7-25 Port Data Register (PDR)

01234567

89101112131415

PD0PD1PD2PD3PD4PD5


1617181920212223

AA0690

STDn SRDn SCKn SCKn2 SCKn1 SCKn0 PDRC: ESSI0, X:$FFFFBDPDRD: ESSI1, X:#FFFFAD

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SECTION 8

SERIAL COMMUNICATION INTERFACE (SCI)

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8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-38.2 SCI I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-38.3 SCI Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-48.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-218.5 GPIO Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .8-27

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Introduction


8.1 INTRODUCTION

The DSP56305’s Serial Communications Interface (SCI) provides a full-duplex port for serial communication to other DSPs, microprocessors, or peripherals such as modems. The SCI interfaces without additional logic to peripherals that use TTL-level signals. With a small amount of additional logic, the SCI can connect to peripheral interfaces that have non-TTL level signals, such as the RS232C, RS422, etc.

This interface uses three dedicated signals: Transmit Data (TXD), Receive Data (RXD), and SCI Serial Clock (SCLK). It supports industry-standard asynchronous bit rates and protocols, as well as high-speed synchronous data transmission (up to 10.0 Mbps for an 80 MHz clock). The asynchronous protocols supported by the SCI include a Multidrop mode for master/slave operation with Wakeup On Idle Line and Wakeup On Address Bit capability. This mode allows the DSP56305 to share a single serial line efficiently with other peripherals.

The SCI consists of separate transmit and receive sections that can operate asynchronously with respect to each other. A programmable baud-rate generator provides the transmit and receive clocks. An enable vector and an interrupt vector have been included so that the baud-rate generator can function as a general purpose timer when it is not being used by the SCI, or when the interrupt timing is the same as that used by the SCI.

8.2 SCI I/O SIGNALS

Each of the three SCI signals (RXD, TXD, and SCLK) can be configured as either a General Purpose I/O (GPIO) signal or as a specific SCI signal. Each signal is independent of the others. For example, if only the TXD signal is needed, the RXD and SCLK signals can be programmed for GPIO. However, at least one of the three signals must be selected as an SCI signal to release the SCI from reset.

SCI interrupts can be enabled by programming the SCI control registers before any of the SCI signals are programmed as SCI functions. In this case, only one transmit interrupt can be generated because the Transmit Data Register is empty. The timer and timer interrupt operate when one or more of the SCI signals is programmed as an SCI signal.

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SCI I/O signals

8.2.1 Receive Data (RXD)

This input signal receives byte-oriented serial data and transfers the data to the SCI Receive Shift Register. Asynchronous input data is sampled on the positive edge of the receive clock (1 × SCLK) if SCKP is cleared. RXD can be configured as a GPIO signal (PE0) when the SCI RXD function is not being used.

8.2.2 Transmit Data (TXD)

This output signal transmits serial data from the SCI Transmit Shift Register. Data changes on the negative edge of the asynchronous transmit clock (SCLK) if SCKP is cleared. This output is stable on the positive edge of the transmit clock. TXD can be programmed as a GPIO signal (PE1) when the SCI TXD function is not being used.

8.2.3 SCI Serial Clock (SCLK)

This bidirectional signal provides an input or output clock from which the transmit and/or receive baud rate is derived in the Asynchronous mode and from which data is transferred in the Synchronous mode. SCLK can be programmed as a GPIO signal (PE2) when the SCI SCLK function is not being used. This signal can be programmed as PE2 when data is being transmitted on TXD, since the clock does not need to be transmitted in the Asynchronous mode. Because SCLK is independent of SCI data I/O, there is no connection between programming the PE2 signal as SCLK and data coming out the TXD signal.

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SCI Programming Model


8.3 SCI PROGRAMMING MODEL

The SCI programming model can be viewed as three types of registers:

• Control

– SCI Control Register (SCR) in Figure 8-1

– SCI Clock Control Register (SCCR) in Figure 8-3

• Status

– SCI Status Register (SSR) in Figure 8-2

• Data transfer

– SCI Receive Data Registers (SRX) in Figure 8-8

– SCI Transmit Data Registers (STX) in Figure 8-8

– SCI Transmit Data Address Register (STXA) in Figure 8-8

The SCI also contains GPIO functionality, as described in Section 8.5 .

The following paragraphs describe each bit in the programming model.

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7 6 5 4 3 2 1 0WOMS RWU WAKE SBK SSFTD WDS2 WDS1 WDS0

15 14 13 12 11 10 9 8SCKP STIR TMIE TIE RIE ILIE TE RE

23 22 21 20 19 18 17 16REIE

AA0854

Figure 8-1 SCI Control Register (SCR)

7 6 5 4 3 2 1 0R8 FE PE OR IDLE RDRF TDRE TRNE

15 14 13 12 11 10 9 8

23 22 21 20 19 18 17 16

AA0855

Figure 8-2 SCI Status Register (SSR)

7 6 5 4 3 2 1 0CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0

15 14 13 12 11 10 9 8TCM RCM SCP COD CD11 CD10 CD9 CD8

23 22 21 20 19 18 17 16

Reserved bit - read as 0 should be written with 0 for future compatibilityAA0856

Figure 8-3 SCI Clock Control Register (SCCR)

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Figure 8-4 SCI Data Word Formats (SSFTD=0)

Mode 0

8-bit Synchronous Data (Shift Register Mode)

TX(SSFTD = 0)

One Byte From Shift Register

Mode 2

10-bit Asynchronous (1 Start, 8 Data, 1 Stop)

TX(SSFTD = 0)

D7 orData Type

StopBit

Mode 4

11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop)

TX(SSFTD = 0)

D7 orData Type

StopBit

EvenParity

Mode 5

11-bit Asynchronous (1 Start, 8 Data, 1 Odd Parity, 1 Stop)

TX(SSFTD = 0)

StartBit

D7 orData Type

StopBit

OddParity

Mode 6

11-bit Asynchronous Multidrop (1 Start, 8 Data, 1 Data Type, 1 Stop)

TX(SSFTD = 0)

StartBit

StopBit

DataType

Note: 1. Modes 1, 3, and 7 are reserved.2. D0 = LSB; D7 = MSB3. Data is transmitted and received LSB first if SSFTD = 0, or MSB first if SSFTD = 1

D0 D1 D2 D3 D4 D5 D6 D7

0 1 0

D0 D1 D2 D3 D4 D5 D6

WDS2 WDS1 WDS0

0 0 0

1 0 0

D0 D1 D2 D3 D4 D5 D6

D0 D1 D2 D3 D4 D5 D6

StartBit

WDS2 WDS1 WDS0

StartBit

WDS2 WDS1 WDS0

1 0 1

WDS2 WDS1 WDS0

D0 D1 D2 D3 D4 D5 D6 D7

1 1 0

WDS2 WDS1 WDS0

0 = Data ByteData Type: 1 = Address Byte

AA0691a

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Figure 8-5 SCI Data Word Formats (SSFTD=1)

Mode 0

8-bit Synchronous Data (Shift Register Mode)

TX(SSFTD = 1)

One Byte From Shift Register

Mode 2

10-bit Asynchronous (1 Start, 8 Data, 1 Stop)

TX(SSFTD = 1)

StartBit

StopBit

Mode 4

11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop)

TX(SSFTD = 1)

StartBit

StopBit

EvenParity

Mode 5

11-bit Asynchronous (1 Start, 8 Data, 1 Odd Parity, 1 Stop)

TX(SSFTD = 1)

StartBit

D0 orData Type

StopBit

OddParity

Mode 6

11-bit Asynchronous Multidrop (1 Start, 8 Data, 1 Data Type, 1 Stop)

TX(SSFTD = 1)

StartBit

StopBit

DataType

D7 D6 D5 D4 D3 D2 D1 D0

WDS2 WDS1 WDS0

0 0 0

Note: 1. Modes 1, 3, and 7 are reserved.2. D0 = LSB; D7 = MSB3. Data is transmitted and received LSB first if SSFTD = 0, or MSB first if SSFTD = 1

0 = Data ByteData Type: 1 = Address Byte

AA0691b

D0 orData Type

D7 D6 D5 D4 D3 D2 D1

D7 D6 D5 D4 D3 D2 D1

D0 orData Type

D7 D6 D5 D4 D3 D2 D1

D7 D6 D5 D4 D3 D2 D1 D0

WDS2 WDS1 WDS0

0 1 0

WDS2 WDS1 WDS0

1 0 0

WDS2 WDS1 WDS0

1 0 1

WDS2 WDS1 WDS0

1 1 0

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8.3.1 SCI Control Register (SCR)

The SCI Control Register (SCR) is a 24-bit read/write register that controls the serial interface operation. Seventeen of the twenty-four bits are currently defined. Each bit is described in the following paragraphs.

8.3.1.1 Word Select (WDS[0:2]) SCR Bits 0-2The word select WDS[0:2] bits select the format of transmitted and received data. Format modes are listed in Table 8-1 and described in Figure 8-4.

The Asynchronous modes are compatible with most UART-type serial devices, and support standard RS232C communication links. The Multidrop Asynchronous mode is compatible with the MC68681 DUART, the M68HC11 SCI interface, and the Intel 8051 serial interface. The Synchronous data mode is essentially a high-speed shift register used for I/O expansion and stream-mode channel interfaces. Data synchronization is accomplished by the use of a gated transmit and receive clock that is compatible with the Intel 8051 serial interface mode 0.

Table 8-1 Word Formats

WDS2 WDS1 WDS0 Mode Word Formats

0 0 0 0 8-Bit Synchronous Data (shift register mode)

0 0 1 1 Reserved

0 1 0 2 10-Bit Asynchronous (1 start, 8 data, 1 stop)

0 1 1 3 Reserved

1 0 0 4 11-Bit Asynchronous(1 start, 8 data, 1 even parity, 1 stop)

1 0 1 5 11-Bit Asynchronous (1 start, 8 data, 1 odd parity, 1 stop)

1 1 0 6 11-Bit Multidrop Asynchronous(1 start, 8 data, 1 data type, 1 stop)

1 1 1 7 Reserved

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When odd parity is selected, the transmitter counts the number of 1s in the data word. If the total is not an odd number, the parity bit is set, thus producing an odd number. If the receiver counts an even number of 1s, an error in transmission has occurred. When even parity is selected, an even number must result from the calculation performed at both ends of the line or an error in transmission has occurred.

The word select bits are cleared by hardware and software reset.

8.3.1.2 SCI Shift Direction (SSFTD) SCR Bit 3The SSFTD bit determines the order in which the SCI Data Shift Registers shift data in or out: MSB first when set, LSB first when cleared. The parity and data type bits do not change their position in the frame, and remain adjacent to the stop bit. SSFTD is cleared by hardware and software reset.

8.3.1.3 Send Break (SBK) SCR Bit 4A break is an all-zero word frame—a start bit 0, characters of all 0s (including any parity), and a stop bit 0 (i.e., ten or eleven 0s, depending on the mode selected). If SBK is set and then cleared, the transmitter completes transmission of the current frame, sends ten or eleven 0s (depending on WDS mode), and reverts to idle or sending data. If SBK remains set, the transmitter continually sends whole frames of 0s (ten or eleven bits with no stop bit). At the completion of the break code, the transmitter sends at least one high (set) bit before transmitting any data to guarantee recognition of a valid start bit. Break can be used to signal an unusual condition, message, etc. by forcing a frame error, which is caused by a missing stop bit. Hardware and software reset clear SBK.

8.3.1.4 Wakeup Mode Select (WAKE) SCR Bit 5When WAKE is cleared, the Wakeup On Idle Line mode is selected. In the Wakeup On Idle Line mode, the SCI receiver is re-enabled by an idle string of at least ten or eleven (depending on WDS mode) consecutive 1s. The transmitter’s software must provide this idle string between consecutive messages. The idle string cannot occur within a valid message because each word frame contains a start bit that is 0.

When WAKE is set, the Wakeup On Address Bit mode is selected. In the Wakeup On Address Bit mode, the SCI receiver is re-enabled when the last (eighth or ninth) data bit received in a character (frame) is 1. The ninth data bit is the address bit (R8) in the 11-bit Multidrop mode; the eighth data bit is the address bit in the 10-bit Asynchronous and 11-bit Asynchronous with parity modes. Thus, the received character is an address that has to be processed by all sleeping processors—that is, each processor has to compare the received character with its own address and decide whether to receive or ignore all following characters. WAKE is cleared by hardware and software reset.

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8.3.1.5 Receiver Wakeup Enable (RWU) SCR Bit 6When RWU is set and the SCI is in an Asynchronous mode, the wakeup function is enabled — that is, the SCI is asleep, and can be awakened by the event defined by the WAKE bit. In the Sleep state, all interrupts and all receive flags except IDLE are disabled. When the receiver wakes up, RWU is cleared by the wakeup hardware. The programmer can also clear the RWU bit to wake up the receiver.

RWU can be used by the programmer to ignore messages that are for other devices on a multidrop serial network. Wakeup On Idle Line (WAKE is cleared) or Wakeup On Address Bit (WAKE is set) must be chosen.

1. When WAKE is cleared and RWU is set, the receiver does not respond to data on the data line until an idle line is detected.

2. When WAKE is set and RWU is set, the receiver does not respond to data on the data line until a data frame with Bit 9 set is detected.

When the receiver wakes up, the RWU bit is cleared, and the first frame of data is received. If interrupts are enabled, the CPU is interrupted and the interrupt routine reads the message header to determine if the message is intended for this DSP.

1. If the message is for this DSP, the message is received, and RWU is set to wait for the next message.

2. If the message is not for this DSP, the DSP immediately sets RWU. Setting RWU causes the DSP to ignore the remainder of the message and wait for the next message.

RWU is cleared by hardware and software reset. RWU is ignored in the Synchronous mode.

8.3.1.6 Wired-OR Mode Select (WOMS) SCR Bit 7When the WOMS bit is set, the SCI TXD driver is programmed to function as an open-drain output and can be wired together with other TXD signals in an appropriate bus configuration, such as a master-slave multidrop configuration. An external pullup resistor is required on the bus. When the WOMS is cleared, the TXD signal uses an active internal pullup. WOMS is cleared by hardware and software reset.

8.3.1.7 Receiver Enable (RE) SCR Bit 8When RE is set, the receiver is enabled. When RE is cleared, the receiver is disabled, and data transfer from the Receive Shift Register to the Receive Data Register (SRX) is inhibited. If RE is cleared while a character is being received, the reception of the character is completed before the receiver is disabled. RE does not inhibit RDRF or receive interrupts. RE is cleared by hardware and software reset.

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8.3.1.8 Transmitter Enable (TE) SCR Bit 9When TE is set, the transmitter is enabled. When TE is cleared, the transmitter completes transmission of data in the SCI Transmit Data Shift Register, then the serial output is forced high (i.e., idle). Data present in the SCI Transmit Data Register (STX) is not transmitted. STX may be written and TDRE cleared, but the data is not transferred into the shift register. TE does not inhibit TDRE or transmit interrupts. TE is cleared by hardware and software reset.

Setting TE causes the transmitter to send a preamble of ten or eleven consecutive 1s (depending on WDS). This procedure gives the programmer a convenient way to ensure that the line goes idle before starting a new message. To force this separation of messages by the minimum idle line time, the following sequence is recommended:

1. Write the last byte of the first message to STX.

2. Wait for TDRE to go high, indicating the last byte has been transferred to the Transmit Shift Register.

3. Clear TE and set TE. This queues an idle line preamble to follow immediately the transmission of the last character of the message (including the stop bit).

4. Write the first byte of the second message to STX.

In this sequence, if the first byte of the second message is not transferred to STX prior to the finish of the preamble transmission, the transmit data line marks idle until STX is finally written.

8.3.1.9 Idle Line Interrupt Enable (ILIE) SCR Bit 10When ILIE is set, the SCI interrupt occurs when IDLE (SSR Bit 3) is set. When ILIE is cleared, the IDLE interrupt is disabled. ILIE is cleared by hardware and software reset.

An internal flag, the Shift Register Idle Interrupt (SRIINT) flag, is the interrupt request to the interrupt controller. SRIINT is not directly accessible to the user.

When a valid start bit has been received, an idle interrupt is generated if both IDLE and ILIE are set. The idle interrupt acknowledge from the interrupt controller clears this interrupt request. The idle interrupt is not asserted again until at least one character has been received. The results are as follows:

1. The IDLE bit shows the real status of the receive line at all times.

2. An idle interrupt is generated once for each idle state, no matter how long the idle state lasts.

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8.3.1.10 SCI Receive Interrupt Enable (RIE) SCR Bit 11The RIE bit is set to enable the SCI Receive Data interrupt. If RIE is cleared, the Receive Data interrupt is disabled, and then the RDRF bit in the SCI Status Register must be polled to determine if the Receive Data Register is full. If both RIE and RDRF are set, the SCI requests an SCI Receive Data interrupt from the interrupt controller.

Receive interrupts with exception have higher priority than normal Receive Data interrupts. Therefore, if an exception occurs (i.e., if PE, FE, or OR are set) and REIE is set, the SCI requests an SCI Receive Data with Exception interrupt from the interrupt controller. RIE is cleared by hardware and software reset.

8.3.1.11 SCI Transmit Interrupt Enable (TIE) SCR Bit 12The TIE bit is set to enable the SCI Transmit Data interrupt. If TIE is cleared, Transmit Data interrupts are disabled, and the Transmit Data Register Empty (TDRE) bit in the SSR must be polled to determine if the Transmit Data Register is empty. If both TIE and TDRE are set, the SCI requests an SCI Transmit Data interrupt from the interrupt controller. TIE is cleared by hardware and software reset.

8.3.1.12 Timer Interrupt Enable (TMIE) SCR Bit 13The TMIE bit is set to enable the SCI timer interrupt. If TMIE is set, timer interrupt requests are sent to the interrupt controller at the rate set by the SCCR. The timer interrupt is automatically cleared by the timer interrupt acknowledge from the interrupt controller. This feature allows DSP programmers to use the SCI baud rate generator as a simple periodic interrupt generator if the SCI is not in use, if external clocks are used for the SCI, or if periodic interrupts are needed at the SCI baud rate. The SCI internal clock is divided by 16 (to match the 1 × SCI baud rate) for timer interrupt generation. This timer does not require that any SCI signals be configured for SCI use to operate. TMIE is cleared by hardware and software reset.

8.3.1.13 Timer Interrupt Rate (STIR) SCR Bit 14 The STIR bit controls a divide by 32 in the SCI Timer interrupt generator. When STIR is cleared, the divide by 32 is inserted in the chain. When STIR is set, the divide by 32 is bypassed, thereby increasing timer resolution by a factor of thirty-two. This bit is cleared by hardware and software reset. To ensure proper operation of the timer, STIR must not be changed during timer operation (i.e., if TMIE = 1).

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8.3.1.14 SCI Clock Polarity (SCKP) SCR Bit 15The SCKP bit controls the clock polarity sourced or received on the clock signal (SCLK), eliminating the need for an external inverter. When SCKP is cleared, the clock polarity is positive; when SCKP is set, the clock polarity is negative. In the Synchronous mode, positive polarity means that the clock is normally positive and transitions negative during valid data. Negative polarity means that the clock is normally negative and transitions positive during valid data. In the Asynchronous mode, positive polarity means that the rising edge of the clock occurs in the center of the period that data is valid. Negative polarity means that the falling edge of the clock occurs during the center of the period that data is valid. SCKP is cleared on hardware and software reset.

8.3.1.15 SCI Receive with Exception Interrupt Enable (REIE) SCR Bit 16The REIE bit is set to enable the SCI Receive Data with Exception interrupt. If REIE is cleared, the Receive Data with Exception interrupt is disabled. If both REIE and RDRF are set, and PE, FE, and OR are not all cleared, the SCI requests an SCI Receive Data with Exception interrupt from the interrupt controller. REIE is cleared by hardware and software reset.

8.3.2 SCI Status Register (SSR)

The SCI Status Register (SSR) is a 24-bit read-only register used by the DSP to determine the status of the SCI. The status bits are described in the following paragraphs. When the SSR is read into the internal data bus, the register contents occupy the low-order byte of the data bus and all high-order portions are zero-filled.

8.3.2.1 Transmitter Empty (TRNE) SSR Bit 0The TRNE flag bit is set when both the Transmit Shift Register and Transmit Data Register (STX) are empty to indicate that there is no data in the transmitter. When TRNE is set, data written to one of the three STX locations or to the Transmit Data Address Register (STXA) is transferred to the Transmit Shift Register and is the first data transmitted. TRNE is cleared when TDRE is cleared by writing data into the STX or the STXA, or when an idle, preamble, or break is transmitted. This bit, when set, indicates that the transmitter is empty; therefore, the data written to STX or STXA is transmitted next. That is, there is no word in the Transmit Shift Register presently being transmitted. This procedure is useful when initiating the transfer of a message (i.e., a string of characters). TRNE is set by the hardware, software, SCI individual, and stop reset.

8.3.2.2 Transmit Data Register Empty (TDRE) SSR Bit 1The TDRE flag bit is set when the SCI Transmit Data Register is empty. When TDRE is set, new data can be written to one of the SCI Transmit Data Registers (STX) or the Transmit Data Address Register (STXA). TDRE is cleared when the SCI Transmit Data

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Register is written. TDRE is set by the hardware, software, SCI individual, and stop reset.

In the Synchronous mode, when using the internal SCI clock, there is a delay of up to 5.5 serial clock cycles between the time that STX is written until TDRE is set, indicating the data has been transferred from the STX to the Transmit Shift Register. There is a 2 to 4 serial clock cycle delay between writing STX and loading the Transmit Shift Register; in addition, TDRE is set in the middle of transmitting the second bit. If the clock stops when using an external serial transmit clock, the SCI transmitter stops. TDRE is not set until the middle of the second bit transmitted after the external clock starts. Gating the external clock off after the first bit has been transmitted delays TDRE indefinitely.

In the Asynchronous mode, the TDRE flag is not set immediately after a word is transferred from the STX or STXA to the Transmit Shift Register nor when the word first begins to be shifted out. TDRE is set 2 cycles of the 16 × clock after the start bit—that is, 2 16 × clock cycles into the transmission time of the first data bit.

8.3.2.3 Receive Data Register Full (RDRF) SSR Bit 2The RDRF bit is set when a valid character is transferred to the SCI Receive Data Register from the SCI Receive Shift Register (regardless of the error bits condition). RDRF is cleared when the SCI Receive Data Register is read or by the hardware, software, SCI individual, and stop resets.

8.3.2.4 Idle Line Flag (IDLE) SSR Bit 3IDLE is set when ten (or eleven) consecutive 1s are received. IDLE is cleared by a start-bit detection. The IDLE status bit represents the status of the receive line. The transition of IDLE from 0 to 1 can cause an IDLE interrupt (ILIE). IDLE is cleared by the hardware, software, SCI individual, and Stop resets.

8.3.2.5 Overrun Error Flag (OR) SSR Bit 4The OR flag bit is set when a byte is ready to be transferred from the Receive Shift Register to the Receive Data Register (SRX) that is already full (RDRF = 1). The Receive Shift Register data is not transferred to the SRX. The OR flag indicates that character(s) in the received data stream may have been lost. The only valid data is located in the SRX. OR is cleared when the SCI status Register (SSR) is read, followed by a read of SRX. The OR bit clears the FE and PE bits—that is, overrun error has higher priority than FE or PE. OR is cleared by the hardware, software, SCI individual, and stop resets.

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8.3.2.6 Parity Error (PE) SSR Bit 5In the 11-bit Asynchronous modes, the PE bit is set when an incorrect parity bit has been detected in the received character. It is set simultaneously with RDRF for the byte which contains the parity error—that is, when the received word is transferred to the SRX. If PE is set, further data transfer into the SRX is not inhibited. PE is cleared when the SSR is read, followed by a read of SRX. PE is also cleared by the hardware, software, SCI individual, or stop reset. In the 10-bit Asynchronous mode, the 11-bit Multidrop mode, and the 8-bit Synchronous mode, the PE bit is always cleared since there is no parity bit in these modes. If the byte received causes both parity and overrun errors, the SCI receiver recognizes only the overrun error.

8.3.2.7 Framing Error Flag (FE) SSR Bit 6The FE bit is set in the Asynchronous modes when no stop bit is detected in the data string received. FE and RDRE are set simultaneously when the received word is transferred to the SRX. However, the FE flag inhibits further transfer of data into the SRX until it is cleared. FE is cleared when the SSR is read followed by reading the SRX. The hardware, software, SCI individual, and stop reset also clear FE. In the 8-bit Synchronous mode, FE is always cleared. If the byte received causes both framing and overrun errors, the SCI receiver recognizes only the overrun error.

8.3.2.8 Received Bit 8 Address (R8) SSR Bit 7In the 11-bit Asynchronous Multidrop mode, the R8 bit is used to indicate whether the received byte is an address or data. R8 is set for addresses and is cleared for data. R8 is not affected by reading the SRX or SSR. The hardware, software, SCI individual, and stop resets clear R8.

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8.3.3 SCI Clock Control Register (SCCR)

The SCCR is a sixteen bit read/write register that used to select clock modes and baud rates for the transmitter and receiver sections of the SCI interface. The control bits are described in the following paragraphs. The SCCR is cleared by hardware reset. The basic features of the clock generator (see Figure 8-6 and Figure 8-7) are:

• The SCI logic always uses a 16 × internal clock in the Asynchronous modes and a 2 × internal clock in the Synchronous mode. The maximum internal clock available to the SCI peripheral block is the oscillator frequency divided by 4. With an 80 MHz DSP56305 processor, this gives a maximum data rate of 1.25 Mbps for asynchronous data and 10.0 Mbps for synchronous data. These maximum rates are the same for internally or externally supplied clocks.

• The 16 × clock is necessary for the Asynchronous modes to synchronize the SCI to the incoming data (see Figure 8-6).

• In the Asynchronous modes, the user must provide a 16 × clock if the user wishes to use an external baud rate generator (i.e., SCLK input).

• In the Asynchronous modes, the user can select either 1 × or 16 × for the output clock when using internal TX and RX clocks (TCM = 0 and RCM = 0).

• If SCKP = 0, the data transmitted on the TXD signal changes on the negative edge of the 1 × serial clock and is stable on the positive edge. If SCKP = 1, the data changes on the positive edge and is stable on the negative edge.

• If SCKP = 0, the data received on the RXD signal is sampled on the positive edge or if SCKP = 1, on the negative edge of the 1 × serial clock.

• In the Asynchronous modes, the output clock is continuous.

• In the Synchronous mode, a 1 × clock is used for the output or input baud rate. The maximum 1 × clock is the crystal frequency divided by 8.

• In the Synchronous mode, the clock is gated.

• In the Synchronous mode, the transmitter and receiver are synchronous with each other.

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8.3.3.1 Clock Divider (CD[11:0]) SCCR Bits 11–0The CD[11:0] bits specify the divide ratio of the prescale divider in the SCI clock generator. A divide ratio from 1 to 4096 (CD[11:0] = $000 to $FFF) can be selected. Hardware and software reset clear CD[11:0].

8.3.3.2 Clock Out Divider (COD) SCCR Bit 12The clock output divider is controlled by COD and the SCI mode. If the SCI mode is synchronous, the output divider is fixed at divide by 2.

If the SCI mode is asynchronous, either:

• If COD is cleared and SCLK is an output (i.e., TCM and RCM are both cleared), the SCI clock is divided by 16 before being output to the SCLK signal. Thus, the SCLK output is a 1 × clock.

• If COD is set and SCLK is an output, the SCI clock is fed directly out to the SCLK signal. Thus, the SCLK output is a 16 × baud clock.

The COD bit is cleared by hardware and software reset.

8.3.3.3 SCI Clock Prescaler (SCP) SCCR Bit 13The SCP bit selects a divide by 1 (SCP is cleared) or divide by 8 (SCP is set) prescaler for the clock divider. The output of the prescaler is further divided by 2 to form the SCI clock. Hardware and software reset clear SCP.

Figure 8-6 16 x Serial Clock

RX, TX Data(SSFTD = 0)

Idle Line

Start

Select 8-or 9-bit Words

x1 Clock

x16 Clock(SCKP = 0)

10 2 3 4 5 6 7 8

AA0692

Stop Start

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8.3.3.4 Receive Clock Mode Source Bit (RCM) SCCR Bit 14RCM selects whether an internal or external clock is used for the receiver. If RCM is cleared, the internal clock is used. If RCM is set, the external clock (from the SCLK signal) is used. Hardware and software reset clear RCM.

Table 8-2 TCM and RCM Bit Configuration

TCM RCM TX Clock RX Clock SCLK Signal Mode

0 0 Internal Internal Output Synchronous/Asynchronous

0 1 Internal External Input Asynchronous Only

1 0 External Internal Input Asynchronous Only

1 1 External External Input Synchronous/Asynchronous

Figure 8-7 SCI Baud Rate Generator

Fcore

DivideBy 2

12-bit Counter Prescaler:Divide by

1 or 8

CD11–CD0SCP

Internal Clock

TimerInterrupt

(STMINT)

SCI Core LogicUses Divide by 16 for

AsynchronousUses Divide by 2 for

Synchronous

COD

SCKP

If AsynchronousDivide by 1 or 16If Synchronous

Divide By 2

TO SCLK

FcoreBPS = 64 × (7 × SCP + 1) × CD + 1)

where: SCP = 0 or 1CD = $000 to $FFF

AA0693

DivideBy 2

DivideBy 16

SCKP = 0SCKP = 1

+–

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8.3.3.5 Transmit Clock Source Bit (TCM) SCCR Bit 15TCM selects whether an internal or external clock is used for the transmitter. If TCM is cleared, the internal clock is used. If TCM is set, the external clock (from the SCLK signal) is used. Hardware and software reset clear TCM.

8.3.4 SCI Data Registers

The SCI data registers are divided into two groups: receive and transmit (see Figure 8-8). There are two receive registers—a Receive Data Register (SRX) and a serial-to-parallel Receive Shift Register. There are also two transmit registers—a Transmit Data Register (called either STX or STXA) and a parallel-to-serial Transmit Shift Register.

Figure 8-8 SCI Programming Model - Data Registers

SRXH

SRXM

SRXL

RXD SCI Receive Data Shift Register

Note: SRX is the same register decoded at three different addresses.

STXH

STXM

STXL

TXDSCI Transmit Data Shift Register

Note: 1. Bytes are masked on the fly.2. STX is the same register decoded at four different addresses.

STXA

(a) Receive Data Register

(b) Transmit Data RegisterAA0694

SCI Receive Data Register High (Read Only)

SCI Receive Data Register Middle (Read Only)

SCI Receive Data Register Low (Read Only)

078151623

078151623

078151623

SCI Transmit Data Register High (Write Only)

SCI Transmit Data Register Middle (Write Only)

SCI Transmit Data Register Low (Write Only)

SCI Transmit Data Address Register (Write Only)

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8.3.4.1 SCI Receive Registers (SRX)Data bits received on the RXD signal are shifted into the SCI Receive Shift Register. When a complete word has been received, the data portion of the word is transferred to the byte-wide SRX. This process converts the serial data to parallel data and provides double-buffering. Double-buffering provides flexibility to the programmer and increased throughput since the programmer can save (and process) the previous word while the current word is being received.

The SRX can be read at three locations as SRXL, SRXM, and SRXH. When SRXL is read, the contents of the SRX are placed in the low byte of the data bus and the remaining bits on the data bus are read as 0s. Similarly, when SRXM is read, the contents of SRX are placed in the middle byte of the bus, and when SRXH is read, the contents of SRX are placed in the high byte with the remaining bits are read as 0s. Mapping SRX as described allows three bytes to be efficiently packed into one 24-bit word by ORing three data bytes read from the three addresses.

The length and format of the serial word are defined by the WDS0, WDS1, and WDS2 control bits in the SCR. The clock source is defined by the Receive Clock Mode (RCM) select bit in the SCR.

In the Synchronous mode, the start bit, the eight data bits, the address/data indicator bit and/or the parity bit, and the stop bit are received in that order. Data bits are sent LSB first if SSFTD is cleared, and MSB first if SSFTD is set. In Synchronous mode, the synchronization is provided by gating the clock.

In either Synchronous or Asynchronous modes, when a complete word has been clocked in, the contents of the Shift Register can be transferred to the SRX and the flags: RDRF, FE, PE, and OR are changed appropriately. Because the operation of the Receive Shift Register is transparent to the DSP, the contents of this register are not directly accessible to the programmer.

8.3.4.2 SCI Transmit RegistersThe Transmit Data Register is a one byte-wide register mapped into four addresses as STXL, STXM, STXH, and STXA. In the Asynchronous mode, when data is to be transmitted, STXL, STXM, and STXH are used. When STXL is written, the low byte on the data bus is transferred to the STX. When STXM is written, the middle byte is transferred to the STX. When STXH is written, the high byte is transferred to the STX. This structure makes it easy for the programmer to unpack the bytes in a 24-bit word for transmission. STXA should be written in the 11-bit Asynchronous Multidrop mode when the data is an address and it is desired that the ninth bit (the address bit) be set. When STXA is written, the data from the low byte on the data bus is stored in it. The address data bit is cleared in the 11-bit Asynchronous Multidrop mode when any of

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STXL, STXM or STXH is written. When either STX (STXL, STXM, or STXH) or STXA is written, TDRE is cleared.

The transfer from either STX or STXA to the Transmit Shift Register occurs automatically, but not immediately, when the last bit from the previous word has been shifted out; that is, when the Transmit Shift Register is empty. Like the receiver, the transmitter is double-buffered. However, a 2 to 4 serial clock cycle delay occurs between when the data is transferred from either STX or STXA to the Transmit Shift Register and when the first bit appears on the TXD signal. (A serial clock cycle is the time required to transmit one data bit). The Transmit Shift Register is not directly addressable, and a dedicated flag for this register does not exist. Because of this fact and the 2 to 4 cycle delay, two bytes cannot be written consecutively to STX or STXA without polling, as the second byte might overwrite the first byte. The TDRE flag should always be polled prior to writing STX or STXA to prevent overruns unless transmit interrupts have been enabled. Either STX or STXA is usually written as part of the interrupt service routine. An interrupt is generated only if TDRE is set. The Transmit Shift Register is indirectly visible via the TRNE bit in the SSR.

In the Synchronous mode, data is synchronized with the transmit clock, which can have either an internal or external source, as defined by the TCM bit in the SCCR. The length and format of the serial word is defined by the WDS0, WDS1, and WDS2 control bits in the SCR. In the Asynchronous modes, the start bit, the eight data bits (with the LSB first if SSFTD = 0 and the MSB first if SSFTD = 1), the address/data indicator bit or parity bit, and the stop bit are transmitted in that order.

The data to be transmitted can be written to any one of the three STX addresses. If SCKP is set and SSHTD is set, the SCI Synchronous mode is equivalent to the SSI operation in the 8-bit Data On-demand mode.

Note: When writing data to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated. If the user reads any of those status bits within the next two cycles, the bit will not reflect its current status. See the DSP56300 Family Manual, Appendix B, “Polling a Peripheral Device for Write,” for further details.

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Operating Modes


8.4 OPERATING MODES

The operating modes for the DSP56305 SCI are:

• 8-bit Synchronous (shift register mode)

• 10-bit Asynchronous (1 start, 8 data, 1 stop)

• 11-bit Asynchronous (1 start, 8 data, 1 even parity, 1 stop)

• 11-bit Asynchronous (1 start, 8 data, 1 odd parity, 1 stop)

• 11-bit Multidrop Asynchronous (1 start, 8 data, 1 data type, 1 stop)This mode is used for master/slave operation with Wakeup On Idle Line and Wakeup On Address Bit capability. It allows the DSP56305 to share a single serial line efficiently with other peripherals.

These modes are selected using the WD[0:2] bits in the SCR.

The Synchronous data mode is essentially a high-speed shift register used for I/O expansion and stream-mode channel interfaces. Data synchronization is accomplished by the use of a gated transmit and receive clock that is compatible with the Intel 8051 serial interface mode 0.

The Asynchronous modes are compatible with most UART-type serial devices. Standard RS232C communication links are supported by these modes.

The Multidrop Asynchronous modes are compatible with the MC68681 DUART, the M68HC11 SCI interface, and the Intel 8051 serial interface.

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Operating Modes

8.4.1 SCI After Reset

There are four different methods of resetting the SCI.

1. Hardware reset

2. Software resetBoth hardware and software resets clear the Port Control Register bits, which configure all I/O as GPIO input. The SCI remains in the Reset state as long as all SCI signals are programmed as GPIO (CC2, CC1, and CC0 all are cleared); the SCI becomes active only when at least one of the SCI I/O signals is not programmed as GPIO.

3. Individual resetDuring program execution, the CC2, CC1, and CC0 bits can be cleared (individual reset), which causes the SCI to stop serial activity and enter the Reset state. All SCI status bits are set to their Reset state. However, the contents of the SCR are not affected, allowing the DSP program to reset the SCI separately from the other internal peripherals. During individual reset, internal DMA accesses to the data registers of the SCI are not valid and the data read will be unknown.

4. Stop processing state resetExecuting the STOP instruction halts operation of the SCI until the DSP is restarted, causing the SSR to be reset. No other SCI registers are affected by the STOP instruction. Table 8-3 illustrates how each type of reset affects each register in the SCI.

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Operating Modes


Table 8-3 SCI Registers after Reset

Register Mnemonic Bit Mnemonic Bit Number

Reset Type

HW Reset

SW Reset

IR Reset

ST Reset

REIE 16 0 0 — —

SCKP 15 0 0 — —

STIR 14 0 0 — —

TMIE 13 0 0 — —

TIE 12 0 0 — —

RIE 11 0 0 — —

ILIE 10 0 0 — —

TE 9 0 0 — —

SCR RE 8 0 0 — —

WOMS 7 0 0 — —

RWU 6 0 0 — —

WAKE 5 0 0 — —

SBK 4 0 0 — —

SSFTD 3 0 0 — —

WDS[2:0] 2–0 0 0 — —

R8 7 0 0 0 0

FE 6 0 0 0 0

PE 5 0 0 0 0

SSR OR 4 0 0 0 0

IDLE 3 0 0 0 0

RDRF 2 0 0 0 0

TDRE 1 1 1 1 1

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Operating Modes

TRNE 0 1 1 1 1

TCM 15 0 0 — —

RCM 14 0 0 — —

SCCR SCP 13 0 0 — —

COD 12 0 0 — —

CD[11:0] 11–0 0 0 — —

SRX SRX [23:0] 23–16, 15–8, 7–0 — — — —

STX STX[23:0] 23–0 — — — —

SRSH SRS[8:0] 8–0 — — — —

STSH STS[8:0] 8–0 — — — —

Note: 1. SRSH—SCI Receive Shift Register, STSH — SCI Transmit Shift Register2. HW—Hardware reset is caused by asserting the external RESET signal.3. SW—Software reset is caused by executing the RESET instruction.4. IR—Individual reset is caused by clearing PCRE (bits 0–2) (configured for GPIO).5. ST—Stop reset is caused by executing the STOP instruction.6. 1—The bit is set during this reset.7. 0—The bit is cleared during this reset.8. — — The bit is not changed during this reset

Table 8-3 SCI Registers after Reset (Continued)

Register Mnemonic Bit Mnemonic Bit Number

Reset Type

HW Reset

SW Reset

IR Reset

ST Reset

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Operating Modes


8.4.2 SCI Initialization

The correct way to initialize the SCI is as follows:

1. Hardware or software reset

2. Program SCI control registers

3. Configure at least one SCI signal as SCI, not GPIO

If interrupts are used, the signals must be selected and interrupts must be enabled and unmasked before the SCI can operate. Any one of these three requirements for interrupts may be used to enable the SCI, the order does not matter.

A synchronous application usually requires an exact frequency, so the crystal frequency must be chosen carefully. An alternative to selecting the system clock to accommodate SCI requirements is to provide an external clock to the SCI.

8.4.3 SCI Initialization Example

One way to initialize the SCI is described below (as an example).

1. Let the SCI be in SCI individual reset state (PCR = $0).

2. Configure the control registers (SCR, SCCR) according to the operating mode, but do not enable either transmitter (TE = 0) or receiver (RE = 0).

It is possible to set the interrupt enable bits used during the operation (no interrupt occurs).

3. Enable the SCI by setting the PCR bits according to signals used during operation.

4. If the transmit interrupt is not used, write data to the transmitter.

If the transmitter interrupt enable is set, an interrupt is issued and the interrupt handler should write data into the transmitter.

The SCI transmit request is serviced by a DMA channel if it is programmed to service the SCI transmitter.

5. Enable the transmitters (TE = 1) and receiver (RE = 1), according to usage.

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Operating Modes

Operation starts as follows:

• For an internally generated clock, the SCLK signal starts operation immediately after the SCI is enabled (Step 3 above) in Asynchronous modes. In Synchronous mode, the SCLK signal is active only while transmitting (the clock is gated).

• Data is received only when the receiver is enabled (RE = 1) and after the SCI receive sequence occurs on the RXD signal, as defined by the operating mode (e.g., idle line sequence).

• Data is transmitted only after the transmitter is enabled (TE = 1), and after transmitting the initialization sequence defined by the operating mode.

8.4.4 Preamble, Break, and Data Transmission Priority

More than one transmission command may be set at the same time:

1. Preamble (TE is set.)

2. Break (SBK is set or is cleared.)

3. Data for transmission available (TDRE is cleared.)

After the current character transmission, if two or more of these commands are set, the transmitter executes them in the following order:

1. Preamble

2. Break

3. Data Available

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GPIO Signals and Registers


8.4.5 SCI Exceptions

The SCI can cause five different exceptions in the DSP. These exceptions are as follows (ordered from the highest to the lowest priority):

1. SCI Receive Data with Exception Status is caused when the Receive Data Register is full and has a receive error (parity, framing, or overrun). Clearing the pending interrupt is done by reading the SSR, followed by reading SRX. A long interrupt service routine should be used to handle the error condition. This interrupt is enabled by SCR Bit 16 (REIE).

2. SCI Receive Data is caused when the Receive Data Register is full. Reading SRX clears the pending interrupt. This error-free interrupt can use a fast interrupt service routine for minimum overhead. This interrupt is enabled by SCR Bit 11 (RIE).

3. SCI Transmit Data is caused when the Transmit Data Register is empty. Writing STX clears the pending interrupt. This error-free interrupt can use a fast interrupt service routine for minimum overhead. This interrupt is enabled by SCR Bit 12 (TIE).

4. SCI Idle Line is caused when the receive line enters the idle state (when there have been ten or eleven bits of 1s transmitted). This interrupt is latched and then automatically reset when the interrupt is accepted. This interrupt is enabled by SCR Bit 10 (ILIE).

5. SCI Timer is caused when the baud rate counter reaches zero. This interrupt is automatically reset when the interrupt is accepted. This interrupt is enabled by SCR Bit 13 (TMIE).

8.5 GPIO SIGNALS AND REGISTERS

The GPIO functionality of port SCI is controlled by three registers: Port E Control Register (PCRE), Port E Direction Register (PRRE) and Port E Data Register (PDRE).

8.5.1 Port E Control Register (PCRE)

The read/write 24-bit PCRE controls the functionality of SCI GPIO signals. Each of PC[2:0] bits controls the functionality of the corresponding port signal. When a PC[i] bit is set, the corresponding port signal is configured as a SCI signal. When a PC[i] bit is cleared, the corresponding port signal is configured as a GPIO signal.

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Note: Hardware and software reset clear all PCRE bits.

8.5.2 Port E Direction Register (PRRE)

The read/write 24-bit PRRE controls the direction of SCI GPIO signals. When port signal[i] is configured as GPIO, PDC[i] controls the port signal direction. When PDC[i] is set, the GPIO port signal[i] is configured as output. When PDC[i] is cleared the GPIO port signal[i] is configured as input.

Note: Hardware and software reset clear all PRRE bits.

Figure 8-9 Port E Control Register (PCRE)

Figure 8-10 Port E Direction Register (PRRE)

PC0PC1PC2

Reserved Bit, Read as 0, Should be Written with 0 for Future Compatibility

Port Control Bits: 1 = SCI0 = GPIO

01234567

89101112131415

1617181920212223

AA0695

01234567

PDC0PDC1PDC2

Direction Control Bits: 1 = Output0 = Input89101112131415

1617181920212223


AA0696

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The following table describes the port signal configurations.

8.5.3 Port E Data Register (PDRE)

The read/write 24-bit PDRE is used to read or write data to or from SCI GPIO signals. Bits PD[2:0] are used to read or write data from or to the corresponding port signals if they are configured as GPIO. If a port signal [i] is configured as a GPIO input, then the corresponding PD[i] bit reflects the value of this signal. If a port signal [i] is configured as a GPIO output, then the value of the corresponding PD[i] bit is reflected on this signal.

Note: Hardware and software reset clear all PDRE bits.

Table 8-4 Port Control Register and Port Direction Register Bits Functionality

PC[i] PDC[i] Port Signal[i] Function

1 1 or 0 SCI

0 0 GPIO input

0 1 GPIO output

Figure 8-11 Port E Data Register (PDRE)

01234567

89101112131415

PD0PD1PD2

1617181920212223


AA0697

Data Value Bits

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SECTION 9

TIMER/EVENT COUNTER

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Timer/Event Counter

9.1 Introduction to the Timer/Event Counter . . . . . . . . . . . . . . . . . . .9-39.2 Timer/Event Counter Architecture . . . . . . . . . . . . . . . . . . . . . . . .9-39.3 Timer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-79.4 Timer Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-18

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Timer/Event Counter

Introduction to the Timer/Event Counter


9.1 INTRODUCTION TO THE TIMER/EVENT COUNTER

This section describes the internal Timer/Event Counter module (TEC) in the DSP56305. The TEC comprises:

• a 21-bit prescaler counter

• a 24-bit Timer Prescaler Load Register (TPLR)

• a 24-bit Timer Prescaler Count Register (TPCR)

• three identical independent general purpose 24-bit timer/event counters, each having its own register set

Each timer/event counter comprises:

• a 24-bit counter

• a 24-bit read/write Timer Control and Status Register (TCSR)

• a 24-bit write-only Timer Load Register (TLR)

• a 24-bit read/write Timer Compare Register (TCPR)

• a 24-bit read-only Timer Count Register (TCR)

• logic for clock selection and interrupt/DMA trigger generation

Figure 9-1 shows the TEC block diagram. Figure 9-2 shows the TEC programming model. Figure 9-5 shows the generic timer block diagram. Figure 9-6 shows the generic timer programming model.

9.2 TIMER/EVENT COUNTER ARCHITECTURE

The following sections details the TEC architecture’s component parts.

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Timer/Event Counter

Timer/Event Counter Architecture

9.2.1 Timer/Event Counter Block Diagram

9.2.2 Timer/Event Counter Programming Model

The programming model for the TEC consists of the 21-bit prescaler counter, the 24-bit Timer Prescaler Load Register (TPLR), and the 24-bit Timer Prescaler Count Register (TPCR). Figure 9-3 shows the TEC programming model.

Figure 9-1 Timer/Event Counter Block Diagram

Timer PrescalerCount Register

GDB 24

24

TPLR24

Timer 0

Timer 2

Timer 121-bit Prescaler

CLK/2 TIO0 TIO1 TIO2

TPCR

Timer PrescalerLoad Register

24

AA0673

Counter

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Timer/Event Counter



9.2.3 Prescaler Counter

The prescaler counter is a 21-bit counter decremented on the rising edge of the prescaler input clock. The counter is enabled when at least one timer is both enabled (i.e., one or more of the Timer Enable (TE, TCSR Bit 0) bits are set) and using the prescaler output as its source (i.e., one or more of the Prescaler Clock Enable (PCE, TCSR Bit 15) bits are set).

9.2.4 Timer Prescaler Load Register (TPLR)

The Timer Prescaler Load Register (TPLR) is a 24-bit read/write register that controls the prescaler divide factor (i. e., the number that the prescaler counter loads and begins counting from) and the source for the prescaler input clock. The control bits are described below (see Figure ).

Figure 9-2 Timer/Event Counter Programming Model

23 22 21 20 19 18 17 16 15 14 13 12

PS1 PS0 PL20 PL19 PL18 PL17 PL16 PL15 PL14 PL13 PL12

11 10 9 8 7 6 5 4 3 2 1 0

PL11 PL10 PL9 PL8 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0

— reserved, read as 0, should be written with 0 for future compatibility

Figure 9-3 Timer Prescaler Load Register (TPLR)

23 0Timer Prescaler LoadRegister (TPLR)TPLR = $FFFF83

23 0Timer Prescaler CountRegister (TPCR)TPLR = $FFFF82

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Timer/Event Counter


9.2.4.1 Prescaler Preload Value PL[20:0] — TPLR Bits 20-0These 21 bits contain the prescaler preload value. This value is loaded into the prescaler counter when the counter value reaches zero or the counter switches state from disabled to enabled.

If PL[20:0] = N, then the prescaler counts N+1 source clock cycles before generating a prescaler clock pulse. Therefore, the prescaler divide factor = (preload value) + 1.

The PL[20:0] bits are cleared by a hardware RESET signal or a software RESET instruction.

9.2.4.2 Prescaler Source PS[1:0] — TPLR Bits 22-21The two Prescaler Source (PS) bits control the source of the prescaler clock. Table 9-1 summarizes PS bit functionality. The prescaler’s use of a TIO signal is not affected by the TCSR settings of the timer corresponding to the TIO signal being used.

If the prescaler source clock is external, the prescaler counter is incremented by signal transitions on the TIO signal. The external clock is internally synchronized to the internal clock. The external clock frequency must be less than the DSP56305 internal operating frequency divided by 4 (CLK/4).

The PS[1:0] bits are cleared by a hardware RESET signal or a software RESET instruction.

Note: To ensure proper operation, change the PS[1:0] bits only when the prescaler counter is disabled. Disable the prescalar counter by clearing the TE (TCSR Bit 0) bit in each of the three timers.

9.2.4.3 Reserved Bit — TPLR Bit 23This reserved bit is read as 0 and should be written with 0 for future compatibility.

Table 9-1 Prescaler Source Selection

PS1 PS0 PRESCALER CLOCK SOURCE

0 0 Internal CLK/2

0 1 TIO0

1 0 TIO1

1 1 TIO2

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Timer/Event Counter

Timer Architecture


9.2.5 Timer Prescaler Count Register (TPCR)

The Timer Prescaler Count Register (TPCR) is a 24-bit read-only register that reflects the current value in the prescaler counter. The register bits are described below in Figure 9-4.

9.2.5.1 Prescaler Counter Value PC[20:0] — TPCR Bits 20-0 These 21 bits contain the current value of the prescaler counter.

9.2.5.2 Reserved Bits — TPCR Bits 23-21These reserved bits are read as 0 and should be written with 0 for future compatibility.

9.3 TIMER ARCHITECTURE

The DSP56305 views each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory space. Either standard polled or interrupt programming techniques can be used to service the timers. The three timers are identical in functionality. Figure 9-5 shows the block diagram for a generic timer. Figure 9-6 shows the programming model for a generic timer.

Each timer can use internal or external clocking and can interrupt the processor after a number of events (clocks) specified by a user program, or signal an external device after counting internal events. Each timer can also be used to trigger DMA transfers after a specified number of events (clocks) has occurred. Each timer may use the prescaler clock as its clock source.

Each timer uses one bidirectional signal as a timer signal (or GPIO signal, when not used as a timer signal), called TIO0–2 for timers 0–2 respectively. Note the name is the same, whether the signal is used for the timer or for GPIO.

23 22 21 20 19 18 17 16 15 14 13 12

PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12

11 10 9 8 7 6 5 4 3 2 1 0

PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

— reserved, read as 0, should be written with 0 for future compatibility

Figure 9-4 Timer Prescaler Count Register (TPCR)

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Timer/Event Counter

Timer Architecture

The timers can be used to generate timed pulses, to capture an event, or as pulse width modulators. When a timer signal (TIOn) is used as an input, the timer is functioning as an external event counter or is measuring external pulse width or signal period. When a timer signal (TIOn) is used as an output, the timer is functioning as a timer, a watchdog timer, or a pulse width modulator, and TIOn becomes the timer pulse.

Timer modes are controlled by the TC[3:0] bits of the Timer Control/Status Register (TCSR). For a listing of the timer modes, see Section 9.4 . For a description of their operation, see Section 9.4.1 .

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Timer/Event Counter

Timer Architecture


9.3.1 Timer Block Diagram

9.3.2 Timer Programming Model

The timer programming model consists of a 24-bit counter, a 24-bit read/write Timer Control and Status Register (TCSR), a 24-bit write-only Timer Load Register (TLR), a 24-bit read/write Timer Compare Register (TCPR), and a 24-bit read-only Timer Count Register (TCR). The timers are functionally identical. Figure 9-6 shows the timer programming model.

Figure 9-5 Timer Block Diagram

GDB

Control/StatusRegister

TCSR

Counter

Timer Interrupt/

Timer Control

CLK/2TIO

CompareRegister

TCPR

=

24

24

DMA Request

Logic

LoadRegister

CountRegister

TLR

Prescaler CLK

TCR

AA0676

24249

2

24242424

24

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Timer/Event Counter

Timer Architecture

9.3.3 Timer Control/Status Register (TCSR)

The Timer Control/Status Register (TCSR) is a 24-bit read/write register controlling the timer and reflecting its status. The control and status bits are described below.

Figure 9-6 Timer Programming Model

DO DI DIR

15 14 13 12 11 10 9 8

TC1 TC0

INV

TCIE TE

7 6 5 4 3 2 1 0

Timer Control/StatusRegister (TCSR)

- reserved, read as 0, should be written with 0 for future compatibility

23 0Timer LoadRegister (TLR)

23 22 21 20 19 18 17 16

23 0Timer CompareRegister (TCPR)

PCE TRM

TCF TOF

TOIETC2

23 0Timer CountRegister (TCR)

TC3

TCSR0 = $FFFF8FTCSR1 = $FFFF8BTCSR2 = $FFFF87

TLR0 = $FFFF8ETLR1 = $FFFF8BTLR2 = $FFFF87

TCR0 = $FFFF8CTCR1 = $FFFF88TCR2 = $FFFF84

TCPR0 = $FFFF8FTCPR1 = $FFFF86TCPR2 = $FFFF87

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Timer/Event Counter

Timer Architecture


9.3.3.1 Timer Enable (TE) — TCSR Bit 0The Timer Enable (TE) bit, when set, enables the timer and clears the timer counter. The counter starts counting according to the mode selected by the Timer Control (TC[3:0]) bit values.

Clearing the TE bit disables the timer. The TE bit is cleared by a hardware RESET signal or a software RESET instruction.

Note: When all three timers are disabled and the signals are not in GPIO mode, all three TIO signals are tri-stated. To prevent undesired spikes on the TIO signals when switching from tri-state into active state, these signals should be tied to the high or low signal state by the use of pull-up or pull-down resistors.

9.3.3.2 Timer Overflow Interrupt Enable (TOIE) — TCSR Bit 1The Timer Overflow Interrupt Enable (TOIE) bit, when set, enables the timer overflow interrupts. The timer counter can hold a maximum value of $FFFFFF. When the counter value is at the maximum value and a new event causes the counter to be incremented (to $000000), the timer generates an overflow interrupt if TOIE is set.

Clearing the TOIE bit disables overflow interrupt generation. The TOIE bit is cleared by a hardware RESET signal or a software RESET instruction.

9.3.3.3 Timer Compare Interrupt Enable (TCIE) — TCSR Bit 2The Timer Compare Interrupt Enable (TCIE) bit, when set, enables the timer compare interrupts. In the Timer, PWM, or Watchdog modes, a compare interrupt is generated after the counter value matches the TCPR value. The counter starts counting up from the number loaded from the TLR. If the TCPR value is N and the TLR value is M, an interrupt occurs after (N – M + 1) events.

Clearing the TCIE bit disables the compare interrupts. The TCIE bit is cleared by a hardware RESET signal or a software RESET instruction.

9.3.3.4 Timer Control (TC[3:0]) — TCSR Bits 4-7The four Timer Control (TC) bits control the source of the timer clock, the behavior of the TIO signal, and the timer mode of operation. Table 9-2 summarizes the TC bit functionality. A detailed description of the timer operating modes is given in Section 9.4 Timer Modes of Operation.

The TC bits are cleared by a hardware RESET signal or a software RESET instruction.

Note: If the clock is external, the counter is incremented by the transitions on the TIO signal. The DSP56305 synchronizes the external clock to the internal clock.

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Timer/Event Counter

Timer Architecture

The external clock frequency should be less than the internal operating frequency divided by 4 (i.e. CLK/4).

Note: To ensure proper operation, the TC[3:0] bits should be changed only when the timer is disabled (when the TE bit is cleared).

Table 9-2 Timer/Event Counter Control Bits

Bit Settings Mode Characteristics

TC3 TC2 TC1 TC0 ModeNumber Mode TIO Clock

0 0 0 0 0 Timer and GPIO GPIO * Internal

0 0 0 1 1 Timer Pulse Output Internal

0 0 1 0 2 Timer Toggle Output Internal

0 0 1 1 3 Event Counter Input External

0 1 0 0 4 Input Width Measurement

Input Internal

0 1 0 1 5 Input Period Measurement

Input Internal

0 1 1 0 6 Capture Event Input Internal

0 1 1 1 7 Pulse Width Modulation (PWM)

Output Internal

1 0 0 0 8 Reserved — —

1 0 0 1 9 Watchdog Pulse Output Internal

1 0 1 0 10 Watchdog Toggle Output Internal

1 0 1 1 11 Reserved — —

1 1 0 0 12 Reserved — —

1 1 0 1 13 Reserved — —

1 1 1 0 14 Reserved — —

1 1 1 1 15 Reserved — —

Note: The GPIO function is enabled only if the TC[3:0] bits are all 0.

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Timer/Event Counter

Timer Architecture


9.3.3.5 Inverter (INV) — TCSR Bit 8The Inverter (INV) bit affects the polarity of the incoming signal on the TIO input signal and the polarity of the output pulse generated on the TIO output signal. The effects of the INV bit are summarized in Table 9-3.

Table 9-3 Inverter (INV) Bit Operation

ModeTIO Programmed as Input TIO Programmed as Output

INV = 0 INV = 1 INV = 0 INV = 1

0 GPIO signal on the TIO signal read directly

GPIO signal on the TIO signal inverted

Bit written to GPIO put on TIO signal directly

Bit written to GPIO inverted and put on TIO signal

1 Counter is incremented on the rising edge of the signal from the TIO signal

Counter is incremented on the falling edge of the signal from the TIO signal

— —



TCRx output put on TIO signal directly

TCRx output inverted and put on TIO signal



— —

4 Width of the high input pulse is measured.

Width of the low input pulse is measured.

— —

5 Period is measured between the rising edges of the input signal.

Period is measured between the falling edges of the input signal.

— —

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Timer/Event Counter

Timer Architecture

The INV bit is cleared by a hardware RESET signal or a software RESET instruction.

Note: The INV bit affects both the timer and GPIO modes of operation. To ensure correct operation, this bit should be changed only when one or both of the following conditions is true:

• The timer has been disabled by clearing the TE bit in the TCSR.

• The timer is in GPIO mode.

The INV bit does not affect the polarity of the prescaler source when the TIO is used as input to the prescaler.

9.3.3.6 Timer Reload Mode (TRM) — TCSR Bit 9The Timer Reload Mode (TRM) bit controls the counter preload operation.

If the TRM bit is set:

• In Timer (0–3) and Watchdog (9–10) modes, the counter is reloaded each time after it reaches the value contained by the TCPR. Initially, the counter is preloaded with the TLR value after the TE bit is set and the first internal or external clock signal is received.

6 Event is captured on the rising edge of the signal from the TIO signal

Event is captured on the falling edge of the signal from the TIO signal

— —

7 — — Pulse generated by the timer has positive polarity

Pulse generated by the timer has negative polarity





Table 9-3 Inverter (INV) Bit Operation (Continued)

ModeTIO Programmed as Input TIO Programmed as Output

INV = 0 INV = 1 INV = 0 INV = 1

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Timer/Event Counter

Timer Architecture


• In PWM mode (7), the counter is reloaded each time counter overflow occurs.

• In Measurement (4–5) modes, if the TE bit is also set, the counter is preloaded with the TLR value on each appropriate edge of the input signal.

If the TRM bit is cleared, for each mode, the counter operates as free running counter and is incremented on each incoming event. The TRM bit is cleared by a hardware RESET signal or a software RESET instruction.

9.3.3.7 Direction (DIR) — TCSR Bit 11The Direction (DIR) bit determines the behavior of the TIO signal when it is used as a GPIO signal. When the DIR bit is set, the TIO signal is an output; when the DIR bit is cleared, the TIO signal is an input. The TIO signal can be used as a GPIO signal only when the TC[3:0] bits are all cleared. If any of the TC[3:0] bits are set, then the GPIO function is disabled and the DIR bit has no effect.

The DIR bit is cleared by a hardware RESET signal or a software RESET instruction.

9.3.3.8 Data Input (DI) — TCSR Bit 12The Data Input (DI) bit reflects the value of the TIO input signal. If the INV bit is set, the value of the TIO signal is inverted before it is written to the DI bit. If the INV bit is cleared, the value of the TIO signal is written directly to the DI bit.

The DI bit is cleared by a hardware RESET signal or a software RESET instruction.

9.3.3.9 Data Output (DO) — TCSR Bit 13The Data Output (DO) bit is the source of the TIO value when it is a data output signal. The TIO signal is data output when the GPIO mode is enabled and DIR is set. A value written to the DO bit is written to the TIO signal. If the INV bit is set, the value of the DO bit is inverted when written to the TIO signal. When the INV bit is cleared, the value of the DO bit is written directly to the TIO signal. When GPIO mode is disabled, writing the DO bit has no effect.

The DO bit is cleared by a hardware RESET signal or a software RESET instruction.

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Timer/Event Counter

Timer Architecture

9.3.3.10 Prescaler Clock Enable (PCE) — TCSR Bit 15The Prescaler Clock Enable (PCE) bit selects which clock is the timer source clock. When the PCE bit is cleared, the timer uses either an internal (CLK/2) signal or an external (TIO) signal as its source clock. When the PCE bit is set, the prescaler output is used as the timer source clock for the counter regardless of the timer operating mode. To ensure proper operation, the PCE bit should be changed only when the timer is disabled (when the TE bit is cleared). The source clock used for the prescaler is determined by the PS[1:0] bits of the TPLR. A timer can be clocked by a prescaler clock derived from the TIO of another timer.

The PCE bit is cleared by a hardware RESET signal or a software RESET instruction.

9.3.3.11 Timer Overflow Flag (TOF) — TCSR Bit 20The Timer Overflow Flag (TOF) bit indicates that counter overflow has occurred. This bit is cleared by writing a 1 to the TOF bit. Writing a 0 to the TOF bit has no effect. The bit is also cleared when the timer overflow interrupt is serviced.

The TOF bit is cleared by a hardware RESET signal, a software RESET instruction, the STOP instruction, or by clearing the TE bit to disable the timer.

9.3.3.12 Timer Compare Flag (TCF) — TCSR Bit 21The Timer Compare Flag (TCF) bit is set to indicate that the event count is complete. In the Timer, PWM, and Watchdog modes, the TCF bit is set when (N – M + 1) events have been counted. (N is the value in the compare register and M is the TLR value.) In the Measurement modes, the TCF bit is set when the measurement has been completed.

The TCF bit is cleared by writing a 1 into the TCF bit. Writing a 0 into the TCF bit has no effect. The bit is also cleared when the timer compare interrupt is serviced.

The TCF bit is cleared by a hardware RESET signal, a software RESET instruction, the STOP instruction, or by clearing the TE bit to disable the timer.

Note: The TOF and TCF bits are cleared by writing a 1 to that bit. In order to assure that only the desired bit is cleared, do not use the BSET command. The proper way to clear these bits is to write (using a MOVEP instruction) a 1 to the flag to be cleared and a 0 to the other flag.

9.3.3.13 Reserved Bits — TCSR Bits 3, 10, 14, 16-19, 22, 23These reserved bits are read as 0 and should be written with 0 for future compatibility.

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Timer/Event Counter

Timer Architecture


9.3.4 Timer Load Register (TLR)

The Timer Load Register (TLR) is a twenty-four bit write-only register. In all modes, the counter is preloaded with the TLR value after the TE bit (TCSR Bit 0) is set and a first event occurs.

If the TRM bit is set:

• In Timer modes(0-3), the counter is reloaded each time after it has reached the value contained by the Timer Compare Register and the new event occurs.

• In Measurement modes (4-5), if the TE bit is also set, the counter is reloaded with the TLR value on each appropriate edge of the input signal.

• In the PWM mode (7) the counter is reloaded each time after it has overflowed and the new event occurs.

• In Watchdog (9-10) modes, the counter is reloaded each time after it has reached the value contained in the Timer Compare Register (TCPR) and the new event occurs. In these modes, the counter is also reloaded whenever the TLR is written with a new value while the TE bit is set.

If the TRM bit is cleared, in all modes the counter operates as a free-running counter.

9.3.5 Timer Compare Register (TCPR)

The Timer Compare Register (TCPR) is a twenty-four bit read/write register that contains the value to be compared with the counter value. These two values are compared every timer clock after the TE bit (TCSR Bit 0) is set. When the values match, the Timer Compare Flag (TCF) bit (TCSR Bit 21) is set and an interrupt is generated if interrupts are enabled (i.e., the Timer Compare Interrupt Enable (TCIE) bit (TCSR Bit 2) is set). The TCPR is ignored in Measurement modes.

9.3.6 Timer Count Register (TCR)

The Timer Count Register (TCR) is a twenty-four bit read-only register. In Timer and Watchdog modes, the counter’s contents can be read at any time by reading the TCR. In Measurement modes, the TCR is loaded with the current value of the counter on the appropriate edge of the input signal, and its value can be read to determine the width, period, or delay of the leading edge of the input signal. When the timer is in Measurement modes, the TIO signal is used for the input signal.

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Timer/Event Counter

Timer Modes of Operation

9.4 TIMER MODES OF OPERATION

Each timer has various operational modes that meet a variety of system requirements. These modes are:

• Timer

– GPIO, Mode 0: Internal timer interrupt generated by the internal clock (free running counter)

– Pulse, Mode 1: External timer pulse generated by the internal clock

– Toggle, Mode 2: Output timing signal toggled by the internal clock

– Event Counter, Mode 3: Internal timer interrupt generated by an external clock

• Measurement

– Input Width, Mode 4: Input pulse width measurement

– Input Pulse, Mode 5: Input signal period measurement

– Capture, Mode 6: Capture external signal

• PWM, Mode 7: Pulse Width Modulation

• Watchdog

– Pulse, Mode 9: Output pulse, internal clock

– Toggle, Mode 10: Output toggle, internal clock

These modes are described in detail below. To select a mode, first enable the timer by setting the TE bit. Timer mode is selected by inputting correct values to the TC[3:0] bits (TCSR Bits 4-7) as shown in Table 9-2. This table also shows the TIO signal direction and the clock source for each timer mode.

Note: To ensure proper operation, the TC[3:0] bits should be changed only when the timer is disabled (when the TE bit (TCSR Bit 0) is cleared).

To enable the timer, set the TE bit. If the TE bit is cleared, the TIO (timer) signal acts as a GPIO signal.

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Timer/Event Counter



9.4.1 Timer Modes

The following Timer modes are provided:

• Timer GPIO

• Timer Pulse

• Timer Toggle

• Event Counter

9.4.1.1 Timer GPIO (Mode 0)

In this mode, the timer generates an internal interrupt when a counter value is reached (if the timer compare interrupt is enabled) or when the overflow interrupt is enabled.

Set the TE bit (TCSR Bit 0) to clear the counter and enable the timer. Load the timer count value into the TCPR. The counter is loaded with the TLR value when the first timer clock signal is received. The timer clock signal can be taken from either the DSP56300 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent timer clock signal increments the counter.

When the counter value equals the TCPR value, the TCF bit (TCSR Bit 21) is set, and if the TCIE bit (TCSR Bit 2) is set, a compare interrupt is generated. If the TRM bit (TCSR Bit 9) is set, the counter is reloaded with the TLR value on the next timer clock signal and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock signal.

This process is repeated until the timer is disabled (i.e., until the TE bit is cleared). If the counter overflows, the TOF bit (TCSR Bit 20) is set; if the TOIE bit (TCSR Bit 1) is set, an overflow interrupt is generated and the counter is reloaded with the TLR value. The counter contents can be read at any time by reading the TCR.


TC3 TC2 TC1 TC0 TIO Clock # KIND NAME

0 0 0 0 GPIO Internal 0 Timer GPIO

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Timer/Event Counter


9.4.1.2 Timer Pulse (Mode 1)

In this mode, the timer generates an external pulse on its TIO signal when the timer count reaches a pre-set value.

Set the TE bit (TCSR Bit 0) to clear the counter and enable the timer. Load the timer count value into the TCPR. The counter is loaded with the TLR value when the first timer clock signal is received. The timer clock signal can be taken from either the DSP56300 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent timer clock signal increments the counter.

When the counter value equals the TCPR value, the TCF bit (TCSR Bit 21) is set, and if the TCIE bit (TCSR Bit 2) is set, a compare interrupt is generated. Also, a TIO pulse with width equal to the timer clock period is output. The TIO signal polarity is determined by the value of the INV bit (TCSR Bit 8). On the next timer clock signal, if the TRM bit (TCSR Bit 9) is set, the counter is reloaded with the TLR value and the count is resumed; but if the TRM bit is cleared, the counter continues to be incremented on each timer clock signal.

This process is repeated until the timer is disabled (i.e., until the TE bit is cleared). If the counter overflows, the TOF bit (TCSR Bit 20) is set, and if the TOIE bit (TCSR Bit 1) is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR.

The TLR value sets the delay between starting the timer and generating the output pulse. To generate successive output pulses with a delay of X clocks between signals, set the TLR value to X/2 and set the TRM bit.

Note: The TIO bit polarity is dependent on the INV bit value. When TE is set, the TIO signal output value is put equal to the INV bit value to guarantee the first signal transition is correct.



0 0 0 1 Output Internal 1 Timer Pulse

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Timer/Event Counter



9.4.1.3 Timer Toggle (Mode 2)

In this mode, the timer periodically toggles the polarity of the TIO signal.

Set the TE bit (TCSR Bit 0) to clear the counter and enable the timer. Load the timer count value into the TCPR. The counter is loaded with the TLR value when the first timer clock signal is received. The TIO signal is loaded with the value of the INV bit (TCSR Bit 8). The timer clock signal can be taken from either the DSP56300 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent timer clock signal increments the counter.

When the counter value matches the TCPR value, the polarity of the TIO output signal is inverted. The TCF bit (TCSR Bit 21) is set and, if the TIE bit (TCSR Bit 2) is set, a compare interrupt is generated. On the next timer clock signal, if the TRM bit (TCSR Bit 9) is set, the counter is loaded with the TLR value and the count is resumed; but if the TRM bit is cleared, the counter continues to be incremented on each timer clock signal.


The TLR value and the TCPR sets the delay between starting the timer and toggling the TIO signal. To generate output signals with a delay of X clock cycles between toggles (assuming a clock of CLK/2), the TLR value should be set to 0, the TCPR should be set to X/2, and the TRM bit should be set.

Note: The TIO bit polarity is dependent on the INV bit value. When TE is set, the TIO signal output value is put equal to the INV bit value to guarantee the first signal transition is correct.



0 0 1 0 Output Internal 0 Timer Toggle

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Timer/Event Counter


9.4.1.4 Timer Event Counter (Mode 3)

In this mode, the timer counts external events and issues an interrupt when a preset number of events is counted.

Set the TE bit (TCSR Bit 0) to clear the counter and enable the timer. Load the timer count value into the TCPR. The counter is loaded with the TLR value when the first timer clock signal is received. The timer clock signal can be taken from either the TIO input signal or the prescaler clock output. Each subsequent clock signal increments the counter. If an external clock is used, it must be internally synchronized to the internal clock and its frequency must be less than the DSP56305 internal operating frequency divided by four (i.e., CLK/4).

The value of the INV bit (TCSR Bit 8) determines whether low-to-high (0 to 1) transitions or high-to-low (1 to 0) transitions increment the counter. If the INV bit is set, high-to-low transitions increment the counter. If the INV bit is cleared, low-to-high transitions increment the counter.

When the counter matches the TCPR value, the TCF bit (TCSR Bit 21) is set, if the TCIE bit (TCSR Bit 2) is set, a compare interrupt is generated. If the TRM bit (TCSR Bit 9) is set, the counter is loaded with the TLR value on the next timer clock signal and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock signal.




0 0 1 1 Input External 3 Timer Event Counter

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Timer/Event Counter



9.4.2 Signal Measurement Modes

The following Signal Measurement modes are provided:

• Measurement Input Width

• Measurement Input Period

• Measurement Capture

9.4.2.1 Measurement AccuracyThe external signal is synchronized with the internal clock used to increment the counter. This synchronization process can cause the number of clocks measured for the selected signal value to vary from the actual signal value by plus or minus one counter clock cycle.

9.4.2.2 Measurement Input Width (Mode 4)

In this mode, the timer counts the number of clocks that occur between opposite edges of an input signal.

Set the TE bit to clear the counter and enable the timer. After the first appropriate transition (as determined by the INV bit) occurs on the TIO input signal, the counter is loaded with the TLR value on the first timer clock signal received either from the DSP56305 clock divided by two (CLK/2) or from the prescaler clock input. Each subsequent clock signal increments the counter.

In this mode the TIO signal acts as a gating signal for the internal timer clock. The TIO polarity depends on the INV bit value. If the INV bit is set, the timer starts on the first high-to-low (1 to 0) signal transition on the TIO signal. If the INV bit is cleared, the timer starts on the first low-to-high (0 to 1) transition on the TIO signal.

When the first transition of opposite polarity to the INV bit occurs on the TIO signal, the counter stops. The TCF bit in the TCSR is set, and if the TCIE bit is set, a compare interrupt is generated. The value of the counter (which measures the width of the TIO pulse) is loaded into the TCR. The TCR can be read to determine the external signal pulse width. If the TRM bit is set, the counter is loaded with the TLR value on the first


TC3 TC2 TC1 TC0 Mode Name Kind TIO Clock

0 1 0 0 4 Input Width Measurement Input Internal

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Timer/Event Counter


timer clock received following the next valid transition occurring on the TIO input signal and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock, accumulating measurement results.

This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set; if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR.

9.4.2.3 Measurement Input Period (Mode 5)

In this mode, the timer counts the period between the reception of signal edges of the same polarity across the TIO signal.

Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the TLR. After the first appropriate transition (as determined by the INV bit) occurs on the TIO input signal, the counter is loaded with the TLR value on the first timer clock signal received from either the DSP56305 clock divided by two (CLK/2), or the prescaler clock output. Each subsequent clock signal increments the counter.

On each following signal transition of the same polarity that occurs on TIO, the TCF bit in the TCSR is set, and if the TCIE bit is set, a compare interrupt is generated. The counter contents are loaded into the TCR. The TCR then contains the elapsed time between two signal transitions on the TIO signal (that is, the distance between TIO edges).

On the next timer clock signal, if the TRM bit is set, the counter is loaded with the TLR value, and the count is resumed, but if the TRM bit is cleared, the counter continues being incremented on each timer clock signal, accumulating measurement results.

This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set, and if the TOIE bit is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR.

The value of the INV bit determines whether the period is measured between consecutive low-to-high (0 to 1) transitions of TIO or between consecutive high-to-low (1 to 0) transitions of TIO. If INV is set, high-to-low signal transitions are selected. If INV is cleared, low-to-high signal transitions are selected.



0 1 0 1 5 Input Period Measurement Input Internal

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Timer/Event Counter



9.4.2.4 Measurement Capture (Mode 6)

In this mode, the timer counts the number of clocks that elapse between starting the timer and receiving an external signal.

Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the TLR. When the first timer clock signal is received, the counter is loaded with the TLR value. The timer clock signal can be taken from either the DSP56305 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter.

At the first appropriate transition of the external clock detected on the TIO signal, the TCF bit in the TCSR is set and if the TCIE bit is set a compare interrupt is generated. The counter halts. The counter contents are loaded into the TCR. The TCR value represents the delay between setting the TE bit and detecting the first clock edge signal on the TIO signal.

The value of the INV bit determines whether a high-to-low (1 to 0) or low-to-high (0 to 1) transition of the external clock signals the end of the timing period. If the INV bit is set, a high-to-low transition signals the end of the timing period. If INV is cleared, a low-to-high transition signals the end of the timing period.

If the counter overflows, the TOF bit is set; if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR.



0 1 1 0 6 Capture Measurement Input Internal

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Timer/Event Counter


9.4.3 Pulse Width Modulation (PWM, Mode 7)

In this mode, the timer generates periodic pulses of a preset width.

Set the TE bit to clear the counter and enable the timer. When first timer clock is received from either the DSP56305 internal clock divided by two (CLK/2) or the prescaler clock output, the counter is loaded with the TLR value. Each subsequent timer clock increments the counter.

When the counter value comes to equal the TCPR value (which has been loaded with the Pulse Width), the TIO output signal is toggled and the TCF bit in the TCSR is set; if the TCIE bit is set, a compare interrupt is generated. The counter continues to be incremented on each timer clock. The TLR value determines the output period ($FFFFFF − TLR + 1). The timer counter increments the initial TLR value and toggles the TIO signal when the counter value exceeds $FFFFFF.

If counter overflow occurs, the TIO output signal is toggled, the TOF bit in TCSR is set, and if the TOIE bit is set an overflow interrupt is generated. If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock.

This process is repeated until the timer is disabled by clearing the TE bit. The counter contents can be read at any time by reading the TCR.

TIO signal polarity is determined by the INV bit value. When the counter is started by setting the TE bit, the TIO output signal assumes the value of the INV bit, to guarantee the first pin transition will be correct. On each subsequent toggling of the TIO signal, the polarity of the TIO signal is inverted. For example, if the INV bit is set, the TIO signal may generate the signal: 1010. If the INV bit is cleared, the TIO signal would generate the signal: 0101.

The duty cycle of the TIO signal is determined by the TCPR value. When the TLR value is incremented to be equal to the TCPR value, the TIO signal is toggled. The duty cycle is



0 1 1 1 7 Pulse Width Modulation

PWM Output Internal

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Timer/Event Counter



equal to [($FFFFFF – TCPR) / ($FFFFFF − TLR + 1)]. For a 50% duty cycle, the TCPR value is equal to ($FFFFFF + TLR + 1) / 2.

Note: The TCPR value must be greater than the TLR value.

9.4.4 Watchdog Modes

The following Watchdog Timer modes are provided:

• Watchdog Pulse

• Watchdog Toggle

9.4.4.1 Watchdog Pulse (Mode 9)

In this mode, the timer generates an external signal at a preset rate. The signal period is equal to the period of one timer clock.

Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the TCPR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56305 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter.

When the counter matches the TCPR value, the TCF bit in the TCSR is set, and if the TCIE bit is also set a compare interrupt is generated.

If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each subsequent timer clock.

This process is repeated until the timer is disabled (i.e., TE is cleared).

If the counter overflows, the TOF bit is set; if TOIE is set, an overflow interrupt is generated. At the same time, a pulse is output on the TIO signal with a pulse width equal to the timer clock period. The pulse polarity is determined by the value of the INV bit. If



1 0 0 1 9 Pulse Watchdog Output Internal

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Timer/Event Counter


the INV bit is set, the pulse polarity is high (logical 1). If the INV bit is cleared, the pulse polarity is low (logical 0).

The counter contents can be read at any time by reading the TCR. The counter is reloaded whenever the TLR is written with a new value while the TE bit is set.

Note: In this mode, internal logic preserves the TIO value and direction for an additional 2.5 internal clock cycles after the DSP56305 hardware reset signal is asserted. This ensures that a valid RESET signal is generated when the TIO signal is used to reset the DSP56305.

9.4.4.2 Watchdog Toggle (Mode 10)

In this mode, the timer toggles an external signal after a preset period.

Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the TCPR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56305 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter. The TIO signal is set to the value of the INV bit.

When the counter equals the TCPR value, the TCF bit in the TCSR is set; if the TCIE bit is also set, a compare interrupt is generated. If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each subsequent timer clock.

When counter overflow has occurred, the polarity of the TIO output signal is inverted, and the TOF bit in the TCSR is set; if the TOIE bit is also set an overflow interrupt is generated. The TIO polarity is determined by the INV bit. On the first transition TIO is set if INV is cleared and TIO is cleared if INV is set.

The counter is reloaded whenever the TLR is written with a new value while the TE bit is set. This process is repeated until the timer is disabled by clearing the TE bit. The counter contents can be read at any time by reading the TCR register.



1 0 1 0 10 Toggle Watchdog Output Internal

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Timer/Event Counter



Note: In this mode, internal logic preserves the TIO value and direction for an additional 2.5 internal clock cycles after the DSP56305 hardware reset signal is asserted. This ensures that a valid reset signal is generated when the TIO signal is used to reset the DSP56305.

9.4.5 Reserved Modes

Modes 8, 11, 12, 13, 14, and 15 are reserved.

9.4.6 Special Cases

Timer behavior during Wait and Stop processing states are special cases.

9.4.6.1 Timer Behavior during WaitTimer clocks are active during the execution of the WAIT instruction, and timer activity is undisturbed. If a timer interrupt is generated, the DSP56305 leaves the Wait state and services the interrupt.

9.4.6.2 Timer Behavior during StopDuring the execution of the STOP instruction, the timer clocks are disabled, timer activity is stopped, and the TIO signals are disconnected. Any external changes to the TIO signals are ignored when the DSP56305 is the Stop state. To ensure correct operation, the timers should be disabled before the DSP56305 is placed into the Stop state.

9.4.7 DMA Trigger

Each timer can also be used to trigger DMA transfers. For this to occur, a DMA channel must be programmed to be triggered by a timer event. The timer issues a DMA trigger on every compare event in all modes of operation. The DMA channel does not have the capability to save multiple DMA triggers generated by the timer. To ensure that all DMA triggers are serviced, the user must provide for the preceding DMA trigger to be serviced before the next trigger is received by the DMA channel.

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Timer/Event Counter


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SECTION 10

ON-CHIP EMULATION MODULE

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On-Chip Emulation Module

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-310.2 OnCE Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-310.3 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-410.4 OnCE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-510.5 OnCE Memory Breakpoint Logic . . . . . . . . . . . . . . . . . . . . . . .10-1010.6 OnCE Trace Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1510.7 Methods of Entering the Debug Mode. . . . . . . . . . . . . . . . . . .10-1610.8 Pipeline Information and OGDBR . . . . . . . . . . . . . . . . . . . . . .10-1810.9 Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2010.10 OnCE Commands and Serial Protocol . . . . . . . . . . . . . . . . . .10-2310.11 Target Site Debug System Requirements . . . . . . . . . . . . . . . .10-2310.12 Examples of Using the OnCE . . . . . . . . . . . . . . . . . . . . . . . . .10-2410.13 Examples of JTAG and OnCE interaction . . . . . . . . . . . . . . . .10-29

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Introduction


10.1 INTRODUCTION

The DSP56300 core On-Chip Emulation (OnCE™) module provides a means of unintrusive interaction with the DSP56300 core and its peripherals. The OnCE module allows the user to examine registers, memory, or on-chip peripherals, thus facilitating hardware and software development on the DSP56300 core processor. Special circuits and dedicated signals on the DSP56300 core are defined to avoid sacrificing any user-accessible on-chip resource. The OnCE module resources can be accessed only after executing the JTAG instruction ENABLE_ONCE. See Section 11, JTAG Port, for a description of the JTAG functionality and its relation to the OnCE. Figure 10-1 shows the block diagram of the OnCE module.

10.2 OnCE MODULE SIGNALS

The OnCE module controller functionality is accessed through the JTAG Test Access Port (TAP). There are no dedicated OnCE module signals for clock, data in, or data out. The JTAG signals TCK, TDI, and TDO are used to shift data and instructions in and out. See JTAG Signals on page 11-5 for the description of the JTAG signals. To facilitate emulation-specific functions, one additional signal, called DE, is provided on the DSP56305.

Figure 10-1 OnCE Module Block Diagram

TraceBuffer

BreakpointLogic

Pipeline Information Trace Logic

OnCE Controller

PABYABXAB

PDB PIL GDB

TDO

TRST

TDI

TCK

TagsBuffer

Control Bus

DE

AA0702

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Debug Event (DE)

10.3 DEBUG EVENT (DE)

The bidirectional open drain Debug Event Signal (DE) provides a fast means of entering the Debug mode of operation from an external command controller, and a fast means of acknowledging the entering of the Debug mode of operation to an external command controller . The assertion of this signal by a command controller causes the DSP56300 core to finish the current instruction being executed, save the instruction pipeline information, enter the Debug mode, and wait for commands to be entered from the TDI line. If the DE signal is used to enter the Debug mode, then it must be deasserted after the OnCE port responds with an acknowledge, before sending the first OnCE command. The assertion of this signal by the DSP56300 core indicates that the DSP has entered the Debug mode and is waiting for commands to be entered from the TDI line. The DE Signal also facilitates multiple processor connections, as shown in Figure 10-2.

The user can stop all the devices in the system when one of the devices enters the Debug mode. The user can also stop all the devices synchronously by asserting the DE line.

Figure 10-2 OnCE Module Multiprocessor Configuration

TDI TDO TDI TDOTDI TDOTDI

TMS

TCK

DE

TDO

TRST AA0703

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OnCE Controller


10.4 OnCE CONTROLLER

The OnCE controller contains the following blocks: OnCE Command Register (OCR), OnCE Decoder, and the status/control register. Figure 10-3 depicts the block diagram of the OnCE controller.

10.4.1 OnCE Command Register (OCR)

The OnCE Command Register (OCR) is an 8-bit shift register that receives its serial data from the TDI signal. It holds the 8-bit commands to be used as input for the OnCE Decoder. The OCR is shown in Figure 10-4.

Figure 10-3 OnCE Controller Block Diagram

Figure 10-4 OnCE Command Register

OnCE Command RegisterTDITCK

Status and ControlRegister TDO

Mode Select

OnCE DecoderISDEBUG

ISBKPT

ISSWDBG

ISDRISTRACE

Register WriteRegister Read

Update

AA0704

OCROnCE Command

RegisterReset = $00

Write Only

R/W GO EX RS4 RS3 RS2 RS1 RS0

7 6 5 4 3 2 1 0

AA0106

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OnCE Controller

10.4.1.1 Register Select (RS4–RS0) Bits 0–4The Register Select bits define which register is source/destination for the read/write operation. Table 10-4 shows the OnCE register addresses.

10.4.1.2 Exit Command (EX) Bit 5If the EX bit is set, leave Debug mode and resume normal operation. The EXIT command is executed only if the GO command is issued, and the operation is write to OPDBR or read/write to “No Register Selected.” Otherwise, the EX bit is ignored. Table 10-1 shows the definition of the EX bit.

10.4.1.3 GO Command (GO) Bit 6If the GO bit is set, execute the instruction that resides in the PIL register. To execute the instruction, the core leaves the Debug mode. The core returns to the Debug mode immediately after executing the instruction if the EX bit is cleared. The core goes on to normal operation if the EX bit is set. The GO command is executed only if the operation is write to OPDBR or read/write to “No Register Selected.” Otherwise, the GO bit is ignored. Table 10-2 shows the definition of the GO bit.

10.4.1.4 Read/Write Command (R/W ) Bit 7The R/W bit specifies the direction of data transfer.

Table 10-1 EX Bit Definition

EX Action

0 Remain in Debug mode

1 Leave Debug mode

Table 10-2 GO Bit Definition

GO Action

0 Inactive—no action taken

1 Execute instruction in PIL

Table 10-3 R/W Bit Definition

R/W Action

0 Write the data associated with the command into the register specified by RS4–RS0.

1 Read the data contained in the register specified by RS4–RS0.

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OnCE Controller


Table 10-4 OnCE Register Select Encoding

RS[4:0] Register Selected

00000 OnCE Status and Control Register (OSCR)

00001 Memory Breakpoint Counter (OMBC)

00010 Breakpoint Control Register (OBCR)

00011 Reserved Address


00101 Memory Limit Register 0 (OMLR0)

00110 Memory Limit Register 1 (OMLR1)



01001 GDB Register (OGDBR)

01010 PDB Register (OPDBR)

01011 PIL Register (OPILR)

01100 PDB GO-TO Register (for GO TO command)

01101 Trace Counter (OTC)


01111 PAB Register for Fetch (OPABFR)

10000 PAB Register for Decode (OPABDR)

10001 PAB Register for Execute (OPABEX)

10010 Trace Buffer and Increment Pointer


101xx Reserved Address

11xx0 Reserved Address

11x0x Reserved Address

110xx Reserved Address

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OnCE Controller

10.4.2 OnCE Decoder (ODEC)

The OnCE Decoder (ODEC) supervises the entire OnCE module activity. It receives as input the 8-bit command from the OCR, a signal from JTAG Controller (indicating that 8/24 bits have been received and update of the selected data register must be performed), and a signal indicating that the core was halted. The ODEC generates all the strobes required for reading and writing the selected OnCE registers.

10.4.3 OnCE Status and Control Register (OSCR)

The OnCE Status and Control Register (OSCR) is a 24-bit register used to enable the Trace mode of operation and to indicate the cause of entering the Debug mode. The control bits are read/write while the status bits are read-only. The OSCR bits are cleared on hardware reset. The OSCR is shown in Figure 10-5.

10.4.3.1 Trace Mode Enable (TME) Bit 0The Trace Mode Enable (TME) control bit, when set, enables the Trace mode of operation.

10.4.3.2 Interrupt Mode Enable (IME) Bit 1 The Interrupt Mode Enable (IME) control bit, when set, causes the chip to execute a vectored interrupt to the address VBA:$06 instead of entering the Debug mode.

11111 No Register Selected

Figure 10-5 OnCE Status and Control Register (OSCR)

Table 10-4 OnCE Register Select Encoding (Continued)

RS[4:0] Register Selected

OnCE Status andControl Register

Read/Write

OS1 OS0 TO MBO SWO IME TME

9 8 7 6 5 4 3 2 1 023

Indicates reserved bits, written as 0 for future compatibility AA0705

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OnCE Controller


10.4.3.3 Software Debug Occurrence (SWO) Bit 2 The Software Debug Occurrence (SWO) bit is a read-only status bit that is set when the Debug mode of operation is entered because of the execution of the DEBUG or DEBUGcc instruction with condition true. This bit is cleared when leaving the Debug mode.

10.4.3.4 Memory Breakpoint Occurrence (MBO) Bit 3 The Memory Breakpoint Occurrence (MBO) bit is a read-only status bit that is set when the Debug mode of operation is entered because a memory breakpoint has been encountered. This bit is cleared when leaving the Debug mode.

10.4.3.5 Trace Occurrence (TO) Bit 4 The Trace Occurrence (TO) bit is a read-only status bit that is set when the Debug mode of operation is entered when the Trace Counter is zero while Trace mode is enabled. This bit is cleared when leaving the Debug mode.

10.4.3.6 Reserved OCSR Bit 5Bit 5 is reserved for future use. It is read as 0 and should be written with 0 for future compatibility.

10.4.3.7 Core Status (OS0, OS1) Bits 6-7 The Core Status (OS0, OS1) bits are read-only status bits that provide core status information. By examining the status bits, the user can determine whether the chip has entered the Debug mode. Examining SWO, MBO, and TO identifies the cause of entering the Debug mode. The user can also examine these bits and determine the cause why the chip has not entered the Debug mode after debug event assertion (DE) or as a result of the execution of the JTAG DEBUG REQUEST instruction (core waiting for the bus, STOP or WAIT instruction, etc.). These bits are also reflected in the JTAG instruction shift register, which allows the polling of the core status information at the JTAG level. This is useful when the DSP56300 core executes the STOP instruction (and therefore there are no clocks) to allow the reading of OSCR. See Table 10-5 for the definition of the OS0–OS1 bits.

Table 10-5 Core Status Bits Description

OS1 OS0 Description

0 0 DSP56300 core is executing instructions

0 1 DSP56300 core is in Wait or Stop

1 0 DSP56300 core is waiting for bus

1 1 DSP56300 core is in Debug mode

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OnCE Memory Breakpoint Logic

10.4.3.8 Reserved Bits 8-23 Bits 8–23 are reserved for future use. They are read as 0 and should be written with 0 for future compatibility.

10.5 OnCE MEMORY BREAKPOINT LOGIC

Memory breakpoints can be set on program memory or data memory locations. In addition, the breakpoint does not have to be in a specific memory address, but within an approximate address range of where the program may be executing. This significantly increases the programmer’s ability to monitor what the program is doing in real-time.

The breakpoint logic, described in Figure 10-6, contains a latch for the addresses, which are registers that store the upper and lower address limit, address comparators, and a breakpoint counter.

Figure 10-6 OnCE Memory Breakpoint Logic 0

Memory Address Latch

PAB XAB YAB

Memory Bus Select

Memory Limit Register 1

Address Comparator 1

Memory Limit Register 0

Address Comparator 0

TDITDO

TCK

Breakpoint Counter

MemoryBreakpointSelection

DEC

Breakpoint

Count = 0

Occurred

N,V

N,V

Breakpoint Control

TDI TDOTCK

ISBKPT

AA0706

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Address comparators are useful in determining where a program may be getting lost or when data is being written where it should not be written. They are also useful in halting a program at a specific point to examine/change registers or memory. Using address comparators to set breakpoints enables the user to set breakpoints in RAM or ROM and while in any operating mode. Memory accesses are monitored according to the contents of the OBCR as specified in OnCE Breakpoint Control Register (OBCR) on page 10-12.

10.5.1 OnCE Memory Address Latch (OMAL)

The OnCE Memory Address Latch (OMAL) is a 16-bit register that latches the PAB, XAB or YAB on every instruction cycle according to the MBS1–MBS0 bits in OBCR.

10.5.2 OnCE Memory Limit Register 0 (OMLR0)

The OnCE Memory Limit Register 0 (OMLR0) is a 16-bit register that stores the memory breakpoint limit. Before enabling breakpoints, OMLR0 must be loaded by the external command controller. OMLR0 can be read or written through the JTAG port.

10.5.3 OnCE Memory Address Comparator 0 (OMAC0)

The OnCE Memory Address Comparator 0 (OMAC0) compares the current memory address (stored in OMAL0) with the OMLR0 contents.

10.5.4 OnCE Memory Limit Register 1 (OMLR1)

The OnCE Memory Limit Register 1 (OMLR1) is a 16-bit register that stores the memory breakpoint limit. OMLR1 can be read or written through the JTAG TAP. Before enabling breakpoints, OMLR1 must be loaded by the external command controller.

10.5.5 OnCE Memory Address Comparator 1 (OMAC1)

The OnCE Memory Address Comparator 1 (OMAC1) compares the current memory address (stored in OMAL0) with the OMLR1 contents.

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10.5.6 OnCE Breakpoint Control Register (OBCR)

The OnCE Breakpoint Control Register (OBCR) is a 16-bit register used to define the memory breakpoint events. OBCR can be read or written through the JTAG port. All the bits of the OBCR are cleared on hardware reset. The OBCR is described in Figure 10-7.

10.5.6.1 Memory Breakpoint Select (MBS0–MBS1) Bits 0–1The Memory Breakpoint Select bits (MBS0–MBS1) enable memory breakpoints 0 and 1, allowing them to occur when a memory access is performed on P, X, or Y space. See Table 10-6 for the definition of the MBS0–MBS1 bits.

10.5.6.2 Breakpoint 0 Read/Write Select (RW00–RW01) Bits 2–3The Breakpoint 0 Read/Write Select bits (RW00–RW01) define the memory breakpoints 0 to occur when a memory address accesses is performed for read, write or both. See Table 10-7 for the definition of the RW00–RW01 bits.

Figure 10-7 OnCE Breakpoint Control Register (OBCR)

Table 10-6 Memory Breakpoint 0 and 1 Select Table

MBS1 MBS0 Description

0 0 Reserved

0 1 Breakpoint on P access

1 0 Breakpoint on X access

1 1 Breakpoint on Y access

OnCE BreakpointControl Register

Reset = $0010Read/Write

BT1 BT0 CC CC RW RW CC CC RW RW MB MB* * * *

11 10 9 8 7 6 5 4 3 2 1 015 14 13 12

* Indicates reserved bits, written as 0 for future compatibility

1011 11 10 01 00 01 00 S1 S0

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10.5.6.3 Breakpoint 0 Condition Code Select (CC00–CC01) Bits 4–5 The Breakpoint 0 Condition Code Select bits (CC00–CC01) define the condition of the comparison between the current Memory Address (OMAL0) and the Memory Limit Register 0 (OMLR0). See Table 10-8 for the definition of the CC00–CC01 bits.

10.5.6.4 Breakpoint 1 Read/Write Select (RW10–RW11) Bits 6–7 The Breakpoint 1 Read/Write Select (RW10–RW11) bits control define memory breakpoint 1 to occur when a memory address accesses is performed for read, write or both. See Table 10-9 for the definition of the RW10–RW11 bits.

Table 10-7 Breakpoint 0 Read/Write Select Table

RW01 RW00 Description

0 0 Breakpoint disabled

0 1 Breakpoint on write access

1 0 Breakpoint on read access

1 1 Breakpoint on read or write access

Table 10-8 Breakpoint 0 Condition Select Table

CC01 CC00 Description

0 0 Breakpoint on not equal

0 1 Breakpoint on equal

1 0 Breakpoint on less than

1 1 Breakpoint on greater than

Table 10-9 Breakpoint 1 Read/Write Select Table

RW11 RW10 Description

0 0 Breakpoint disabled

0 1 Breakpoint on write access

1 0 Breakpoint on read access

1 1 Breakpoint read or write access

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10.5.6.5 Breakpoint 1 Condition Code Select (CC10–CC11) Bits8–9 The Breakpoint 1 Condition Code Select bits (CC10–CC11) define the condition of the comparison between the current memory address (OMAL0) and the OnCE Memory Limit Register 1 (OMLR1). See Table 10-10 for the definition of the CC10–CC11 bits.

10.5.6.6 Breakpoint 0 and 1 Event Select (BT0–BT1) Bits10–11 The Breakpoint 0 and 1 Event Select bits (BT0–BT1) define the sequence between Breakpoint0 and 1. If the condition defined by BT0–BT1 is met, then the Breakpoint Counter (OMBC) is decremented. See Table 10-11 for the definition of the BT0–BT1 bits.

10.5.6.7 OnCE Memory Breakpoint Counter (OMBC) The OnCE Memory Breakpoint Counter (OMBC) is a 16-bit counter that is loaded with a value equal to the number of times minus one that a memory access event should occur before a memory breakpoint is declared. The memory access event is specified by the OBCR and by the memory limit registers. On each occurrence of the memory access event, the breakpoint counter is decremented. When the counter reaches 0 and a new occurrence takes place, the chip enters the Debug mode. The OMBC can be read or written through the JTAG port. Every time that the limit register is changed, or a different breakpoint event is selected in the OBCR, the breakpoint counter must be written afterwards. This ensures that the OnCE breakpoint logic is reset and that no previous events can affect the new breakpoint event selected. The breakpoint counter is cleared by hardware reset.

Table 10-10 Breakpoint 1 Condition Select Table

CC11 CC10 Description

0 0 Breakpoint on not equal

0 1 Breakpoint on equal

1 0 Breakpoint on less than

1 1 Breakpoint on greater than

Table 10-11 Breakpoint 0 and 1 Event Select Table

BT1 BT0 Description

0 0 Breakpoint 0 and Breakpoint 1

0 1 Breakpoint 0 or Breakpoint 1

1 0 Breakpoint 1 after Breakpoint 0

1 1 Breakpoint 0 after Breakpoint 1

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OnCE Trace Logic


10.5.6.8 Reserved Bits 12-15 Bits 12–15 are reserved for future use. They are read as 0 and should be written with 0 for future compatibility.

10.6 OnCE TRACE LOGIC

Using the OnCE Trace Logic, execution of instructions in single or multiple steps is possible. The OnCE Trace Logic causes the chip to enter the Debug mode of operation after the execution of one or more instructions and wait for OnCE commands from the debug serial port. The OnCE Trace Logic block diagram is shown in Figure 10-8.

The Trace mode has a counter associated with it so that more than one instruction can be executed before returning back to the Debug mode of operation. The objective of the counter is to allow the user to take multiple instruction steps real-time before entering the Debug mode. This feature helps the software developer debug sections of code that do not have a normal flow or are getting hung up in infinite loops. The Trace Counter also enables the user to count the number of instructions executed in a code segment.

To enable the Trace mode of operation, the counter is loaded with a value, the program counter is set to the start location of the instruction(s) to be executed real-time, the TME bit is set in the OSCR, and the DSP56300 core exits the Debug mode by executing the appropriate command issued by the external command controller.

Figure 10-8 OnCE Trace Logic Block Diagram

TDI

TDO

TCK

Trace CounterDEC

End of Instruction

Count = 0

ISTRACE AA0708

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Methods of Entering the Debug Mode

Upon exiting the Debug mode, the counter is decremented after each execution of an instruction. Interrupts are serviceable and all instructions executed, including fast interrupt services and the execution of each repeated instruction, cause the Trace Counter to be decremented. Upon decrementing to 0, the DSP56300 core re-enters the Debug mode, the Trace Occurrence bit (TO) in the OSCR register is set, the core Status bits OS[1:0] are set to 11, and the DE signal is asserted to indicate that the DSP56300 core has entered Debug mode and is requesting service.

The OnCE Trace Counter (OTC) is a 16-bit counter that can be read or written through the JTAG port. If N instructions are to be executed before entering the Debug mode, the Trace Counter should be loaded with N – 1. The Trace Counter is cleared by hardware reset.

10.7 METHODS OF ENTERING THE DEBUG MODE

Entering the Debug mode is acknowledged by the chip by setting the Core Status bits OS1 and OS0 and asserting the DE line. This informs the external command controller that the chip has entered the Debug mode and is waiting for commands.The DSP56300 core can disable the OnCE module if the ROM Security option is implemented. If the ROM Security is implemented, the OnCE module remains inactive until a write operation to the OGDBR is executed by the DSP56300 core.

10.7.1 External Debug Request During RESET Assertion

Holding the DE line asserted during the assertion of RESET causes the chip to enter the Debug mode. After receiving the acknowledge, the external command controller must negate the DE line before sending the first command.

Note: In this case, the chip does not execute any instruction before entering the Debug mode.

10.7.2 External Debug Request During Normal Activity

Holding the DE line asserted during normal chip activity causes the chip to finish the execution of the current instruction and then enter the Debug mode. After receiving the acknowledge, the external command controller must negate the DE line before sending the first command. This process is the same for any newly fetched instruction, including

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Methods of Entering the Debug Mode


instructions fetched by the interrupt processing or instructions that will be aborted by the interrupt processing.

Note: In this case the chip completes the execution of the current instruction and stops after the newly fetched instruction enters the instruction latch.

10.7.3 Executing the JTAG DEBUG_REQUEST Instruction

Executing the JTAG instruction DEBUG_REQUEST asserts an internal debug request signal. Consequently, the chip finishes the execution of the current instruction and stops after the newly fetched instruction enters the instruction latch. After entering the Debug mode, the Core Status bits OS1 and OS0 are set and the DE line is asserted, thus acknowledging the external command controller that the Debug mode of operation has been entered.

10.7.4 External Debug Request During Stop Mode

Executing the JTAG instruction DEBUG_REQUEST (or asserting DE) while the chip is in the Stop state (i. e., has executed a STOP instruction) causes the chip to exit the Stop state and enter the Debug mode. After receiving the acknowledge, the external command controller must negate DE before sending the first command.

Note: In this case, the chip completes the execution of the STOP instruction and halts after the next instruction enters the instruction latch.

10.7.5 External Debug Request During Wait Mode

Executing the JTAG instruction DEBUG_REQUEST (or asserting DE) while the chip is in the Wait state (i. e., has executed a WAIT instruction) causes the chip to exit the Wait state and enter the Debug mode. After receiving the acknowledge, the external command controller must negate DE before sending the first command.

Note: In this case, the chip completes the execution of the WAIT instruction and halts after the next instruction enters the instruction latch.

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Pipeline Information and OGDBR

10.7.6 Software Request During Normal Activity

Upon executing the DSP56300 core instruction DEBUG (or DEBUGcc when the specified condition is true), the chip enters the Debug mode after the instruction following the DEBUG instruction has entered the instruction latch.

10.7.7 Enabling Trace Mode

When the Trace mode mechanism is enabled and the Trace Counter is greater than zero, the Trace Counter is decremented after each instruction execution. Execution of an instruction when the value in the Trace Counter is 0 causes the chip to enter the Debug mode after completing the execution of the instruction. Only instructions actually executed cause the Trace Counter to decrement. An aborted instruction does not decrement the Trace Counter and does not cause the chip to enter the Debug mode.

10.7.8 Enabling Memory Breakpoints

When the memory breakpoint mechanism is enabled with a Breakpoint Counter value of 0, the chip enters the Debug mode after completing the execution of the instruction that caused the memory breakpoint to occur. In case of breakpoints on executed Program memory fetches, the breakpoint is acknowledged immediately after the execution of the fetched instruction. In case of breakpoints on accesses to X, Y, or Program memory spaces by MOVE instructions, the breakpoint is acknowledged after the completion of the instruction following the instruction that accessed the specified address.

10.8 PIPELINE INFORMATION AND OGDBR

To restore the pipeline and to resume normal chip activity upon returning from the Debug mode, a number of on-chip registers store the chip pipeline status. Figure 10-9 shows the block diagram of the Pipeline Information Registers, with the exception of the PAB registers, which are shown in Figure 10-10 on page 10-22.

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Pipeline Information and OGDBR


10.8.1 OnCE PDB Register (OPDBR)

The OnCE Program Data Bus Register (OPDBR) is a 24-bit latch that stores the value of the Program Data Bus generated by the last program memory access of the core before the Debug mode is entered. The OPDBR register can be read or written through the JTAG port. This register is affected by the operations performed during the Debug mode and must be restored by the external command controller when returning to Normal mode.

10.8.2 OnCE PIL Register (OPILR)

The OnCE PIL Register (OPILR) is a 24-bit latch that stores the value of the Instruction Latch before the Debug mode is entered. OPILR can only be read through the JTAG port.

Note: Since the Instruction Latch is affected by the operations performed during the Debug mode, it must be restored by the external command controller when returning to Normal mode. Since there is no direct write access to the Instruction Latch, the task of restoring is accomplished by writing to OPDBR with no-GO and no-EX. In this case the data written on PDB is transferred into the Instruction Latch.

Figure 10-9 OnCE Pipeline Information and GDB Registers

PDB Register (OPDBR)

GDB Register (OGDBR)

TDI

TDO TCK

PIL Register (OPILR)

PIL

PDB

GDB

AA0709

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Trace Buffer

10.8.3 OnCE GDB Register (OGDBR)

The OnCE GDB Register (OGDBR) is a 16-bit latch that can only be read through the JTAG port. The OGDBR is not actually required for restoring the pipeline status, but is required as a means of passing information between the chip and the external command controller. The OGDBR is mapped on the X internal I/O space at address $FFFC. Whenever the external command controller needs the contents of a register or memory location, it forces the chip to execute an instruction that brings that information to the OGDBR. Then the contents of the OGDBR are delivered serially to the external command controller by the command READ GDB REGISTER.

10.9 TRACE BUFFER

To ease debugging activity and keep track of program flow, the DSP56300 core provides a number of on-chip dedicated resources. There are three read-only PAB registers that give pipeline information when the Debug mode is entered, and a Trace buffer that stores the address of the last instruction that was executed, as well as the addresses of the last twelve change of flow instructions.

10.9.1 OnCE PAB Register for Fetch (OPABFR)

The OnCE PAB Register for Fetch Register (OPABFR) is a 16-bit register that stores the address of the last instruction whose fetch was started before the Debug mode was entered.The OPABFR can only be read through the JTAG port. This register is not affected by the operations performed during the Debug mode.

10.9.2 PAB Register for Decode (OPABDR)

The OnCE PAB Register for Decode Register (OPABDR) is a 16-bit register that stores the address of the instruction currently on the PDB. This is the instruction whose fetch was completed before the chip has entered the Debug mode. The OPABDR can only be read through the JTAG port. This register is not affected by the operations performed during the Debug mode.

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Trace Buffer


10.9.3 OnCE PAB Register for Execute (OPABEX)

The OnCE PAB Register for Execute (OPABEX) is a 16-bit register that stores the address of the instruction currently in the Instruction Latch. This is the instruction that would have been decoded and executed if the chip would not have entered the Debug mode. The OPABEX register can only be read through the JTAG port. This register is not affected by the operations performed during the Debug mode.

10.9.4 Trace Buffer

The Trace buffer stores the addresses of the last twelve change of flow instructions that were executed, as well as the address of the last executed instruction. The Trace buffer is implemented as a circular buffer containing twelve 17-bit registers and one 4-bit counter. All the registers have the same address, but any read access to the Trace buffer address causes the counter to increment, thus pointing to the next Trace buffer register. The registers are serially available to the external command controller through their common Trace buffer address. Figure 10-10 on page 10-22 shows the block diagram of the Trace buffer. The Trace buffer is not affected by the operations performed during the Debug mode except for the Trace buffer pointer increment when reading the Trace buffer. When entering the Debug mode, the Trace buffer counter is pointing to the Trace buffer register containing the address of the last executed instructions. The first Trace buffer read obtains the oldest address and the following Trace buffer reads get the other addresses from the oldest to the newest, in order of execution.

Notes: 1. To ensure Trace buffer coherence, a complete set of twelve reads of the Trace buffer must be performed. This is necessary due to the fact that each read increments the Trace buffer pointer, thus pointing to the next location. After twelve reads, the pointer indicates the same location as before starting the read procedure.

2. On any change of flow instruction, the Trace buffer stores both the address of the change of flow instruction, as well as the address of the target of the change of flow instruction. In the case of conditional change of flows, the address of the change of flow instruction is always stored (regardless of the fact that the change of flow is true or false), but if the conditional change of flow is false (i.e., not taken) the address of the target is not stored. In order to facilitate the program trace reconstruction, every Trace buffer location has an additional ‘invalid bit’ (the 25th bit). If a conditional change of flow instruction has a ‘condition false’, the invalid bit is set, thus marking this instruction as not taken. Therefore, it is imperative to read seventeen bits of

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Trace Buffer

data when reading the twelve Trace buffer registers. Since data is read LSB first, the invalid bit is the first bit to be read.

Figure 10-10 OnCE Trace Buffer

Fetch Address (OPABFR)

PAB

Decode Address (OPABDR)

CircularBufferPointer

Trace Buffer Shift RegisterTDOTCK

Trace Buffer Register 0




Execute Address (OPABEX)

TDIAA0710

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OnCE Commands and Serial Protocol


10.10 ONCE COMMANDS AND SERIAL PROTOCOL

To permit an efficient means of communication between the external command controller and the DSP56300 core chip, the following protocol is adopted. Before starting any debugging activity, the external command controller has to wait for an acknowledge on the DE line indicating that the chip has entered the Debug mode (optionally the external command controller can poll the OS1 and OS0 bits in the JTAG instruction shift register). The external command controller communicates with the chip by sending 8-bit commands that can be accompanied by 24 bits of data. Both commands and data are sent or received Least Significant Bit (LSB) first. After sending a command, the external command controller should wait for the DSP56300 core chip to acknowledge execution of the command. The external command controller can send a new command only after the chip has acknowledged execution of the previous command.

The OnCE commands are classified as follows:

• Read commands (when the chip delivers the required data)

• Write commands (when the chip receives data and writes the data in one of the OnCE registers)

• Commands that do not have data transfers associated with them

The commands are 8 bits long and have the format shown in Figure 10-4.

10.11 TARGET SITE DEBUG SYSTEM REQUIREMENTS

A typical debug environment consists of a target system where the DSP56300 core-based device resides in the user defined hardware. The JTAG port interfaces to the external command controller over a 8-line link consisting of the five JTAG port lines, one OnCE module line, a ground, and a reset line. The reset line is optional and is only used to reset the DSP56300 core-based device and its associated circuitry.

The external command controller acts as the medium between the DSP56300 core target system and a host computer. The external command controller circuit acts as a JTAG port driver and host computer command interpreter. The controller issues commands based on the host computer inputs from a user interface program that communicates with the user.

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Examples of Using the OnCE

10.12 EXAMPLES OF USING THE OnCE

Following are some examples of debugging procedures. All these examples assume that the DSP is the only device in the JTAG chain. If there is more than one device in the chain (additional DSPs or other devices), the other devices can be forced to execute the JTAG BYPASS instruction such as their effect in the serial stream will be one bit per additional device. The events such as select-DR, select-IR, update-DR, and shift-DR refer to bringing the JTAG TAP in the corresponding state. Please refer to Section 11 (JTAG), for a detailed description of the JTAG protocol.

10.12.1 Checking Whether the Chip has Entered the Debug Mode

There are two methods to verify that the chip has entered the Debug mode:

1. Every time the chip enters the Debug mode, a pulse is generated on the DE signal. A pulse is also generated every time the chip acknowledges the execution of an instruction while in Debug mode. An external command controller can connect the DE line to an interrupt signal in order to sense the acknowledge.

2. An external command controller can poll the JTAG instruction shift register for the status bits OS[1:0]. When the chip is in Debug mode, these bits are set to the value 11.

Note: In the following paragraphs, the ACK notation denotes the operation performed by the command controller to check whether the Debug mode has been entered (either by sensing DE or by polling JTAG instruction shift register).

10.12.2 Polling the JTAG Instruction Shift Register

In order to poll the core status bits in the JTAG Instruction Shift register the following sequence must be performed:

1. Select shift-IR. Passing through capture-IR loads the core status bits into the instruction shift register.

2. Shift in ENABLE_ONCE. While shifting-in the new instruction the captured status information is shifted-out. Pass through update-IR.

3. Return to Run-Test/Idle.

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The external command controller can analyze the information shifted out and detect whether the chip has entered the Debug mode.

Note: JTAG compliance requires a preamble of 01 prior to shifting out status information.

10.12.3 Saving Pipeline Information

The debugging activity is accomplished by means of DSP56300 core instructions supplied from the external command controller. Therefore, the current state of the DSP56300 core pipeline must be saved prior to starting the debug activity and of course the state must be restored prior to returning to the Normal mode of operation. Following is the description of the saving procedure (assume that ENABLE_ONCE has been executed and Debug mode has been entered and verified, as described in Checking Whether the Chip has Entered the Debug Mode on page 10-24):

1. Select shift-DR. Shift in the “Read PDB”. Pass through update-DR.

2. Select shift-DR. Shift out the 24-bit OPDB register. Pass through update-DR.

3. Select shift-DR. Shift in the “Read PIL”. Pass through update-DR.

4. Select shift-DR. Shift out the 24-bit OPILR register. Pass through update-DR.

Note that there is no need to verify acknowledge between steps 1 and 2, as well as 3 and 4, because completion is guaranteed by design.

10.12.4 Reading the Trace Buffer

An optional step during debugging activity is reading the information associated with the Trace buffer in order to enable an external program to reconstruct the full trace of the executed program. Following is the description of the read Trace buffer procedure (assume that all actions described in Saving Pipeline Information have been executed):

1. Select shift-DR. Shift in the “Read PABFR”. Pass through update-DR.

2. Select shift-DR. Shift out the 16-bit OPABFR register. Pass through update-DR.

3. Select shift-DR. Shift in the “Read PABDR”. Pass through update-DR.

4. Select shift-DR. Shift out the 16-bit OPABDR register. Pass through update-DR.

5. Select shift-DR. Shift in the “Read PABEX”. Pass through update-DR.

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6. Select shift-DR. Shift out the 16-bit OPABEX register. Pass through update-DR.

7. Select shift-DR. Shift in the “Read FIFO”. Pass through update-DR.

8. Select shift-DR. Shift out the 17-bit FIFO register. Pass through update-DR.

9. Repeat steps 7 and 8 for the entire FIFO (12 times).

Note: The user must read the entire FIFO, since each read increments the FIFO pointer, thus pointing to the next FIFO location. At the end of this procedure, the FIFO pointer points back to the beginning of the FIFO.

The information that has been read by the external command controller now contains the address of the newly fetched instruction, the address of the instruction currently on the PDB, the address of the instruction currently on the instruction latch, as well as the addresses of the last twelve instructions that have been executed and are change of flow. A user program can now reconstruct the flow of a full trace based on this information and on the original source code of the currently running program.

10.12.5 Displaying a Specified Register

The DSP56300 must be in Debug mode and all actions described in Saving Pipeline Information on page 10-25 have been executed. The sequence of actions is:

1. Select shift-DR. Shift in the “Write PDB with GO no-EX”. Pass through update-DR.

2. Select shift-DR. Shift in the 24-bit opcode: “MOVE reg, X:OGDB”. Pass through update-DR to actually write OPDBR and thus begin executing the MOVE instruction.

3. Wait for DSP to reenter Debug mode (wait for DE or poll core status).

4. Select shift-DR and shift in “READ GDB REGISTER”. Pass through update-DR (this selects OGDBR as the data register for read).

5. Select shift-DR. Shift out the OGDBR contents. Pass through update-DR. Wait for next command.

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10.12.6 Displaying X Memory Area Starting at Address $xxxx

The DSP56300 must be in Debug mode and all actions described in Saving Pipeline Information on page 10-25 must have been executed. Since R0 is used as pointer for the memory, R0 is saved first. The sequence of actions is:


2. Select shift-DR. Shift in the 24-bit opcode: “MOVE R0, X:OGDB”. Pass through update-DR to actually write OPDBR and thus begin executing the MOVE instruction.



5. Select shift-DR. Shift out the OGDBR contents. Pass through update-DR. R0 is now saved.

6. Select shift-DR. Shift in the “Write PDB with no-GO no-EX”. Pass through update-DR.

7. Select shift-DR. Shift in the 24-bit opcode: “MOVE #$xxxx,R0”. Pass through update-DR to actually write OPDBR.


9. Select shift-DR. Shift in the second word of the 24-bit opcode: “MOVE #$xxxx,R0” (the $xxxx field). Pass through update-DR to actually write OPDBR and execute the instruction. R0 is loaded with the base address of the memory block to be read.



12. Select shift-DR. Shift in the 24-bit opcode: “MOVE X:(R0)+, X:OGDB”. Pass through update-DR to actually write OPDBR and thus begin executing the MOVE instruction.



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15. Select shift-DR. Shift out the OGDBR contents. Pass through update-DR. The memory contents of address $xxxx has been read.

16. Select shift-DR. Shift in the “NO SELECT with GO no-EX”. Pass through update-DR. This re-executes the same “MOVE X:(R0)+, X:OGDB” instruction.

17. Repeat from step 14 to complete the reading of the entire block. When finished, restore the original value of R0.

Note: Polling for status through the JTAG instruction register is preferable to reading the OnCE status register through the DR path.

10.12.7 Going from Debug to Normal Mode in a Current Program

In this case, the user has finished examining the current state of the machine, changed some of the registers, and wishes to return and continue execution of its program from the point where it stopped. Therefore, the user must restore the pipeline of the machine end enable normal instruction execution. The sequence of actions is:


2. Select shift-DR. Shift in the 24 bits of saved PIL (instruction latch value). Pass through update-DR to actually write the Instruction Latch.

3. Select shift-DR. Shift in the “Write PDB with GO and EX”. Pass through update-DR.

4. Select shift-DR. Shift in the 24 bits of saved PDB. Pass through update-DR to actually write the PDB. At the same time the internally saved value of the PAB is driven back from the PABFR register onto the PAB, the ODEC releases the chip from Debug mode and the normal flow of execution is continued.

10.12.8 Going from Debug to Normal Mode in a New Program

In this case, the user has finished examining the current state of the machine, changed some of the registers, and wishes to start the execution of a new program (the GOTO command). Therefore, the user must force a “change of flow” to the starting address of the new program ($xxxx). The sequence of actions is:


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Examples of JTAG and OnCE interaction


1. Select shift-DR. Shift in the 24-bit “$0AF080” which is the opcode of the JUMP instruction. Pass through update-DR to actually write the Instruction Latch.

2. Select shift-DR. Shift in the “Write PDB-GO-TO with GO and EX”. Pass through update-DR.

3. Select shift-DR. Shift in the 16 bit of “$xxxx”. Pass through update-DR to actually write the PDB. At this time the ODEC releases the chip from Debug mode and the execution is started from the address $xxxx.

Note: If the Debug mode is entered during a DO LOOP, REP instruction, or other special cases such as interrupt processing, STOP, WAIT, or conditional branching, the user must first reset the DSP56300 and before proceeding with the execution of the new program.

10.13 EXAMPLES OF JTAG AND OnCE INTERACTION

This subsection lists the details of the JTAG port/OnCE module interaction and TMS sequencing required in order to achieve the communication described in Examples of Using the OnCE on page 10-24.

The external command controller can force the DSP56300 into Debug mode by executing the JTAG instruction DEBUG_REQUEST. In order to check that the DSP56300 has entered the Debug mode, the external command controller must poll the status by reading the OS[1:0] bits in the JTAG instruction shift register.

After executing the JTAG instructions DEBUG_REQUEST and ENABLE_ONCE and after the core status was polled to verify that the chip is in Debug mode, the pipeline saving procedure must take place. The TMS sequencing for this procedure is depicted in Table 10-12.

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The sequencing of enabling the OnCE module is described in Table 10-13.

In “step n” the external command controller verifies that the OS[1:0] bits have the value 11, indicating that the chip has entered the Debug mode. If the chip has not yet entered the Debug mode, the external command controller goes to “step b”, “step c” etc. until the Debug mode is acknowledged.

Table 10-12 TMS Sequencing for DEBUG_REQUEST

Step TMS JTAG Port OnCE Module Note

a 0 Run-Test/Idle Idle

b 1 Select-DR-Scan Idle

c 1 Select-IR-Scan Idle

d 0 Capture-IR Idle The status is sampled in the shifter.

e 0 Shift-IR Idle The four bits of the JTAG DEBUG_REQUEST (0111) are

shifted in while status is shifted out.

..................................................................

e 0 Shift-IR Idle

f 1 Exit1-IR Idle

g 1 Update-IR Idle The debug request is generated.

h 1 Select-DR-Scan Idle

i 1 Select-IR-Scan Idle

j 0 Capture-IR Idle The status is sampled in the shifter.

k 0 Shift-IR Idle The four bits of the JTAG DEBUG_REQUEST (0111) are

shifted in while status is shifted out

..................................................................

k 0 Shift-IR Idle

l 1 Exit1-IR Idle

m 1 Update-IR Idle

n 0 Run-Test/Idle Idle This step is repeated, enabling an external command controller to

poll the status. ................................................

n 0 Run-Test/Idle Idle

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Table 10-13 TMS Sequencing for ENABLE_ONCE


a 1 Test-Logic-Reset Idle

b 0 Run-Test/Idle Idle

c 1 Select-DR-Scan Idle

d 1 Select-IR-Scan Idle

e 0 Capture-IR Idle The core status bits are captured.

f 0 Shift-IR Idle The four bits of the JTAG ENABLE_ONCE instruction

(0110) are shifted into the JTAG instruction register while status is

shifted out.

g 0 Shift-IR Idle

h 0 Shift-IR Idle

i 0 Shift-IR Idle

j 1 Exit1-IR Idle

k 1 Update-IR Idle The OnCE module is enabled.

l 0 Run-Test/Idle Idle This step can be repeated, enabling an external command

controller to poll the status. ................................................

l 0 Run-Test/Idle Idle

Table 10-14 TMS Sequencing for Reading Pipeline Registers


a 0 Run-Test/Idle Idle

b 1 Select-DR-Scan Idle

c 0 Capture-DR Idle

d 0 Shift-DR Idle The eight bits of the OnCE command “Read PIL”

(10001011) are shifted in. ..................................................................

d 0 Shift-DR Idle

e 1 Exit1-DR Idle

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f 1 Update-DR Execute “Read PIL” The PIL value is loaded in the shifter.

g 1 Select-DR-Scan Idle

h 0 Capture-DR Idle

i 0 Shift-DR Idle The 24 bits of the PIL are shifted out (24 steps).

..................................................................

i 0 Shift-DR Idle

j 1 Exit1-DR Idle

k 1 Update-DR Idle

l 1 Select-DR-Scan Idle

m 0 Capture-DR Idle

n 0 Shift-DR Idle The eight bits of the OnCE command “Read PDB”

(10001010) are shifted in. ..................................................................

n 0 Shift-DR Idle

o 1 Exit1-DR Idle

p 1 Update-DR Execute “Read PDB” PDB value is loaded in shifter

q 1 Select-DR-Scan Idle

r 0 Capture-DR Idle

s 0 Shift-DR Idle The 24 bits of the PDB are shifted out (24 steps).

..................................................................

s 0 Shift-DR Idle

t 1 Exit1-DR Idle

u 1 Update-DR Idle

Table 10-14 TMS Sequencing for Reading Pipeline Registers (Continued)


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During “step v” the external command controller stores the pipeline information and afterwards it can proceed with the debug activities as requested by the user.

v 0 Run-Test/Idle Idle This step can be repeated, enabling an external

command controller to analyze the information.

................................................

v 0 Run-Test/Idle Idle

Table 10-14 TMS Sequencing for Reading Pipeline Registers (Continued)


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SECTION 11

JTAG PORT

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JTAG Port

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-311.2 JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-511.3 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-611.4 DSP56300 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12

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JTAG Port

Introduction


11.1 INTRODUCTION

The DSP56300 core provides a dedicated user-accessible Test Access Port (TAP) that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high density circuit boards have led to development of this proposed standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The DSP56300 core implementation supports circuit-board test strategies based on this standard.

The test logic includes a TAP that consists of five dedicated signal signals, a 16-state controller, and three test data registers. A Boundary Scan Register (BSR) links all device signal signals into a single shift register. The test logic, implemented with static logic design, is independent of the device system logic. The DSP56300 core implementation provides the following capabilities:

• Perform boundary scan operations to test circuit-board electrical continuity (EXTEST).

• Bypass the DSP56300 core for a given circuit-board test by effectively reducing the BSR to a single cell (BYPASS).

• Sample the DSP56300 core-based device system signals during operation and transparently shift out the result in the BSR. Preload values to output signals prior to invoking the EXTEST instruction (SAMPLE/PRELOAD).

• Disable the output drive to signals during circuit-board testing (HI-Z).

• Provide a means of accessing the On-Chip Emulation (OnCE) controller and circuits to control a target system (ENABLE_ONCE).

• Provide a means of entering the Debug Mode of operation (DEBUG_REQUEST).

• Query identification information (manufacturer, part number and version) from a DSP56300 core-based device (IDCODE).

• Force test data onto the outputs of a DSP56300 core-based device while replacing its Boundary Scan Register in the serial data path with a single bit register (CLAMP).

This section, which includes aspects of the JTAG implementation specific to the DSP56300 core, is intended to be used with the supporting IEEE 1149.1 document. The discussion includes those items required by the standard to be defined and, in certain cases, provides additional information specific to the DSP56300 core implementation. For internal details and applications of the standard, refer to the IEEE 1149.1 document. Figure 11-1 shows a block diagram of the TAP port.

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JTAG Port

Introduction

Figure 11-1 TAP Block Diagram

Boundary Scan Register

Bypass

MU

X

4-Bit Instruction Register

TDO

TAPCtrl

TDI

TMS

TCK

023 1

OnCE Logic

ID Register

TRST

Decoder

MU

X

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JTAG Port

JTAG Signals


11.2 JTAG SIGNALS

As described in the IEEE 1149.1 document, the JTAG port requires a minimum of four signals to support TDI, TDO, TCK, and TMS signals. The DSP56300 family also provides the optional TRST signal. On the DSP56305, the Debug Event (DE) signal is provided for use by the OnCE module; it is described in Section 10, On-Chip Emulation Module. The signal functions are described in the following paragraphs.

11.2.1 Test Clock (TCK)

The Test Clock Input (TCK) Signal is used to synchronize the test logic.

11.2.2 Test Mode Select (TMS)

The Test Mode Select Input (TMS) Signal is used to sequence the test controller’s state machine. The TMS is sampled on the rising edge of TCK and it has an internal pullup resistor.

11.2.3 Test Data Input (TDI)

Serial test instruction and data are received through the Test Data Input (TDI) Signal. TDI is sampled on the rising edge of TCK and it has an internal pullup resistor.

11.2.4 Test Data Output (TDO)

The Test Data Output (TDO) Signal is the serial output for test instructions and data. TDO is tri-stateable and is actively driven in the Shift-IR and Shift-DR controller states. TDO changes on the falling edge of TCK.

11.2.5 Test Reset (TRST )

The Test Reset Input (TRST) Signal is used to asynchronously initialize the test controller. The TRST signal has an internal pullup resistor.

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JTAG Port

TAP Controller

11.3 TAP CONTROLLER

The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal. It is a synchronous state machine that controls the operation of the JTAG logic. The state machine is shown in Figure 11-2. The TAP controller responds to changes at the TMS and TCK signals. Transitions from one state to another occur on the rising edge of TCK. The value shown adjacent to each state transition represents the value of the TMS signal sampled on the rising edge of TCK signal. For a description of the TAP controller states, please refer to the IEEE 1149.1 document.

Figure 11-2 TAP Controller State Machine

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Test-Logic-Reset

Run-Test/Idle

Update-DR

1

0

0

1

0

1

1

0

1

1

0

0

1 0

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

0

0

1

0

1

1

0

1

1

0

0

1 0

01

0

1 1

AA0114

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JTAG Port

TAP Controller


11.3.1 Boundary Scan Register

The Boundary Scan Register (BSR) in the DSP56305 JTAG implementation contains bits for all device signal and clock signals and associated control signals. All DSP56305 bidirectional signals have a single register bit in the BSR for signal data, and are controlled by an associated control bit in the BSR. The DSP56305 BSR bit definitions are described in Table 11-2.

11.3.2 Instruction Register

The DSP56305 JTAG implementation includes the three mandatory public instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS), and also supports the optional CLAMP instruction defined by IEEE 1149.1. The HI-Z public instruction provides the capability for disabling all device output drivers. The ENABLE_ONCE public instruction enables the JTAG port to communicate with the OnCE circuitry. The DEBUG_REQUEST public instruction enables the JTAG port to force the DSP56300 core into the Debug mode of operation. The DSP56300 core includes a 4-bit instruction register without parity consisting of a shift register with four parallel outputs. Data is transferred from the shift register to the parallel outputs during the Update-IR controller state. Figure 11-3 shows the JTAG Instruction Register.

The four bits are used to decode the eight unique instructions shown in Table 11-1. All other encodings are reserved for future enhancements and are decoded as BYPASS.

Figure 11-3 JTAG Instruction Register

JTAG InstructionRegister (IR) B3 B2 B1 B0

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JTAG Port

TAP Controller

The parallel output of the instruction register is reset to 0010 in the Test-Logic-Reset controller state, which is equivalent to the IDCODE instruction.

During the Capture-IR controller state, the parallel inputs to the instruction shift register are loaded with 01 in the Least Significant Bits as required by the standard. The two Most Significant Bits are loaded with the values of the core status bits OS1 and OS0 from the OnCE controller. See Section 10, On-Chip Emulation Module, for a description of the status bits.

Table 11-1 JTAG Instructions

CodeInstruction

B3 B2 B1 B0

0 0 0 0 EXTEST

0 0 0 1 SAMPLE/PRELOAD

0 0 1 0 IDCODE

0 0 1 1 CLAMP

0 1 0 0 HI-Z

0 1 0 1 RESERVED

0 1 1 0 ENABLE_ONCE

0 1 1 1 DEBUG_REQUEST

1 0 x x RESERVED

1 1 0 x RESERVED

1 1 1 0 RESERVED

1 1 1 1 BYPASS

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JTAG Port

TAP Controller


11.3.2.1 EXTEST (B[3:0] = 0000)The external test (EXTEST) instruction selects the BSR. EXTEST also asserts internal reset for the DSP56300 core system logic to force a predictable internal state while performing external boundary scan operations.

By using the TAP, the BSR is capable of the following:

• Scanning user-defined values into the output buffers

• Capturing values presented to input signals

• Controlling the direction of bidirectional signals

• Controlling the output drive of tri-statable output signals

For more details on the function and use of the EXTEST instruction, please refer to the IEEE 1149.1 document.

11.3.2.2 SAMPLE/PRELOAD (B[3:0] = 0001)The SAMPLE/PRELOAD instruction provides two separate functions. First, it provides a means to obtain a snapshot of system data and control signals. The snapshot occurs on the rising edge of TCK in the Capture-DR controller state. The data can be observed by shifting it transparently through the BSR.

Note: Since there is no internal synchronization between the JTAG clock (TCK) and the system clock (CLK), the user must provide some form of external synchronization to achieve meaningful results.

The second function of the SAMPLE/PRELOAD instruction is to initialize the BSR output cells prior to selection of EXTEST. This initialization ensures that known data appears on the outputs when entering the EXTEST instruction.

11.3.2.3 IDCODE (B[3:0] = 0010)The IDCODE instruction selects the ID register. This instruction is provided as a public instruction to allow the manufacturer, part number, and version of a component to be determined through the TAP. Figure 11-4 shows the ID register configuration.

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JTAG Port

TAP Controller

One application of the ID register is to distinguish the manufacturer(s) of components on a board when multiple sourcing is used. As more components emerge which conform to the IEEE 1149.1 standard, it is desirable to allow for a system diagnostic controller unit to blindly interrogate a board design in order to determine the type of each component in each location. This information is also available for factory process monitoring and for failure mode analysis of assembled boards.

Motorola’s Manufacturer Identity is 00000001110. The Customer Part Number consists of two parts: Motorola Design Center Number (bits 27:22) and a sequence number (bits 21:12). The sequence number is divided into two parts: Core Number (bits 21:17) and Chip Derivative Number (bits 16:12). Motorola Semiconductor IsraeL (MSIL) Design Center Number is 000110 and DSP56300 core number is 00001. For the DSP56305, the chip derivative number is 00011.

Once the IDCODE instruction is decoded, it selects the ID register, which is a 32-bit data register. The Bypass register loads a logic 0 at the start of a scan cycle, whereas the ID register loads a logic 1 into its Least Significant Bit; thus, examination of the first bit of data shifted out of a component during a test data scan sequence immediately following exit from Test-Logic-Reset controller state shows whether such a register is included in the design. When the IDCODE instruction is selected, the operation of the test logic has no effect on the operation of the on-chip system logic as required by the IEEE 1149.1 standard.

11.3.2.4 CLAMP (B[3:0] = 0011)The CLAMP instruction is not included in the IEEE 1149.1 standard. It is provided as a public instruction that selects the 1-bit Bypass register as the serial path between TDI and TDO while allowing signals driven from the component signals to be determined from the BSR. During testing of ICs on PCB, it may be necessary to place static guarding values on signals that control operation of logic not involved in the test. The EXTEST instruction could be used for this purpose, but since it selects the Boundary Scan

Figure 11-4 JTAG ID Register

011112272831

0 0 0 0 10 0 0 0 0 0 0 1 1 1 0

Design CoreNumber

ChipDerivativeNumber

2122 1617

0 0 0 0 0 0 0 0 1 1 0

CenterNumber

0 0 0 1 1

ManufacturerIdentity

VersionInformation

Customer Part Number 1

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JTAG Port

TAP Controller


Register, the required guarding signals would be loaded as part of the complete serial data stream shifted in, both at the start of the test and each time a new test pattern is entered. Since the CLAMP instruction allows guarding values to be applied using the Boundary Scan Register of the appropriate ICs while selecting their Bypass registers, it allows much faster testing than does the EXTEST instruction. Data in the boundary scan cell remains unchanged until a new instruction is shifted in or the JTAG state machine is set to its reset state. The CLAMP instruction also asserts internal reset for the DSP56300 core system logic to force a predictable internal state while performing external boundary scan operations.

11.3.2.5 HI-Z (B[3:0] = 0100)The HI-Z instruction is not included in the IEEE 1149.1 standard. It is provided as a manufacturer’s optional public instruction to prevent having to backdrive the output signals during circuit-board testing. When HI-Z is invoked, all output drivers, including the two-state drivers, are turned off (i.e., high impedance). The instruction selects the Bypass register. The HI-Z instruction also asserts internal reset for the DSP56300 core system logic to force a predictable internal state while performing external boundary scan operations

11.3.2.6 ENABLE_ONCE(B[3:0] = 0110)The ENABLE_ONCE instruction is not included in the IEEE 1149.1 standard. It is provided as a public instruction to allow the user to perform system debug functions. When the ENABLE_ONCE instruction is decoded the TDI and TDO signals are connected directly to the OnCE registers. The particular OnCE register connected between TDI and TDO at a given time is selected by the OnCE controller depending on the OnCE instruction currently being executed. All communication with the OnCE controller is done through the Select-DR-Scan path of the JTAG TAP Controller. See Section 10, On-Chip Emulation (OnCE), for more information.

11.3.2.7 DEBUG_REQUEST(B[3:0] = 0111)The DEBUG_REQUEST instruction is not included in the IEEE 1149.1 standard. It is provided as a public instruction to allow the user to generate a debug request signal to the DSP56300 core. When the DEBUG_REQUEST instruction is decoded, the TDI and TDO signals are connected to the Instruction Registers. Due to the fact that in the Capture-IR state of the TAP the OnCE status bits are captured in the Instruction shift register, the external JTAG controller must continue to shift-in the DEBUG_REQUEST instruction while polling the status bits that are shifted-out until the Debug mode of operation is entered (acknowledged by the combination 11 on OS1–OS0). After acknowledgment of the Debug mode is received, the external JTAG controller must issue the ENABLE_ONCE instruction to allow the user to perform system debug functions.

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JTAG Port

DSP56300 Restrictions

11.3.2.8 BYPASS (B[3:0] = 1111)The BYPASS instruction selects the single-bit Bypass register, as shown in Figure 11-5. This creates a shift-register path from TDI to the Bypass register, and finally to TDO, circumventing the BSR. This instruction is used to enhance test efficiency when a component other than the DSP56300 core-based device becomes the device under test. When the Bypass register is selected by the current instruction, the shift-register stage is set to a logic 0 on the rising edge of TCK in the Capture-DR controller state. Therefore, the first bit shifted out after selecting the Bypass register is always a logic 0.

11.4 DSP56300 RESTRICTIONS

The control afforded by the output enable signals using the BSR and the EXTEST instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. The user must avoid situations in which the DSP56300 core output drivers are enabled into actively driven networks. In addition, the EXTEST instruction can be performed only after power-up or regular hardware reset while EXTAL was provided. Then during the execution of EXTEST, EXTAL can remain inactive.

There are two constraints related to the JTAG interface. First, the TCK input does not include an internal pullup resistor and should not be left unconnected. The second constraint is to ensure that the JTAG test logic is kept transparent to the system logic by forcing the TAP into the Test-Logic-Reset controller state, using either of two methods. During power-up, TRST must be externally asserted to force the TAP controller into this state. After power-up is concluded, TMS must be sampled as a logic 1 for five consecutive TCK rising edges. If TMS either remains unconnected or is connected to VCC, then the TAP controller cannot leave the Test-Logic-Reset state, regardless of the state of TCK.

Figure 11-5 Bypass Register

1

1Mux

G1

CD

To TDOFrom TDI

0

Shift DR

CLOCKDR AA0115

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JTAG Port

DSP56305 Boundary Scan Register


The DSP56300 core features a low-power Stop mode, which is invoked using the STOP instruction. The interaction of the JTAG interface with low-power Stop mode is as follows:

1. The TAP controller must be in the Test-Logic-Reset state to either enter or remain in the low-power Stop mode. Leaving the TAP controller Test-Logic-Reset state negates the ability to achieve low-power, but does not otherwise affect device functionality.

2. The TCK input is not blocked in low-power Stop mode. To consume minimal power, the TCK input should be externally connected to VCC or GND.

3. The TMS and TDI signals include on-chip pullup resistors. In low-power Stop mode, these two signals should remain either unconnected or connected to VCC to achieve minimal power consumption.

Since during Stop mode all DSP56305 core clocks are disabled, the JTAG interface provides the means of polling the device status (sampled in the Capture-IR state).

11.5 DSP56305 BOUNDARY SCAN REGISTER

Table 11-2 describes the DSP56305 Boundary Scan Register (BSR) contents.

Table 11-2 DSP56305 Boundary Scan Register (BSR) Bit Definitions

Bit # Pin Name Pin Type BSR Cell Type

0 IRQA Input Data

1 IRQB Input Data

2 IRQC Input Data

3 IRQD Input Data

4 D23 Input/Output Data






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JTAG Port





13 D[23:13] — Control













26 D[12:0] — Control




30 A17 Tri-State Data



33 A[17:9] — Control

Table 11-2 DSP56305 Boundary Scan Register (BSR) Bit Definitions (Continued)


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JTAG Port












43 A[8:0] — Control







50 BG Input Data

51 AA0 Tri-State Data


53 RD Tri-State Data

54 WR Tri-State Data

55 AA0 — Control

56 AA1 — Control

57 BB — Control



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JTAG Port


58 BB Input/Output Data

59 BR Output Data

60 TA Input Data

61 BCLK Tri-State Data

62 BCLK Tri-State Data

63 CLKOUT Output Data

64 RD, WR, BCLK,

BCLK, BS

— Control

65 CAS — Control

66 AA2 — Control

67 AA3 — Control

68 EXTAL Input Data

69 CAS Tri-State Data



72 RES Input Data

73 HAD0 — Control

74 HAD0 Input/Output Data

75 HAD1 — Control


77 HAD2 — Control


79 HAD3 — Control




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JTAG Port



81 HAD4 — Control


83 HAD5 — Control


85 HAD6 — Control


87 HAD7 — Control


89 HAS/A0 — Control

90 HAS/A0 Input/Output Data

91 HA8/A1 — Control

92 HA8/A1 Input/Output Data

93 HA9/A2 — Control

94 HA9/A2 Input/Output Data

95 HCS/A10 — Control

96 HCS/A10 Input/Output Data

97 TIO0 — Control

98 TIO0 Input/Output Data

99 TIO1 — Control


101 TIO2 — Control


103 HREQ/TRQ

— Control



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JTAG Port


104 HREQ/TRQ

Input/Output Data

105 HACK/RRQ

— Control

106 HACK/RRQ

Input/Output Data

107 HRW/RD — Control

108 HRW/RD Input/Output Data

109 HDS/WR — Control

110 HDS/WR Input/Output Data

111 SCK0 — Control

112 SCK0 Input/Output Data

113 SCK1 — Control

114 SCK1 Input/Output Data

115 SCLK — Control

116 SCLK Input/Output Data

117 TXD — Control

118 TXD Input/Output Data

119 RXD — Control

120 RXD Input/Output Data

121 SC00 — Control

122 SC00 Input/Output Data



125 STD0 — Control



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JTAG Port



126 STD0 Input/Output Data

127 SRD0 — Control

128 SRD0 Input/Output Data

129 PINIT Input Data

130 DE — Control

131 DE Input/Output Data





136 STD1 — Control

137 STD1 Input/Output Data

138 SRD1 — Control

139 SRD1 Input/Output Data







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JTAG Port


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Filter Co-Processor


SECTION 12

FILTER CO-PROCESSOR

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Filter Co-Processor

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-312.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-412.3 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-412.4 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-612.5 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1412.6 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-40

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Filter Co-Processor

Introduction


12.1 INTRODUCTION

The Filter Co-Processor (FCOP) is a peripheral module designed as a general purpose fully programmable complex FIR filter, with up to 21 complex taps.

It also has dedicated modes of operation optimized for cellular Global System for Mobile Communications (GSM) base station applications, taking advantage of the special GMSK modulation scheme used in GSM.

12.1.1 FCOP Support for GSM

The FCOP assists the DSP56300 core to perform channel equalization of one radio carrier in a GSM base station, which involves both correlation and matched filtering. A matched filter is commonly used in channel equalization to maximize the Signal-to-Noise Ratio (SNR) at sampling time. In the base station receiver path (uplink), FCOP performs cross correlation between the received training sequence and a known mid-amble sequence. The result of this correlation is used to determine the impulse channel response, which is then used to calculate the coefficients for match filtering on the received data symbols (bits).

The FCOP simplifies computation of the cross correlation and match filter outputs fed into the Maximum Likelihood Sequential Estimation (MLSE) process performed by the Viterbi Co-Processor (VCOP). In GSM, while the MLSE algorithm uses the Ungerboeck scheme, the match filter output can be represented by a sequence of ordered pairs (x, y) such that x, y are real numbers.

The main features of FCOP supporting GSM are as follows:

• Special optimized mode (Mode 3) for performing cross correlation between the received training sequence and a pre-defined mid-amble

• Special optimized mode (Mode 2) for performing matched filtering required for channel equalization using the Ungerboeck scheme

• Internal data and coefficient memory banks supports GSM normal burst, as well as GSM access burst.

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Filter Co-Processor

Features

12.2 FEATURES

• Fully programmable complex FIR filter with 16-bit resolution

• Operates concurrently with the core processor and requires minimal CPU intervention

• Independent internal 84 × 16-bit data memory bank and 42 × 16-bit coefficient memory bank

• Four modes of operation with optimized performance

– Mode 0—Real FIR machine with up to 42 real taps

– Mode 1—Complex FIR machine with up to 21 complex taps

– Mode 2—Complex FIR machine generating pure real and imaginary outputs alternately. In GSM, used for performing match filtering

– Mode 3—Complex correlation of a complex data sequence with a pure real and imaginary sequence. In GSM, used for performing cross correlation between the received training sequence and a pre-defined mid-amble

• Two options for filter output decimation available in each operation mode, without loss of performance

– No decimation

– Decimation by 2

• I/O data transfers via core or DMA for minimal core involvement

• Four-word deep input data buffer (24-bit word) for maximal performance

12.3 BLOCK DESCRIPTION

The FCOP comprises the following main functional blocks: PMB Interface — includes the Data Input Buffer, Coefficients Input Buffer, Output Buffer, and Filter Counter (FCNT)—, FCOP Data Memory Bank (FDM), FCOP Coefficients Memory Bank (FCM), FCOP MAC machine (FMAC), Address Generator, and Control Logic.

The block diagram is presented in Figure 12-1.

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Filter Co-Processor

Block Description


12.3.1 Peripheral Module Bus (PMB) Interface

The Peripheral Module Bus (PMB) interface block provides the control and status registers, buffers the internal bus from the coprocessor, decodes addresses, and generates and controls the handshake signals required for DMA and interrupt operations. The block generates the interrupt and DMA trigger signals, whenever data transfer is required.

The control and status registers in the PMB are described in detail in the programming model (see Section 12.4). The interface registers are accessible to the DSP56300 core through the PMB.

Figure 12-1 Filter Co-Processor Block Diagram

Filter Count

AddressGenerator

Control

4-Word 1-Word Coefficient

DataMemory Bank

84 × 16-bit

CoefficientsMemory Bank

42 × 16-bit

FMAC16 × 16 → 40-bit

Output Buffer

Rounding & Limiting

DMA BUS

GDB BUSPMB

Interface

Logic

Data Input Buffer Input BufferFDIR

FDM FCM

FCIR

FDOR

FCNT

AA1118

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Filter Co-Processor

Programming Model

12.3.2 FCOP Memory Banks

The FCOP contains two memory banks: the FCOP Data Memory bank (FDM) and the FCOP Coefficients Memory bank (FCM).

• FCOP Data Memory bank (FDM):84-word 16-bit wide memory, used to store data samples for filter processing by the FCOP. It is written via a 4-word FIFO (FDIR) and its addressing is generated by the FCOP Address Generation logic. The data samples are sequentially read from FDM into the MAC for filter processing. The FDM can be written by both the core and DMA.

• FCOP Coefficients Memory Bank (FCM):42-word 16-bit wide memory, used to store filter coefficients for filter processing by the FCOP. It is written via an input buffer (FCIR) and its addressing is generated by the FCOP Address Generation logic. The filter samples are sequentially read from FDM into the MAC for filter processing. The FCM can only be written by the core.

12.3.3 Multiplier and Accumulator (FMAC)

The FCOP Multiplier and Accumulator (FMAC) machine is capable of performing a 16-bit × 16-bit multiplication with accumulation in a 40-bit accumulator. The FMAC operates in a pipeline fashion, with the multiplication performed in one clock cycle and the accumulation in the following clock cycle. The throughput is one MAC result per clock cycle. The two MAC operands are read from the FDM and the FCM. The full 40-bit width of the accumulator is used for intermediate results during the filter calculations. After all the filter taps have been processed, the result is rounded to the nearest even and limited to the greatest (most positive) number ($7FFF) if overflow occurred or to the least (most negative) number ($8000) if underflow occurred. The rounding and limiting operations take two additional clock cycles after the filter processing is completed. The 16-bit result from FMAC is stored in the FDOR to be read by the DSP56300 core.


The programming model discusses the FCOP registers available to the programmer, and interrupts and DMA access.

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Filter Co-Processor

Programming Model


12.4.1 FCOP Registers

The FCOP programmable registers are listed in Table 12-1. The registers are described in detail in the following sections.

Table 12-1 FCOP Programming Model

All FCOP registers are 16 bits wide. They are of three types as listed in Table 12-2.

Base Address

PlusRegister Name Register

Abbreviation

$0 FCOP Data Input Register FDIR

$1 FCOP Data Output Register FDOR

$2 FCOP Coefficients Input Register FCIR

$3 FCOP Filter Count Register FCNT

$4 FCOP Control/Status Register FCSRNote: The base address is found in the ioequ.asm file, in Appendix B. It is $FFFFB0.

Table 12-2 3 Types of 16-Bit FCOP Registers

Data source • FCOP Data Output Register (FDOR)

Data destination • FCOP Data Input Register (FDIR)• FCOP Coefficients Input Register (FCIR)

Non-data • FCOP Filter Count Register (FCNT)• FCOP Control Status Register (FCSR)

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Filter Co-Processor

Programming Model

Reads and writes of data and non-data are treated differently, as detailed below in Table 12-3.

12.4.2 FCOP Data Input Register (FDIR)

The FCOP Data Input Register (FDIR) is a 4-word deep 16-bit wide FIFO used for DSP-to-FCOP data transfers. Up to four data samples can be written into FDIR using the same address. Data from FDIR is transferred to the FCOP Data Memory bank (FDM) for filter processing. For proper operation, data should be written to FDIR only if the FDIBE status bit is set, indicating that the FIFO is empty. Writing to FDIR clears FDIBE. The user may use interrupt requests or DMA requests to trigger the DSP56300 core for data transfers. FDIR can be written by the DSP56300 core and DMA. FDIR is also referred to as the FCOP Data Input Buffer.

12.4.3 FCOP Data Output Register (FDOR)

The FCOP Data Output Register (FDOR) is a 16-bit wide, read-only register used for FCOP-to-DSP data transfers. Data is transferred from the FMAC to FDOR after processing of all filter taps is completed for a specific set of input samples, that is, after filter processing has been completed. For proper operation, data should be read from FDOR only if the FDOBF status bit is set, indicating that FDOR contains data. The user may use interrupt or DMA requests to trigger the DSP56300 core for data transfers. FDOR can be read by the DSP56300 core and DMA. FDOR is also referred to as the FCOP Data Output Buffer.

Table 12-3 FCOP Register Read/Write Handling

Data Transfers

• When a data source (FDOR) is read to a 24-bit destination (bus, register, memory, etc.), the 16-bit data value occupies the 16 Most Significant Bits (MSBs) of the 24-bit destination and the 8 Least Significant Bits (LSBs) are zeroed.

• When a 24-bit source (bus, register, memory, etc.) is written to a data destination (FDIR or FCIR), the 16 MSBs of the 24-bit source will be written to the 16-bit destination.

Non-Data Transfers

• When a non-data register (FCNT or FCSR) is read to a 24-bit destination (bus, register, memory, etc.), the 16-bit value will be zero extended to a 24-bit value.

• When a 24-bit source (bus, register, memory, etc.) is written to a non-data register, the 8 MSBs must be written with zero for future compatibility.

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12.4.4 FCOP Coefficients Input Register (FCIR)

The FCOP Coefficients Input Register (FCIR) is a 16-bit write-only register used for DSP-to-FCOP coefficients transfers. The filter coefficients are written to FCIR and transferred to the FCOP Coefficients Memory bank (FCM) before starting the filter processing. The FCIR can be written by the DSP56300 core.

12.4.5 FCOP Filter Count Register (FCNT)

The FCOP Filter Count Register (FCNT) is a 16-bit read/write register used for setting the filter length (number of filter taps). The actual value written to FCNT register is the number of coefficient values minus one. The number of coefficient values is actually the number of locations used in the FCM. For a real FIR filter, the number of coefficient values is equal to the number of filter taps. For a complex FIR filter, the number of coefficient values is twice the number of filter taps. The number of taps in FCNT is used by the FCOP Address Generation logic to supply the correct addressing to the FDM and FCM memory banks.

The FCOP can only be written to by the core. Write to FCNT before enabling FCOP (by setting FEN). FCNT should be changed only when FCOP is in the FCOP individual reset state (FEN = 0), otherwise improper operation may result. The number stored in FCNT is used by the FCOP Address Generation logic to generate the correct addressing for the FDM and the FCM.

12.4.6 FCOP Control/Status Register (FCSR)

The FCOP Control/Status Register (FCSR) is a 16-bit read/write register used by the DSP56300 core to control the main operation modes and to monitor the status of the module. The FCSR bits are described in the following paragraphs. All FCSR bits are cleared after hardware and software reset.

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Programming Model

Figure 12-2 FCOP Control/Status Register (FCSR)

12.4.6.1 FCOP Enable (FEN)—FCSR Bit 0The FCOP Enable (FEN) read/write control bit, when set, enables FCOP operation. When FEN is cleared, the FCOP is disabled and is in the FCOP individual reset state. In this state, the FCNT contents and the FCSR control bits are unchanged, while the FCSR status bits and internal logic bits are reset to the same state produced by hardware or software reset. The status bits are cleared (for instance FDIBE, FDOIE, FSAT). The rest of the control bits in FCSR and other registers remain unchanged. The internal logic is cleared, hence the data remaining in FDIR, FDOR, and FCIR become meaningless.

12.4.6.2 FCOP Operation Mode (FOM[1:0])—FCSR Bits 4–5The FCOP Operation Mode (FOM[1:0]) read/write control bits select the operation mode. The operation modes are shown in Table 12-4. FOM[1:0] should only be changed when FCOP is in the FCOP individual reset state (FEN = 0), otherwise improper operation may result. FOM[1:0] are cleared by hardware or software reset. For a detailed description of FCOP operation in the various modes, refer to Figure 12.5.

Table 12-4 FCOP Operation Modes

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FDOBF FDIBE FSAT FDOIE FDIIE FDCM FOM1 FOM0 FEN

Reserved unused bit, read as zero, should be written with zero for future compatibility

Reserved bit for internal use (such as testing), must be written with zero for proper operation

AA1119

FOM1 FOM0 Mode Mode Function

0 0 0 Real FIR Filter

0 1 1 Full Complex FIR Filter

1 0 2 Complex FIR filter with alternate Pure Real/Imaginary outputs

1 1 3 Optimized Complex Correlation

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12.4.6.3 FCOP Decimation (FDCM)—FCSR Bit 8The FCOP Decimation (FDCM) read/write control bit determines the decimation function. When FDCM is set, decimation by 2 occurs and when FDCM is cleared, no decimation occurs. No decimation is chosen for non-oversampled data while decimation by 2 is used for 2× oversampled data. FDCM should only be changed when FCOP is in the FCOP individual reset state (FEN = 0), otherwise improper operation may result. FDCM is cleared by hardware or software reset. For more details about the effect of FDCM on the module’s operation, refer to Section 12.5.

12.4.6.4 FCOP Data Input Interrupt Enable (FDIIE)—FCSR Bit 10The FCOP Data Input Interrupt Enable (FDIIE) read/write control bit, when set, enables the Data Input Buffer Empty Interrupt. When FDIIE is cleared, the Data Input Buffer Empty Interrupt is disabled, and the FDIBE status bit should be polled to determine if FDIR is empty. The following table describes the effect of the possible combined states of FDIIE and FDIBE:

Table 12-5 Relationship of FDIIE and FDIBE

DMA transfer is enabled if a DMA channel is activated and allocated for FCOP Data Input Buffer Empty (FDIBE is set). FDIR should be written either by the interrupt routine or the DMA transfer, but not both, so it is highly recommended to enable either the interrupt or DMA, but not both.

FDIIE FDIBE Effect

0 0 Data Input Buffer Empty Interrupt is disabled. FCOP Data Input Register (FDIR) is not empty. Do not write to FDIR.

0 1 Data Input Buffer Empty Interrupt is disabled. FCOP Data Input Register (FDIR) is empty. DMA write to FDIR possible.

1 0 Data Input Buffer Empty Interrupt is enabled. FCOP Data Input Register (FDIR) is not empty. Do not write to FDIR.

1 1 Data Input Buffer Empty Interrupt is enabled. FCOP Data Input Register (FDIR) is empty. FCOP requests a Data Input Buffer Empty Interrupt service from the DSP56300 core. Interrupt write to FDIR is possible.

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12.4.6.5 FCOP Data Output Interrupt Enable (FDOIE)—FCSR Bit 11The FCOP Data Output Interrupt Enable (FDOIE) read/write control bit, when set, enables the Data Output Interrupt. When FDOIE is cleared, the Data Output Interrupt is disabled and the FDOBF status bit should be polled to determine if FDOR is full. The following table describes the effect of the possible combined states of FDOIE and FDOBF:

Table 12-6 Relationship of FDOIE and FDOBF

DMA transfer is enabled if a DMA channel is activated and allocated for FCOP Data Output Buffer Full (FDOBF is set). FDOR should be read by the interrupt routine or by the DMA transfer, but not both; thus it is highly recommended to enable either the interrupt or DMA, but not both.

12.4.6.6 FCOP Data Saturation (FSAT)—FCSR Bit 12The FCOP Data Saturation (FSAT) read-only status bit indicates, when set, that overflow or underflow occurred in the MAC result. FSAT is a sticky status bit, set by hardware and cleared by hardware reset, software reset, or FCOP individual reset. When overflow occurs, the result will be saturated to the most positive number $7FFF. When underflow occurs, the result will be saturated to the most negative number $8000.

FDOIE FDOBF Effect

0 0 Data Output Interrupt is disabled. FCOP Data Output Register (FDOR) is not full. Do not read from FDOR.

0 1 Data Output Interrupt is disabled. FCOP Data Output Register (FDOR) is full. DMA read from FDOR is possible.

1 0 Data Output Interrupt is enabled. FCOP Data Output Register (FDOR) is not full. Do not read from FDOR.

1 1 Data Output Interrupt is enabled. FCOP Data Output Register (FDOR) is full. FCOP requests a Data Output Interrupt service from the DSP56300 core. Interrupt read from FDOR is possible.

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12.4.6.7 FCOP Data Input Buffer Empty (FDIBE)—FCSR Bit 14The FCOP Data Input Buffer Empty (FDIBE) read-only status bit indicates, when set, that the FCOP Data Input Buffer (or Register, FDIR) is empty and the DSP can write data to it. FDIBE is set when all four FDIR locations are empty. For proper operation, data should be written to FDIR only if FDIBE is set. Writing to FDIR clears FDIBE. FDIBE is also cleared by hardware, software, or FCOP individual reset. When FCOP is enabled (by setting FEN), FDIBE is set indicating that FDIR is empty. When FDIBE is set and the interrupt is enabled (FDIIE is also set), FCOP generates a Data Input Buffer Empty Interrupt request to the DSP56300 core. A DMA request is always generated when FDIBE is set, but a DMA transfer only takes place if a DMA channel is activated and allocated for FCOP Data Input Buffer Empty (FDIBE is set).

12.4.6.8 FCOP Data Output Buffer Full (FDOBF)—FCSR Bit 15The FCOP Data Output Buffer Full (FDOBF) read-only status bit indicates, when set, that the Data Output Buffer (FDOR) is full and the DSP can read data from FDOR. FDOBF is set when a result from FMAC is transferred to FDOR. For proper operation, data should be read from FDOR only if FDOBF is set. Reading FDOR clears FDOBF. FDOBF is also cleared by hardware, software, or FCOP individual reset. When FDOBF is set and the interrupt is enabled (FDOIE is also set), FCOP generates a Data Output Buffer Full Interrupt request to the DSP56300 core. A DMA request is always generated when FDOBF is set, but a DMA transfer only takes place if a DMA channel is activated and allocated for FCOP Data Output Buffer Full (FDOBF is set).

12.4.6.9 FCOP Reserved Unused Bits—FCSR Bits 1, 3, 9, 13These bits are reserved and unused. They read as zeroes and should be written with zero for future compatibility.

12.4.6.10 FCOP Reserved Used Bits—FCSR Bits 2, 6, 7These bits are reserved for internal testing and debugging. They must be written with zeroes for proper operation.

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12.4.7 Interrupts and DMA

The FCOP interrupt vector table is listed in Table 12-7.

Table 12-7 FCOP Interrupt Vectors and DMA

12.5 OPERATION MODES

The FCOP operation modes are controlled by the FOM[0:1] bits in the FCSR as described in Section 12.4.6.2. In each mode, the FDCM bit in FCSR selects between no decimation or decimation by two. The following sections describe the operation of FCOP in each mode, either with no decimation or with decimation by two. The description includes: equation of the implemented filter, initialization and processing steps, data and coefficients input scheme, output data scheme.

InterruptAddress

InterruptVector Priority Interrupt

EnableInterrupt

ConditionsDMA

Capability

VBA + Base* + 0 Data Input Register Empty

highest FDIIE FDIBE = 1 Yes

VBA + Base* + 2 Data Output Register Full

lowest FDOIE FDOBF = 1 Yes

Note: The base address is found in intequ.asm, in Appendix A. It is $78.

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12.5.1 Terminology Used in this Section

Note: Some items on this list have two forms, for example D(n), D=R(n). In such cases the D(n) form is used when only real values are present, and the DR(n) form is used when complex values are present.

12.5.2 Input DMA Activation

The DMA for input data transfers can be activated only after enabling FCOP (FEN set) and after the core has initialized the coefficients bank through FCIR. Then, the DMA input channel can be enabled in order to start transferring data whenever there are free locations in the input FIFO, while the FCOP state machine grabs data words from that FIFO whenever required.The FCOP state machine starts computation as soon as both coefficient and data banks complete the initialization phase (according to #filter_count value).

A good practice is to program the input data DMA channel for single word transfer or line of 2, 3, or 4 word transfer (since the input buffer FIFO depth is 4), triggered by the FDIBE bit in FCSR.

Compute Perform all calculations to determine one filter output F(n) for a specific set of input data samples.

Get Write a data word to the FCOP Data Memory buffer (FDM) via FDIR.

D(n), DR(n): Real data sample number n.

DI(n) Imaginary data sample number n.

H(n), HR(n) Real filter coefficient number n.

HI(n) Imaginary filter coefficient number n.

F(n), FR(n) Real output result number n.

FI(n) Imaginary output result number n.

#filter_count Number of coefficient values in the FCOP coefficients Memory bank FCM (equals contents of FCNT register plus 1).

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12.5.3 Output DMA Activation

The DMA for output data transfers should be programmed for single word transfers triggered by the FDOBF bit. The DMA can be activated at any time (even before the FCOP is enabled).

12.5.4 Decimation by 2

FIR decimation by 2 is performed on input, when the FDCM bit is set. When FCOP decimates input, it waits until it gets two input data items (depending on the mode, the data may be real or complex) in FDM and then performs the FIR calculation on the second input data items only. This is equivalent to performing the full FIR filter but reading only every second FIR result, thus saving half the calculations.

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12.5.5 FCOP Mode 0: Real FIR Filter

Mode 0 is selected when FOM[1:0] = 00. In this mode, calculation of filter outputs considers data and coefficient words as real numbers.

12.5.5.1 Mode 0 (Real FIR Filter), No Decimation

The following equation is implemented:

Set Up • Load Filter Count Register (FCNT) with (number of coefficient values – 1)

• Choose operation mode (FOM[1:0], FDCM=0) and enable FCOP (FEN = 1)

DSP Initialization

• Core initializes coefficients in FCM in reverse order by executing #filter_count writes to FCIR

• Core or DMA initializes data in FDM in direct order by executing #filter_count writes to FDIR

Processing • Whenever FDIR is empty (FDIBE = 1), FCOP triggers core or DMA to transfer up to four new data words to FDM via FDIR

• Compute F(n) and store result in FDOR• FCOP triggers core or DMA for output data transfer• Get new data word• FCOP increments data memory pointer

F n( ) H i( ) D n i–( )⋅i 0=

N 1–

∑=

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Figure 12-3 Input and Output Stream for Real FIR Filter without Decimation

D(0)

D(1)D(2)D(3)D(4)D(5)——

H(8)

H(7)H(6)H(5)H(4)H(3)—

Data Coefficient

F(0)

F(1)F(2)F(3)F(4)F(5)——

Output Data

MemoryBank

MemoryBank(FCM)(FDM) Stream

AA1122

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12.5.5.2 Mode 0 (Real FIR Filter), Decimation by 2


The set up and initialization steps are the same as in Mode 0 without decimation. Processing is also the same, except 2 ‘get’ operations are required, so that output results are calculated only for even indexes (see below).


• Choose operation mode (FOM[1:0], FDCM=0) and enable FCOP (FEN = 1)

DSP Initialization



Processing • Whenever FDIR is empty (FDIBE = 1), FCOP triggers core or DMA to transfer up to four new data words to FDM via FDIR

• Compute F(n) and store result in FDOR• FCOP triggers core or DMA for output data transfer• Get new data word• FCOP increments data memory pointer• Get new data word• FCOP increments data memory pointer

F neven

( ) H i( ) D n i–( )⋅i 0=

N 1–

∑=

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Figure 12-4 Input and Output Stream for Real FIR Filter with Decimation by 2

D(0)

D(1)D(2)D(3)D(4)D(5)——

H(8)

H(7)H(6)H(5)H(4)H(3)—

Data Coefficient

F(0)

F(2)F(4)F(6)F(8)

F(10)——

Output Data

MemoryBank


AA1123

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12.5.5.3 Mode 0 (Complex FIR Filter Generating Real Outputs Only), Decimation by 2



• Choose operation mode (FOM[1:0], FDCM=0, 0, 1) and enable FCOP (FEN = 1)

DSP Initialization

• Core initializes coefficients in FCM in reverse order, while imaginary coefficients are first negated, by executing #filter_count writes to FCIR


Processing • Whenever FDIR is empty (FDIBE = 1), the FCOP triggers core or the DMA to transfer two or four new data words (one or two complex pairs) to the FDM via FDIR

• Compute F(n) and store result in FDOR• FCOP triggers core or DMA for output data transfer• Get new data word• FCOP increments data memory pointer• Get new data word• FCOP increments data memory pointer

FR n( ) HR i( ) DR n i–( )⋅( ) HI i( ) DI n i–( )⋅( )–i 0=

N 1–

∑=

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Figure 12-5 Input and Output Stream for Complex FIR Filter Generating Real Outputs Only with Decimation by 2

DR(0)

DI(0)DR(1)DI(1)DR(2)DI(2)

——

HR(8)

–HI(8)HR(7)–HI(7)HR(6)–HI(6)

—FR(0)

FR(1)FR(2)FR(3)FR(4)FR(5)

——

Data Coefficient

Output Data

MemoryBank


AA1124

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12.5.6 FCOP Mode 1: Full Complex FIR Filter

Mode 1 is selected when FOM[1:0] = 01. In this mode, for each complex input, a complex output is generated.

12.5.6.1 Mode 1(Full Complex FIR Filter), No Decimation

The following equations are implemented:


• Choose operation mode (FOM[1:0], FDCM = 0, 1, 0) and enable FCOP (FEN = 1)

DSP Initialization




• Compute FR(n) and store result in FDOR• FCOP triggers core or DMA for output data transfer• Compute FI(n) and store result in FDOR• FCOP triggers core or DMA for output data transfer• Get new data word (DR)• FCOP increments data memory pointer• Get new data word (DI)• FCOP increments data memory pointer

FR n( ) HR i( ) DR n i–( )⋅( ) HI i( ) DI n i–( )⋅( )–i 0=

N 1–

∑=

FI n( ) HR i( ) DI n i–( )⋅( ) HI i( ) DR n i–( )⋅( )+i 0=

N 1–

∑=

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Figure 12-6 Input and Output Stream for Full Complex FIR Filter without Decimation

DR(0)


——

HR(8)

HI(8)HR(7)HI(7)HR(6)HI(6)

—FR(0)

FI(0)FR(1)FI(1)FR(2)FI(2)——

Data Coefficient

Output Data

MemoryBank


AA1125

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12.5.6.2 Mode 1 (Full Complex Correlation Filter), No Decimation




DSP Initialization

• Core initializes coefficients in FCM in direct order, while imaginary coefficients are first negated, by executing #filter_count writes to FCIR



• Compute FR(n) and store result in FDOR• FCOP triggers core or DMA for output data transfer• Compute FI(n) and store result in FDOR• FCOP triggers core or DMA for output data transfer• Get new data word (DR)• FCOP increments data memory pointer• Get new data word (DI)• FCOP increments data memory pointer

FR n( ) HR i( ) DR n i+( )⋅( ) HI i( ) DI n i+( )⋅( )+i 0=

N 1–

∑=

FI n( ) HR i( ) DI n i+( )⋅( ) HI i( ) DR n i+( )⋅( )–i 0=

N 1–

∑=

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Figure 12-7 Input and Output Stream for Full Complex Correlation Filter without Decimation

DR(0)


——

HR(0)

–HI(0)HR(1)–HI(1)HR(2)–HI(2)

—FR(0)

FI(0)FR(1)FI(1)FR(2)FI(2)——

Data Coefficient

Output Data

MemoryBank


AA1126

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12.5.6.3 Mode 1 (Full Complex FIR Filter), Decimation by 2




DSP Initialization

• Core initializes coefficients in FCM in reverse order, by executing #filter_count writes to FCIR



• Compute FR(n) and store result in FDOR• FCOP triggers core or DMA for output data transfer• Compute FI(n) and store result in FDOR• FCOP triggers core or DMA for output data transfer• Get new data word (DR)• FCOP increments data memory pointer• Get new data word (DI)• FCOP increments data memory pointer• Get new data word (DR)• FCOP increments data memory pointer• Get new data word (DI)• FCOP increments data memory pointer

FR neven

( ) HR i( ) DR n i–( )⋅( ) HI i( ) DI n i–( )⋅( )–i 0=

N 1–

∑=

FI neven

( ) HR i( ) DI n i–( )⋅( ) HI i( ) DR n i–( )⋅( )+i 0=

N 1–

∑=

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Figure 12-8 Input and Output Stream for Full Complex Filter with Decimation

DR(0)


——

HR(8)


—FR(0)

FI(0)FR(2)FI(2)FR(4)FI(4)——

Data Coefficient

Output Data

MemoryBank


AA1127

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12.5.7 FCOP Mode 2: Full Complex FIR Filter

Mode 2 is selected when FOM[1:0] = 10. Each complex input consists of two filter outputs: the first real, the second imaginary, generated alternately.

12.5.7.1 Mode 2 (Complex FIR Filter Generating Pure Real or Pure Imaginary Outputs Alternately), No Decimation




DSP Initialization




• Compute FR(n) and store result in FDOR• FCOP triggers core or DMA for output data transfer• Get new data word (DR)• FCOP increments data memory pointer• Get new data word (DI)• FCOP increments data memory pointer• Compute FI(n) and store result in FDOR• FCOP triggers core or DMA for output data transfer• Get new data word (DR)• FCOP increments data memory pointer• Get new data word (DI)• FCOP increments data memory pointer

FR neven

( ) HR i( ) DR n i–( )⋅( ) HI i( ) DI n i–( )⋅( )–i 0=

N 1–

∑=

FI nodd

( ) HR i( ) DI n i–( )⋅( ) HI i( ) DR n i–( )⋅( )+i 0=

N 1–

∑=

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Figure 12-9 Input and Output Stream for Complex FIR Filter Generating Pure Real or Pure Imaginary Outputs Alternately without Decimation

DR(0)


——

HR(8)


—FR(0)

FI(1)FR(2)FI(3)FR(4)FI(5)——

Data Coefficient

Output Data

MemoryBank


AA1128

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12.5.7.2 Mode 2 (Complex FIR Filter Generating Pure Real and Pure Imaginary Outputs Alternately), Decimation by 2


FR n0 4 8 etc, , ,( ) HR i( ) DR n i–( )⋅( ) HI i( ) DI n i–( )⋅( )–

i 0=

N 1–

∑=

FI n2 6 10 etc, , ,( ) HR i( ) DI n i–( )⋅( ) HI i( ) DR n i–( )⋅( )+

i 0=

N 1–

∑=

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Operation Modes


• Choose operation mode (FOM[1:0], FDCM = 1, 0, 1) and enable FCOP(FEN = 1)

DSP Initialization




• Compute FR(n) and store result in FDOR• FCOP triggers core or DMA for output data transfer• Get new data word (DR)• FCOP increments data memory pointer• Get new data word (DI)• FCOP increments data memory pointer• Get new data word (DR)• FCOP increments data memory pointer• Get new data word (DI)• FCOP increments data memory pointer• Compute FI(n) and store result in FDOR• FCOP triggers core or DMA for output data transfer• Get new data word (DR)• FCOP increments data memory pointer• Get new data word (DI)• FCOP increments data memory pointer• Get new data word (DR)• FCOP increments data memory pointer• Get new data word (DI)• FCOP increments data memory pointer

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Figure 12-10 Input and Output Stream for Complex FIR Filter Generating Pure Real and Pure Imaginary Outputs Alternately with Decimation by 2

DR(0)


——

HR(8)


—FR(0)

FI(2)FR(4)FI(6)FR(8)FI(10)

——

Data Coefficient

Output Data

MemoryBank


AA1129

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Operation Modes

12.5.8 FCOP Mode 3: Optimized Complex Correlation Function

Mode 3 is selected when FOM[1:0] = 11. Mode 3 is capable of performing complex correlation between a complex data sequence and a pure real/imaginary sequence. In GSM, it is used to correlate between the received training sequence and a known midamble sequence.

The received training sequence can be non-oversampled (one pair of in-phase and quadrature (I&Q) samples per bit), or 2× oversampled (2 pair of I&Q samples per bit). The midamble sequence consists of alternate pure real/pure imaginary values.

The basic correlation function is:

However, since the midamble has zero components, the actual calculations are simpler, as shown in the following sections.

12.5.8.1 Mode 3 (Complex Correlation of Non-Oversampled Data), No Decimation

The received training sequence is complex (one pair of I&Q samples per bit). The midamble sequence consists of alternate pure real/pure imaginary values (one pure complex value per bit). Refer to the following table:

FR n( ) HR i( ) DR n i+( )⋅( ) HI i( ) DI n i+( )⋅( )+i 0=

N 1–

∑=

FI n( ) HR i( ) DI n i+( )⋅( ) HI i( ) DR n i+( )⋅( )–i 0=

N 1–

∑=

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Filter Co-Processor

Operation Modes


Table 12-8 Non-Oversampled Data Sequence

Taking advantage of the “zero” components of the midamble sequence, we get the following equations from the basic correlation equations, so that a complex output is calculated for each complex input, requiring half the MAC operations:

Sample (index) Bit # Received Input

Received Quadrature

Midamble Input

Midamble Quadrature

0 0 DR(0) DI(0) HR(0) 0

1 1 DR(1) DI(1) 0 HI(1)

2 2 DR(2) DI(2) HR(2) 0

3 3 DR(3) DI(3) 0 HI(3)

4 4 DR(4) DI(4) HR(4) 0

5 5 DR(5) DI(5) 0 HI(5)

6 6 DR(6) DI(6) HR(6) 0

7 7 DR(7) DI(7) 0 HI(7)

FR n( ) HR 2i( ) DR n 2i+( )⋅( ) HI 2i 1+( ) DI n 2i 1+ +( )⋅( )+i 0=

N 2⁄ 1–

∑=

FI n( ) HR 2i( ) DI n 2i+( )⋅( ) HI 2i 1+( ) DR n 2i 1+ +( )⋅( )–i 0=

N 2⁄ 1–

∑=

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Filter Co-Processor

Operation Modes

Set Up • Load Filter Count Register (FCNT) with (number of coefficient values – 1).

• Choose operation mode (FOM[1:0], FDCM = 1, 1, 0) and enable FCOP (FEN = 1).

DSP Initialization

• Core initializes coefficients in FCM in direct order by executing #filter_count writes to FCIR.

• Core or DMA initializes data in FDM in direct order by executing #filter_count writes to FDIR.

Processing • Whenever FDIR is empty (FDIBE = 1), the FCOP triggers core or the DMA to transfer two or four new data words (one or two complex pairs) to the FDM via FDIR.

• Compute FR(n) and store result in FDOR.• FCOP triggers core or DMA for output data transfer.• Compute FI(n) and store result in FDOR.• FCOP triggers core or DMA for output data transfer.• Get new data word (DR).• FCOP increments data memory pointer.• Get new data word (DI).• FCOP increments data memory pointer.

Figure 12-11 Input and Output Stream for Complex Correlation of Non-Oversampled Data without Decimation

DR(0)


——

HR(0)


—FR(0)

FI(0)FR(1)FI(1)FR(2)FI(2)——

Data Coefficient

Output Data

MemoryBank


AA1130

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Filter Co-Processor

Operation Modes


12.5.8.2 Mode 3 (Complex Correlation of 2 × Oversampled Data), No Decimation

The received training sequence is 2× oversampled (two pairs of I&Q samples per bit). The midamble sequence consists of alternate pure real/pure imaginary values (one pure complex value per bit). Before correlation, the midamble should be interpolated by 2. Refer to the following table:

Table 12-9 2 × Oversampled Data Sequence

Taking advantage of the “zero” components of the interpolated midamble sequence, we get the following equations from the basic correlation equations:

When n is even, the filter outputs are independent of the odd input samples, and when n is odd, the filter outputs are independent of the even input samples. As a result, even and odd outputs can be calculated separately, requiring half of the data memory bank size.

Sample (index) Bit # Received

InputReceived

QuadratureMidamble

InputMidamble Quadrature

0 0 DR(0) DI(0) HR(0) 0

1 DR(1) DI(1) 0 0

2 1 DR(2) DI(2) 0 HI(2)

3 DR(3) DI(3) 0 0

4 2 DR(4) DI(4) HR(4) 0

5 DR(5) DI(5) 0 0

6 3 DR(6) DI(6) 0 HI(6)

7 DR(7) DI(7) 0 0

FR n( ) HR 4i( ) DR n 4i+( )⋅( ) HI 4i 2+( ) DI n 4i 2+ +( )⋅( )+i 0=

N 4⁄ 1–

∑=

FI n( ) HR 4i( ) DI n 4i+( )⋅( ) HI 4i 2+( ) DR n 4i 2+ +( )⋅( )–i 0=

N 4⁄ 1–

∑=

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Filter Co-Processor

Operation Modes

For calculating the even outputs, the following equations are implemented:



DSP Initialization

• Core initializes coefficients in FCM in direct order by executing #filter_count writes to FCIR.

• Core or DMA initializes data in FDM in direct order by executing #filter_count writes to FDIR.

Processing • Whenever FDIR is empty (FDIBE = 1), the FCOP triggers core or the DMA to transfer two or four new data words (one or two complex pairs) to the FDM via FDIR.

• Compute FR(n) and store result in FDOR.• FCOP triggers core or DMA for output data transfer.• Compute FI(n) and store result in FDOR.• FCOP triggers core or DMA for output data transfer.• Get new data word (DR).• FCOP increments data memory pointer.• Get new data word (DI).• FCOP increments data memory pointer.

FR neven

( ) HR 4i( ) DR n 4i+( )⋅( ) HI 4i 2+( ) DI n 4i 2+ +( )⋅( )+i 0=

N 4⁄ 1–

∑=

FI neven

( ) HR 4i( ) DI n 4i+( )⋅( ) HI 4i 2+( ) DR n 4i 2+ +( )⋅( )–i 0=

N 4⁄ 1–

∑=

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Filter Co-Processor

Operation Modes


Figure 12-12 Input and Output Stream for Complex Correlation of 2× Oversampled Data without Decimation

DR(0)


——

HR(0)

HI(2)HR(4)HI(6)HR(8)HI(10)

—FR(0)

FI(0)FR(2)FI(2)FR(4)FI(4)——

Data Coefficient

Output Data

MemoryBank


AA1131

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Filter Co-Processor

Performance Analysis

12.6 PERFORMANCE ANALYSIS

FCOP cycle count calculations are based on the following expressions. Table 12-10 is a summary of FCOP cycle counts in a GSM base station.

Cycle count for match filter of Non-Oversampled data (Mode 2, FDCM = 0):

Cycle count for match filter of 2x Oversampled data (Mode 2, FDCM = 1):

Cycle count for optimized correlation (Mode 3, FDCM = 0):

Where:

• Fl is the filter length (the number of values in the coefficient memory)

• N is the number of output values generated by FCOP

Table 12-10 FCOP Cycle Count in GSM Base Station

Over-sampled

Data

BurstType

FilterMode

DataLength

FilterLength

(Fl)

No. ofOutputs

(N)

No. ofCycles

Duration@80MHz

No Normal Match Filter 61 x 2 9 x 2 61 1340 16.75 µs

No Normal Correlation 26 x 2 26 52 x 2 3078 38.5 µs

No Access Match Filter 36 x 2 9 x 2 36 840 10.5 µs

No Access Correlation 41 x 2 41 82 x 2 7308 91.5 µs

2 x Normal Match Filter 61 x 2 9 x 2 61 1474 18.5 µs

2 x Normal Correlation 26 x 2 26 52 x 2 3078 38.5 µs

2 x Access Match Filter 36 x 2 9 x 2 36 924 11.6 µs

2 x Access Correlation 41 x 2 41 82 x 2 7308 91.5 µs

2 Fl⋅ 6+( ) 4 Fl⋅( ) N Fl 2+( )⋅+ + N 6+( ) Fl 2+( ) 6–⋅=

2 Fl⋅ 6+( ) 4 Fl⋅( ) N Fl 4+( )⋅+ + N 6+( ) Fl 4+( ) 18–⋅=

2 Fl⋅ 6+( ) 8 Fl⋅( ) N Fl 1+( )⋅+ + N 10+( ) Fl 1+( ) 4–⋅=

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VITERBI CO-PROCESSOR


SECTION 13


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13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-313.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-513.3 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-613.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1013.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1613.6 Chip Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3013.7 Viterbi Butterfly Implementation. . . . . . . . . . . . . . . . . . . . . . . .13-3313.8 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3413.9 Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-37

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Introduction


13.1 INTRODUCTION

The Viterbi Co-Processor (VCOP) is a dedicated, programmable peripheral module, integrated with the DSP56300 core; it is designed to perform convolutional coding and channel equalization algorithms. It operates independently of the core, requiring minimum CPU-time overhead. Although its original design purpose is to support base stations for the Global System for Mobile Communication (GSM) standard, it can support several standard convolutional coding algorithms, based on common 1/n rates or their puncture derivatives, as used by GSM, PCN, and NADC.

The VCOP is designed for a wide range of standard applications requiring the Viterbi algorithm for convolutional coding or channel equalization (in particular maximum likelihood decoding) used for the following applications:

• Maximum Likelihood Sequential Estimation (MLSE) equalizer

• Channel decoder

• Convolutional encoder

In recent years, the Viterbi algorithm has been widely used in several telecommunications areas, such as modems, cellular phone systems, and satellite communications.

13.1.1 VCOP Support for GSM

The channel coding scheme specified by GSM is described in the following block diagram:

The blocks using the VCOP (framed in bold, above) are convolutional encoding, convolutional decoding, and channel equalization. The next section gives an example of using the Viterbi algorithm for channel equalization.

Figure 13-1 Block Diagram of a Typical Data Communication System

InterleavingConvolutionalEncoding

BurstFormatting Ciphering

De-ConvolutionalDecoding

BurstFormatting De-ciphering

ModulatorRF Transmit

RF Receiver& Equalizerinterleaving

Speechor Data

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Introduction

13.1.2 MLSE Equalizer

The equalizer implements the Ungerboeck form of an MLSE-based channel equalizer. Such an equalizer (see Figure 13-2) uses the MLSE algorithm to find the most likely transmitted sequence over a channel with InterSymbol Interference (ISI).

The equalized data is then fed to a convolutional decoder (also implemented using the Viterbi algorithm) that may take advantage of soft decision information for the decoding process, thereby achieving higher Signal-to-Noise Ratio (SNR) values over hard-decision-only convolutional decoders.

Figure 13-2 Ungerboeck Form of MLSE Channel Equalizer

ComputeChannelImpulse

Response

Compute MFCoefficients

Matched

Auto- ComputeL-Metrics MLSE

Hard DecisionEqualized Data

InputData

AA1312

correlation

Filter

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Features


13.2 FEATURES

The following VCOP features support the GSM standard:

• Implements MLSE machine using Viterbi algorithm, for both channel decoding and channel equalization

• Ungerboeck1 metrics for channel equalization

• Manhattan metrics for channel decoding

• Constraint length of 4, 5, 6, or 7 (8, 16, 32 or 64 trellis states)

• Uses fixed trellis depth of 36

• Decision depth greater than five times the greatest constraint length (36)

• Code rates of 1/2, 1/3, 1/4, or 1/6

• Up to 6 polynomial tap registers

• Ability to specify INIT_STATE, END_STATE, INIT_METRIC

• 8-bit (256 level) soft-decision input for channel decoding

• Punctured codes derived from the supported 1/n rate codes

• Hard decision output (16-bits wide) when performing channel decoding and equalization

• Number of bit errors corrected during channel decoding when required

• Window Error Detection function (as required for GSM half-rate code)

• Access to intermediate path metrics for the implementation of differential metric scheme3, and channel parameters adaptations model

___________________________________________

References: The following articles will be cited as reference sources in several sections of this chapter. These references are duplicated as endnotes to this chapter, for the reader’s convenience.

1. Ungerboeck, Gottfried 1974. Adaptive Maximum-Likelihood Receiver for Carrier-Modulated Data-Transmission Systems. IEEE Transactions on Communications vol. COM-22, no. 5:624–636. May 1974.2. Forney, G. David, Jr. 1973. The Viterbi Algorithm. Proceedings of the IEEE, vol. 61 no. 3:268–278. March 1973.3. Koch, Wolfgang, and Baier, Alfred 1990. “Optimum and Sub-optimum Detection of Coded Data Disturbed by Time-varying Intersymbol Interference,” in Communications: Connecting the Future, vol. 3:1679–1684. Global Telecommunications Conference and Exhibition, San Diego, Dec. 2–5, 1990. (IEEE catalog number 90CH2827–4).

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Block Description

13.3 BLOCK DESCRIPTION

The Viterbi Co-Processor is composed of the following main functional blocks: Peripheral Module Bus (PMB) Interface, Flow Control, Branch Metric, Add-Compare-Select (ACS), Window Error Detection (WED), Trellis, Data Control, and Receive Quality Error.

Figure 13-3 VCOP Block Diagram

Addr

Flow Control

Branch Metric

ACS

ReceiveQuality

brma,b

vdr rx

qual

/ en

c-da

ta

PMB Interface

VP

Metric

DELAY

PMB (Peripheral Module Bus)

16H

ard

Dat

a

CLKRESETDMA ACCESS SIGNALSINTERRUPT SIGNALS CORE ACCESS SIGNALS

ConvolutionalEncoder

tap

a,b,

c,d,

e,f

Mod

e

Trellis

Trellis

hard

/ da

ta

Addr

Con

trol

s

stg_endControls

6

surv. bit

Start

star

t

Mode

DM

A r

ead

req

16

WED

WED16 w

ed_v

al

Delay

16

32

Addr

2 × 17

Addr

vcra,vcrb,vtrs,vwes,vber

wed 16

Data Control

63 × 16 bit /Output Buff

1023 × 1 bit

RAMRAM

Con

trol

s

tab_survivor

RAM

RAM

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Block Description


13.3.1 Peripheral Module Bus (PMB) Interface

The Peripheral Module Bus (PMB) Interface block provides control and status registers, buffers the internal bus, decodes addresses, and generates and controls handshake signals required for DMA and interrupt operations. This block also generates interrupt and DMA trigger signals whenever data transfer is required.

13.3.2 Flow Control

The Flow Control block controls the Viterbi algorithm operations for one update cycle – called a stage in the trellis.

13.3.3 Branch Metric

The Branch Metric block calculates a pair of branch metrics for every execution cycle. The branch metrics values are calculated differently depending on the operation mode.

Viterbi Parameters (VP), loaded in the VP RAM, are required for the branch metric calculation and for equalization. The DSP56300 core calculates the VPs based upon the channel impulse response. The VCOP makes use of the symmetrical property of VP values (V(k)=–V(n–k)), by requiring only n/2 VP values for an n-state trellis calculation, for instance VP0–7 for a 16-state, and VP0–15 for a 32-state.

When performing decoding, the branch metrics calculation is based on the input symbol data, the tap vectors, and the trellis state number.

When calculating an ACS butterfly2, the pair of branch metrics are opposites. The branch metric block calculates one value and negates it prior to delivering it to the ACS block. For every ACS butterfly there are two associated VP values.

When performing equalization, the calculation is based on demodulated symbol data which is the output of a Matched Filter (MF). The MF value is stored in the VDR as a 16-bit value.

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Block Description

13.3.4 Add-Compare-Select (ACS)

The ACS block performs the Add-Compare-Select function:

• Add (add a branch metric to its associated path metric)

• Compare (compare two updated path metrics)

• Select (select the optimal path of the two states and save the survivor path metric for every state)

The ACS is performed for every pair of states, according to the ACS butterfly scheme2. The ACS adds to each state metric (from the path metric RAM) its associated branch metric and compares the two sums. In the scheme employed in the VCOP, the greater value determines the survivor path and is written into the path metric RAM. The Trellis RAM is updated with the survivor decision bit (0 or 1). The two ACS operations composing a full ACS butterfly are done sequentially using the same pair of state metrics.

13.3.5 Window Error Detection (WED)

The Window Error Detection (WED) block performs the WED computation on a window of the decoded block of bits (as specified in the VWES register). This block runs in lockstep with the ACS block. For every ACS operation in the window, the difference in path metrics is passed to WED. The block updates WED RAM with the minimal-difference decision along every path within the WED window.

Figure 13-4 Window Error Detection Function

ACS

CMP

MUX

Previous

Minimal

Update State’sMinimal Difference

DecisionWED RAM

AA1314

Difference State’s

Difference

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Block Description


13.3.6 Trellis

The Trellis block manages the path history of every path of the trellis associated with every state in the trellis. The block also provides the hardware required to read the survivor’s hard decision decoded data from the Viterbi. The trellis RAM modules store the actual decoded data bits (not the pointers). The pass over the trellis states is done in parallel to the pass over the path metrics. The decision depth of the algorithm is fixed at 36 bits (more than five times the maximum constraint length of seven), implemented using Trellis RAM (64 × 36 bits).

13.3.7 Data Control

The Data Control block provides control data output flow during decoding, encoding, and equalization. The block generates interrupts and DMA triggers whenever data is ready to be read out of the VCOP according to the interrupt modes. The hardware consists of a 1023 × 1-bit or 64 × 16-bit output buffer used in decoding, encoding, and equalization.

13.3.8 Receive Quality Error

The Receive Quality Error block supplies information on the quality of the received block of data. This information is used only in the decoding mode. The block calculates the Bit Error (BER) count by re-encoding the hard decision data produced by the trellis block and comparing it with the hardened input symbols. The value obtained is the number of symbol bits corrected by the decoder. The block supports puncture codes, by not counting neutral value symbols (e.g., $000000). The BER is available to the DSP56300 core processor via the VBER.

Note: The BER value is true only if the data was successfully decoded, so the decoding should be checked using CRC.

Figure 13-5 Bit Error Count Function

Delay

Viterbi

HardSymbol

SoftSymbol

BER Count

Encoder

xor

Algorithm

AA1315

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Operating Modes

13.4 OPERATING MODES

The VCOP can be programmed to operate in the following modes:

• Equalization

• Encoder

• Decoder

• Memory Access

• Flush

Each operating mode has a data flow scheme associated with it.

There are also two states in which the VCOP is not functional:

• VCOP Individual Reset

• Idle

13.4.1 Equalization Mode

The Equalization mode is started by setting the EQEN bit (VCRA Bit 4). Its functioning is summarized in Figure 13-6.

The received signal, which may have been corrupted by InterSymbol Interference (ISI) or additive noise (AWGN), is equalized through the use of an MLSE equalizer. Ungerboeck presented a type of MLSE equalizer employing a Matched Filter combined with a Viterbi Algorithm section, for which a block diagram is given in Figure 13-21. The MLSE equalizer output is hard decision (0,1) data bits. Soft data used as input to a Viterbi decoder is proven to achieve similar results to the best alternative methods. The equalizer should be supplied with the Viterbi parameters (VP) - the state transition metrics for the equalization scheme, based on the linear combination of the channel impulse response coefficients.

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Operating Modes


13.4.1.1 InitializationEnter the expected number of bits to equalize into VCNT, or select the continuous operation mode by setting the CME bit (VCRB Bit 3).

13.4.1.2 Normal OperationA 16-bit MF value is supplied to the VCOP. For every update-cycle, a pass over all trellis states is performed. The survivor is found by the ACS block and a decoded bit is delivered from the Trellis block. The equalized data is then moved to the output buffer used for data transfers to the DSP56300 core processor. The equalized data can be read one symbol-bit at a time, using a core interrupt or DMA transfer. When all the input data have been processed, the VCOP flushes the data remaining in the trellis.

13.4.1.3 Flush OperationIn this stage, there are no more MF inputs and only the remaining bits in the trellis memory are left to process. The trellis path is selected according to the Flush Control mode (ending state or best metric), and the remaining bits are shifted out.

Figure 13-6 Viterbi Co-Processor in Equalization Mode

BM ACS Data Control

PMB Interface

VP RAM Metric RAM 63 × 16 bit /Output Buff

Trellis

Trellis RAM

WED

WED RAM

1023 × 1 bit32 × 16 64 × 22 64 × 36 × 1

64 × 16

Rx Qual


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Operating Modes

13.4.2 Encoder Mode

The Encoder mode is started by setting the ENCEN bit (VCRA Bit 3). Its functioning is summarized in Figure 13-7.

During convolutional encoding the input data bits are encoded according to the rate, constraint, and given tap polynomials as programmed. The bits to be encoded are written one at a time to VDR as a hard value word ($800000 = 0 or $7FFF00 = 1). The encoded bits (a symbol) are written to the output buffer (1023 × 1 bit RAM) The encoded bits are read through the VDOR register. The number of VDOR reads per input bit varies according to the rate, for instance: 2, 3, 4, 6 reads for 1/2, 1/3, 1/4, 1/6 rate, respectively, given in a hard value format ($800000 for 0, or $7FFF00 for 1). The encoder operates at the fixed rate of 1 input bit per 16 cycles.

Figure 13-7 Viterbi Co-Processor in Encoder Mode

13.4.2.1 InitializationIn order to initialize the starting state in the VCOP encoder, write the initial state IS[5:0] in VTSR register, prior to starting the encoding operation.

13.4.3 Decoder Mode

The Decoder mode is started by setting the DECEN bit (VCRA Bit 2). Its functioning is summarized in Figure 13-8.

The received stream of input symbols is supplied to the VCOP one symbol at a time through the VDR FIFO (that is, sequential writes of symbol-bits combine to create a symbol, written to VDR either by core or DMA). The branch metrics values based on that symbol are calculated by the Branch Metric block.

The VCOP implements the convolutional decoder using a modified Viterbi algorithm that can operate on soft-decision symbol inputs. The Manhattan metric system is used. The decoder provides the Bit Error count (BER), the number of bits corrected by the decoder. The BER is available to the DSP56300 core as the contents of the (read-only) VBER.

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Operating Modes


13.4.3.1 InitializationEnter the code parameters (rate, taps, trellis size) and the expected number of bits to decode into VCNT, or select the continuous operation mode by setting the CME bit (VCRB Bit 3).

13.4.3.2 Normal OperationThe VDR FIFO must be written for every update cycle (from two to six writes must be performed per cycle, depending on the code rate). Then a pass over all trellis states is performed and the branch metrics are calculated. The survivor is found by the ACS block and a decoded bit is delivered from the Trellis block to the output buffer. The decoded data is re-encoded by the BER block to be compared with the original input symbol.

Figure 13-8 Viterbi Co-Processor in Decoder Mode

BM ACS Data Control

PMB Interface

VP RAM Metric RAM 63 × 16 bit /Output Buff

Trellis

Trellis RAM

WED

WED RAM

1023 × 1 bit32 × 16 64 × 22 64 × 36 × 1

64 × 16

Rx Qual


AA1317

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Operating Modes

13.4.3.3 Flush OperationIn this stage, there are no more symbol inputs and only the remaining bits in the trellis memory are left to process. The trellis path is selected according to the Flush Control modes (end_state or best metric). The remaining bits are shifted out and (as in normal operation) re-encoding and BER calculation is applied.

13.4.4 Memory Access Mode

The Memory Access mode enables the DSP56300 core to write data into SP, VP and the Metric internal RAMs. The VBER register/counter holds the address of the access while the data is held in VMEM. During the Memory Access mode every memory write of VMEM increments the memory address such that the next access is performed at the consecutive location. When accessing SP and VP RAMs (which are 16-bit wide), full 16-bit data words are written via VMEM.

For the support of differential metric schemes a 24-bit word is used to read/write the Metric RAM, where the metric data occupies the 22 least significant bits, zero extended3. The address value in the Metric RAM represents the state value, e.g. reading the content of address #J in the Metric RAM gives the Path Metric value of state #J. A sequential read of the Metric RAM contents gives the Path Metric values from state #0 to state #(n–1) sequentially. Refer to memory access examples in Section 13.9.3, and see Section 13.7 for a detailed description on the trellis state formation.

13.4.5 Flush Mode

During both equalization and decoding modes, the Flush mode is enabled automatically by VCOP after the completion of an input block of data when the VCNT register reaches zero. In this mode the remaining bits in the trellis RAM are shifted out and processed (i.e. BER computation for channel decoding). The desired trellis-path is selected according to the Flush Control modes – ending state or best metric. At the end of the flush process the VCOP returns to idle state. The Flush mode can also be invoked explicitly during decoding or equalization by clearing DECEN or EQEN and setting the FLEN bit in VCRA. In this case the VCOP will suspend the current processing and start the flush operation as described above.

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Operating Modes


13.4.6 VCOP Individual Reset State

The VCOP Individual Reset state is entered whenever the ME bit in VCRA is cleared. In this state, status bits are cleared, internal pointers and internal circuits are reset to their default values. Control bits are preserved.

13.4.7 Idle State

The Idle state is entered upon exiting the VCOP individual reset state, whenever the VCOP operation is disabled (all of the bits MAEN, DECEN, ENCEN, EQEN, and FLEN in VCRA are cleared) and at the end of processing a block of data. In this state, the VCOP state machine is idle; clocks are enabled but internal pointers and internal circuits are reset to their default values. Control bits and OPC status bit in VSTR are preserved, while the remaining status bits in VSTR are cleared.

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The VCOP control and status registers are accessible to the DSP56300 core through the PMB. They are summarized in Table 13-1.

All VCOP registers are 16-bits wide, except VMEM which is 24-bits wide. Data register (VDR, VDOR, VWED) access to a 24-bit resource (such as a bus, register, memory, etc.) is left aligned. That is, the 24-bit resource is read as zero padded ($DDDD00) and the data is written with the eight LSBs ignored ($DDDDXX). Control register (VCRA, VCRB, VSTR, VCNT, VTPA, VTPB, VTSR, VBER, VWES) access to a 24-bit resource is right aligned. That is. the registers are read zero padded ($00DDDD) and written with the eight MSBs ignored ($XXDDDD). When writing the control registers from a 24-bit resource, the 8 MSBs must be written with 0 for future compatibility.

Table 13-1 VCOP Programming Model

Base Address Register Name Register

Abbreviation

$0 VCOP Data Register/FIFO VDR

$1 VCOP Data Out Register VDOR

$2 VCOP Control Register A VCRA

$3 VCOP Control Register B VCRB

$4 VCOP Status Register VSTR

$5 VCOP Data Count Register VCNT

$6 VCOP Tap Register A VTPA

$7 VCOP Tap Register B VTPB

$8 VCOP Trellis Setup Register VTSR

$9 VCOP Bit Error Rate Register VBER

$A VCOP WED Setup Register VWES

$B VCOP WED Data Register VWED

$C VCOP Memory Access Register VMEM

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13.5.1 Viterbi Data Register/FIFO (VDR)

The Viterbi Data Register/FIFO (VDR) holds the input data for the decoding, encoding, and equalization operations. It is of variable depth according to rate and mode, with a maximum depth of six locations, and is 16-bits wide. VDR can be accessed by the core and DMA.

In decoding and equalization modes, “double-buffering” is implemented to obtain maximum throughput.

In equalization the VDR (register) should be written with 16-bit word data obtained from the Matched Filter (MF). In encoding, the VDR (register) holds a 1-bit hard-value word (‘0’, ‘1’ bit for encoding - $7FFF00, $800000 respectively). In both equalization and encoding, one write access is required for every data request.

In decoding, the VDR (FIFO) should be written with 8-bit hard or soft data symbols, one symbol-bit at a time; it should be written with a symbol for every data request. The write of a symbol is composed of two, three, four, or six (depending on the code’s rate - 1/2, 1/3, 1/4, 1/6 respectively) write accesses, each containing a soft symbol-bit occupying the 8 most significant bits of the data word. The symbol-bit write order should match the TAP polynomials (g(0), g(1), g(2),...etc.) starting with g(0).

13.5.2 Viterbi Data Out Register (VDOR)

The Viterbi Data Out Register (VDOR) is a 16-bit read-only register used for reading data from the VCOP output buffer. The VDOR is used for encoding, decoding and equalization. The VDOR can be accessed by the core and DMA.

In encoding, the VDOR holds (a hard-value of an encoded symbol-bit) or (the single bit value of a decoded symbol). The value read is either $800000 for ‘1’ or $7FFF00 for ‘0’. The bits are read in ascending order; that is, the bit generated by Tap polynomial 0 is the first one read.

In decoding, the VDOR holds the decoded bit in the same hard value format ($800000 for ‘1’ or $7FFF00 for ‘0’) and should be written with 16-bit words of packed decoded bits.

In equalization, the VDOR holds a hard value.

Consecutive single cycle reads of VDOR are not allowed.

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13.5.3 Viterbi Control Register A (VCRA)

The Viterbi Control Register A (VCRA) is a 16-bit read/write control register used by the DSP56300 core to control the main operation modes of the module. The VCRA bits are described in the following paragraphs. All the VCRA bits are cleared after Hardware and Software Reset.

When the five enable bits (MAEN, DECEN, ENCEN, EQEN, and FLEN) are cleared, the module is in the idle state. In this mode, the module is inactive but the register contents are preserved and they can be read or written by the DSP56300 core.

Only one of MAEN, DECEN, ENCEN, and EQEN may be set at a time. Setting more than one of these bits is an illegal condition and will cause the VCOP operation to be unpredictable.

13.5.3.1 Module Enable (ME)—VCRA Bit 0The Module Enable bit (ME), when set, enables the operation of the VCOP. When ME is cleared, the operation is disabled and the VCOP is in the VCOP individual reset state. While in the VCOP individual reset state, internal logic and status bits are reset to the same state produced by hardware or software reset. Control bits are not affected when ME is cleared. ME is cleared by hardware or software reset.

13.5.3.2 Memory Access Enable (MAEN)—VCRA Bit 1The Memory Access Mode enable bit (MAEN), when set, enables the core to access the data of the internal RAMs. The VBER contains the address of the memory access while VMEM contains the data. This mode is used when setting the SP and VP values for channel equalization. After setting these parameters, the MAEN bit must be cleared by the DSP56300 core.

Figure 13-9 Viterbi Control Register A (VCRA)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CNST1 CNST0 RATE1 RATE0 FLEN EQEN ENCENDECEN MAEN ME

Reserved bit, Read as zero, should be written with zero for future compatibilityAA1318

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13.5.3.3 Decoding Enable (DECEN)—VCRA Bit 2The Decoding Enable bit (DECEN), when set, enables the module to perform convolutional decoding. All mode parameters specifying the type of coding must be set prior to entering this mode (that is, the registers VCRA, VCRB, VTPA, and VTPB must be written, and VCNT, VWES, and VTSR may need to be written, prior to this operation). At the end of the decoding (i.e. after VCNT reaches zero and the flush operation is completed), the DECEN bit is cleared by the internal logic. When the VCOP is in continuous mode (CME is set), the flush operation does not take place, and DECEN is not cleared by the internal logic. When DECEN is cleared, the decoding operation halts and the register contents are preserved. The decoding operation is resumed if DECEN is set again.

13.5.3.4 Encoding Enable (ENCEN)—VCRA Bit 3The Encoding Enable bit (ENCEN), when set, enables the module to perform convolutional encoding. All mode parameters specifying the type of the coding must be set prior to entering this mode; that is, the registers VCRA, VCRB, VTPA, and VTPB must be written, and VCNT may need to be written, prior to this operation. At the end of the encoding (i.e. after VCNT reaches zero) the ENCEN bit is cleared by the internal logic. When the VCOP is in continuous mode (CME is set), ENCEN is not cleared by the internal logic. When ENCEN is cleared, the encoding operation halts and the register contents are preserved. The encoding operation is resumed if ENCEN is set again.

13.5.3.5 Equalization Enable (EQEN)—VCRA Bit 4The Equalization Enable bit (EQEN), when set, enables the module to perform channel equalization. All mode parameters specifying the type of the equalization must be set prior to entering this mode (that is, the registers VCRA and VCRB must be written, and VCNT and VTSR may need to be written, prior to this operation). Equalization uses S-parameters and V-parameters, therefore these values (contained in the SP RAM and VP RAM respectively) must be written using the Memory Access Mode prior to starting equalization. At the end of equalization (that is, after VCNT reaches zero and the flush operation is complete), the EQEN bit is cleared by the internal logic. When the VCOP is in continuous mode (CME is set), the flush operation does not take place, and EQEN is not cleared by the internal logic. When EQEN is cleared, the equalization operation halts and the register contents are preserved. The equalization operation is resumed if EQEN is set again.

13.5.3.6 Flush Enable (FLEN)—VCRA Bit 5The Flush Enable bit (FLEN), when set, enables the module to perform the flush operation in order to complete the current operation prior to its normal ending (i.e. before the counter reaches zero), forcing the module to extract survivor path bits remaining in Trellis RAM. The path to be flushed is defined by the VTSR register. At the end of the flush operation the FLEN bit is cleared by the internal logic.

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13.5.3.7 Code Rate (RATE[1:0])—VCRA Bits 8–9The Code Rate bits (RATE[1:0]) define the convolutional code rate for both decoding and encoding (see Table 13-2). The Code Rate bits are ignored in other modes.

13.5.3.8 Constraint Length (CNST[1:0])—VCRA Bit 12–13The Constraint Length bits (CNST[1:0]) define the number of states in the trellis diagram. The bit settings defining constraint length and number of trellis states are given in Table 13-3.

13.5.3.9 VCRA Reserved—VCRA Bits 6–7, 10–11, 14–15These bits are reserved and should be written with zero.

Table 13-2 Code Rate Definition

RATE[1:0] RATE Symbol Size In Bits1

00 1/2 2

01 1/3 3

10 1/4 4

11 1/6 6

Note: 1. Size required for decoding each symbol-bit represented in a soft decision format

Table 13-3 Trellis States

CNST[1:0] Number of trellis states Constraint length

00 8 4

01 16 5

10 32 6

11 64 7

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13.5.4 Viterbi Control Register B (VCRB)

The Viterbi Control Register B (VCRB) is a 16-bit read/write control register used by the DSP56300 core to control the enabling of the interrupts generated by the module and the operation modes of the module. The VCRB bits are described in the following paragraphs. All VCRB bits are cleared after hardware and software reset.

13.5.4.1 Initial State Enable (ISE)—VCRB Bit 0The Initial State Enable bit (ISE) controls the decoder starting path metric values. When ISE is set, the state defined by the IS[5:0] bits in the VTSR is initialized to an initial value of 219, while the rest of the states are initialized to zero. When ISE is cleared, all trellis states path metrics are initialized to zero.

13.5.4.2 Flush Control (FLC)—VCRB Bit 1The Flush Control bit (FLC) controls the Flush Mode of operation by determining which ending state to flush to, as defined in Table 13-4.

13.5.4.3 Continuous Mode Enable (CME)—VCRB Bit 3The Continuous Mode Enable (CME) bit enables the VCOP to operate continuously. When CME is cleared, the VCOP operates on data blocks of length defined in the VCNT register. When CME is set, the VCNT contents are ignored and the VCOP operates continuously upon receiving new data words. When CME is set, the flush operation does not take place as part of the decoding and equalization process, and bits ENCEN,

Figure 13-10 Viterbi Control Register B (VCRB)

Table 13-4 Flush Modes

FLC Flush operation flushes the path

0 with the maximal path metric value

1 defined by the End State (ES[5:0]) bits

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OCIE DNIE DOIE BFIE DIIE WEDE CME FLC ISE

Reserved bit, Read as zero, should be written with zero for future compatibility

Reserved for internal use. Should be written with zero for proper operation.

AA1319

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DECEN, and EQEN in VCRA are not cleared by the internal logic. The CME bit should be changed only when VCOP is in the VCOP individual reset state.

13.5.4.4 Data Mode (HD[0])—VCRB Bits 4–5The Data Mode bit (HD[0]) defines whether hard decision data bits are available for performing channel equalization. In the current revision of the DSP56305, only hard decision data bits are available.

13.5.4.5 Window Error Detection Enable (WEDE)—VCRB Bit 6The Window Error Detection Enable (WEDE) bit, when set, enables the WED function while performing channel decoding

13.5.4.6 Data-In Interrupt Enable (DIIE)—VCRB Bit 8The Data-In Interrupt Enable (DIIE) bit, when set, enables the interrupts caused by request for data input (DREQ bit in VSTR).

13.5.4.7 Buffer Full Interrupt Enable (BFIE)—VCRB Bit 10The Data Buffer Full Interrupt Enable (BFIE) bit, when set, enables the interrupts caused by output-buffer full signal (DOBF bit in VSTR is set).

13.5.4.8 Data Out Interrupt Enable (DOIE)—VCRB Bit 11The Data Out Interrupt Enable (DOIE) bit, when set, enables the interrupts caused by data ready in the output buffer (DRDY bit in VSTR is set).

13.5.4.9 Processing Done Interrupt Enable (DNIE)—VCRB Bit 12The Processing Done Interrupt Enable (DNIE) bit, when set, enables the interrupts caused by done processing signal (DONE bit in VSTR is set).

13.5.4.10 Operation Complete Interrupt Enable (OCIE)—VCRB Bit 13The Operation Complete Interrupt Enable (OCIE) bit, when set, enables the interrupts caused by operation complete signal (OPC bit in VSTR is set).

13.5.4.11 Reserved Bits—VCRB Bits 2, 5, 9, 14–15These bits are reserved and should be written with zero.

Table 13-5 Data Modes

HD[1:0] Data Mode VDOR Content (24-bit)

0 Hard Data hard values: $7FFF00 = 1 / $80000 = 0

1 Reserved

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13.5.4.12 Internal Reserved Bits—VCRB Bits 4, 7These bits are reserved for internal use and should be written with zero for proper operation.

13.5.5 Viterbi Status Register (VSTR)

The Viterbi Status Register (VSTR) is a 16-bit read-only status register used by the DSP56300 core to examine VCOP status and flags. All VSTR bits are cleared following hardware, software, or VCOP individual reset. All the VSTR bits except OPC are also cleared when VCOP is in the Idle state.

13.5.5.1 Initialize Flag (INIT)—VSTR Bit 0The Initialize Flag (INIT) bit, when set, indicates the VCOP is being initialized. At initialization the metric RAM is initialized with the start-up values (equal for all states or a preferred starting state). Initialization lasts a period of time equal to the time required for a single pass over all trellis states (i.e. a one-stage period), and is thus dependent upon the number of states in the given code. This bit is cleared when initialization is complete.

13.5.5.2 Flush Flag (FLSH)—VSTR Bit 1The Flush Flag (FLSH) bit, when set, indicates the VCOP is performing a flush operation. It is cleared when the flush operation is complete.

13.5.5.3 Operation Complete (OPC)—VSTR Bit 4The Operation Complete (OPC) flag bit, when set, indicates the VCOP has completed its operation and all the processed data block has been read out. The OPC bit indicates that the VCOP is ready to start processing a new data block. It is cleared when any one of the five enable bits (MAEN, DECEN, ENCEN, EQEN, and FLEN) is set. When OPC and OCIE are set, an interrupt request is generated and OPC is cleared upon servicing that interrupt request. This bit is disabled when CME (VCRB Bit 3) is set.

Figure 13-11 Viterbi Status Register (VSTR)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DOBF DREQ ESTG DRDY DONE OPC FLSH INIT

Reserved bit, Read as zero.AA1320

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For the three major VCOP operating modes, the OPC bit is set:

• At encoding, after VCNT reaches zero, and the last symbol-bits word is read out (via VDOR).

• At decoding, after VCNT reaches zero and flush operation is complete, when the last data word has been read from the output buffer (via VDOR).

• At equalization, after VCNT reaches zero and flush operation completes, when reading the last soft data (via VDOR ) is complete.

13.5.5.4 Processing Done (DONE)—VSTR Bit 5The Processing Done(DONE) flag bit, when set, signals that the data block has finished its processing (including the flush operation), resides in the output buffer, and is ready to be transferred to the DSP56300 core. This bit is functional in decoding or equalization modes (i.e. while CME bit in VCRB is cleared). The DONE bit is cleared after reading the last word from the data output buffer (VDOR).

13.5.5.5 Data Ready (DRDY)—VSTR Bit 6The Data Ready (DRDY) flag bit indicates, when set, that data is ready in VDOR. The bit is functional in equalization, encoding, and decoding modes. The bit is cleared when the VDOR register is read.

13.5.5.6 End Stage (ESTG)—VSTR Bit 7The End Stage (ESTG) status bit indicates, when set, that the VCOP has finished all operations of the current stage, including all piped operations. The bit is cleared whenever ‘stage update’ (a pass over all states) begins.

13.5.5.7 Data Request (DREQ)—VSTR Bit 8The Data Request (DREQ) flag bit indicates, when set, that new data is required for processing. The bit is cleared when the VDR FIFO/register is written.

13.5.5.8 Data Output Buffer Full (DOBF)—VSTR Bit 9The Data Output Buffer Full (DOBF) flag bit indicates, when set, that the output buffer (VDOR) is full, causing processing to stop at the end of the current stage. The DOBF is cleared by reading the VDOR register, thus enabling further processing.

13.5.5.9 Reserved Bits—VSTR Bits 2, 3, 10–15These bits are reserved and should be written with zero.

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13.5.6 Viterbi Data Counter (VCNT)

The Viterbi Data Counter (VCNT) is a 10-bit wide counter determining the number of stages which must be performed to process a block of data. If n is the number of data bits to process, VCNT should contain n–1 for each of the three processing modes. The counter value may be read during operation to check how many bits remain to be processed. VCNT is ignored when the continuous mode (CME, VCRB Bit 3) is enabled.

13.5.7 Viterbi Tap A Register (VTPA)

The Viterbi Tap A register (VTPA) is a 16-bit write-only register containing (during encoding and decoding) convolutional code tap polynomials. The VTPA is used for the three least significant polynomials: G2, G1, G0. The polynomial taps are represented as 1 for a existing tap and 0 for a non-existent tap. The tap bits do not include the MSB and LSB of the polynomial, which are 1 for all codes. Tap values must be programmed before starting encoding or decoding.

13.5.7.1 Tap Vector A (TAPA{4:0])—VTPA Bits 4–0The Tap Vector A (TAPA[4:0]) bits contain the vector 0 taps (G0), excluding its MSB and LSB.

13.5.7.2 Tap Vector B (TAPB[4:0])—VTPA Bits 9–5The Tap Vector B (TAPB[4:0]) bits contain the vector 1 taps (G1), excluding its MSB and LSB.

13.5.7.3 Tap Vector C (TAPC[4:0])—VTPA Bits 14–10The Tap Vector C (TAPC[4:0]) bits contain the vector 2 taps (G2), excluding its MSB and LSB.

13.5.7.4 Reserved Bit—VTPA Bit 15This bit is reserved and should be written with zero.

Figure 13-12 Viterbi Tap A Register (VTPA)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TAPC4 TAPC3 TAPC2 TAPC1 TAPC0 TAPB4 TAPB3 TAPB2 TAPB1 TAPB0 TAPA4 TAPA3 TAPA2 TAPA1 TAPA0

Reserved bit, should be written with zero for future compatibility.AA1321

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13.5.8 Viterbi Tap Register B (VTPB)

The Viterbi Tap B register (VTPB) is a 16-bit write-only register containing (during encoding and decoding) convolutional code tap polynomials. The VTPB is used for the three most significant polynomials: G5, G4, G3. The polynomial taps are represented as 1 for a existing tap and 0 for a non-existent tap. The tap bits do not include the MSB and LSB of the polynomial, which are 1 for all codes. Tap values must be programmed before starting encoding or decoding.

13.5.8.1 Tap Vector D (TAPD{4:0])—VTPB Bits 4–0The Tap Vector D (TAPD[4:0]) bits contain the vector 3 taps (G3), excluding its MSB and LSB.

13.5.8.2 Tap Vector E (TAPE[4:0])—VTPB Bits 9–5The Tap Vector E (TAPE[4:0]) bits contain the vector 4 taps (G4), excluding its MSB and LSB.

13.5.8.3 Tap Vector F (TAPF[4:0])—VTPB Bits 14–10The Tap Vector F (TAPF[4:0]) bits contain the vector 5 taps (G5), excluding its MSB and LSB.

13.5.8.4 Reserved Bit—VTPB Bit 15This bit is reserved and should be written with zero.

Figure 13-13 Viterbi Tap Register B (VTPB)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TAPF4 TAPF3 TAPF2 TAPF1 TAPF0 TAPE4 TAPE3 TAPE2 TAPE1 TAPE0 TAPD4 TAPD3 TAPD2 TAPD1 TAPD0

Reserved bit, Read as zero.AA1322

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13.5.9 Viterbi Trellis Setup Register (VTSR)

The Viterbi Trellis Setup Register is a 16-bit register that determines the Initial State and End State of the trellis diagram. The values of the VTSR bits are used together with the values of ISE and FLC (VCRB, Bits 0 and 1).

13.5.9.1 Initial State (IS[5:0])—VTSR Bits 5–0The Initial State (IS[5:0]) bits define the starting state of the decoder or equalizer. The state is selected by assigning the selected state a high path metric value during the initialization stage. If ISE is cleared, all trellis states are equally weighted with the value 0. If ISE is set, the start state (defined by the IS[5:0] bits) is assigned an initial path metric value of 219. See Section 13.7 for a detailed description of trellis state formation.

13.5.9.2 End State (ES[5:0])—VTSR Bits 13–8The End State bits (ES[5:0]) define a known ending state of the trellis diagram. During Flush operation the path in the trellis diagram is chosen according to bit FLC. See Section 13.7 for a detailed description on the trellis state formation.

13.5.9.3 Reserved Bits—VTSR Bits 6, 7, 14, 15These bits are reserved and should be written with zero.

13.5.10 Viterbi Bit Error Rate Register/Counter (VBER)

The Viterbi Bit Error Rate Register/Counter (VBER) is used in the Decoder and the Memory Access operation modes.

In Decoder mode, the VBER is a 16-bit read-only register containing the BER value. The BER value is the number of symbol-bits corrected so far by the decoding process. The register value is valid at the end of decoding.

In Memory Access mode, the VBER is a read/write address register/counter for accessing memory modules of the VCOP. Bits 7–6 select the accessed RAM module

Figure 13-14 Viterbi Trellis Setup Register (VTSR)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ES5 ES4 ES3 ES2 ES1 ES0 IS5 IS4 IS3 IS2 IS1 IS0

Reserved bit, Read as zero, should be written with zero for future compatibilityAA1323

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while bits 5–0 define the address in it, see Table 13-7 below. The VBER is cleared when Memory Access mode is enabled, and can be set to any valid start address. Every read/write operation to any of the RAM modules increments the counter to the next address location. When the VBER is cleared (and the VCOP is in Memory Access mode) then loaded with another start address, every write to VMEM post-increments its value. For accessing the Branch Metric RAM, the VBER value is taken as the Trellis state, according to the state of the internal logic. For valid addresses of VCOP RAMs see Table 13-7.

Note: The Metric RAM is a 22-bit wide word RAM. The data accessed via VMEM register occupies the 22 least significant bits, zero extended to bits [23:22].

13.5.11 Viterbi WED Setup Register (VWES)

The VWES is a 16-bit write-only setup register used to define the WED parameters. The WED function is operational for block sizes of up to 256 decoded bits, that is,if VCNT ≤ 256.

Table 13-6 Memory Addresses

Memory Size VBER[7:6] VBER[5:0]

VP 32 x 16 00 $0 – $1F

Reserved 7 x 16 01 $0 – $6

WED 64 x 16 00 $0 – $3F

Path Metric 64 x 22 10 $0 – $3F

DELAY 45 x 16 11 $0 – $2C

Figure 13-15 Viterbi WED Setup Register (VWES)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WLEN7 WLEN6 WLEN5 WLEN4 WLEN3 WLEN2 WLEN1 WLEN0 WSTR7WSTR6WSTR5WSTR4WSTR3WSTR2WSTR1WSTR0

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13.5.11.1 Window Start Location (WSTR[7:0])—VWES Bits 7–0The Window Start Location (WSTR[7:0]) bits are used to specify the start location of the WED window in the data block. The value assigned to WSTR[7:0] should be (N–L–1), where N is the number of decoded bits in the data block and L is the start bit location for WED computation.

13.5.11.2 Window Length (WLEN[7:0])—VWES Bits 15–8The Window Length (WLEN[7:0]) bits specify the length of the WED window. The value assigned to WLEN[7:0] should be the window bit-length minus one.

For example, assuming a GSM half rate speech data block (TCH/HS) of 104 decoded bits, numbered 1, 2, 3,..., 104, in which the WED window starts at bit 75, and the WED window length is 25 bits, the following parameters need to be input:

VCNT = block_size – 1 = 104 – 1 = 103 = $67WSTR = block_size – start_bit – 1 = 104 – 75 – 1 = 28 = $1CWLEN = window_length – 1 = 25 – 1 = 24 = $18

13.5.12 Viterbi WED Data Register (VWED)

The VWED is a 16-bit read-only data register used for reading the WED value. The calculation of the WED is enabled by setting WEDE (VCRB Bit 6). The value provided is the minimal difference in path metrics of all ACS decisions along the survivor path within the defined window. The window is defined using the VWES register. The VWED is cleared when the decoding mode is enabled. The WED function is performed during decoding only.

13.5.13 Viterbi Memory Access Register (VMEM)

The Viterbi Memory Access Register (VMEM) is a 24-bit read/write data register, used in Memory Access mode to access the VCOP RAM modules (excluding Output Buffer and Trellis RAM). When accessing 16-bit word data RAM, the data occupies the sixteen most significant bits of VMEM, zero padded at the [7:0] bits. For the Metric RAM access, the data bits occupies bits [21:0] of VMEM, zero extended to bits [23:22]. The data address is defined by the VBER, see Table 13-7 on page 30. WED accuracy, (as given in the VWED register), is plus or minus one of the correct minimal difference decision along the surviving path.

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Chip Description

13.6 CHIP DESCRIPTION

This section describes the memory, interrupts, DMA source, and soft decision formats of the VCOP of the DSP56305.

13.6.1 Memory description

Note: 1. There is no continuity in accessing different memory sections. Therefore, whenever a new memory section is to be accessed, VBER should be explicitly assigned a starting address of that memory section.

2. WED and VP RAMs are implemented by a common physical RAM, allocated for either WED (at decoding) or as VP (at equalization).

Table 13-7 Memory modules usage and access

Memory Module1

Memory Size

Address(VBER)

Operation Modes Using the Module

Accessed ByEqualiz-

ation Decoding Encoding

VP 2 32 x 16 $0 – $1F yes - - VMEM Register

WED 2 64 x 16 $0 – $3F - yes, if enabled

- VMEM Register

Reserved 7 x 16 $40 – $46 reserved reserved reserved VMEM Register

Path Metric

64 x 22 $80 – $BF yes yes -. VMEM Register

DELAY 45 x 16 $C0 – $EC yes yes - VMEM Register

Trellis 64 x 36 yes yes Internal logic only

OUTPUT BUFF

1023 x 1 or 63 x 16

yes yes yes VDOR

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Chip Description


13.6.2 Interrupt and DMA Sources

13.6.3 I/O Register and Related Interrupts for Different Modes

Table 13-8 Interrupt and DMA Sources

Interrupt Source Interrupt Vector Interrupt Vector Address

DMA Request

Availability

DREQ Viterbi Data In Request BASE + $0 Yes

DOBF Viterbi Output Buffer Full BASE + $2 Yes

DRDY Viterbi Data Out Request BASE + $4 Yes

DONE Viterbi Processing Done BASE + $6 Yes

OPC Viterbi Operation Complete BASE + $8 No

Table 13-9 I/O Register Usage

Operation Mode Input Output Interrupt

Enable Bit Status Bit Register Content

Equalization VDR DIIE DREQ 16-bit MF Value

VDOR DOIE DRDY Hard Data

Decoding VDR1 DIIE DREQ Symbol-Bit, Soft Value

VDOR DOIE DRDY Hard Decoded Value

Encoding VDR DIIE DREQ Hard Input to Encoder

VDOR DOIE DRDY Symbol-Bit Output

Note: 1. A sequential write of all symbol-bits to VDR-FIFO is required for each request.

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Chip Description

13.6.4 Soft Decision Format

The module uses soft data in decoding in 8- and 16-bit precision. The 16-bit equalizer output can be fed gluelessly into the decoder, because the decoder metric computations are performed on the 8-most significant bits of the symbol-bits value (in the VDR). Table 13-10 below presents the soft values in both 8 and 16-bit precisions, as being read or written via a 24-bit VCOP register.

Table 13-10 Soft Decision Format

Soft Value 8-bit Precision(Symbol Input to Decoder)

16-bit Precision(Equalizer Output)

Strong ‘0’ 0x7F0000 0x7FFF00

...Weak ‘0’

Neutral valueWeak ‘1’

...

...0x0100000x0000000xFF0000

...

...all other values

reserved...

Strong ‘1’ 0x800000 0x800000

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Viterbi Butterfly Implementation


13.7 VITERBI BUTTERFLY IMPLEMENTATION

Bits enter the Trellis state Least Significant Bit first (i.e. from right to left). As an example, assume a16-state trellis (constraint length = 5). Let w, x, y, z each denote a binary digit so that ‘wxyz’ represents a state in the trellis. The Viterbi butterfly is then defined as a transition from the current states ‘0xyz’ and ‘1xyz’ to the next states ‘xyz0’ and ‘xyz1’ as shown in Figure 13-16.

In Decode mode, a Branch Metric (BM) value is evaluated for each butterfly. In general, BM is a weighted value of the received data symbols with reference to the expected convolutional encoded bits of that particular state.

In Equalization mode, the BM for each transition within a Viterbi butterfly is a function of the Matched Filter output (MF) and the L-Metric Viterbi Parameters (VP). The VP values come from the channel sounding. After extracting the channel impulse response coefficients via a cross correlation process (also referred to as the S parameters), the VP value for a particular state ‘wxyz’ is usually calculated as follows:

For full flexibility, calculating the VP values is done by software within the DSP core. Notice that VP values are symmetric, , thus requiring the storage of only half of the L-metric table in the VP RAM. For a 64-state trellis (constraint length equals 7), the VP values for each state are calculated in an analogous way making use of S parameters S1 to S7.

Figure 13-16 Viterbi Butterfly Structure

Decode Equalization

AA1325

BM

BM

–BM

–BM

0xyz

1xyz

xyz0

xyz1

(MF–VP0xyz)

–(MF–VP1xyz)(M

F–VP 1xyz)

–(MF–VP0xyz )

0xyz

1xyz

xyz0

xyz1

VP w x y z, , ,( ) 1–( )wS4⋅ 1–( )x

S3 1–( )yS2 1–( )z

S1⋅+⋅+⋅+=

VP w x y z, , ,( ) VP w x y z, , ,( )–=

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13.8 PERFORMANCE ANALYSIS

The following table summarizes maximal VCOP performance in various GSM channels.

The number of cycles required to decode one bit grows exponentially depending on the constraint length.

The VCOP processing time for other codes can be estimated using the following equations, where values are as shown in Table 13-12 :

Table 13-11 Performance of Various GSM Channels

Channel Type Rate Constraint

LengthTrellis States

Data Bits In a Block (After

Decode)

Clock Cycles1 (for

Block Transfer)

Time1 At 80 Mhz (For

Block Transfer)

TCH / F9.6 1/2 5 16 244 8,416 105.2 µs

TCH / F4.8 1/3 5 16 152 5,472 68.4 µs

TCH / F2.4 1/6 5 16 72 2,912 36.4 µs

TCH / FS 1/2 5 16 189 6,656 83.2 µs

TCH / H4.8 1/2 5 16 244 8,416 105.2 µs

TCH / H2.4 1/3 5 16 152 5,472 68.4 µs

TCH / HS 1/3 7 64 104 14,016 175.2 µs

Equalization N/A 16 61 2,656 33.2 µs



Note: 1. Setup and reset time excluded.

Table 13-12 Variables for Calculating Processing Time

Symbol Number Meaning

S Trellis_States

P Bits_to_Process

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• Total processing time for equalization (Teq):

• Total processing time for decoding (Td):

Note that:

• The reset time is negligible.

• The setup time is small but variable – about 80 cycles for equalization, and about 40 cycles for decoding.

The equations for processing time are derived from the following:

• Total processing time (TTotalProcess):

• Time to perform one stage (Tstage):

L Bits_Left_in_Buffer

F Clock_Frequency

Table 13-12 Variables for Calculating Processing Time

Symbol Number Meaning

Teq2 S P( 1) L+ +( ) 704+

F-------------------------------------------------------=

Td2 S P( 1) L+ +( ) 576+

F-------------------------------------------------------=

TTotalProcess Bits_to_Process 1+( ) Tstage× T flush Treadbuff+ +=

Tstage Trellis_StatesTacs

2----------×=

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• Time required to perform one ACS butterfly (Tacs):

• Cycle time (Tc):

• Flush time (Tflush):

– The flush time differs for equalization and decoding.

– In equalization, the time for generation of data at flush is:

Note: This equation has not been verified, and may be inaccurate.

– In decoding, the time for BER calculation time at flush is:

• Time required for reading data out of the VCOP (Treadbuff):

Tacs 4 Tc×=

Tc1

Clock_Frequency------------------------------------------=

T flush 36 8+( ) 16Tc× 704Tc= =

T flush 36 16Tc× 576Tc= =

Treadbuff Bits_Left_in_Buffer( ) 2Tc×=

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Programming Examples


13.9 PROGRAMMING EXAMPLES

13.9.1 Channel Encode

;#############################################################################;; VCOP Encode with Rate=1/2 and Constraint_length=5;; Revised: June ‘96;;#############################################################################

START equ $100

include “ioequz.asm” include “intequz.asm”

org P:0 jmp START

org P:START move #$250,r5 ; Output Buffer move #$200,r6 ; Encoder Input movep #60,y:M_VCNT ; 61 input bits to be encoded (example) movep #$1c65,y:M_VTPA ; program tap polynomials

movep #$1009,y:M_VCRA ; enable Encoding mode do #61,endd jclr #8,y:M_VSTR,* ; wait till DREQ movep x:(r6)+,y:M_VDR ; input data nop ; pipeline delay nop ; (see section B-5.1 in DSP56300 Family Manual)endd jclr #5,y:M_VSTR,* ; wait till Proc_Done

rep #122 ; 122 output bits from encoder (Rate=1/2) movep y:M_VDOR,y:(r5)+

jclr #4,y:M_VSTR,* ; wait till OPC

stop

org x:$200 ; Input to the Encoder

dc $800000dc $800000dc $7F0000

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dc $7F0000dc $800000dc $800000dc $7F0000dc $7F0000dc $800000dc $800000dc $7F0000dc $7F0000dc $800000dc $800000dc $7F0000dc $7F0000dc $800000dc $800000dc $800000dc $800000dc $7F0000dc $7F0000dc $800000dc $7F0000dc $800000dc $800000dc $7F0000dc $7F0000dc $800000dc $7F0000dc $7F0000dc $7F0000dc $800000dc $800000dc $7F0000dc $7F0000dc $800000dc $800000dc $7F0000dc $7F0000dc $800000dc $800000dc $7F0000dc $7F0000dc $800000dc $800000dc $7F0000dc $7F0000dc $800000dc $800000dc $800000dc $800000dc $7F0000dc $7F0000dc $800000dc $7F0000

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dc $800000dc $800000dc $7F0000dc $7F0000dc $800000

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13.9.2 Channel Decode

;#############################################################################; VCOP Decode with Rate=1/3 and Constraint_length=5;; Revised: June ‘96;#############################################################################

START equ $100

include “ioequz.asm” include “intequz.asm”

org P:0 jmp START

org P:START move #$0,r0 ; pointer to input symbols. move #$0,r4 ; pointer to BER and WED results move #$250,r5 ; Output Buffer movep #60,y:M_VCNT ; 61 decoded bits movep #$1c45,y:M_VTPA ; tapa=1+D+D 3̂+D 4̂,tapb=1+D 2̂+D 4̂,tapc=1+D+D 2̂+D 3̂+D 4̂ movep #$0000,y:M_VTSR ; ES=0,IS=0 movep #$1010,y:M_VWES ; set WED start location and window length movep #$0041,y:M_VCRB ; Init_state,Max_path enable,WED enable; movep #$1105,y:M_VCRA ; Enable Decoding at Rate 1/3 cnst=5 do #61,endd jclr #8,y:M_VSTR,* ; wait till DREQ; rep #3 movep x:(r0)+,y:M_VDR ; read input symbols nop ; pipeline delay nop ; (see section B-5.1 in DSP56300 Family Manual)endd jclr #5,y:M_VSTR,* ; wait till Proc_Done jclr #6,y:M_VSTR,* ; wait till DRDY; movep y:M_VBER,y:(r4)+ ; read BER (Rx Qual) value movep y:M_VWED,y:(r4)+ ; read WED value; rep #61 ; read decoded bits from output buffer movep y:M_VDOR,y:(r5)+

jclr #4,y:M_VSTR,* ; wait till OPC stop

org x:$0 ; Input to decoder, 61x3 symbolsdc $800000dc $800000dc $800000

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dc $7fff00dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $7fff00dc $7fff00

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dc $800000dc $800000dc $7fff00dc $7fff00dc $800000dc $7fff00dc $7fff00dc $7fff00dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $7fff00dc $800000dc $7fff00dc $800000dc $7fff00dc $7fff00dc $800000dc $800000dc $800000dc $7fff00dc $7fff00dc $800000dc $800000dc $800000dc $7fff00dc $800000dc $7fff00dc $800000dc $7fff00dc $800000dc $7fff00dc $7fff00dc $800000dc $800000dc $800000dc $7fff00dc $800000dc $7fff00dc $7fff00dc $7fff00dc $7fff00dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000

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dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $7fff00dc $800000dc $800000dc $7fff00dc $800000dc $7fff00dc $7fff00dc $800000dc $800000dc $7fff00dc $7fff00dc $800000dc $7fff00dc $7fff00dc $7fff00dc $7fff00dc $800000

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dc $800000dc $7fff00dc $800000dc $7fff00dc $800000dc $7fff00dc $800000dc $7fff00dc $7fff00dc $800000dc $800000dc $800000dc $7fff00dc $7fff00dc $800000dc $800000dc $800000dc $7fff00dc $800000dc $7fff00dc $800000

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13.9.3 Channel Equalization with DMA, including Read/Write Memory Access

;#############################################################################;; VCOP Equalization Test including examples of Memory Access; This test activates the DMA for data input and output;; Revised: June ‘96;;#############################################################################

START equ $100

include “ioequz.asm”include “intequz.asm”

org P:0 jmp START

org P:START move #$150,r2 ; pointer to input data (from MF output) move #$1a0,r3 ; pointer to VP parameters move #$1e0,r4 ; pointer to SP parameters move #$200,r5 ; pointer to output data

movep #$0063,y:M_VCRB ; enable Init_State (IS) and End_state (ES) ; hard data format in output buffer movep #$0003,y:M_VCRA ; enable Memory Access

;************************************; Memory access to initialize the VP memory;************************************ movep #$0000,y:M_VBER ; VP memory address rep #8 movep x:(r3)+,y:M_VMEM ; Load VP

;************************************; Memory access to initialize the SP memory (not necessary);************************************ movep #$0040,y:M_VBER ; SP memory address rep #7 movep x:(r4)+,y:M_VMEM ; Load SP

;************************************; Example of memory access to read the VP memory in VCOP (not necessary);************************************

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movep #$0000,y:M_VBER nop ; pipeline delay nop ; pipeline delay movep y:M_VMEM,y:(r4) ; dummy read movep y:M_VMEM,y:(r4) ; dummy read rep #8 movep y:M_VMEM,y:(r4)+

;************************************; Example of memory access to read the SP memory in VCOP (not necessary);************************************ movep #$0040,y:M_VBER nop ; pipeline delay nop ; pipeline delay movep y:M_VMEM,y:(r4) ; dummy read movep y:M_VMEM,y:(r4) ; dummy read rep #7 movep y:M_VMEM,y:(r4)+

;************************************; Process First Half of Normal Burst;************************************; Initialize input DMA channel movep #$150,x:M_DSR0 ; source address movep #M_VDR,x:M_DDR0 ; destination address movep #60,x:M_DCO0 ; 61 bits (61 transfers) movep #$8CAA54,x:M_DCR0 ; word transfers

; Initialize output DMA channel movep #M_VDOR,x:M_DSR1 ; source address movep #$0,x:M_DDR1 ; destination address movep #60,x:M_DCO1 ; 61 bits (61 transfers) movep #$86C2C1,x:M_DCR1 ; block transfer

movep #60,y:M_VCNT ; 61 bits (half of Normal Burst) movep #$0401,y:M_VTSR ; ES=4,IS=1 movep #$1011,y:M_VCRA ; enable Equalization mode

jclr #4,y:M_VSTR,* ; wait till OPC nop nop

;************************************; Process Second Half of Normal Burst;************************************; Initialize input DMA channel movep #$200,x:M_DSR0 ; source address movep #M_VDR,x:M_DDR0 ; destination address movep #60,x:M_DCO0 ; 61 bits (61 transfers)

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movep #$8CAA54,x:M_DCR0 ; word transfers

; Initialize output DMA channel movep #M_VDOR,x:M_DSR1 ; source address movep #$0,x:M_DDR1 ; destination address movep #60,x:M_DCO1 ; 61 bits (61 transfers) movep #$86C2C1,x:M_DCR1 ; block transfer

movep #60,y:M_VCNT ; 61 bits (half of Normal Burst) movep #$000e,y:M_VTSR ; ES=0,IS=$E movep #$1011,y:M_VCRA ; enable Equalization mode

jclr #5,y:M_VSTR,* ; wait till Proc_Done jclr #4,y:M_VSTR,* ; wait till OPC nop nop

stop

org x:$150 ; First half Input data (output of Match Filter)

dc $f1cb00dc $f6ac00dc $f4c300dc $efbf00dc $f02000dc $073100dc $f55600dc $f28500dc $0dde00dc $f33100dc $f47f00dc $fad600dc $135700dc $fc4800dc $f30000dc $076800dc $0be400dc $03db00dc $115000dc $062b00dc $f2ed00dc $052600dc $f40f00dc $071500dc $0a8400dc $ee7300dc $0ac800

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dc $03ed00dc $fa7b00dc $fc3800dc $f8d100dc $072500dc $06b800dc $0fe300dc $08e500dc $105500dc $f43300dc $099c00dc $ffb600dc $f72d00dc $075100dc $0b3c00dc $104f00dc $f8f400dc $0a6800dc $061b00dc $083300dc $145c00dc $0b4900dc $146f00dc $09fd00dc $f7b000dc $f9fa00dc $f97f00dc $f19f00dc $f06400dc $024100dc $0ac000dc $11d500dc $0c6a00dc $f36f00

org x:$1a0 ; VP Parameters (16 states = 8 params)

dc $ffca00dc $ffca00dc $003500dc $003500dc $ffca00dc $ffca00dc $003500dc $003500

org x:$200 ; Second half Input data (output of Match Filter)

dc $f73200dc $edfc00dc $f0b200dc $063500dc $f57a00

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dc $084200dc $04db00dc $f4b500dc $05a600dc $fcd900dc $087400dc $0b1000dc $09ba00dc $ee4200dc $f26a00dc $06c900dc $0a3800dc $fd9f00dc $f1a300dc $031e00dc $fe9f00dc $f5b700dc $f2b800dc $f8dd00dc $0eab00dc $10e700dc $f26d00dc $f76300dc $09fd00dc $f8b000dc $faee00dc $0a1900dc $fd0100dc $0c0600dc $0ecc00dc $f78900dc $f63700dc $fd1900dc $f41c00dc $f24f00dc $049100dc $05fc00dc $150c00dc $efcd00dc $05f000dc $013700dc $f87400dc $0c1e00dc $f0f500dc $f1a700dc $f51e00dc $f50a00dc $f3c700dc $0b5300dc $f7b300dc $0c8d00dc $f87c00dc $09c800

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dc $05d900dc $000000dc $000000

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References


13.10 REFERENCES

The following articles are cited within this chapter.

1. Ungerboeck, Gottfried 1974. Adaptive Maximum-Likelihood Receiver for Carrier-Modulated Data-Transmission Systems. IEEE Transactions on Communications vol. COM-22, no. 5:624–636. May 1974.2. Forney, G. David, Jr. 1973. The Viterbi Algorithm. Proceedings of the IEEE, vol. 61 no. 3:268–278. March 1973.3. Koch, Wolfgang, and Baier, Alfred 1990. “Optimum and Sub-optimum Detection of Coded Data Disturbed by Time-varying Intersymbol Interference,” in Communications: Connecting the Future, vol. 3:1679–1684. Global Telecommunications Conference and Exhibition, San Diego, Dec. 2–5, 1990. (IEEE catalog number 90CH2827–4).

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References

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CYCLIC CODE CO-PROCESSOR


SECTION 14


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14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-314.2 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-314.3 CCOP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-414.4 CCOP Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-614.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-2114.6 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . .14-2314.7 Configuration Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-27

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Introduction


14.1 INTRODUCTION

The Cyclic Code Co-Processor (CCOP) is a peripheral module which executes cyclic code calculations for data ciphering and deciphering and parity coding generation and checking. The CCOP is designed to operate independently of the DSP56300 core, requiring minimal CPU-time overhead. This peripheral is fully programmable and not dedicated to any specific algorithm, although it is well suited for the GSM A5.x data ciphering algorithms.

CCOP data processing occurs in four programmable CCOP Linear Feedback Shift Registers (CFSR[A:D]). For each CFSR, there are four control registers which configure its operation: CCOP Feedback Tap Register (CFBT[A:D]), CCOP Feedforward Tap Register (CFFT[A:D]), CCOP Bit Select Register (CBSR[A:D]), and CCOP Mask Register (CMSK[A:D]).

The CCOP has four operational modes, two each for cipher and parity coding. The modes are:

• Normal Cipher Mode (CFSR[A:D] enabled)

• Step-by-step Cipher Mode (CFSR[A:D] enabled)

• Parity Coding Mode using one CFSR (CFSRA only enabled)

• Parity Coding Mode using two concatenated CFSRs (CFSRA and CFSRB enabled)

14.2 KEY FEATURES

• Contains fully programmable cyclic code engine

• Operates concurrently with the DSP56300 core with minimal CPU intervention

• Generates mask sequences for data ciphering

• Supports Fire encoding and decoding for burst error correction using any generator polynomial of any degree up to 48

• Generates Cyclic Redundancy Code (CRC) syndrome using any generator polynomial of any degree up to 48

• Provides a 5 × 24-bit word input/output FIFO accessible via core or DMA

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CCOP Block Diagram

14.3 CCOP BLOCK DIAGRAM

The CCOP architecture is shown in Figure 14-1.

14.3.1 Cipher Mode Register Configuration

Figure 14-2 shows how the control register contents relate to CFSR configuration in the Cipher modes.

Figure 14-1 CCOP Block Diagram

CFSR

Feedback Taps

Feedfwd Taps

Bit Select

Mask TapsInput Counter

Run Counter

Output Counter

Input Data Buffer

Output Data Buffer

Control

PMBInterface

8 × 4 bitStep

FunctionTable

Data FIFO Bank

AA1300

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CCOP Block Diagram


14.3.2 Parity Coding Modes Register Configuration

Figure 14-3 shows how the control register contents relate to CFSR configuration in the Parity Coding modes.

Figure 14-2 CFSR Configuration in the Cipher Modes

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAJ

InputData

OutputData

Feedback

Feedforward Tap

Majority Bit SelectMajority Mask

ToSteppingFunction

Feedback Tap 0001 0001 0000 0100 0001 0000

Feedfwd Tap 0000 0000 1000 1000 0000 0000

Bit Select 0000 1000 0010 0010 0000 0000

Mask Tap 0000 1000 0000 0000 0000 0000

InputData

’0’

AA1301

Tap

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CCOP Programming Model

14.4 CCOP PROGRAMMING MODEL

The CCOP registers available to the programmer are shown in Table 14-1. All accessible registers are mapped into the internal I/O memory space. These registers may be accessed through regular MOVE instructions or by peripheral move (MOVEP) instructions.

The registers are discussed in the following sections by functional block:

• Input/Output

– CCOP Data FIFO Register (CDFR)

• Count Register

– CCOP Count Register (CCNT)

• Step Function

– CCOP Step Function Select Register (CSFS),

– CCOP Step Function Table A (CSFTA),

Figure 14-3 CFSR Configuration in the Parity Coding Modes

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Feedback Tap 0001 0000 0000 0101 0010 0000

Feedfwd Tap 0000 0100 1000 0001 0000 0000

Bit Select 1111 1111 1111 0000 0000 0000

Mask Tap 0000 0000 0000 0000 0000 0100

Feedback Tap

InputData

Feedfwd Tap

Mask

Zero Detect

Bit

’0’

InputData

AA1302

Select

Tap

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– CCOP Step Function Table B (CSFTB)

• Control Register

– CCOP Control Register (CCSR)

• Cyclic Code Processing

– CCOP Linear FeedBack Shift Register A–D (CFSR[A:D]),

– CCOP FeedBack Tap Register A–D (CFBT[A:D])

– CCOP FeedForward Tap Register A–D (CFFT[A:D])

– CCOP Bit Select Register A–D (CBSR[A:D])

– CCOP Mask Register A–D (CMSK[A:D])

Note: The Cyclic Code Processing Registers exist in four functionally identical sets (for instance, CFSRA, CFSRB, CFSRC, and CFSRD are CCOP Linear Feedback Shift Registers for sets A, B, C, and D, respectively). They are discussed below generically (for instance, as CFSRz), but each set must be programmed independently. In the Parity Coding Modes sets C and D are never available, and B is available only when using both A and B together.

Table 14-1 CCOP Programming Model

Base Address Register Name Register

Abbreviation

$0 CCOP Data FIFO Register CDFR

$2 CCOP Count Register CCNT

$3 CCOP Step Function Select Register CSFS

$4 CCOP Step Function Table A CSFTA

$5 CCOP Step Function Table B CSFTB

$6 CCOP Control Status Register CCSR

$8 CCOP Linear FeedBack Shift Register A CFSRA

$9 CCOP FeedBack Tap Register A CFBTA

$A CCOP FeedForward Tap Register A CFFTA

$B CCOP Bit Select Register A CBSRA

$C CCOP Mask Register A CMSKA

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14.4.1 CCOP Data FIFO Register (CDFR)

The CCOP Data FIFO Register (CDFR) is a 24-bit read/write 5-word deep FIFO register used to store input and output data during the CCOP processing. When CCOP is in the Idle state or in the input phase, CDFR operates as an input data FIFO, and expects data from the DSP56300 core for processing. To load it, up to five successive writes to the same memory location should be executed. If less than 120 bits are to be processed, the value of the unused bits is disregarded.

Data is clocked from the CDFR into the any or all of the CFSRs under the control of the Input Counter of the CCNT (IC[7:0], CCNT bits 0–7). They are shifted in Least Significant Bit (LSB) first.

$10 CCOP Linear FeedBack Shift Register B CFSRB

$11 CCOP FeedBack Tap Register B CFBTB

$12 CCOP FeedForward Tap Register B CFFTB

$13 CCOP Bit Select Register B CBSRB

$14 CCOP Mask Register B CMSKB

$15 CCOP Linear FeedBack Shift Register C CFSRC

$16 CCOP FeedBack Tap Register C CFBTC

$17 CCOP FeedForward Tap Register C CFFTC

$18 CCOP Bit Select Register C CBSRC

$19 CCOP Mask Register C CMSKC

$1A CCOP Linear FeedBack Shift Register D CFSRD

$1B CCOP FeedBack Tap Register D CFBTD

$1C CCOP FeedForward Tap Register D CFFTD

$1D CCOP Bit Select Register D CBSRD

$1E CCOP Mask Register D CMSKD

Table 14-1 CCOP Programming Model

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On the cycle when the Input Counter reaches zero, CFSR input is disabled and the next algorithm phase starts, driven by the Run Counter of the CCNT (RC[7:0], CCNT bits 8–15).

When CCOP is in the output phase, CDFR operates as an output data FIFO, i.e. it stores the output data resulted by the CCOP processing and expects the DSP56300 core to read it. Output data words are also generated and stored into the CDFR LSB first. CDFR is accessible via core or DMA. The FIFO state machine is reset to its initial state by hardware, software or CCOP individual reset.

14.4.2 CCOP Count Register (CCNT)

The CCOP Count Register (CCNT) is a 24-bit read/write register which holds the Input Counter, Run Counter, and Output Counters. CCNT should be written at initialization to set up the above counters, according to the algorithm to be processed by CCOP. The CCNT bits are shown in Figure 14-4 and are described in the following paragraphs.

14.4.2.1 Input Counter (IC[7:0])—CCNT Bits 7–0The Input Counter (IC[7:0]) is the first byte of the CCNT register. It specifies how many bits in the CDFR are to be input into the CFSRs (the range is 0 to 120). After loading the input data into the CDFR, the user should load this counter with the number of valid bits to be shifted (one bit at a time) into the CFSRs. Starting on the following cycle, the Input Counter decrements itself each cycle until it reaches zero. Each cycle that the Input Counter is non-zero, the clock for the shift register is enabled causing a new bit to be input to the CFSRs. The Input Counter is valid if CM (CCNT bit 23) is cleared, and ignored if it is set.

14.4.2.2 Run Counter (RC[7:0])—CCNT Bits 15–8The Run Counter (RC[7:0]) is the middle byte of the CCNT register. It specifies how many cycles the CFSRs are to be shifted for the run phase, without any new data being input (i.e. the data in the CFSRs will be modified only by the action of the feedback taps

Figure 14-4 CCOP Count Register (CCNT)

11 10 9 8 7 6 5 4 3 2 1 0

RC3 RC2 RC1 RC0 IC7 IC6 IC5 IC4 IC3 IC2 IC1 IC0

23 22 21 20 19 18 17 16 15 14 13 12

CM OC6 OC5 OC4 OC3 OC2 OC1 OC0 RC7 RC6 RC5 RC4AA1303

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during this phase). After loading the input data into the CDFR, the user should load this counter with the number of processing cycles desired. Starting with the cycle after the input phase is completed, the Run Counter decrements itself each cycle until it reaches zero. Each cycle the Run Counter is non-zero, the CFSRs perform a shift.

14.4.2.3 Output Counter (OC[6:0])—CCNT Bits 22–16The Output Counter (OC[6:0]) specifies how many bits in the CFSRs are to be sent to the CDFR as output (the range is 0 to 120). After loading the input data into the CDFR, the user should load this counter with the number of valid bits to be shifted (one bit at a time) into the CDFR as output. Starting with the cycle after the run phase is completed, the Output Counter decrements itself each cycle until it reaches zero. Each cycle the Output Counter is non-zero, the outputs from all four CFSRs are XORed together and the resulting bit is shifted into the CDFR as output. The Stepping function is enabled during the Output Counter operation. When the Output Counter reaches zero, the CCOP generates an interrupt indicating to the DSP56300 core that it has finished processing.

14.4.2.4 Continuous Mode (CM)—CCNT Bit 23The Continuous Mode (CM) bit enables the CCOP to operate continuously. When CM is cleared, the CCOP operates on input data blocks of length defined by the Input Counter, then it passes to the run and output phases according to the Run Counter and Output Counter respectively. When CM is set, the Input Counter, Run Counter and Output Counters are ignored and the CFSRs operate in a continuous mode, i.e. upon receiving a new data word, it is shifted into the enabled CFSRs. Only the input phase is activated when CM is set, while the run and output phases are disabled. The continuous mode can be used, for example, to calculate a CRC syndrome value of a large data block transferred to CCOP via core or DMA.

14.4.3 Step Function Registers

The Step Function Registers perform the step functions, one register (CSFS) defining the address to the Step Function Table, the other two (CSFTA and CSFTB) containing the Step Function Table. The eight words in this table are written at initialization. Each of the four output bits of the table controls one CFSR, and is interpreted as shift (one) or no-shift (zero) by the CFSR. The stepping function starts operation after the Input Counter reaches zero, and stops after the Output Counter reaches zero (i.e., it is enabled when the Run Counter and Output Counter are active).

14.4.3.1 Step Function Select Register (CSFS)The Step Function Select Register (CSFS) is a 24-bit read/write register used to select three bits from anywhere in the CFSRs. These bits form the address to the 8 × 4-bit Step Function Table. The register is composed of three bit-sized subregisters (lettered A, B,

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and C), each determining one bit in the address. The subregisters are divided into three parts: a bit select (5 bits, abbreviated SBxx), a register select (2 bits, abbreviated SRxx), and a reserved bit (without name). The CSFS bits are shown in Figure 14-5 and are described in the following paragraphs.

14.4.3.1.1 Select Bit A (SBA[4:0])—CSFS Bits 4–0The Select Bit A (SBA[4:0]) bits determine which bit (0 to 23) in a particular CFSR is selected as the first (LSB) address line of the Step Function Table. Which CFSR is used is determined by bits SRA[1:0] in CSFS. The values 24 to 31 are invalid and should not be used.

14.4.3.1.2 Select Register A (SRA[1:0])—CSFS Bits 6–5The Select Register A (SRA[1:0]) bits select which CFSR from which the selected bit (by SBA[4:0]) is connected to the first (LSB) address line of the Step Function Table. The combination of SBA[4:0] and SRA[1:0] determine which bit of which CFSR is used as the first address line of the Step Function Table.

14.4.3.1.3 Select Bit B (SBB[4:0])—CSFS Bits 12–8The Select Bit B (SBB[4:0]) bits determine which bit (0 to 23) in a particular CFSR is selected as the second (middle byte) address line of the Step Function Table. Which CFSR is used is determined by bits SRB[1:0] in CSFS. The values 24 to 31 are invalid and should not be used.

14.4.3.1.4 Select Register B (SRB[1:0])—CSFS Bits 14–13The Select Register B (SRB[1:0]) bits select which CFSR from which the selected bit (by SBB[4:0]) is connected to the second (middle byte) address line of the Step Function Table. The combination of SBB[4:0] and SRB[1:0] determine which bit of which CFSR is used as the second address line of the Step Function Table.

Figure 14-5 Step Function Select Register (CSFS)

11 10 9 8 7 6 5 4 3 2 1 0

SBB3 SBB2 SBB1 SBB0 SRA1 SRA0 SBA4 SBA3 SBA2 SBA1 SBA0

23 22 21 20 19 18 17 16 15 14 13 12

SRC1 SRC0 SBC4 SBC3 SBC2 SBC1 SBC0 SRB1 SRB0 SBB4

Reserved bit, Read as zero, should be written with zero for future compatibility AA1304

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14.4.3.1.5 Select Bit C (SBC[4:0])—CSFS Bits 20–16The Select Bit C (SBC[4:0]) bits determine which bit (0 to 23) in a particular CFSR is selected as the last (MSB) address line of the Step Function Table. Which CFSR is used is determined by bits SRC[1:0] in CSFS. The values 24 to 31 are invalid and should not be used.

14.4.3.1.6 Select Register C (SRC[1:0])—CSFS Bits 22–21The Select Register C (SRC[1:0]) bits select which CFSR from which the selected bit (by SBC[4:0]) is connected to the last (MSB) address line of the Step Function Table. The combination of SBC[4:0] and SRC[1:0] determine which bit of which CFSR is used as the last address line of the Step Function Table.

14.4.3.1.7 Reserved Bits—CSFS Bits 7, 15, 23These bits are reserved and should be written as zero for future compatibility.

14.4.3.2 Step Function Table A (CSFTA)The Step Function Table A (CSFTA) is a 24-bit read/write register containing the first six words of the Step Function Table. The words are 4-bit width.

14.4.3.3 Step Function Table B (CSFTB)The Step Function Table B (CSFTB) is a 24-bit read/write register containing the last two 4-bit words of the Step Function Table. In addition, CSFTB is used to enable the data input into the CFSRs during the input phase (using INE[3:0], CSFTB Bits 19–16), and to enable the data output data from the CFSRs during the output phase (using OUT[3:0], CSFTB Bits 23–20).

Figure 14-6 Step Function Table A Register (CSFTA)

11 10 9 8 7 6 5 4 3 2 1 0

WRDC3 WRDC2 WRDC1 WRDC0 WRDB3 WRDB2 WRDB1 WRDB0 WRDA3 WRDA2 WRDA1 WRDA0

23 22 21 20 19 18 17 16 15 14 13 12

WRDF3 WRDF2 WRDF1 WRDF0 WRDE3 WRDE2 WRDE1 WRDE0 WRDD3 WRDD2 WRDD1 WRDD0

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Together, CSFTA and CSFTB form the Step Function Table as shown in Table .

14.4.3.4 Input Enable bits (INE[3:0])—CSFTB Bits 19–16The Input Enable bits (INE[3:0]) are used to enable data input into CFS[D:A] respectively during the input phase. When the INEx bit is cleared, data input to CFSRz is disabled for the input phase. When the INEx bit is set, data input to CFSRz is enabled for the input phase. Table 14-3 lists the bit numbers and their corresponding registers.

Figure 14-7 Step Function Table B Register (CSFTB)

Table 14-2 Step Function Table

Word Address Data Bits Bit Location

0 WRDA[3:0] CSFTA 3–0

1 WRDB[3:0] CSFTA 7–4

2 WRDC[3:0] CSFTA 11–8

3 WRDD[3:0] CSFTA 15–12

4 WRDE[3:0] CSFTA 19–16

5 WRDF[3:0] CSFTA 23–20

6 WRDG[3:0] CSFTB 3–0

7 WRDH[3:0] CSFTB 7–4

11 10 9 8 7 6 5 4 3 2 1 0

WRDH3WRDH2WRDH1WRDH0WRDG3WRDG2WRDG1WRDG0

23 22 21 20 19 18 17 16 15 14 13 12

OUTE3 OUTE2 OUTE1 OUTE0 INE3 INE2 INE1 INE0


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When CCOP operates in the Parity Coding Mode Using One CFSR (OPM[1:0] = 10 in CCSR), INE[3:1] are not applicable since only CFSRA is active (the remaining CFSRs are disabled). INE0 is used to enable (INE0 = 1) or disable (INE0 = 0) data input to the feedback path of the active CFSR. Data input to the feedforward path is always enabled and is not affected by INEx bits.

When CCOP operates in the Parity Coding Mode Using Two Concatenated CFSRs (OPM[1:0] = 11 in CCSR), INE[3:2] are not applicable since only CFSRA and CFSRB are active while CFSRC and CFSRD are disabled. In this mode INE0 must be equal to INE1 for proper operation of the concatenated scheme. INE0 = INE1 = 1 enables the input data bit to the feedback path of the concatenated CFSR. INE0 = INE1 = 0 disables the input data bit to the feedback path of the concatenated CFSR. The input data to the feedforward path is always enabled and not affected by INEx.

14.4.3.5 Output Enable bits (OUTE[3:0])—CSFTB Bits 23–20The Output Enable bits (OUTE[3:0]) are used to enable output from CFSR[D:A] respectively during the output phase. When OUTEx is cleared, the output bit from CFSRz is gated, so it does not affect the final output data bit (generated by XORing all enabled output bits from the CFSRs). When OUTEx bit is set, the output bit from CFSRz is enabled, and it is XORed together with other CFSR enabled output bits to form the output data bit that goes to the output buffer.

14.4.4 CCOP Control Status Register (CCSR)

The CCOP Control Status Register (CCSR) is a 24-bit read/write register used to control and interrogate the operation of the CCOP. The CCSR bits are shown in Figure 14-8 and are described in the following paragraphs. Control bits in the CCSR should not be changed while the CCOP is operating, except for the interrupt enable bits, otherwise improper operation may result. The control bits OPM[1:0] and LRC (which select the CFSR configuration) should only be changed when CCOP is in the CCOP individual

Table 14-3 INE[3:0], OUTE[3:0] Bits and their Respective CFSRs

Bit Number Register Letter

0 A

1 B

2 C

3 D

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reset state (CEN = 0). Other control bits in CCSR can be changed when CCOP is in the CCOP individual reset state, or when the processing is idle (PREN = 0).

14.4.4.1 Enable bit (CEN)—CCSR Bit 0The CCSR Enable bit (CEN), when set, enables the operation of the CCOP. When CEN is cleared, the operation is disabled and the CCOP is in the CCOP individual reset state. While in the CCOP individual reset state, internal state machine logic and status bits are reset to the same state produced by hardware or software reset, while control bits are not affected.

14.4.4.2 Processing Enable bit (PREN)—CCSR Bit 1The Processing Enable bit (PREN), when set, enables the CCOP to start processing according to the specified configuration, counter settings and control bits. When CEN is set and PREN is cleared, CCOP is in the Idle state. While in the Idle state, all CCOP processing is frozen and data in registers and the FIFO is preserved, thus allowing the programmer to read, write or modify counters, shifters, configuration and control registers as well as accessing the FIFO. The counters, CFSR configuration registers and control registers must be assigned prior to setting PREN. Following assertion, the PREN bit is cleared automatically by the internal logic after completion of some sort of processing depending on the selected operation mode. While not in the Step-by-step mode, PREN is cleared at the end of the shift processing, i.e. after the input, run and output phases have been completed. While in the Step-by-step mode (OPM[1:0] = 01) PREN is cleared (and thus returns to the Idle state) after executing one single shift. PREN can also be explicitly cleared by software forcing cessation of operation.

14.4.4.3 Operating Mode bits (OPM[1:0])—CCSR Bits 5–4The Operating Mode bits (OPM[1:0]) are used to determine the CFSR’s mode of operation. The operating modes supported in CCOP are shown in Table . OPM[1:0] should be changed only when CCOP is in CCOP individual reset.

Figure 14-8 CCOP Control Status Register (CCSR)

11 10 9 8 7 6 5 4 3 2 1 0

FOSH HOZD LRC OPM1 OPM0 PREN CEN

23 22 21 20 19 18 17 16 15 14 13 12

PCDN CIDN OFNE INFE INBE PDIE CDIE DOIE DIIE


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14.4.4.4 Left-Right Connection bit (LRC)—CCSR Bit 8The Left-Right Connection bit (LRC) determines whether the input data bit is connected to the left or right end of the CFSRs, if enabled. The input data is connected to the left end of the CFSR when LRC is cleared, and to the right end when LRC is set. In the Parity Coding mode with concatenated CFSRs (OPM[1:0] equals 11) the first two CFSRs (if enabled by INE[1:0] bits in CSFTB) are treated as one long CFSR, and thus the input data is connected either to the left end of CFSRB (LRC cleared) or to the right end of CFSRA (LRC set). LRC should only be changed when CCOP is in CCOP individual reset.

14.4.4.5 Halt On Zero Detect bit (HOZD)—CCSR Bit 9The Halt On Zero Detect control bit (HOZD) bit, when set, halts CCOP processing if a zero is detected by the Zero Detect function during the run phase. This bit is directly related to the Zero Detect function, thus it is operational in the Parity Coding modes and ignored in the Cipher modes. When HOZD is cleared, the Zero Detect function does not affect processing, and Parity Coding processing terminates after the Run Counter reaches zero (Note that the output phase is disabled in the Parity Coding modes). When HOZD is set, Parity Coding processing terminates when any of the following are zero in the run phase:

• the Run Counter

• the bits specified by the Bit Select register CBSRA in Parity Coding Mode using one CFSR (OPM[1:0] = 10)

Table 14-4 CCOP Operation Modes

OPM[1:0] Mode of operation

00 Normal Cipher mode

01 Step-by-step Cipher mode

10 Parity Coding mode using one CFSR

11 Parity Coding mode using two concatenated CFSRs

Table 14-5 LRC Settings

LRC Description

0 Connect Input Data to Left End of CFSR

1 Connect Input Data to Right End of CFSR

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• the bits specified by the Bit Select registers CBSRA or CBSRB in Parity Coding Mode using two concatenated CFSRs (OPM[1:0] = 11)

In this case the processing is terminated (PREN is cleared and PCDN is set) and the Run Counter can be used to calculate the pointer to the erroneous burst in the data sequence that should be corrected.

14.4.4.6 Force Shift bit (FOSH)—CCSR Bit 10The FOrce SHift bit (FOSH) is a control bit used to force an unconditional extra shift in all CFSRs during a Cipher processing session. FOSH is operational in the Step-by-step Cipher mode only (OPM[1:0] = 01), and is ignored otherwise. When FOSH is cleared and a new step is activated (PREN is set), a single shift is executed to CFSRs selected according to the Step Function Table (if this step belongs to the run or output phase), the associated counter is decremented (which counter is decremented depends on which processing phase this particular step belongs to), and an output bit is generated (if this step belongs to the output phase). After this single step is accomplished PREN is automatically cleared causing CCOP to re-enter the Idle state. When FOSH is set and a new step is activated (PREN is set) a single shift is forced to all CFSRs independent of the Step Function Table. This extra shift can be inserted at any Cipher processing operating phase. It does not cause any counter decrement and (if executed in the output phase) does not generate an output bit to the output FIFO. Combining doing a single step with FOSH cleared and a single step with FOSH set accomplishes one step of the Cipher process in which the stepping function varies between 1 and 2 shifts instead of 0 and 1 shift.

14.4.4.7 Data In Interrupt Enable bit (DIIE)—CCSR Bit 12The Data In Interrupt Enable bit (DIIE), when set, enables the interrupt caused by the input FIFO empty signal (when the INFE bit, CCSR Bit 20, is set). When INFE is cleared, the interrupt is disabled.

14.4.4.8 Data Out Interrupt Enable bit (DOIE)—CCSR Bit 13The Data Out Interrupt Enable bit (DOIE), when set, enables the interrupt caused by the output FIFO not empty signal (when the OFNE bit, CCSR Bit 21, is set). When OFNE is cleared, the interrupt is disabled.

14.4.4.9 Cipher Done Interrupt Enable bit (CDIE)—CCSR Bit 14The Cipher Done Interrupt Enable bit (CDIE), when set, enables the interrupt caused by terminating CCOP Cipher mode processing (when CIDN, CCSR Bit 22, is set). If both CDIE and CIDN bits are set, the CCOP requests a Cipher Done interrupt request from the interrupt controller. When CDIE is cleared, the interrupt is disabled.

14.4.4.10 Parity Coding Done Interrupt Enable bit (PDIE)—CCSR Bit 15The Parity Coding Done Interrupt Enable bit (PDIE), when set, enables the interrupt caused by terminating the CCOP Parity Coding mode processing (when PCDN, CCSR

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Bit 23, is set). If both PDIE and PCDN bits are set, the CCOP requests a Parity Coding Done interrupt request from the interrupt controller. When PDIE is cleared, the interrupt is disabled.

14.4.4.11 Input Buffer Empty bit (INBE)—CCSR Bit 19The read-only status bit Input Buffer Empty (INBE), when set, indicates that the whole input path is empty and there are no more data bits to be sent to the CFSRs. INBE is set when the input FIFO is empty and the shift register/buffer (containing the last FIFO word) has shifted out all its contents to the CFSRs but yet the Input Counter has not reached zero, or when the continuous mode is being used (CM bit is set). In this situation CCOP ceases processing waiting for new data to be input, or the programmer can explicitly clear PREN causing normal completion of the processing. INBE is cleared after a data word has been written to the FIFO. INBE does not generate any interrupt. INBE is set by hardware, software, or CCOP individual reset.

14.4.4.12 Input FIFO Empty bit (INFE)—CCSR Bit 20The read-only status bit Input FIFO Empty (INFE), when set, indicates that the Data FIFO Register (CDFR), while operating as the input FIFO, is empty and can be written by the DSP56300 core. CDFR operates as the input FIFO when CCOP is in the Idle state and data is expected to be input to FIFO, or when CCOP is in the input or run phase. INFE is set when the last word of the input FIFO is transferred to the shift register for shifting into the CFSRs, emptying the input FIFO. It is possible to write up to five data words (the FIFO depth) each time the INFE is set. INFE is cleared after a data word has been written to the FIFO. INFE is set by hardware, software, or CCOP individual reset.

14.4.4.13 Output FIFO Not Empty bit (OFNE)—CCSR Bit 21The read-only status bit Output FIFO Not Empty (OFNE), when set, indicates that the Data FIFO Register (CDFR), while operating as the output FIFO, has at least one data word which is ready to be read by the DSP56300 core. CDFR operates as the output FIFO when CCOP is in the output phase or when CCOP is in the Idle state and data is expected to be read from FIFO. OFNE is set when the output FIFO is not empty. OFNE is cleared when the CDFR is read by the DSP56300 core reducing the number of words in the output FIFO to zero. Since output data bits are written to CDFR in the output phase only, OFNE is only operational in the Cipher modes (OPM1 = 0) and when CM,CCNT Bit 23, is cleared. OFNE is cleared by hardware, software, or CCOP individual reset.

14.4.4.14 Cipher Done bit (CIDN)—CCSR Bit 22The read-only status bit Cipher Done (CIDN), when set, indicates that the Cipher processing on the input data block was terminated. CIDN is enabled when CCOP operates in the Cipher modes (OPM1 = 0) and is disabled otherwise. CIDN is set when the CCOP has completed all phases of the processing (i.e Input, Run, and Output phases) and all output data has been transferred to the FIFO. If CIDN and CDIE are set, a Cipher Done interrupt is generated. CIDN is cleared after reading (via CDFR) all the

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data words previously generated and transferred to the output FIFO. CIDN can also be cleared by reading CFSRA- this is used when CCOP processing is terminated without entering the output phase (e.g. Output Counter = 0). CIDN is cleared by hardware, software, or CCOP individual reset.

14.4.4.15 Parity Coding Done bit (PCDN)—CCSR Bit 23The read-only status bit Parity Coding Done (PCDN), when set, indicates that Parity Coding processing on the input data block is terminated. PCDN is enabled when CCOP operates in the Parity Coding modes (OPM1 = 1) and is disabled otherwise. PCDN is set when the CCOP has completed all phases of the processing (i.e., the Input and Run phases). If HOZD is set, Parity Coding processing terminates either when the Run Counter reaches zero or when a zero was detected by the Zero Detect function, and then PREN is cleared and PCDN is set. These conditions allow easy implementation of cyclic Fire decoders for burst error detection and correction. As a result, the contents of the Run Counter can be used to calculate the location of the erroneous burst in the data block, and the contents of CFSRs (CFSRA and CFSRB) can be used to determine the burst correction sequence. If PCDN and PDIE are set, a Parity Coding Done interrupt vector is generated. PCDN is cleared when CFSRA is read by the DSP56300 core. PCDN is cleared by hardware, software. or CCOP individual reset.

Interrupt options are summarized in Table .

14.4.5 Cyclic Code Processing Registers

These registers are grouped into four identical sets, so this discussion refers to them generically (for instance as CFSR) instead of individually (for instance as CFSRA, CFSRB, CFSRC, or CFSRD). In programming these registers, it is necessary to specify which of the register sets are being programmed (A, B, C, or D).

Table 14-6 CCOP Interrupt Vectors

InterruptAddress

InterruptVector

InterruptEnable

InterruptConditions

DMACapability

VBA+Base+0 Input FIFO Empty DIIE INFE = 1 Yes

VBA+Base+2 Output FIFO Not Empty DOIE OFNE = 1 No

VBA+Base+4 Cipher Processing Done CDIE CIDN = 1 Yes

VBA+Base+6 Parity Coding Processing Done PDIE PCDN = 1 No

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All of the registers may be used in the Cipher modes, but in the Parity Coding modes only the first (set A, in Parity Coding Using One CFSR) or the first and second (sets A and B, in Parity Coding Using Two Concatenated CFSRs) sets are enabled.

14.4.5.1 CCOP Linear Feedback Shift Register (CFSRz)The CCOP Linear Feedback Shift Register (CFSRz) is a 24-bit read/write shift register, which manipulates input data according to the feedback taps configuration. Input data can be shifted in serially while it is connected to the left-end or to the right-end of the CFSR. The input can also be gated (zero) for certain periods of the CCOP processing so that data shifted into the CFSR is derived exclusively from its feedback taps. Data shift is always from left to right. CFSRz is cleared by hardware, software or CCOP individual reset.

14.4.5.2 CCOP FeedBack Tap Register (CFBTz)The CCOP FeedBack Tap Register (CFBTz) is the first 24-bit read/write register which configures the operation of CFSRz. In the Cipher modes, this register specifies the position of the feedback taps (XOR gates) in CFSRz. In the Parity Coding modes, this register specifies the position of the XOR gates between adjacent bits of CFSRz connected to the feedback taps.

14.4.5.3 CCOP FeedForward Tap Register (CFFTz)The CCOP FeedForward Tap Register (CFFTz) is the second 24-bit read/write register which configures the operation of CFSRz. In the Cipher modes, this register specifies the position of the feedforward taps in CFSRz, from which the output data is derived. In the Parity Coding modes, this register specifies the position of the XOR gates between adjacent bits of CFSRz connected to the input bit.

14.4.5.4 CCOP Bit Select Register (CBSRz)The CCOP Bit Select Register (CBSRz) is the third 24-bit read/write register which configures the operation of CFSRz. In the Cipher modes, this register specifies which bits from CFSRz will be selected for use by the Bitwise Majority function. In the Parity Coding modes, this register specifies which bits from CFSRz will be selected for the Zero Detect function.

14.4.5.5 CCOP Mask Register (CMSKz)The CCOP Mask Register (CMSKz) is the fourth 24-bit read/write register which configures the operation of CFSRz. In the Cipher modes, this register defines which of the bits determined by CBSRz will be XORed with one (inverted) before it goes to the Bitwise Majority function. In the Parity Coding modes, this register selects which bit in CFSRz drives the feedback line. In the Parity Coding modes, CMSKz should have only one bit set, specifying the CFSR bit from which the feedback line is driven (i.e. the degree of the generator polynomial).

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Operating Modes


14.5 OPERATING MODES

There are four operating modes in the CCOP, two each for Cipher and Parity Coding processing. The operating mode is determined by the OPM[1:0] bits, as described in on page 14-16.

14.5.1 Cipher Modes

When OPM1 is cleared, the CCOP operates in one of the Cipher modes. In these modes the CFSRs are configured as shown in Figure 14-2 CFSR Configuration in the Cipher Modes on page 14-5. The Cipher modes are used to generate mask sequences for data ciphering. When in the Cipher modes:

• The Feedback Tap register (CFBTz) specifies the position of the feedback taps in the CFSRs.

• The Feedforward Tap register (CFFTz) specifies the position of the feedforward taps from which the output data is derived.

• The Bit Select register (CBSRz) specifies which bits from the CFSR are selected for use by the bitwise Majority function.

• The Mask register (CMSKz) specifies which of the bits selected by the Bit Select register will be inverted before input to the bitwise majority function.

In the Cipher modes the bitwise majority function is enabled, and together with the feedforward taps it determines the output data bit of each CFSR. Then the CFSRs output bits are XORed together (with respect to OUTE[3:0] bits in CSFTB) to form the final output data bit that goes to the output buffer.

14.5.1.1 Normal Cipher ModeWhen OPM[1:0] equals 00, the CCOP operates in Normal Cipher mode. In this mode the Cipher processing session progresses fluently, starting at the input phase then passing through the run phase and finally ending in the output phase. After writing the input data bits in the FIFO, the processing session begins by setting PREN according to the specified configuration, counter settings, and control bits. At the end of the session, the DSP56300 core is interrogated to read the generated data from the output FIFO. The Normal Cipher mode operates concurrently with the DSP56300 core and requires minimum CPU-time overhead.

14.5.1.2 Step-by-step Cipher ModeWhen OPM[1:0] equals 01, the CCOP operates in the Step-by-step Cipher mode. In this mode the Cipher processing session halts after each step. This mode of operation enables

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Operating Modes

the user to change CFSR configuration after each step. Every step is activated by setting PREN, and is halted automatically after completing a single shift of the session by clearing PREN and entering the Idle state. A single step session in the Step-by-step Cipher mode takes two DSP clocks to complete, therefore for proper operation, a step can be re-activated (PREN = 1) every two or more DSP clock cycles.

14.5.2 Parity Coding Modes

When OPM1 is set, the CCOP operates in one of the Parity Coding modes. In these modes the CFSRs are configured as shown in Figure 14-3 CFSR Configuration in the Parity Coding Modes on page 14-6. The Parity Coding modes are used to calculate a Cyclic Redundancy Code (CRC) syndrome for encoding or decoding. When in the Parity Coding modes:

• The Feedback Tap register (CFBT) specifies the position of the taps between adjacent bits of the CFSR connected to the feedback line.

• The Feedforward Tap register (CFFT) specifies the position of the taps of the pre-multiplier polynomial.

• The Bit Select register (CBSR) specifies which bits from the CFSR are selected for use by the Zero Detect function.

• The Mask register (CMSK) selects the bit in the CFSR which drives the feedback line. In both Parity Coding modes, the bit driving the feedback line is always selected by programming Mask Register A (CMSKA).

In the Parity Coding modes, the Mask tap register (i.e. CMSKA) should have only one bit set, specifying the CFSR (CFSRA) bit by which the feedback is driven (i.e. the degree of the generator polynomial). In the Parity Coding modes the bitwise majority function and the output phase are disabled. The Zero Detect function is enabled (if HOZD, CCSR Bit 9, is set) and can affect the processing. Therefore, the relevant output data are the contents of the CFSRs, and in some cases the counter values.

14.5.2.1 Parity Coding Mode Using One CFSRWhen OPM[1:0] = 10 only the first CFSR (CFSRA) is enabled. In this mode, cyclic parity codes using generator polynomials of up to 24 stages (maximum degree of 24) can be generated.

14.5.2.2 Parity Coding Mode Using Two Concatenated CFSRsWhen OPM[1:0] = 11 only two CFSRs (CFSRA and CFSRB) are enabled and concatenated together to form one double-length CFSR. CFSRB and CFSRA are positioned on the left and right sides respectively, while the LSB of CFSRB drives the MSB of CFSRA. In this mode, cyclic parity codes using generator polynomials of up to 48

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Programming Considerations


stages (maximum degree of 48) can be generated. The Zero Detect function is signaled if the bits defined in the Bit Select register (CBSRz) of both CFSRs are zero. The feedback line to both CFSRs is driven by the bit selected by the Mask register (CMSKA) of CFSRA. This mode is suitable for encoding and decoding of Fire codes with long burst error correction capability.

14.6 PROGRAMMING CONSIDERATIONS

The processing session consists of three phases: input phase, run phase, and output phase, driven by the Input Counter, Run Counter, and Output Counter, respectively.

14.6.1 Input Phase

The input phase takes an input data bit coming from the pre-loaded data FIFO register (CDFR) and shifts it into the enabled CFSRs (according to INE[3:0] bits in CSFTB and OPM[1:0] bits in CCSR). Following every bit shift the Input Counter is decremented. The input phase is entered if the Input Counter is non-zero or if CM is set. When in the input phase, the stepping function and the output data bits are disabled. The input phase terminates when the Input Counter reaches zero provided that CM bit in CCNT is cleared.

14.6.2 Run Phase

The run phase starts immediately after the input phase completes, if the Run Counter is non-zero. In the run phase, data input is disabled and the CFSRs (enabled according to the OPM[1:0] bits in CCSR) are shifted without any new data being input. Every shift causes the Run Counter to be decremented.

In the Cipher modes (OPM1 = 0), the stepping function is enabled during the run and output phases, that is, CFSRs can selectively be disabled from shifting according to the contents of the Step Function Table. In the Parity Coding modes (OPM1 = 1) shifts are always enabled.

Data output is disabled during the run phase. Usually the run phase terminates when the Run Counter reaches zero. However, the run phase may terminate earlier, if the CCOP operates in Parity Mode (OPM1 = 1) and HOZD is set. In this condition the Zero Detect function is enabled on selected bits, and when zero is detected the run phase is terminated and the Run Counter is frozen. It is therefore possible for a run phase to be

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terminated immediately upon starting - if a zero is detected at once, no shift will be performed during that run phase.

14.6.3 Output Phase

The output phase is enabled only in the Cipher modes (OPM1 = 0). The output phase is entered immediately after the run phase completes, if the Output Counter is non-zero. When in the output phase data input is disabled and the CFSRs are shifted without any new data being input. Every shift causes the Output Counter to be decremented. During the output phase the stepping function is enabled, i.e. CFSRs can be selectively disabled from shifting according to the contents of the Step Function Table. The output data bits (and thus the feedforward tap path and the Bitwise Majority function of the CFSRs) are enabled in the output phase. The output data bit that goes to the data FIFO register (CDFR) is generated by XORing all enabled output bits coming from the CFSRs (according to OUTE[3:0] bits in CSFTB). The output phase terminates when the Output Counter reaches zero.

In the output phase, the output data bit is generated by first executing a shift in the enabled CFSRs and then calculating the bit’s value according to the feedforward tap path and the Associated Bitwise Majority function. This procedure is suitable for some ciphering algorithms such as the GSM A5/1. Other algorithms (e.g. GSM A5/2), which require the output data bit to be first calculated and then the CFSRs shifted, can be implemented by executing one shift fewer during the run phase than specified in the algorithm (i.e. the programmer should write (#Value – 1) to the Run Counter where #Value is the number of shifts specified by the ciphering algorithm for the run phase).

Processing is done when the input, run, and (when enabled) output phases have completed processing.

14.6.4 Cipher Mode Processing

Cipher mode supports implementation of algorithms for data ciphering and de-ciphering. Cipher processing is enabled when the CCOP is programmed to operate in one of the Cipher modes (i.e., if OPM1 = 0). The processing flow is identical in both Cipher modes.

The only difference between the two is that Step-by-step mode (OPM[1:0] = 01) clears PREN and returns to the Idle state after executing one shift. Every shift must then be explicitly activated (by re-setting PREN). Step-by-step mode thus allows the programmer more intervention during Cipher processing than Normal mode.

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Table summarizes the operations being conducted at the input, run and output phases in every (enabled) CFSR during a Cipher processing session.

14.6.4.1 Cipher Mode InitializationAssuming the CCOP is in the CCOP individual reset state, a Cipher processing session is initialized by the following steps. There is no required order to these steps except that data should be written to the CFSRs and CDFR while CCOP is enabled (CEN in CCSR is set), and the counter and configuration registers (CCNT, CSFS, CSFTA, and CSFTB) should be written when the processing is disabled (PREN in CCSR is cleared).

1. Enable CCOP in Cipher mode (in CCSR: set CEN, clear PREN, clear OPM1, and program OPM0 and LRC as required).

2. Initialize CFSRs value as required (CFSRA, CFSRB, CFSRC, and CFSRD).

3. Configure CFSRz parameter registers as required by the Cipher algorithm (CFBTz, CFFTz, CBSRz, and CMSKz).

4. Initialize the counter register (CCNT), step function select register (CSFS) and step function table and input/output enable registers (CSFTA and CSFTB).

5. Write the input data block into the Data FIFO Register (CDFR).

6. Enable processing (set PREN in CCSR).

14.6.4.2 Cipher Mode OutputAfter Cipher processing is completed (i.e., CIDN is set), the DSP56300 core should read the output data sequence from the Data FIFO Register (CDFR). CIDN is cleared after all expected data words were read from CDFR.

Table 14-7 Operations During Cipher Mode Processing

Input Phase Run Phase Output Phase

Input Data Enabled if INEx in CSFTB set

Disabled Disabled

Shifts Enabled Enabled according toStep Function Table

Enabled according toStep Function Table

Output Data Disabled Disabled Enabled if OUTEx in CSFTB set

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14.6.5 Parity Coding Processing

Parity Coding processing is enabled when the CCOP is programmed to operate in one of the Parity Coding modes (i. e., if OPM1 = 1). The processing flow is identical in both Parity Coding modes.

The only difference between the two is that when OPM[1:0] = 11, two CFSRs (CFSRA and CFSRB) are concatenated together to form one big CFSR with up to 48 stages. The unused CFSRs are disabled to reduce power consumption.

The Parity Coding mode using one CFSR (OPM[1:0] = 10) is used to calculate the Cyclic Redundancy Code (CRC) syndrome with a generator polynomial of up to 24 stages (maximum degree of 24). This mode is basically used for the calculation of the Frame Check Sequence (FCS) of a data block prior to transmission, or for the calculation of the CRC for error detection of a received data block. In this mode only the first CFSR (CFSRA) is enabled for shifts. It is possible to implement Fire coding and decoding for burst error correction using this mode if the generator polynomial is of degree of 24 or less. However, in practice, fire codes use higher degree generator polynomials, and they can be implemented using Parity Coding mode with two concatenated CFSRs (OPM[1:0] = 11).

The Parity Coding mode using two concatenated CFSRs (OPM[1:0] = 11) is used to calculate the Cyclic Redundancy Code (CRC) syndrome with a generator polynomial of up to 48 stages (maximum degree of 48). In practice, this mode is used for Fire coding and decoding of burst error correction. The Fire coding is identical to FCS calculation with generator polynomial of degree up to 48. In Fire decoding, the CCOP implements a pre-multiply calculation and a zero detect function, and upon completion it provides the DSP programmer with useful data for computing the burst location and the burst error correction sequence.

Table summarizes the operations being conducted at the input and run phases in every (enabled) CFSR during a Parity Coding processing session.

Table 14-8 Operations During Parity Coding Processing

Input Phase Run Phase

Input Data Enabled if INEx in CSFTB set Disabled

Shifts Enabled Enabled

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Configuration Examples


14.6.5.1 Parity Coding Mode InitializationAssuming the CCOP is in CCOP individual reset state, a Parity Coding processing session is initiated by the following steps. There is no required order to these steps except that data should be written to the CFSRs and CDFR while CCOP is enabled (CEN in CCSR is set), and the counter and configuration registers (CCNT, CSFS, CSFTA, and CSFTB) should be written when the processing is disabled (PREN in CCSR is cleared).

1. Enable CCOP in Parity Coding mode (in CCSR: set CEN, clear PREN, set OPM1, and program OPM0, LRC, and HOZD as required).

2. Initialize CFSRs value if required (CFSRA only or both CSFRA and CFSRB).

3. Configure CFSRz parameter registers as required by the Parity Coding algorithm (CFBTz, CFFTz, CBSRz, and CMSKz).

4. Initialize the counter register (CCNT) and input enable bits (INE[1:0] in CSFTB).Notice that INE0 = INE1 if OPM[1:0] = 11.

5. Write the input data block into the Data FIFO Register (CDFR).

6. Enable processing (set PREN in CCSR).

14.6.5.2 Parity Coding Mode OutputAfter Parity Coding processing is completed (i.e., PCDN is set), the DSP56300 core should read the contents of the CCNT counter and the CFSRs as needed. For data blocks larger than the CDFR capacity, it is possible to use continuous mode (CM is set), or to divide the data block into several parts and execute Parity Coding processing on each part separately.

14.7 CONFIGURATION EXAMPLES

This section describes three examples of configuring the CCOP for some common situations in Parity Coding.

14.7.1 Programming a general circuit in Parity Coding mode

Figure 14-9 illustrates a general circuit for multiplying the data sequence D(x) by a multiplication polynomial and dividing the product by a n-degree polynomial

. This circuit is commonly used for implementing shortened cyclic codes, the kind of code to which Fire codes for burst error correction belong.

M x( ) m0 m1 x⋅ m2 x2 ⋅ ⋅ ⋅+⋅ mn 1– x

n 1–⋅+ + +=

G x( ) 1 g1 x g2 x2⋅ gn 1– x

n 1–⋅ xn

+ +⋅ ⋅ ⋅+ +⋅+=

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Two programming cases are considered:

14.7.1.1 Case 1 - Polynomials of degree n ≤ 24In this case the Parity Coding mode using one CFSR is used (OPM[1:0] = 10 in CCSR), that is, only CFSRA is configured. Since the data sequence is input from the left side, LRC is cleared. The values of the coefficients g1 and m1 are input into bit 23 (the most significant bit) of CFBTA and CFFTA, respectively. Similarly, g2 and m2 are input into bit 22 of CFBTA and CFFTA, respectively. The other coefficients (ga and ma) are input into bit (24–a) of CFBTA and CFFTA, respectively. The polynomial degree, n, is input by setting bit (24–n) of CMSKA while all other bits are cleared. The parameter, m0, is input into INE0. If m0 = 1, INE0 = 1, and if m0 = 0, INE0 = 0. Notice that the input data to the feedforward path is always enabled and not affected by the INE0 bit.

14.7.1.2 Case 2 - Polynomials of degree n, such that 25 ≤ n ≤ 48In this case the Parity Coding mode using two concatenated CFSRs is used (OPM[1:0] = 11 in CCSR), that is, CFSRB and CFSRA are concatenated together to form one double-length CFSR. Since the data sequence is input from the left side, the LRC bit in CCSR is cleared. The values of the coefficients g1 and m1 are input into bit 23 (the most significant bit) of CFBTB and CFFTB, respectively. Similarly, g2 and m2 are input into bit 22 of CFBTB and CFFTB, respectively, and so on. The twenty- fourth coefficients, g24 and m24, are input into bit 0 (the least significant bit) of CFBTB and CFFTB, respectively. The twenty-fifth coefficients, g25 and m25, are input into bit 23 (the most significant bit) of

Figure 14-9 Shortened Cyclic Code Circuit

g1

m1

g2

m2

gn–2

mn–2

gn–1

mn–1m0

Input Data

Bit #23 ofCFSRA if n≤24

Bit #23 ofCFSRB if n≤48

Bit #22 ofCFSRA if n≤24

Bit #22 ofCFSRB if n≤48

Bit #(25-n) ofCFSRA if n≤24

Bit #(49-n) ofCFSRA if n≤48

M(x)

G(x)

D(x)

Circuit for multiplying D(x) by M(x) = m0+m1•x+m2•x2+...+mn–1•x

n–1 and dividing the product by G(x) = 1+g1•x+g2•x

2+...+gn–1•xn–1+xn

+ + + + +

AA1308

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CFBTA and CFFTA, respectively. In general, coefficients ga and ma are programmed input into bit (48–a) of CFBTA/B and CFFTA/B, respectively. The polynomial degree, n, is input by setting bit (48–n) of CMSKA/B while all other bits are cleared. The parameter, m0, is determined by the values of bits INE0 and INE1 in CSFTB. If m0 = 1, then INE0 = INE1 = 1, and if m0 = 0, then INE0 = INE1 = 0. Notice that the input data to the feedforward path is always enabled and not affected by INE0/INE1 bits.

14.7.2 GSM Fire Encode

In GSM, Fire coding is defined for burst error correction of 12 bits. Fire encode makes use of the following generator polynomial of degree 40:

Fire encode processing involves calculating a CRC syndrome on the data block using the polynomial G(D). The CCOP is configured in the Parity Coding mode using two concatenated CFSRs (OPM[1:0] = 11) as shown in Figure 14-10.

Figure 14-10 GSM Fire Encode

G D( ) D23

1+( ) D17

D3

1+ +( )× D40

D26

D23

+ + D17

D3

1+ + += =

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Feedback Tap 0010 0000 0000 0000 1000 0010Feedfwd Tap 0000 0000 0000 0000 0000 0000

Bit Select 0000 0000 0000 0000 0000 0000Mask Tap N.A.

Feedback Tap

InputData

‘0’

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Feedback Tap Mask Tap InputData

‘1’

0100 0000 0000 0000 0000 00000000 0000 0000 0000 0000 0000

Bit Select 0000 0000 0000 0000 0000 0000Mask Tap 0000 0000 0000 0001 0000 0000

CFSRA

CFSRB

Feedback TapFeedfwd Tap

AA1309

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14.7.3 GSM Fire Decode

The Fire decode processes the data block plus the CRC sequence calculated by the Fire encode. Fire decode is capable of correcting any burst of errors up to 12 bits in length. The algorithm makes use of the generator polynomial G(D) as well as a multiplication polynomial M(D) given by:

The Fire decode flow is composed of the following steps:

1. Invert the received 40 CRC bits. This is done by the core and is based on the assumption that the CRC bits were inverted prior to transmission.

2. Set Input Counter = 224, and Run Counter = 224 (in CCNT)

3. Set INE0 and INE1 in CSFTB

4. Set OPM[1:0], HOZD, and clear LRC (in CCSR)

5. Insert 224 bits (184 data bits + 40 inverted CRC) - CCOP input phase.

6. If D1 to D40 (the 40 MSB’s of the concatenated CFSR) equal zero, then the data block is error free. Terminate processing.

7. Otherwise, an error is present, enter run phase and:

a. Shift CFSR (input data disabled) until D1 - D28 equals zero. The start location of the burst error is the number of shifts done until D1– D28 equal zero. This is determined by 224 minus the Run Counter value after a zero is detected in bits D1–D28.

b. If the start location lies in the data sequence (bits 0 – 183), the errors are corrected by XORing the data bits with the contents of D40 – D29.The 12-bit correcting sequence is determined by reading CFSRA and extracting the bits D40 – D29 (bits 19:8 in CFSRA).

c. If the number of shifts exceeds 224 without D1 – D28 = 0 detection, data is uncorrectable. This is determined by process termination (PCDN set) while Run Counter equals zero (224 shifts done).

The CFSR configuration for GSM Fire decode is shown in Figure 14-11.

M D( ) D39

D33

D29

D27

D16

D10

D6

+ + + + + + D4

1+ +=

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Figure 14-11 GSM Fire Decode

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Bit Select 1111 1111 1111 1111 1111 1111Mask Tap N.A.

Feedback Tap

InputData

Feedfwd

Zero Detect

Bit

‘1’

InputData

‘1’

23 22 21 2019 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Feedback Tap

Feedfwd Tap

Mask Tap

Zero Detect

Bit Select

InputData‘0’


Bit Select 1111 0000 0000 0000 0000 0000Mask Tap 0000 0000 0000 0001 0000 0000

CFSRA

CFSRB

SelectTap

AA1310

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MOTOROLA DSP56305 User’s Manual A-1

APPENDIX A

BOOTSTRAP CODE

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A-2 DSP56305 User’s Manual MOTOROLA

Bootstrap Code

A.1 BOOTSTRAP CODE FOR THE DSP56305

This is a listing of the default bootstrap code for the DSP56305, which is normally contained in the Bootstrap ROM. The user may modify or replace this with customized code. Contact your Motorola representative for more information.

BOOTSTRAP CODE FOR DSP56305 - (C) Copyright 1996 Motorola Inc.; Revised June 18, 1996.;; Bootstrap through the Host Interface, External EPROM or SCI.;; This is the Bootstrap program contained in the DSP56305 192-word Boot; ROM. This program can load any program RAM segment from an external; EPROM, from the Host Interface or from the SCI serial interface, or can; execute a boot sequence from a user defined Real Time Operating System; (RTOS) ROM.;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; If MD:MC:MB:MA=x000, then the Boot ROM is bypassed and the DSP56305; will start fetching instructions beginning with address $C00000 (MD=0); or $008000 (MD=1) assuming that an external memory of SRAM type is; used. The accesses will be performed using 31 wait states with no; address attributes selected (default area).;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; If MD:MC:MB:MA=0001-0111, then the bootstrap program jumps to the head; of the RTOS ROM (address $FF0800). The program flow then continues from; the RTOS ROM according to the values of MA, MB and MC in OMR.;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; If MD:MC:MB:MA=1001, then it loads a program RAM segment from; consecutive byte-wide P memory locations, starting at P:$D00000 (bits; 7-0). The memory is selected by the Address Attribute AA1 and is; accessed with 31 wait states.;; The EPROM bootstrap code expects first to read 3 bytes specifying the; number of program words, afterwards 3 bytes specifying the address to; start loading the program words and then 3 bytes for each program word; to be loaded. The number of words, the starting address and the program; words are read least significant byte first followed by the mid and; then by the most significant byte.;; The program words will be condensed into 24-bit words and stored in; contiguous PRAM memory locations starting at the specified starting; address. After reading the program words, program execution starts; from the same address where loading started.;;

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Bootstrap Code


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; If MD:MC:MB:MA=1010, then it loads the program RAM from the SCI interface.;; The SCI bootstrap code expects first to receive 3 bytes specifying the; number of program words, afterwards 3 bytes specifying the address to; start loading the program words and then 3 bytes for each program word; to be loaded. The number of words, the starting address and the program; words are received least significant byte first followed by the mid and; then by the most significant byte.;; The program words will be condensed into 24-bit words and stored in; contiguous PRAM memory locations starting at the specified starting; address. After reading the program words, program execution starts; from the same address where loading started.;; The SCI is programmed to work in asynchronous mode with 8 data bits, 1; stop bit and no parity. The clock source is external and the clock; frequency must be 16x the baud rate. After each byte is received, it; is echoed back through the SCI transmitter.;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; If MD:MC:MB:MA=1011, then it loads the program RAM from the Host Interface; programmed to operate in the Universal Bus mode supporting 56301-to-56301 ; glue less connection.;; The HI32 bootstrap code expects first to read a 24-bit word specifying; the number of program words, afterwards a 24-bit word specifying the; address to start loading the program words and then 24-bit word for; each program word to be loaded. ;; The program words will be stored in contiguous PRAM memory; locations starting at the specified starting address. After; reading the program words, program execution starts from the same; address where loading started.;; The Host Interface bootstrap load program may be stopped by setting the; Host Flag 0 (HF0) in HCTR register. This will start execution of the; loaded program from the specified starting address.;; During the access, the HAEN and HA10-HA3 pins must be driven low; pins; HA2-HA0 select the HI32 registers.; Before booting through the Host Interface it is recommended that the; Host boot program will verify that the HI32 is operational, by reading; the status register (HSTR) and confirm that its value is $3.;; Suggested 56301-to-56301 connection:;; slave master; 56301/HI32 56301/PortA;; HA[10:3] <- A[10:3] ; selects HI32 (base address 00000000); HA[2:0] <- A[2:0] ; selects HTXR registers

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Bootstrap Code

; HD[24:0] <-> D[24:0] ; Data bus; HBS_ <- BS_ ; Bus Strobe (optional, see Note1); HAEN <- AAx ; DMA cycle disable (AAx is active low); HTA -> TA_ ; Transfer Acknowledge (optional, see Note2); HIRQ_ -> IRQx_ ; Interrupt Request (active low, open drain); HWR_ <- WR_ ; Write strobe; HRD_ <- RD_ ; Read strobe; HRST <- system reset ; Reset (active low); ; Pins HP31, HP32 and HDAK_ must be tied to Vcc. Pins HP[22:20] may be; used as GPIO pins. Pin HINTA_ may be used as software driven interrupt; request pin.; ; Note1: If HBS_ to BS_ connection is used, the synchronous connection of; the HI32 is used and therefore the 56301/master should access the; 56301/slave as SRAM with 2 wait states. In addition the CLKOUT of; 56301/master should be connected to EXTAL of 56301/slave, and both; master and slave should enable the PLL while in the case of slave; multiplication, division and predivision fuctors should be one to; guarantee syncronization between master and slave.; In the case of asynchronous connection, HBS_ must be tied to Vcc.;; Note2: If HTA to HTA_ connection is not used, it is recommended that; the HOST Processor’s boot program will verify that the Host Interface; is ready, by reading the status register (HSTR) and confirm that TRDY=1; or HTRQ=1.;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; If MD:MC:MB:MA=1100, then it loads the program RAM from the Host; Interface programmed to operate in the PCI target (slave) mode.;; The HI32 bootstrap code expects first to read a 24-bit word specifying; the number of program words, afterwards a 24-bit word specifying the; address to start loading the program words and then 24-bit word for; each program word to be loaded. ;; The program words will be stored in contiguous PRAM memory; locations starting at the specified starting address. After; reading the program words, program execution starts from the same; address where loading started.;; The Host Interface bootstrap load program may be stopped by setting the; Host Flag 0 (HF0) in HCTR register. This will start execution of the; loaded program from the specified starting address.;; The HOST Processor must first configure the Host Interface as PCI slave; and then start writing data to the Host Interface. The HOST Processor; must program the HCTR HTF1-HTF0 bits as 01, 10 or 11 and then; correspondingly drive the 24-bit data mapped into 32-bit PCI bus word.;; Note that for the synchronization purposes, the DSP to PCI clock ratio; should be more then 5/3.

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Bootstrap Code


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; If MD:MC:MB:MA=1101, then it loads the program RAM from the Host; Interface programmed to operate in the Universal Bus mode supporting; ISA (slave) glue less connection.;; Using self configuration mode, the base address in CBMA is initially; written with $2f which corresponds to an ISA HTXR address of $2fe; (Serial Port 2 Modem Status read only register).;; The HI32 bootstrap code expects to read 32 consecutive times the “magic; number” $0037. Subsequently the bootstrap code expects to read a 16-bit word; which is the designated ISA Port Address; this address is written into the ; CBMA. The HOST Processor must poll for the Host Interface to be reconfigured. ; This must be done by reading the HSTR and verifying that the value $0013 is ; read. From this moment the HOST Processor may start writing data to the ; Host Interface.;; The HI32 bootstrap code expects first to read a 24-bit word (see; Note below) specifying the number of program words, afterwards a; 24-bit word specifying the address to start loading the program; words and then 24-bit word for each program word to be loaded.;; The program words will be stored in contiguous PRAM memory; locations starting at the specified starting address. After; reading the program words, program execution starts from the same; address where loading started.;; The Host Interface bootstrap load program may be stopped by setting the; Host Flag 0 (HF0) in HCTR register. This will start execution of the; loaded program from the specified starting address.;; Note: This ISA connection implies 16 bit data width access only and; that the number of 16-bit wide words that are transferred must be; even.;; The 24-bit words has to be packed into 16-bit ISA words and then sent; by the HOST Processor in the following sequence:;; | M0 | L0 |; | L1 | H0 |; | H1 | M1 |;; The boot program will convert every three 16-bit wide host words to two; 24-bit wide 56301 opcodes in the following format:;; | H0 | M0 | L0 |; | H1 | M1 | L1 |;; The Host Processor must program the Host Interface to operate in the; zero fill mode (HTF1-HTF0 = 01 in HCTR).;

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Bootstrap Code

; Sugested 56301 to ISA connection:; ; HA[10] <- SBHE_ ; selects HI32 (base address 10011111); HA[9] <- SA[0] ; selects HI32 (base address 10011111); HA[8:3] <- SA[9:4] ; selects HI32 (base address 10011111); HA[2:0] <- SA[3:1] ; selects HTXR registers; HD[15:0] - SD[15:0] ; Data bus; HD[23:16] - Not connected ; High Data Bus - Should be pulled up or down; HDBEN_ -> OE_ ; Output enable of transcievers; HDBDR -> DIR ; Direction of transcievers; HSAK_ -> IO16_ ; 16 bit data word; HBS_ <- Vcc ; Bus Strobe disabled; HAEN <- AEN ; DMA cycle enable; HTA -> CHRDY ; Channel ready; HWR_ <- IOWC_ ; IO/DMA write strobe; HRD_ <- IORC_ ; IO/DMA read strobe; HRST <- inverted RSTDRV ; invert ISA reset;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; If MD:MC:MB:MA=1110, then it loads the program RAM from the Host; Interface programmed to operate in the Universal Bus (UB) mode, in; double-strobe pin configuration.;; The HI32 bootstrap code expects first to receive 3 bytes specifying the; number of program words, afterwards 3 bytes specifying the address to; start loading the program words and then 3 bytes for each program word; to be loaded. The number of words, the starting address and the program; words are received least significant byte first followed by the mid and; then by the most significant byte.;; The program words will be condensed into 24-bit words and stored in; contiguous PRAM memory locations starting at the specified starting; address. After reading the program words, program execution starts; from the same address where loading started.;; The Host Interface bootstrap load program may be stopped by setting the; Host Flag 0 (HF0) in HCTR register. This will start execution of the; loaded program from the specified starting address.; ; The user must externally decode the port address with active low logic and ; connect the select line to HAEN; all the address lines shall be pulled down ; except for HA3, HA2 and HA1 that select the HOST Interface registers.;; When booting through the Host Interface it is recommended that the Host; boot program will verify that the Host Interface is operational, by; reading the status register (HSTR) and confirm that TRDY=1.;; When booting through the Host Interface, it is recommended that the; HOST Processor’s boot program will verify that the Host Interface is; ready, by reading the status register (HSTR) and confirm that TRDY=1; or HTRQ=1.;

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Bootstrap Code


; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; If MD:MC:MB:MA=1111, then it loads the program RAM from the Host; Interface programmed to operate in the Universal Bus (UB) mode, in; single-strobe pin configuration.;; Other than the single-strob pin configuration, this mode is identical to; the double-strob pin configuration UB mode (MD:MC:MB:MA=1110).;;

RTOSROM equ $FF0800 ; RTOS ROM AddressBOOT equ $D00000 ; this is the location in P memory ; on the external memory bus ; where the external byte-wide ; EPROM would be located AARV equ $D00409 ; AAR1 selects the EPROM as CE~ ; mapped as P from $D00000 to ; $DFFFFF, active low

M_SSR EQU $FFFF93 ; SCI Status RegisterM_STXL EQU $FFFF95 ; SCI Transmit Data Register (low)M_SRXL EQU $FFFF98 ; SCI Receive Data Register (low)M_SCCR EQU $FFFF9B ; SCI Clock Control RegisterM_SCR EQU $FFFF9C ; SCI Control RegisterM_PCRE EQU $FFFF9F ; Port E Control registerM_DCTR EQU $FFFFC5 ; DSP CONTROL REGISTER (DCTR)M_DPMC EQU $FFFFC7 ; DSP PCI MASTER CONTROL REGISTER (DPMC)M_DPAR EQU $FFFFC8 ; DSP PCI ADDRESS REGISTER (DPAR)M_DSR EQU $FFFFC9 ; DSP STATUS REGISTER (DSR)M_DRXR EQU $FFFFCB ; DSP RECEIVE DATA FIFO (DRXR)M_AAR1 EQU $FFFFF8 ; Address Attribute Register 1

ORG PL:$ff0000,PL:$ff0000 ; bootstrap code starts at $ff0000 START jclr #3,omr,RTOSROM ; If MD:MC:MB:MA=0xxx boot from RTOS ROMCONT clr a #$0a,X0 ; clear a and load X0 with constant $0a0000

move #$3e,x1 ; X1=$3E0000 for UB mode host programming ; HM=$3 (UB) ; HIRD=1 (HIRQ_ pin - drive high enabled) ; HIRH=1 (HIRQ_ pin - handshake enabled) ; HRSP=1 (HRST pin - active low) ; HTAP=0 (HTA pin - active high) ; HDSM=0 (Double-strob pin mode enabled) jclr #2,omr,EPRSCILD ; MD:MC:MB:MA=10xx, load EPROM/SCI/56301-56301 jclr #1,omr,IHOSTLD ; MD:MC:MB:MA=110x, load from PCI/ISA HOST jclr #0,omr,UB2HOSTLD ; MD:MC:MB:MA=1110, load double-strob UB Host ; MD:MC:MB:MA=1111, load single-strob UB Host

;========================================================================; This is the routine that loads from the Host Interface in UB (UNIVERSAL) mode,

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Bootstrap Code

; with single-strob pin configuration (RD/WR,DS).; MD:MC:MB:MA=1111 - Host UB

UB1HOSTLD bset #13,x1 ; HDSM=1 (Double-strob pin mode disabled)

;========================================================================; This is the routine that loads from the Host Interface in UB (UNIVERSAL) mode,; with double-strobe pin configuration (RD,WR).; MD:MC:MB:MA=1110 - Host UB

UB2HOSTLD movep x1,X:M_DCTR ; Configure HI32 in UB mode Single or Double strobe

do #6,_LOOP0 ; read # of words and start address jclr #2,X:M_DSR,* ; Wait for SRRQ to go high (i.e. data ready) movep X:M_DRXR,a2 ; asr #8,a,a ; Shift 8 bit data into A1_LOOP0 ; move a1,r0 ; starting address for load move a1,r1 ; save it in r1 ; a0 holds the number of words; Download P memory through UB

do a0,_LOOP1 ; Load instruction words do #3,_LOOP2 ; for each byte_LBLA jset #2,X:M_DSR,_LBLB ; Wait for SRRQ to go high (i.e. data ready) jclr #3,X:M_DSR,_LBLA ; If HF0=1, stop loading new data. enddo ; Must terminate the do loop bra <TERMINATE ; Terminate loop (enddo) and finish_LBLB movep X:M_DRXR,a2 ; Store 16-bit data in accumulator asr #8,a,a ; Shift 8 bit data into A1_LOOP2 ; and go get another 24-bit word. movem a1,p:(r0)+ ; Store 24-bit data in P mem

nop ; movem cannot be at LA._LOOP1 ; and go get another 24-bit word. bra <FINISH ; finish bootstrap

;========================================================================IHOSTLD jclr #0,omr,PCIHOSTLD ; If MD:MC:MB:MA=1100, go load from PCI HOST ;========================================================================; This routine loads from the Host Interface in ISA (UNIVERSAL) mode.; MD:MC:MB:MA=1101 - Host ISA

; Using self configuration mode, the base address in CBMA is written with; $2f which corresponds to an ISA HTXR address of $2fe (Serial Port 2 Modem ; Status read only register).

ISAHOSTLD

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Bootstrap Code


move #$5a,b ; b1=$5a0000 movep b1,X:M_DCTR ; Configure HI32 as Self-Config movep #$00002f,X:M_DPMC ; write to DPMC rep #4 movep X0,X:M_DPAR ; write DPAR (CSTR+CCMR,CCCR+CRID,CLAT,CBMA) ; completing 32 bit write; Switch to ISA mode movep X0,X:M_DCTR ; Software personal reset move #$010020,y1 ; width 16, offset 32 ; (also as replacment to NOP after sw reset!) movep #$3a0000,X:M_DCTR ; HM=$3 (UB) ; HIRD=1 (HIRQ_ pin - drive high enabled) ; HIRH=0 (HIRQ_ pin - handshake disabled) ; HRSP=1 (HRST pin - active low) ; HDRP=0 (HDRQ pin - active high) ; HTAP=0 (HTA pin - active high) ; HDSM=0 (Data-strob pin mode enabled)

; read the “magic sequence” 32 consecutive words with value $37_LBLC do #32,_LOOP3 ; jclr #2,X:M_DSR,* ; Wait for SRRQ to go high (i.e. data ready) movep X:M_DRXR,A1 ; Store 24-bit data into A1 and #$00ffff,A ; Mask upper byte cmp #$37,A ; Compare the 24-bit dat to $000037 beq <_LBLD ; If dat = $37 then go back to loop enddo ; else break the loop and retry bra <_LBLC _LBLD nop_LOOP3

; read new CBMA value (“ISA base address”) jclr #2,X:M_DSR,* ; Wait for SRRQ to go high (i.e. data ready) movep X:M_DRXR,A1 ; Store 24-bit data into A1

; Switch to Self Configuration mode movep X0,X:M_DCTR ; Software personal reset movep A1,X:M_DPMC ; write to DPMC ; (also as replacment to NOP after sw reset!) movep b1,X:M_DCTR ; Configure HI32 as Self-Config rep #4 movep X0,X:M_DPAR ; write DPAR (CSTR+CCMR,CCCR+CRID,CLAT,CBMA)

; Switch to ISA mode movep X0,X:M_DCTR ; Software personal reset move #$010010,x1 ; width 16, offset 16 ; (also as replacment to NOP after sw reset!) movep #$3a0010,x:M_DCTR ; HM=$3 (UB) ; HIRD=1 (HIRQ_ pin - drive high enabled) ; HIRH=0 (HIRQ_ pin - handshake disabled) ; HRSP=1 (HRST pin - active low) ; HDRP=0 (HDRQ pin - active high)

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Bootstrap Code

; HTAP=0 (HTA pin - active high) ; HDSM=0 (Double-strob pin mode enabled) ; HF4 =1 (turn on flag 4 for handshake)

jclr #2,X:M_DSR,* ; Wait for SRRQ to go high (i.e. data ready) movep X:M_DRXR,a0 ; Store number of words jclr #2,X:M_DSR,* ; Wait for SRRQ to go high (i.e. data ready) movep X:M_DRXR,x0 ; Store starting address jclr #2,X:M_DSR,* ; Wait for SRRQ to go high (i.e. data ready) movep X:M_DRXR,y0 ; Store starting address insert x1,x0,a ; concatenate next 16-bit word insert y1,y0,a ; concatenate next 16-bit word move a1,r0 ; start to p-mem move a0,a1 ; number of words to transfer

; Download P memory through UB lsr a r0,r1 ; divide loop count by 2 and save r0

do a1,_LOOP4 ; Load instruction words_LBLE jset #2,X:M_DSR,_LBLF ; Wait for SRRQ to go high (i.e. data ready) jclr #3,X:M_DSR,_LBLE ; If HF0=1, stop loading new data. bra <TERMINATE ; Terminate loop (enddo) and finish_LBLF movep X:M_DRXR,a0 ; Store 16-bit data in accumulator_LBLG jset #2,X:M_DSR,_LBLH ; Wait for SRRQ to go high (i.e. data ready) jclr #3,X:M_DSR,_LBLG ; If HF0=1, stop loading new data. bra <TERMINATE ; Terminate loop (enddo) and finish_LBLH movep X:M_DRXR,x0 ; Store 16-bit data in register_LBLI jset #2,X:M_DSR,_LBLJ ; Wait for SRRQ to go high (i.e. data ready) jclr #3,X:M_DSR,_LBLI ; If HF0=1, stop loading new data. bra <TERMINATE ; Terminate loop (enddo) and finish_LBLJ movep X:M_DRXR,y0 ; Store 16-bit data in register insert x1,x0,a ; concatenate next 16-bit word insert y1,y0,a ; concatenate next 16-bit word movem a0,p:(r0)+ ; Store 24-bit data in P mem. movem a1,p:(r0)+ ; Store 24-bit data in P mem. nop ; movem cannot be at LA._LOOP4 ; and go get another 24-bit word. bra <FINISH ; finish bootstrap

;========================================================================; This is the routine that loads from the Host Interface in PCI mode.; MD:MC:MB:MA=1100 - Host PCI

PCIHOSTLD bset #20,X:M_DCTR ; Configure HI32 as PCI UB3_CONT jclr #2,X:M_DSR,* ; Wait for SRRQ to go high (i.e. data ready)

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Bootstrap Code


movep X:M_DRXR,a0 ; Store number of words jclr #2,X:M_DSR,* ; Wait for SRRQ to go high (i.e. data ready) movep X:M_DRXR,r0 ; Store starting address move r0,r1 ; save r0

do a0,_LOOP5 ; Load instruction words_LBLK jset #2,X:M_DSR,_LBLL ; Wait for SRRQ to go high (i.e. data ready) jclr #3,X:M_DSR,_LBLK ; If HF0=1 stop loading data. Else check SRRQ. bra <TERMINATE ; Terminate loop (enddo) and finish_LBLL movep X:M_DRXR,P:(R0)+ ; Store 24-bit data in P mem. nop ; movem cannot be at LA._LOOP5 ; and go get another 24-bit word. ; finish bootstrap bra <FINISH ;

;========================================================================EPRSCILD jclr #1,omr,EPROMLD ; If MD:MC:MB:MA=1001, go load from EPROM jclr #0,omr,SCILD ; If MD:MC:MB:MA=1010, go load from SCI ; If MD:MC:MB:MA=1011, 56301-to-56301 boot

;========================================================================; This is the routine for 56301-to-56301 boot.; MD:MC:MB:MA=1011 - HI32 in UB mode, double strobe, HTA pin active low

UB3HOSTLD movep #$268000,x:M_DCTR ; HM=$2 (UB) ; HIRD=0 (HIRQ_ pin - open drain) ; HIRH=1 (HIRQ_ pin - handshake enabled) ; HRSP=1 (HRST pin - active low) ; HDRP=0 (HDRQ pin - active high) ; HTAP=1 (HTA pin - active low) ; HDSM=0 (Double-strobe pin mode enabled)

bra <UB3_CONT ; continue

;========================================================================; This is the routine that loads from the SCI.; MD:MC:MB:MA=1010 - external SCI clock

SCILD movep #$0302,X:M_SCR ; Configure SCI Control Reg movep #$C000,X:M_SCCR ; Configure SCI Clock Control Reg movep #7,X:M_PCRE ; Configure SCLK, TXD and RXD

do #6,_LOOP6 ; get 3 bytes for number of ; program words and 3 bytes ; for the starting address jclr #2,X:M_SSR,* ; Wait for RDRF to go high movep X:M_SRXL,A2 ; Put 8 bits in A2

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Bootstrap Code

jclr #1,X:M_SSR,* ; Wait for TDRE to go high movep A2,X:M_STXL ; echo the received byte asr #8,a,a_LOOP6 move a1,r0 ; starting address for load move a1,r1 ; save starting address

do a0,_LOOP7 ; Receive program words do #3,_LOOP8 jclr #2,X:M_SSR,* ; Wait for RDRF to go high movep X:M_SRXL,A2 ; Put 8 bits in A2 jclr #1,X:M_SSR,* ; Wait for TDRE to go high movep a2,X:M_STXL ; echo the received byte asr #8,a,a_LOOP8 movem a1,p:(r0)+ ; Store 24-bit result in P mem. nop ; movem cannot be at LA._LOOP7 bra <FINISH ; Boot from SCI done

;========================================================================; This is the routine that loads from external EPROM.; MD:MC:MB:MA=1001 EPROMLD move #BOOT,r2 ; r2 = address of external EPROM movep #AARV,X:M_AAR1 ; aar1 configured for SRAM types of access

do #6,_LOOP9 ; read number of words and starting address movem p:(r2)+,a2 ; Get the 8 LSB from ext. P mem. asr #8,a,a ; Shift 8 bit data into A1_LOOP9 ; move a1,r0 ; starting address for load move a1,r1 ; save it in r1 ; a0 holds the number of words

do a0,_LOOP10 ; read program words do #3,_LOOP11 ; Each instruction has 3 bytes movem p:(r2)+,a2 ; Get the 8 LSB from ext. P mem. asr #8,a,a ; Shift 8 bit data into A1_LOOP11 ; Go get another byte. movem a1,p:(r0)+ ; Store 24-bit result in P mem. nop ; movem cannot be at LA._LOOP10 ; and go get another 24-bit word. bra <FINISH ; Boot from EPROM done

;========================================================================TERMINATE enddo ; End the loop before exit.FINISH

; This is the exit handler that returns execution to normal

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Bootstrap Code


; expanded mode and jumps to the RESET vector.

andi #$0,ccr ; Clear CCR as if RESET to 0. jmp (r1) ; Then go to starting Prog addr.

; End of bootstrap code. Number of program words: 191.

dup (START+192-*) nop endm

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Equates

MOTOROLA DSP56305 User’s Manual B-1

APPENDIX B

EQUATES

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B-2 DSP56305 User’s Manual MOTOROLA

Equates

B.1 Internal I/0 Equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3B.2 Interrupt Equates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18

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B.1 INTERNAL I/O EQUATES

;***********************************************************************;; EQUATES for DSP56305 I/O registers and ports;;***********************************************************************

page 132,55,0,0,0 opt mex

ioequ ident 1,0

;----------------------------------------------------------------------;; EQUATES for I/O Port Programming;;-----------------------------------------------------------------------

; Register Addresses

M_DATH EQU $FFFFCF ; Host port GPIO data RegisterM_DIRH EQU $FFFFCE ; Host port GPIO direction RegisterM_PCRC EQU $FFFFBF ; Port C Control RegisterM_PRRC EQU $FFFFBE ; Port C Direction RegisterM_PDRC EQU $FFFFBD ; Port C GPIO Data RegisterM_PCRD EQU $FFFFAF ; Port D Control registerM_PRRD EQU $FFFFAE ; Port D Direction Data RegisterM_PDRD EQU $FFFFAD ; Port D GPIO Data RegisterM_PCRE EQU $FFFF9F ; Port E Control registerM_PRRE EQU $FFFF9E ; Port E Direction RegisterM_PDRE EQU $FFFF9D ; Port E Data RegisterM_OGDB EQU $FFFFFC ; OnCE GDB Register

;-----------------------------------------------------------------------;; EQUATES for Host Interface;;-----------------------------------------------------------------------

; Register Addresses M_DTXS EQU $FFFFCD ; DSP SLAVE TRANSMIT DATA FIFO (DTXS)M_DTXM EQU $FFFFCC ; DSP MASTER TRANSMIT DATA FIFO (DTXM)M_DRXR EQU $FFFFCB ; DSP RECEIVE DATA FIFO (DRXR)M_DPSR EQU $FFFFCA ; DSP PCI STATUS REGISTER (DPSR)M_DSR EQU $FFFFC9 ; DSP STATUS REGISTER (DSR)M_DPAR EQU $FFFFC8 ; DSP PCI ADDRESS REGISTER (DPAR)M_DPMC EQU $FFFFC7 ; DSP PCI MASTER CONTROL REGSTER (DPMC)M_DPCR EQU $FFFFC6 ; DSP PCI CONTROL REGISTER (DPCR)

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Equates

M_DCTR EQU $FFFFC5 ; DSP CONTROL REGISTER (DCTR) ; Host Control Register Bit Flags

M_HCIE EQU 0 ; Host Command Interrupt EnableM_STIE EQU 1 ; Slave Transmit Interrupt EnableM_SRIE EQU 2 ; Slave Receive Interrupt EnableM_HF35 EQU $38 ; Host Flags 5-3 MaskM_HF3 EQU 3 ; Host Flag 3M_HF4 EQU 4 ; Host Flag 4M_HF5 EQU 5 ; Host Flag 5M_HINT EQU 6 ; Host Interrupt AM_HDSM EQU 13 ; Host Data Strobe ModeM_HRWP EQU 14 ; Host RD/WR PolarityM_HTAP EQU 15 ; Host Transfer Acknowledge PolarityM_HDRP EQU 16 ; Host Dma Request PolarityM_HRSP EQU 17 ; Host Reset PolarityM_HIRP EQU 18 ; Host Interrupt Request PolarityM_HIRC EQU 19 ; Host Interrupt Request ControlM_HM0 EQU 20 ; Host Interface ModeM_HM1 EQU 21 ; Host Interface ModeM_HM2 EQU 22 ; Host Interface ModeM_HM EQU $700000 ; Host Interface Mode Mask

; Host PCI Control Register Bit Flags

M_PMTIE EQU 1 ; PCI Master Transmit Interrupt EnableM_PMRIE EQU 2 ; PCI Master Receive Interrupt EnableM_PMAIE EQU 4 ; PCI Master Address Interrupt EnableM_PPEIE EQU 5 ; PCI Parity Error Interrupt EnableM_PTAIE EQU 7 ; PCI Transacton Abort Interrupt EnableM_PTTIE EQU 9 ; PCI Transaction Term Interrupt EnableM_PTCIE EQU 12 ; PCI Transfer Complet Interrupt EnableM_CLRT EQU 14 ; Clear TransmitterM_MTT EQU 15 ; Master Transfer TerminateM_SERF EQU 16 ; HSERR~ ForceM_MACE EQU 18 ; Master Access Counter EnableM_MWSD EQU 19 ; Master Wait States DisableM_RBLE EQU 20 ; Receive Buffer Lock EnableM_IAE EQU 21 ; Insert Address Enable

; Host PCI Master Control Register Bit Flags

M_ARH EQU $00ffff ; DSP PCI Transaction Address (High)M_BL EQU $3f0000 ; PCI Data Burst LengthM_FC EQU $c00000 ; Data Transfer Format Control

; Host PCI Address Register Bit Flags

M_ARL EQU $00ffff ; DSP PCI Transaction Address (Low)M_C EQU $0f0000 ; PCI Bus Command

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M_BE EQU $f00000 ; PCI Byte Enables

; DSP Status Register Bit Flags M_HCP EQU 0 ; Host Command pendingM_STRQ EQU 1 ; Slave Transmit Data RequestM_SRRQ EQU 2 ; Slave Receive Data RequestM_HF02 EQU $38 ; Host Flag 0-2 MaskM_HF0 EQU 3 ; Host Flag 0M_HF1 EQU 4 ; Host Flag 1M_HF2 EQU 5 ; Host Flag 2

; DSP PCI Status Register Bit Flags

M_MWS EQU 0 ; PCI Master Wait StatesM_MTRQ EQU 1 ; PCI Master Transmit Data RequestM_MRRQ EQU 2 ; PCI Master Receive Data RequestM_MARQ EQU 4 ; PCI Master Address RequestM_APER EQU 5 ; PCI Address Parity ErrorM_DPER EQU 6 ; PCI Data Parity ErrorM_MAB EQU 7 ; PCI Master AbortM_TAB EQU 8 ; PCI Target AbortM_TDIS EQU 9 ; PCI Target DisconnectM_TRTY EQU 10 ; PCI Target RetryM_TO EQU 11 ; PCI Time Out TerminationM_RDC EQU $3F0000 ; Remaining Data Count Mask (RDC5-RDC0)M_RDC0 EQU 16 ; Remaining Data Count 0M_RDC1 EQU 17 ; Remaining Data Count 1M_RDC2 EQU 18 ; Remaining Data Count 2M_RDC3 EQU 19 ; Remaining Data Count 3M_RDC4 EQU 20 ; Remaining Data Count 4M_RDC5 EQU 21 ; Remaining Data Count 5M_HACT EQU 23 ; Hi32 Active

;----------------------------------------------------------------------;; EQUATES for Serial Communications Interface (SCI);;----------------------------------------------------------------------


M_STXH EQU $FFFF97 ; SCI Transmit Data Register (high)M_STXM EQU $FFFF96 ; SCI Transmit Data Register (middle)M_STXL EQU $FFFF95 ; SCI Transmit Data Register (low)M_SRXH EQU $FFFF9A ; SCI Receive Data Register (high)M_SRXM EQU $FFFF99 ; SCI Receive Data Register (middle)M_SRXL EQU $FFFF98 ; SCI Receive Data Register (low)M_STXA EQU $FFFF94 ; SCI Transmit Address RegisterM_SCR EQU $FFFF9C ; SCI Control Register

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M_SSR EQU $FFFF93 ; SCI Status RegisterM_SCCR EQU $FFFF9B ; SCI Clock Control Register

; SCI Control Register Bit Flags

M_WDS EQU $7 ; Word Select Mask (WDS0-WDS3)M_WDS0 EQU 0 ; Word Select 0M_WDS1 EQU 1 ; Word Select 1M_WDS2 EQU 2 ; Word Select 2M_SSFTD EQU 3 ; SCI Shift Direction M_SBK EQU 4 ; Send BreakM_WAKE EQU 5 ; Wakeup Mode SelectM_RWU EQU 6 ; Receiver Wakeup EnableM_WOMS EQU 7 ; Wired-OR Mode SelectM_SCRE EQU 8 ; SCI Receiver EnableM_SCTE EQU 9 ; SCI Transmitter EnableM_ILIE EQU 10 ; Idle Line Interrupt EnableM_SCRIE EQU 11 ; SCI Receive Interrupt EnableM_SCTIE EQU 12 ; SCI Transmit Interrupt EnableM_TMIE EQU 13 ; Timer Interrupt EnableM_TIR EQU 14 ; Timer Interrupt RateM_SCKP EQU 15 ; SCI Clock PolarityM_REIE EQU 16 ; SCI Error Interrupt Enable (REIE)

; SCI Status Register Bit Flags

M_TRNE EQU 0 ; Transmitter EmptyM_TDRE EQU 1 ; Transmit Data Register EmptyM_RDRF EQU 2 ; Receive Data Register FullM_IDLE EQU 3 ; Idle Line FlagM_OR EQU 4 ; Overrun Error Flag M_PE EQU 5 ; Parity ErrorM_FE EQU 6 ; Framing Error FlagM_R8 EQU 7 ; Received Bit 8 (R8) Address

; SCI Clock Control Register

M_CD EQU $FFF ; Clock Divider Mask (CD0-CD11)M_COD EQU 12 ; Clock Out DividerM_SCP EQU 13 ; Clock PrescalerM_RCM EQU 14 ; Receive Clock Mode Source BitM_TCM EQU 15 ; Transmit Clock Source Bit

;-----------------------------------------------------------------------;; EQUATES for Synchronous Serial Interface (SSI);;-----------------------------------------------------------------------

;; Register Addresses Of SSI0

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M_TX00 EQU $FFFFBC ; SSI0 Transmit Data Register 0M_TX01 EQU $FFFFBB ; SSIO Transmit Data Register 1M_TX02 EQU $FFFFBA ; SSIO Transmit Data Register 2M_TSR0 EQU $FFFFB9 ; SSI0 Time Slot RegisterM_RX0 EQU $FFFFB8 ; SSI0 Receive Data RegisterM_SSISR0 EQU $FFFFB7 ; SSI0 Status RegisterM_CRB0 EQU $FFFFB6 ; SSI0 Control Register BM_CRA0 EQU $FFFFB5 ; SSI0 Control Register AM_TSMA0 EQU $FFFFB4 ; SSI0 Transmit Slot Mask Register AM_TSMB0 EQU $FFFFB3 ; SSI0 Transmit Slot Mask Register BM_RSMA0 EQU $FFFFB2 ; SSI0 Receive Slot Mask Register AM_RSMB0 EQU $FFFFB1 ; SSI0 Receive Slot Mask Register B

; Register Addresses Of SSI1 M_TX10 EQU $FFFFAC ; SSI1 Transmit Data Register 0M_TX11 EQU $FFFFAB ; SSI1 Transmit Data Register 1M_TX12 EQU $FFFFAA ; SSI1 Transmit Data Register 2M_TSR1 EQU $FFFFA9 ; SSI1 Time Slot RegisterM_RX1 EQU $FFFFA8 ; SSI1 Receive Data RegisterM_SSISR1 EQU $FFFFA7 ; SSI1 Status RegisterM_CRB1 EQU $FFFFA6 ; SSI1 Control Register BM_CRA1 EQU $FFFFA5 ; SSI1 Control Register AM_TSMA1 EQU $FFFFA4 ; SSI1 Transmit Slot Mask Register AM_TSMB1 EQU $FFFFA3 ; SSI1 Transmit Slot Mask Register BM_RSMA1 EQU $FFFFA2 ; SSI1 Receive Slot Mask Register AM_RSMB1 EQU $FFFFA1 ; SSI1 Receive Slot Mask Register B

; SSI Control Register A Bit Flags

M_PM EQU $FF ; Prescale Modulus Slct Mask (PM0-PM7)M_PSR EQU 11 ; Prescaler Range M_DC EQU $1F000 ; Frm Rate Divider Contl Mask (DC0-DC7)M_ALC EQU 18 ; Alignment Control (ALC)M_WL EQU $380000 ; Word Length Control Mask (WL0-WL7)M_SSC1 EQU 22 ; Select SC1 as TR #0 drive enable (SSC1)

; SSI Control Register B Bit Flags

M_OF EQU $3 ; Serial Output Flag MaskM_OF0 EQU 0 ; Serial Output Flag 0 M_OF1 EQU 1 ; Serial Output Flag 1 M_SCD EQU $1C ; Serial Control Direction Mask M_SCD0 EQU 2 ; Serial Control 0 Direction M_SCD1 EQU 3 ; Serial Control 1 Direction M_SCD2 EQU 4 ; Serial Control 2 Direction M_SCKD EQU 5 ; Clock Source DirectionM_SHFD EQU 6 ; Shift Direction M_FSL EQU $180 ; Frame Sync Length Mask (FSL0-FSL1)M_FSL0 EQU 7 ; Frame Sync Length 0M_FSL1 EQU 8 ; Frame Sync Length 1M_FSR EQU 9 ; Frame Sync Relative Timing

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M_FSP EQU 10 ; Frame Sync PolarityM_CKP EQU 11 ; Clock Polarity M_SYN EQU 12 ; Sync/Async Control M_MOD EQU 13 ; SSI Mode SelectM_SSTE EQU $1C000 ; SSI Transmit enable Mask M_SSTE2 EQU 14 ; SSI Transmit #2 Enable M_SSTE1 EQU 15 ; SSI Transmit #1 Enable M_SSTE0 EQU 16 ; SSI Transmit #0 Enable M_SSRE EQU 17 ; SSI Receive Enable M_SSTIE EQU 18 ; SSI Transmit Interrupt Enable M_SSRIE EQU 19 ; SSI Receive Interrupt Enable M_STLIE EQU 20 ; SSI Transmit Last Slot Intrupt EnableM_SRLIE EQU 21 ; SSI Receive Last Slot Interupt EnableM_STEIE EQU 22 ; SSI Transmit Error Interrupt Enable M_SREIE EQU 23 ; SSI Receive Error Interrupt Enable

; SSI Status Register Bit Flags

M_IF EQU $3 ; Serial Input Flag Mask M_IF0 EQU 0 ; Serial Input Flag 0 M_IF1 EQU 1 ; Serial Input Flag 1 M_TFS EQU 2 ; Transmit Frame Sync Flag M_RFS EQU 3 ; Receive Frame Sync Flag M_TUE EQU 4 ; Transmitter Underrun Error FLag M_ROE EQU 5 ; Receiver Overrun Error Flag M_TDE EQU 6 ; Transmit Data Register Empty M_RDF EQU 7 ; Receive Data Register Full

; SSI Transmit Slot Mask Register A

M_SSTSA EQU $FFFF ; SSI Xmit Slot Bits Mask A (TS0-TS15)

; SSI Transmit Slot Mask Register B

M_SSTSB EQU $FFFF ; SSI Xmit Slot Bits Mask B (TS16-TS31)

; SSI Receive Slot Mask Register A

M_SSRSA EQU $FFFF ; SSI Rcv Slot Bits Mask A (RS0-RS15) ; SSI Receive Slot Mask Register B

M_SSRSB EQU $FFFF ; SSI Rcv Slot Bits Mask B (RS16-RS31)

;----------------------------------------------------------------------;; EQUATES for Exception Processing ;;----------------------------------------------------------------------

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M_IPRC EQU $FFFFFF ; Interrupt Priority Register CoreM_IPRP EQU $FFFFFE ; Interupt Priority Register Peripheral

; Interrupt Priority Register Core (IPRC)

M_IAL EQU $7 ; IRQA Mode MaskM_IAL0 EQU 0 ; IRQA Mode Interupt Priority Level (low)M_IAL1 EQU 1 ; IRQA Mode Interrupt Priority Level (high)M_IAL2 EQU 2 ; IRQA Mode Trigger ModeM_IBL EQU $38 ; IRQB Mode MaskM_IBL0 EQU 3 ; IRQB Mode Interrupt Priority Level (low)M_IBL1 EQU 4 ; IRQB Mode Interrupt Priority Level (high)M_IBL2 EQU 5 ; IRQB Mode Trigger ModeM_ICL EQU $1C0 ; IRQC Mode MaskM_ICL0 EQU 6 ; IRQC Mode Interrupt Priority Level (low)M_ICL1 EQU 7 ; IRQC Mode Interrupt Priority Level (high)M_ICL2 EQU 8 ; IRQC Mode Trigger ModeM_IDL EQU $E00 ; IRQD Mode MaskM_IDL0 EQU 9 ; IRQD Mode Interrupt Priority Level (low)M_IDL1 EQU 10 ; IRQD Mode Interrupt Priority Level (high)M_IDL2 EQU 11 ; IRQD Mode Trigger ModeM_D0L EQU $3000 ; DMA0 Interrupt priority Level MaskM_D0L0 EQU 12 ; DMA0 Interrupt Priority Level (low)M_D0L1 EQU 13 ; DMA0 Interrupt Priority Level (high)M_D1L EQU $C000 ; DMA1 Interrupt Priority Level MaskM_D1L0 EQU 14 ; DMA1 Interrupt Priority Level (low)M_D1L1 EQU 15 ; DMA1 Interrupt Priority Level (high)M_D2L EQU $30000 ; DMA2 Interrupt priority Level MaskM_D2L0 EQU 16 ; DMA2 Interrupt Priority Level (low)M_D2L1 EQU 17 ; DMA2 Interrupt Priority Level (high)M_D3L EQU $C0000 ; DMA3 Interrupt Priority Level MaskM_D3L0 EQU 18 ; DMA3 Interrupt Priority Level (low)M_D3L1 EQU 19 ; DMA3 Interrupt Priority Level (high)M_D4L EQU $300000 ; DMA4 Interrupt priority Level MaskM_D4L0 EQU 20 ; DMA4 Interrupt Priority Level (low)M_D4L1 EQU 21 ; DMA4 Interrupt Priority Level (high)M_D5L EQU $C00000 ; DMA5 Interrupt priority Level MaskM_D5L0 EQU 22 ; DMA5 Interrupt Priority Level (low)M_D5L1 EQU 23 ; DMA5 Interrupt Priority Level (high)

; Interrupt Priority Register Peripheral (IPRP)

M_HPL EQU $3 ; Host Interrupt Priority Level MaskM_HPL0 EQU 0 ; Host Interrupt Priority Level (low)M_HPL1 EQU 1 ; Host Interrupt Priority Level (high)M_S0L EQU $C ; SSI0 Interrupt Priority Level Mask

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M_S0L0 EQU 2 ; SSI0 Interrupt Priority Level (low)M_S0L1 EQU 3 ; SSI0 Interrupt Priority Level (high)M_S1L EQU $30 ; SSI1 Interrupt Priority Level MaskM_S1L0 EQU 4 ; SSI1 Interrupt Priority Level (low)M_S1L1 EQU 5 ; SSI1 Interrupt Priority Level (high)M_SCL EQU $C0 ; SCI Interrupt Priority Level Mask M_SCL0 EQU 6 ; SCI Interrupt Priority Level (low)M_SCL1 EQU 7 ; SCI Interrupt Priority Level (high)M_T0L EQU $300 ; TIMER Interrupt Priority Level MaskM_T0L0 EQU 8 ; TIMER Interrupt Priority Level (low)M_T0L1 EQU 9 ; TIMER Interrupt Priority Level (high)M_KPL EQU $C00 ; FKOP Interrupt Priority Level MaskM_KPL0 EQU 10 ; FKOP Interrupt Priority Level (low)M_KPL1 EQU 11 ; FKOP Interrupt Priority Level (high)M_VPL EQU $3000 ; VCOP Interrupt Priority Level MaskM_VPL0 EQU 12 ; VCOP Interrupt Priority Level (low)M_VPL1 EQU 13 ; VCOP Interrupt Priority Level (high)M_CPL EQU $C000 ; CCOP Interrupt Priority Level MaskM_CPL0 EQU 14 ; CCOP Interrupt Priority Level (low)M_CPL1 EQU 15 ; CCOP Interrupt Priority Level (high)

;----------------------------------------------------------------------;; EQUATES for TIMER ;;----------------------------------------------------------------------

; Register Addresses Of TIMER0

M_TCSR0 EQU $FFFF8F ; TIMER0 Control/Status Register M_TLR0 EQU $FFFF8E ; TIMER0 Load Reg M_TCPR0 EQU $FFFF8D ; TIMER0 Compare RegisterM_TCR0 EQU $FFFF8C ; TIMER0 Count Register


M_TCSR1 EQU $FFFF8B ; TIMER1 Control/Status Register M_TLR1 EQU $FFFF8A ; TIMER1 Load Reg M_TCPR1 EQU $FFFF89 ; TIMER1 Compare RegisterM_TCR1 EQU $FFFF88 ; TIMER1 Count Register


M_TCSR2 EQU $FFFF87 ; TIMER2 Control/Status Register M_TLR2 EQU $FFFF86 ; TIMER2 Load Reg M_TCPR2 EQU $FFFF85 ; TIMER2 Compare RegisterM_TCR2 EQU $FFFF84 ; TIMER2 Count RegisterM_TPLR EQU $FFFF83 ; TIMER Prescaler Load RegisterM_TPCR EQU $FFFF82 ; TIMER Prescalar Count Register

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; Timer Control/Status Register Bit Flags

M_TE EQU 0 ; Timer Enable M_TOIE EQU 1 ; Timer Overflow Interrupt EnableM_TCIE EQU 2 ; Timer Compare Interrupt EnableM_TC EQU $F0 ; Timer Control Mask (TC0-TC3)M_INV EQU 8 ; Inverter BitM_TRM EQU 9 ; Timer Restart Mode M_DIR EQU 11 ; Direction BitM_DI EQU 12 ; Data InputM_DO EQU 13 ; Data OutputM_PCE EQU 15 ; Prescaled Clock EnableM_TOF EQU 20 ; Timer Overflow FlagM_TCF EQU 21 ; Timer Compare Flag

; Timer Prescaler Register Bit Flags

M_PS EQU $600000 ; Prescaler Source MaskM_PS0 EQU 21M_PS1 EQU 22

; Timer Control Bits

M_TC0 EQU 4 ; Timer Control 0M_TC1 EQU 5 ; Timer Control 1M_TC2 EQU 6 ; Timer Control 2M_TC3 EQU 7 ; Timer Control 3

;----------------------------------------------------------------------;; EQUATES for Direct Memory Access (DMA) ;;----------------------------------------------------------------------

; Register Addresses Of DMA

M_DSTR EQU $FFFFF4 ; DMA Status RegisterM_DOR0 EQU $FFFFF3 ; DMA Offset Register 0M_DOR1 EQU $FFFFF2 ; DMA Offset Register 1M_DOR2 EQU $FFFFF1 ; DMA Offset Register 2M_DOR3 EQU $FFFFF0 ; DMA Offset Register 3

; Register Addresses Of DMA0

M_DSR0 EQU $FFFFEF ; DMA0 Source Address RegisterM_DDR0 EQU $FFFFEE ; DMA0 Destination Address Register M_DCO0 EQU $FFFFED ; DMA0 CounterM_DCR0 EQU $FFFFEC ; DMA0 Control Register

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M_DSR1 EQU $FFFFEB ; DMA1 Source Address RegisterM_DDR1 EQU $FFFFEA ; DMA1 Destination Address Register M_DCO1 EQU $FFFFE9 ; DMA1 CounterM_DCR1 EQU $FFFFE8 ; DMA1 Control Register


M_DSR2 EQU $FFFFE7 ; DMA2 Source Address RegisterM_DDR2 EQU $FFFFE6 ; DMA2 Destination Address Register M_DCO2 EQU $FFFFE5 ; DMA2 CounterM_DCR2 EQU $FFFFE4 ; DMA2 Control Register ; Register Addresses Of DMA4

M_DSR3 EQU $FFFFE3 ; DMA3 Source Address RegisterM_DDR3 EQU $FFFFE2 ; DMA3 Destination Address Register M_DCO3 EQU $FFFFE1 ; DMA3 CounterM_DCR3 EQU $FFFFE0 ; DMA3 Control Register


M_DSR4 EQU $FFFFDF ; DMA4 Source Address RegisterM_DDR4 EQU $FFFFDE ; DMA4 Destination Address Register M_DCO4 EQU $FFFFDD ; DMA4 CounterM_DCR4 EQU $FFFFDC ; DMA4 Control Register


M_DSR5 EQU $FFFFDB ; DMA5 Source Address RegisterM_DDR5 EQU $FFFFDA ; DMA5 Destination Address Register M_DCO5 EQU $FFFFD9 ; DMA5 CounterM_DCR5 EQU $FFFFD8 ; DMA5 Control Register

; DMA Control Register

M_DSS EQU $3 ; DMA Source Space Mask (DSS0-Dss1)M_DSS0 EQU 0 ; DMA Source Memory space 0M_DSS1 EQU 1 ; DMA Source Memory space 1 M_DDS EQU $C ; DMA Destination Space Mask (DDS-DDS1)M_DDS0 EQU 2 ; DMA Destination Memory Space 0M_DDS1 EQU 3 ; DMA Destination Memory Space 1M_DAM EQU $3f0 ; DMA Address Mode Mask (DAM5-DAM0)M_DAM0 EQU 4 ; DMA Address Mode 0M_DAM1 EQU 5 ; DMA Address Mode 1M_DAM2 EQU 6 ; DMA Address Mode 2M_DAM3 EQU 7 ; DMA Address Mode 3M_DAM4 EQU 8 ; DMA Address Mode 4

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M_DAM5 EQU 9 ; DMA Address Mode 5M_D3D EQU 10 ; DMA Three Dimensional ModeM_DRS EQU $F800 ; DMA Request Source Mask (DRS0-DRS4)M_DCON EQU 16 ; DMA Continuous ModeM_DPR EQU $60000 ; DMA Channel PriorityM_DPR0 EQU 17 ; DMA Channel Priority Level (low)M_DPR1 EQU 18 ; DMA Channel Priority Level (high)M_DTM EQU $380000 ; DMA Transfer Mode Mask (DTM2-DTM0)M_DTM0 EQU 19 ; DMA Transfer Mode 0M_DTM1 EQU 20 ; DMA Transfer Mode 1M_DTM2 EQU 21 ; DMA Transfer Mode 2M_DIE EQU 22 ; DMA Interrupt Enable bitM_DE EQU 23 ; DMA Channel Enable bit

; DMA Status Register

M_DTD EQU $3F ; Channel Transfer Done Status MASK (DTD0-DTD5)M_DTD0 EQU 0 ; DMA Channel Transfer Done Status 0M_DTD1 EQU 1 ; DMA Channel Transfer Done Status 1M_DTD2 EQU 2 ; DMA Channel Transfer Done Status 2M_DTD3 EQU 3 ; DMA Channel Transfer Done Status 3M_DTD4 EQU 4 ; DMA Channel Transfer Done Status 4M_DTD5 EQU 5 ; DMA Channel Transfer Done Status 5M_DACT EQU 8 ; DMA Active StateM_DCH EQU $E00 ; DMA Active Channel Mask (DCH0-DCH2)M_DCH0 EQU 9 ; DMA Active Channel 0M_DCH1 EQU 10 ; DMA Active Channel 1M_DCH2 EQU 11 ; DMA Active Channel 2

;-----------------------------------------------------------------------;; EQUATES for Cipher Co-Processor (CCOP) ;;----------------------------------------------------------------------

M_CDFR EQU $FFFF80 ; Input /output data register /FIFOM_CCNT EQU $FFFF82 ; CCOP Count Register M_CSFS EQU $FFFF83 ; Step function select register M_CSFTA EQU $FFFF84 ; Step function table AM_CSFTB EQU $FFFF85 ; Step function table B M_CCSR EQU $FFFF86 ; CCOP Control status RegisterM_CFSRA EQU $FFFF88 ; Feedback shift register AM_CFTBA EQU $FFFF89 ; Feedback tap register AM_CFFTA EQU $FFFF8A ; Feedforward tap register A M_CBSRA EQU $FFFF8B ; Bit select register AM_CMSKA EQU $FFFF8C ; Mask register AM_CFSRB EQU $FFFF90 ; Feedback shift register BM_CFTBB EQU $FFFF91 ; Feedback tap register BM_CFFTB EQU $FFFF92 ; Feedforward tap register B M_CBSRB EQU $FFFF93 ; Bit select register BM_CMSKB EQU $FFFF94 ; Mask register B

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M_CFSRC EQU $FFFF95 ; Feedback shift register CM_CFTBC EQU $FFFF96 ; Feedback tap register CM_CFFTC EQU $FFFF97 ; Feedforward tap register C M_CBSRC EQU $FFFF98 ; Bit select register CM_CMSKC EQU $FFFF99 ; Mask register CM_CFSRD EQU $FFFF9A ; Feedback shift register DM_CFTBD EQU $FFFF9B ; Feedback tap register DM_CFFTD EQU $FFFF9C ; Feedforward tap register D M_CBSRD EQU $FFFF9D ; Bit select register DM_CMSKD EQU $FFFF9E ; Mask register D

;-----------------------------------------------------------------------;; EQUATES for Viterbi Co-Processor (VCOP) ;;----------------------------------------------------------------------

M_VDR EQU $FFFFA0 ; Viterbi data register /FIFOM_VDOR EQU $FFFFA1 ; Viterbi data out register M_VCRA EQU $FFFFA2 ; Viterbi control register AM_VCRB EQU $FFFFA3 ; Viterbi control register BM_VSTR EQU $FFFFA4 ; Viterbi status register M_VCNT EQU $FFFFA5 ; Viterbi data count registerM_VTPA EQU $FFFFA6 ; Viterbi tap register AM_VTPB EQU $FFFFA7 ; Viterbi tap register BM_VTSR EQU $FFFFA8 ; Viterbi trellis setup register M_VBER EQU $FFFFA9 ; Viterbi bit error rate registerM_VWES EQU $FFFFAA ; Viterbi write-only WED setup registerM_VWED EQU $FFFFAB ; Viterbi read-only WED data register M_VMEM EQU $FFFFAC ; Viterbi memory access data register

;-----------------------------------------------------------------------;; EQUATES for Filter Co-Processor (FCOP) ;;----------------------------------------------------------------------

M_FDIR EQU $FFFFB0 ; Filter data input register M_FDOR EQU $FFFFB1 ; Filter data out register M_FCIR EQU $FFFFB2 ; Filter coefficient input registerM_FCNT EQU $FFFFB3 ; Filter counter registerM_FCSR EQU $FFFFB4 ; Filter control status register

;-----------------------------------------------------------------------;; EQUATES for Phase Locked Loop (PLL) ;;----------------------------------------------------------------------

; Register Addresses Of PLL

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M_PCTL EQU $FFFFFD ; PLL Control Register

; PLL Control Register

M_MF EQU $FFF ; Multiplication Factor Bits Mask (MF0-MF11)M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2)M_XTLR EQU 15 ; XTAL Range select bitM_XTLD EQU 16 ; XTAL Disable BitM_PSTP EQU 17 ; STOP Processing State Bit M_PEN EQU 18 ; PLL Enable BitM_PCOD EQU 19 ; PLL Clock Output Disable BitM_PD EQU $F00000 ; PreDivider Factor Bits Mask (PD0-PD3)

;----------------------------------------------------------------------;; EQUATES for BIU

;-----------------------------------------------------------------------

; Register Addresses Of BIU

M_BCR EQU $FFFFFB ; Bus Control RegisterM_DCR EQU $FFFFFA ; DRAM Control RegisterM_AAR0 EQU $FFFFF9 ; Address Attribute Register 0 M_AAR1 EQU $FFFFF8 ; Address Attribute Register 1 M_AAR2 EQU $FFFFF7 ; Address Attribute Register 2 M_AAR3 EQU $FFFFF6 ; Address Attribute Register 3 M_IDR EQU $FFFFF5 ; ID Register

; Bus Control Register

M_BA0W EQU $1F ; Area 0 Wait Control Mask (BA0W0-BA0W4)M_BA1W EQU $3E0 ; Area 1 Wait Control Mask (BA1W0-BA14)M_BA2W EQU $1C00 ; Area 2 Wait Control Mask (BA2W0-BA2W2)M_BA3W EQU $E000 ; Area 3 Wait Control Mask (BA3W0-BA3W3)M_BDFW EQU $1F0000 ; Default Area Wait Control Mask (BDFW0-BDFW4)M_BBS EQU 21 ; Bus StateM_BLH EQU 22 ; Bus Lock HoldM_BRH EQU 23 ; Bus Request Hold

; DRAM Control Register

M_BCW EQU $3 ; In Page Wait States Bits Mask (BCW0-BCW1)M_BRW EQU $C ; Out Of Page Wait States Bits Mask (BRW0-BRW1)M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1)M_BPLE EQU 11 ; Page Logic EnableM_BME EQU 12 ; Mastership EnableM_BRE EQU 13 ; Refresh EnableM_BSTR EQU 14 ; Software Triggered Refresh

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M_BRF EQU $7F8000 ; Refresh Rate Bits Mask (BRF0-BRF7)M_BRP EQU 23 ; Refresh prescaler

; Address Attribute Registers

M_BAT EQU $3 ; External Access Type ;and Pin Definition Bits Mask (BAT0-BAT1)M_BAAP EQU 2 ; Address Attribute Pin PolarityM_BPEN EQU 3 ; Program Space EnableM_BXEN EQU 4 ; X Data Space EnableM_BYEN EQU 5 ; Y Data Space EnableM_BAM EQU 6 ; Address MuxingM_BPAC EQU 7 ; Packing EnableM_BNC EQU $F00 ; No of Addr Bits to Compare Mask (BNC0-BNC3)M_BAC EQU $FFF000 ; Address to Compare Bits Mask (BAC0-BAC11)

; control and status bits in SR

M_CP EQU $c00000 ; mask for CORE-DMA priority bits in SRM_CA EQU 0 ; CarryM_V EQU 1 ; Overflow M_Z EQU 2 ; ZeroM_N EQU 3 ; Negative M_U EQU 4 ; UnnormalizedM_E EQU 5 ; Extension M_L EQU 6 ; LimitM_S EQU 7 ; Scaling Bit M_I0 EQU 8 ; Interupt Mask Bit 0M_I1 EQU 9 ; Interupt Mask Bit 1M_S0 EQU 10 ; Scaling Mode Bit 0M_S1 EQU 11 ; Scaling Mode Bit 1M_SC EQU 13 ; Sixteen_Bit CompatibilityM_DM EQU 14 ; Double Precision MultiplyM_LF EQU 15 ; DO-Loop FlagM_FV EQU 16 ; DO-Forever FlagM_SA EQU 17 ; Sixteen-Bit ArithmeticM_CE EQU 19 ; Instruction Cache EnableM_SM EQU 20 ; Arithmetic SaturationM_RM EQU 21 ; Rounding ModeM_CP0 EQU 22 ; bit 0 of priority bits in SRM_CP1 EQU 23 ; bit 1 of priority bits in SR

; control and status bits in OMR

M_CDP EQU $300 ; mask for CORE-DMA priority bits in OMRM_MA EQU 0 ; Operating Mode AM_MB EQU 1 ; Operating Mode BM_MC EQU 2 ; Operating Mode CM_MD EQU 3 ; Operating Mode DM_EBD EQU 4 ; External Bus Disable bit in OMRM_SD EQU 6 ; Stop Delay

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M_CDP0 EQU 8 ; bit 0 of priority bits in OMRM_CDP1 EQU 9 ; bit 1 of priority bits in OMRM_BEN EQU 10 ; Burst Enable M_TAS EQU 11 ; TA Synchronize SelectM_BRT EQU 12 ; Bus Release Timing M_XYS EQU 16 ; Stack Extension space select bit in OMR.M_EUN EQU 17 ; Extensed stack UNderflow flag in OMR.M_EOV EQU 18 ; Extended stack OVerflow flag in OMR.M_WRP EQU 19 ; Extended WRaP flag in OMR.M_SEN EQU 20 ; Stack Extension Enable bit in OMR.

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B.2 INTERRUPT EQUATES

;***********************************************************************;; EQUATES for DSP56305 interrupts;;***********************************************************************

page 132,55,0,0,0 opt mex

intequ ident 1,0

if @DEF(I_VEC) ;leave user definition as is. elseI_VEC EQU $0 endif

;-----------------------------------------------------------------------; Non-Maskable interrupts;-----------------------------------------------------------------------I_RESET EQU I_VEC+$00 ; Hardware RESETI_STACK EQU I_VEC+$02 ; Stack ErrorI_ILL EQU I_VEC+$04 ; Illegal InstructionI_DBG EQU I_VEC+$06 ; Debug Request I_TRAP EQU I_VEC+$08 ; TrapI_NMI EQU I_VEC+$0A ; Non Maskable Interrupt

;-----------------------------------------------------------------------; Interrupt Request Pins;-----------------------------------------------------------------------I_IRQA EQU I_VEC+$10 ; IRQAI_IRQB EQU I_VEC+$12 ; IRQBI_IRQC EQU I_VEC+$14 ; IRQCI_IRQD EQU I_VEC+$16 ; IRQD

;-----------------------------------------------------------------------; DMA Interrupts;-----------------------------------------------------------------------I_DMA0 EQU I_VEC+$18 ; DMA Channel 0I_DMA1 EQU I_VEC+$1A ; DMA Channel 1I_DMA2 EQU I_VEC+$1C ; DMA Channel 2I_DMA3 EQU I_VEC+$1E ; DMA Channel 3I_DMA4 EQU I_VEC+$20 ; DMA Channel 4I_DMA5 EQU I_VEC+$22 ; DMA Channel 5

;-----------------------------------------------------------------------; Timer Interrupts;-----------------------------------------------------------------------

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I_TIM0C EQU I_VEC+$24 ; TIMER 0 compareI_TIM0OF EQU I_VEC+$26 ; TIMER 0 overflowI_TIM1C EQU I_VEC+$28 ; TIMER 1 compareI_TIM1OF EQU I_VEC+$2A ; TIMER 1 overflowI_TIM2C EQU I_VEC+$2C ; TIMER 2 compareI_TIM2OF EQU I_VEC+$2E ; TIMER 2 overflow

;-----------------------------------------------------------------------; ESSI Interrupts;-----------------------------------------------------------------------I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive DataI_SI0RDE EQU I_VEC+$32 ; ESSI0 Receive Data With Exception StatusI_SI0RLS EQU I_VEC+$34 ; ESSI0 Receive last slotI_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit dataI_SI0TDE EQU I_VEC+$38 ; ESSI0 Transmit Data With Exception StatusI_SI0TLS EQU I_VEC+$3A ; ESSI0 Transmit last slotI_SI1RD EQU I_VEC+$40 ; ESSI1 Receive DataI_SI1RDE EQU I_VEC+$42 ; ESSI1 Receive Data With Exception StatusI_SI1RLS EQU I_VEC+$44 ; ESSI1 Receive last slotI_SI1TD EQU I_VEC+$46 ; ESSI1 Transmit dataI_SI1TDE EQU I_VEC+$48 ; ESSI1 Transmit Data With Exception StatusI_SI1TLS EQU I_VEC+$4A ; ESSI1 Transmit last slot

;-----------------------------------------------------------------------; SCI Interrupts;-----------------------------------------------------------------------I_SCIRD EQU I_VEC+$50 ; SCI Receive Data I_SCIRDE EQU I_VEC+$52 ; SCI Receive Data With Exception StatusI_SCITD EQU I_VEC+$54 ; SCI Transmit DataI_SCIIL EQU I_VEC+$56 ; SCI Idle LineI_SCITM EQU I_VEC+$58 ; SCI Timer

;-----------------------------------------------------------------------; HOST Interrupts;-----------------------------------------------------------------------I_HPTT EQU I_VEC+$60 ; Host PCI Transaction TerminationI_HPTA EQU I_VEC+$62 ; Host PCI Transaction AbortI_HPPE EQU I_VEC+$64 ; Host PCI Parity ErrorI_HPTC EQU I_VEC+$66 ; Host PCI Transfer CompleteI_HPMR EQU I_VEC+$68 ; Host PCI Master ReceiveI_HSR EQU I_VEC+$6A ; Host Slave ReceiveI_HPMT EQU I_VEC+$6C ; Host PCI Master TransmitI_HST EQU I_VEC+$6E ; Host Slave TransmitI_HPMA EQU I_VEC+$70 ; Host PCI Master AddressI_HCNMI EQU I_VEC+$72 ; Host Command/Host NMI (Default)

;-----------------------------------------------------------------------; FKOP Filter Interrupts;-----------------------------------------------------------------------

I_KDIIE EQU I_VEC+$78 ; Filter input buffer empty

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I_KDOIE EQU I_VEC+$7A ; Filter output buffer full;-----------------------------------------------------------------------; VCOP VITERBI Interrupts;-----------------------------------------------------------------------

I_VDREQ EQU I_VEC+$80 ; viterbi data in request I_VDOBF EQU I_VEC+$82 ; viterbi output buffer fullI_VDRDY EQU I_VEC+$84 ; viterbi data out requestI_VDONE EQU I_VEC+$86 ; viterbi processing doneI_VOPC EQU I_VEC+$88 ; viterbi operation complete ;-----------------------------------------------------------------------; CCOP ENCRYPTION Interrupts;-----------------------------------------------------------------------

I_CINFE EQU I_VEC+$90 ; encryption input FIFO emptyI_COFNE EQU I_VEC+$92 ; encryption output FIFO not emptyI_CCIDN EQU I_VEC+$94 ; encryption processing doneI_CPCDN EQU I_VEC+$96 ; encryption parity code processing done

;-----------------------------------------------------------------------; INTERRUPT ENDING ADDRESS;-----------------------------------------------------------------------

I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space

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MOTOROLA DSP56305 User’s Manual C-1

APPENDIX C

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C-2 DSP56305 User’s Manual MOTOROLA

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C.1 JTAG BSDL FILE

-- M O T O R O L A S S D T J T A G S O F T W A R E-- BSDL File Generated: Sun Jun 23 14:42:45 1996---- Revision History:--

entity DSP56305 is generic (PHYSICAL_PIN_MAP : string := "PBGA252");

port ( DE_: inout bit; SC20: inout bit; SC10: inout bit; SC00: inout bit; STD0: inout bit; SCK0: inout bit; SRD0: inout bit; SRD1: inout bit; SCK1: inout bit; STD1: inout bit; SC01: inout bit; SC11: inout bit; SC21: inout bit; TXD: inout bit; SCLK: inout bit; HINTA_: out bit; RXD: inout bit; TIO0: inout bit; TIO1: inout bit; TIO2: inout bit; HAD: inout bit_vector(0 to 31); HBE: inout bit_vector(0 to 3); HGNT_: in bit; HCLK: in bit; HRST_: in bit; HREQ_: out bit; HPAR: inout bit; HSERR_: out bit; HPERR_: inout bit; HLOCK_: inout bit; HSTOP_: inout bit; HDEVSEL_: inout bit; HTRDY_: inout bit; HIRDY_: inout bit; HFRAME_: inout bit; HIDSEL: in bit; IRQD_: in bit; IRQC_: in bit; IRQB_: in bit;

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IRQA_: in bit; D: inout bit_vector(0 to 23); A: out bit_vector(0 to 23); EXTAL: in bit; XTAL: linkage bit; RD_: out bit; WR_: out bit; AA: out bit_vector(0 to 3); BR_: buffer bit; BG_: in bit; BB_: inout bit; PCAP: linkage bit; RES_: in bit; PINIT: in bit; TA_: in bit; CAS_: out bit; BCLK: out bit; CLKOUT: buffer bit; BL_: buffer bit; BS_: out bit; TRST_: in bit; TDO: out bit; TDI: in bit; TCK: in bit; TMS: in bit; RESERVED: linkage bit_vector(0 to 7); SGND: linkage bit_vector(0 to 1); SVCC: linkage bit_vector(0 to 1); QGND: linkage bit_vector(0 to 3); QVCC: linkage bit_vector(0 to 3); HGND: linkage bit_vector(0 to 5); HVCC: linkage bit_vector(0 to 5); DGND: linkage bit_vector(0 to 3); DVCC: linkage bit_vector(0 to 3); AGND: linkage bit_vector(0 to 5); AVCC: linkage bit_vector(0 to 5); NGND: linkage bit_vector(0 to 1); NVCC: linkage bit_vector(0 to 1); XVCC: linkage bit; PVCC: linkage bit; PGND1: linkage bit; PGND: linkage bit; BCLK_: out bit);

use STD_1149_1_1994.all;

attribute PIN_MAP of DSP56305 : entity is PHYSICAL_PIN_MAP;

constant PBGA252 : PIN_MAP_STRING := "AA: (1, 2, 20, 21), " & "NVCC: (18, 3), " &

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"NGND: (19, 4), " & "CLKOUT: 5, " & "BCLK: 6, " & "CAS_: 7, " & "TA_: 8, " & "PINIT: 9, " & "RES_: 10, " & "PVCC: 11, " & "PCAP: 12, " & "PGND: 13, " & "PGND1: 14, " & "BB_: 15, " & "BG_: 16, " & "BR_: 17, " & "WR_: 22, " & "RD_: 23, " & "XTAL: 24, " & "QVCC: (25, 79, 131, 182), " & "EXTAL: 26, " & "QGND: (27, 78, 132, 183), " & "BCLK_: 28, " & "A: (29, 30, 33, 34, 35, 36, 39, 40, 41, 42, 45, 46, 47, 48, 51, 52, 55, 56, 59, 60, " & "61, 62, 65, 66), " & "AGND: (31, 37, 43, 49, 57, 63), " & "AVCC: (32, 38, 44, 50, 58, 64), " & "RESERVED: (53, 54, 103, 104, 157, 158, 207, 208), " & "D: (67, 68, 69, 72, 73, 74, 75, 76, 77, 82, 83, 84, 85, 86, 87, 90, 91, 92, 93, 94, " & "95, 98, 99, 100), " & "DGND: (70, 80, 88, 96), " & "DVCC: (71, 81, 89, 97), " & "IRQA_: 101, " & "IRQB_: 102, " & "IRQC_: 105, " & "IRQD_: 106, " & "HAD: (173, 172, 171, 170, 167, 166, 165, 164, 162, 161, 160, 159, 154, 153, 152, 151, " & "127, 126, 125, 124, 121, 120, 119, 118, 116, 115, 114, 113, 110, 109, 108, 107), " & "HVCC: (135, 144, 156, 169, 111, 122), " & "HGND: (136, 143, 155, 168, 112, 123), " & "HBE: (163, 150, 128, 117), " & "HIDSEL: 129, " & "HFRAME_: 130, " & "HIRDY_: 133, " & "HTRDY_: 134, " & "XVCC: 137, " & "HDEVSEL_: 138, " & "HSTOP_: 139, " & "HLOCK_: 140, " &

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"HPERR_: 141, " & "HSERR_: 142, " & "HPAR: 145, " & "HREQ_: 146, " & "HRST_: 147, " & "HCLK: 148, " & "HGNT_: 149, " & "TIO2: 174, " & "TIO1: 175, " & "TIO0: 176, " & "RXD: 177, " & "SCLK: 178, " & "SVCC: (179, 193), " & "SGND: (180, 194), " & "HINTA_: 181, " & "TXD: 184, " & "SC21: 185, " & "SC11: 186, " & "SC01: 187, " & "STD1: 188, " & "SCK1: 189, " & "SRD1: 190, " & "SRD0: 191, " & "SCK0: 192, " & "STD0: 195, " & "SC00: 196, " & "SC10: 197, " & "SC20: 198, " & "DE_: 199, " & "TMS: 200, " & "TCK: 201, " & "TDI: 202, " & "TDO: 203, " & "TRST_: 204, " & "BS_: 205, " & "BL_: 206 ";

attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_RESET of TRST_ : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);

attribute INSTRUCTION_LENGTH of DSP56305 : entity is 4;

attribute INSTRUCTION_OPCODE of DSP56305 : entity is "EXTEST (0000)," & "SAMPLE (0001)," & "IDCODE (0010)," & "CLAMP (0101)," & "HIGHZ (0100)," &

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"ENABLE_ONCE (0110)," & "DEBUG_REQUEST (0111)," & "BYPASS (1111)";

attribute INSTRUCTION_CAPTURE of DSP56305 : entity is "0001"; attribute IDCODE_REGISTER of DSP56305 : entity is "0000" & -- version "000110" & -- manufacturer's use "0000000101" & -- sequence number "00000001110" & -- manufacturer identity "1"; -- 1149.1 requirement

attribute REGISTER_ACCESS of DSP56305 : entity is "ONCE[8] (ENABLE_ONCE,DEBUG_REQUEST)" ;

attribute BOUNDARY_LENGTH of DSP56305 : entity is 217;

attribute BOUNDARY_REGISTER of DSP56305 : entity is -- num cell port func safe [ccell dis rslt] "0 (BC_1, BS_, output3, X, 7, 1, Z)," & "1 (BC_2, BL_, output2, X)," & "2 (BC_1, AA(0), output3, X, 4, 1, Z)," & "3 (BC_1, AA(1), output3, X, 5, 1, Z)," & "4 (BC_1, *, control, 1)," & "5 (BC_1, *, control, 1)," & "6 (BC_1, *, control, 1)," & "7 (BC_1, *, control, 1)," & "8 (BC_2, CLKOUT, output2, X)," & "9 (BC_1, BCLK, output3, X, 7, 1, Z)," & "10 (BC_1, CAS_, output3, X, 6, 1, Z)," & "11 (BC_2, TA_, input, X)," & "12 (BC_2, PINIT, input, X)," & "13 (BC_2, RES_, input, X)," & "14 (BC_6, BB_, bidir, X, 17, 1, Z)," & "15 (BC_2, BG_, input, X)," & "16 (BC_2, BR_, output2, X)," & "17 (BC_1, *, control, 1)," & "18 (BC_1, *, control, 1)," & "19 (BC_1, *, control, 1)," & -- num cell port func safe [ccell dis rslt] "20 (BC_1, AA(2), output3, X, 18, 1, Z)," & "21 (BC_1, AA(3), output3, X, 19, 1, Z)," & "22 (BC_1, WR_, output3, X, 7, 1, Z)," & "23 (BC_1, RD_, output3, X, 7, 1, Z)," & "24 (BC_2, EXTAL, input, X)," & "25 (BC_1, BCLK_, output3, X, 7, 1, Z)," & "26 (BC_1, A(0), output3, X, 32, 1, Z)," & "27 (BC_1, A(1), output3, X, 32, 1, Z)," & "28 (BC_1, A(2), output3, X, 32, 1, Z)," & "29 (BC_1, A(3), output3, X, 32, 1, Z)," &

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"30 (BC_1, A(4), output3, X, 32, 1, Z)," & "31 (BC_1, A(5), output3, X, 32, 1, Z)," & "32 (BC_1, *, control, 1)," & "33 (BC_1, A(6), output3, X, 32, 1, Z)," & "34 (BC_1, A(7), output3, X, 32, 1, Z)," & "35 (BC_1, A(8), output3, X, 32, 1, Z)," & "36 (BC_1, A(9), output3, X, 32, 1, Z)," & "37 (BC_1, A(10), output3, X, 32, 1, Z)," & "38 (BC_1, A(11), output3, X, 32, 1, Z)," & "39 (BC_1, A(12), output3, X, 45, 1, Z)," & -- num cell port func safe [ccell dis rslt] "40 (BC_1, A(13), output3, X, 45, 1, Z)," & "41 (BC_1, A(14), output3, X, 45, 1, Z)," & "42 (BC_1, A(15), output3, X, 45, 1, Z)," & "43 (BC_1, A(16), output3, X, 45, 1, Z)," & "44 (BC_1, A(17), output3, X, 45, 1, Z)," & "45 (BC_1, *, control, 1)," & "46 (BC_1, A(18), output3, X, 45, 1, Z)," & "47 (BC_1, A(19), output3, X, 45, 1, Z)," & "48 (BC_1, A(20), output3, X, 45, 1, Z)," & "49 (BC_1, A(21), output3, X, 45, 1, Z)," & "50 (BC_1, A(22), output3, X, 45, 1, Z)," & "51 (BC_1, A(23), output3, X, 45, 1, Z)," & "52 (BC_6, D(0), bidir, X, 55, 1, Z)," & "53 (BC_6, D(1), bidir, X, 55, 1, Z)," & "54 (BC_6, D(2), bidir, X, 55, 1, Z)," & "55 (BC_1, *, control, 1)," & "56 (BC_6, D(3), bidir, X, 55, 1, Z)," & "57 (BC_6, D(4), bidir, X, 55, 1, Z)," & "58 (BC_6, D(5), bidir, X, 55, 1, Z)," & "59 (BC_6, D(6), bidir, X, 55, 1, Z)," & -- num cell port func safe [ccell dis rslt] "60 (BC_6, D(7), bidir, X, 55, 1, Z)," & "61 (BC_6, D(8), bidir, X, 55, 1, Z)," & "62 (BC_6, D(9), bidir, X, 55, 1, Z)," & "63 (BC_6, D(10), bidir, X, 55, 1, Z)," & "64 (BC_6, D(11), bidir, X, 55, 1, Z)," & "65 (BC_6, D(12), bidir, X, 68, 1, Z)," & "66 (BC_6, D(13), bidir, X, 68, 1, Z)," & "67 (BC_6, D(14), bidir, X, 68, 1, Z)," & "68 (BC_1, *, control, 1)," & "69 (BC_6, D(15), bidir, X, 68, 1, Z)," & "70 (BC_6, D(16), bidir, X, 68, 1, Z)," & "71 (BC_6, D(17), bidir, X, 68, 1, Z)," & "72 (BC_6, D(18), bidir, X, 68, 1, Z)," & "73 (BC_6, D(19), bidir, X, 68, 1, Z)," & "74 (BC_6, D(20), bidir, X, 68, 1, Z)," & "75 (BC_6, D(21), bidir, X, 68, 1, Z)," & "76 (BC_6, D(22), bidir, X, 68, 1, Z)," & "77 (BC_6, D(23), bidir, X, 68, 1, Z)," & "78 (BC_2, IRQA_, input, X)," &

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"79 (BC_2, IRQB_, input, X)," & -- num cell port func safe [ccell dis rslt] "80 (BC_2, IRQC_, input, X)," & "81 (BC_2, IRQD_, input, X)," & "82 (BC_1, *, control, 1)," & "83 (BC_6, HAD(31), bidir, X, 82, 1, Z)," & "84 (BC_1, *, control, 1)," & "85 (BC_6, HAD(30), bidir, X, 84, 1, Z)," & "86 (BC_1, *, control, 1)," & "87 (BC_6, HAD(29), bidir, X, 86, 1, Z)," & "88 (BC_1, *, control, 1)," & "89 (BC_6, HAD(28), bidir, X, 88, 1, Z)," & "90 (BC_1, *, control, 1)," & "91 (BC_6, HAD(27), bidir, X, 90, 1, Z)," & "92 (BC_1, *, control, 1)," & "93 (BC_6, HAD(26), bidir, X, 92, 1, Z)," & "94 (BC_1, *, control, 1)," & "95 (BC_6, HAD(25), bidir, X, 94, 1, Z)," & "96 (BC_1, *, control, 1)," & "97 (BC_6, HAD(24), bidir, X, 96, 1, Z)," & "98 (BC_1, *, control, 1)," & "99 (BC_6, HBE(3), bidir, X, 98, 1, Z)," & -- num cell port func safe [ccell dis rslt] "100 (BC_1, *, control, 1)," & "101 (BC_6, HAD(23), bidir, X, 100, 1, Z)," & "102 (BC_1, *, control, 1)," & "103 (BC_6, HAD(22), bidir, X, 102, 1, Z)," & "104 (BC_1, *, control, 1)," & "105 (BC_6, HAD(21), bidir, X, 104, 1, Z)," & "106 (BC_1, *, control, 1)," & "107 (BC_6, HAD(20), bidir, X, 106, 1, Z)," & "108 (BC_1, *, control, 1)," & "109 (BC_6, HAD(19), bidir, X, 108, 1, Z)," & "110 (BC_1, *, control, 1)," & "111 (BC_6, HAD(18), bidir, X, 110, 1, Z)," & "112 (BC_1, *, control, 1)," & "113 (BC_6, HAD(17), bidir, X, 112, 1, Z)," & "114 (BC_1, *, control, 1)," & "115 (BC_6, HAD(16), bidir, X, 114, 1, Z)," & "116 (BC_1, *, control, 1)," & "117 (BC_6, HBE(2), bidir, X, 116, 1, Z)," & "118 (BC_2, HIDSEL, input, X)," & "119 (BC_1, *, control, 1)," & -- num cell port func safe [ccell dis rslt] "120 (BC_6, HFRAME_, bidir, X, 119, 1, Z)," & "121 (BC_1, *, control, 1)," & "122 (BC_6, HIRDY_, bidir, X, 121, 1, Z)," & "123 (BC_1, *, control, 1)," & "124 (BC_6, HTRDY_, bidir, X, 123, 1, Z)," & "125 (BC_1, *, control, 1)," & "126 (BC_6, HDEVSEL_, bidir, X, 125, 1, Z)," &

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"127 (BC_1, *, control, 1)," & "128 (BC_6, HSTOP_, bidir, X, 127, 1, Z)," & "129 (BC_1, *, control, 1)," & "130 (BC_6, HLOCK_, bidir, X, 129, 1, Z)," & "131 (BC_1, *, control, 1)," & "132 (BC_6, HPERR_, bidir, X, 131, 1, Z)," & "133 (BC_1, *, control, 1)," & "134 (BC_1, HSERR_, output3, X, 133, 1, Z)," & "135 (BC_1, *, control, 1)," & "136 (BC_6, HPAR, bidir, X, 135, 1, Z)," & "137 (BC_1, *, control, 1)," & "138 (BC_1, HREQ_, output3, X, 137, 1, Z)," & "139 (BC_2, HRST_, input, X)," & -- num cell port func safe [ccell dis rslt] "140 (BC_2, HCLK, input, X)," & "141 (BC_2, HGNT_, input, X)," & "142 (BC_1, *, control, 1)," & "143 (BC_6, HBE(1), bidir, X, 142, 1, Z)," & "144 (BC_1, *, control, 1)," & "145 (BC_6, HAD(15), bidir, X, 144, 1, Z)," & "146 (BC_1, *, control, 1)," & "147 (BC_6, HAD(14), bidir, X, 146, 1, Z)," & "148 (BC_1, *, control, 1)," & "149 (BC_6, HAD(13), bidir, X, 148, 1, Z)," & "150 (BC_1, *, control, 1)," & "151 (BC_6, HAD(12), bidir, X, 150, 1, Z)," & "152 (BC_1, *, control, 1)," & "153 (BC_6, HAD(11), bidir, X, 152, 1, Z)," & "154 (BC_1, *, control, 1)," & "155 (BC_6, HAD(10), bidir, X, 154, 1, Z)," & "156 (BC_1, *, control, 1)," & "157 (BC_6, HAD(9), bidir, X, 156, 1, Z)," & "158 (BC_1, *, control, 1)," & "159 (BC_6, HAD(8), bidir, X, 158, 1, Z)," & -- num cell port func safe [ccell dis rslt] "160 (BC_1, *, control, 1)," & "161 (BC_6, HBE(0), bidir, X, 160, 1, Z)," & "162 (BC_1, *, control, 1)," & "163 (BC_6, HAD(7), bidir, X, 162, 1, Z)," & "164 (BC_1, *, control, 1)," & "165 (BC_6, HAD(6), bidir, X, 164, 1, Z)," & "166 (BC_1, *, control, 1)," & "167 (BC_6, HAD(5), bidir, X, 166, 1, Z)," & "168 (BC_1, *, control, 1)," & "169 (BC_6, HAD(4), bidir, X, 168, 1, Z)," & "170 (BC_1, *, control, 1)," & "171 (BC_6, HAD(3), bidir, X, 170, 1, Z)," & "172 (BC_1, *, control, 1)," & "173 (BC_6, HAD(2), bidir, X, 172, 1, Z)," & "174 (BC_1, *, control, 1)," & "175 (BC_6, HAD(1), bidir, X, 174, 1, Z)," &

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JTAG BSDL


"176 (BC_1, *, control, 1)," & "177 (BC_6, HAD(0), bidir, X, 176, 1, Z)," & "178 (BC_1, *, control, 1)," & "179 (BC_6, TIO2, bidir, X, 178, 1, Z)," & -- num cell port func safe [ccell dis rslt] "180 (BC_1, *, control, 1)," & "181 (BC_6, TIO1, bidir, X, 180, 1, Z)," & "182 (BC_1, *, control, 1)," & "183 (BC_6, TIO0, bidir, X, 182, 1, Z)," & "184 (BC_1, *, control, 1)," & "185 (BC_6, RXD, bidir, X, 184, 1, Z)," & "186 (BC_1, *, control, 1)," & "187 (BC_6, SCLK, bidir, X, 186, 1, Z)," & "188 (BC_1, HINTA_, output2, 1, 188, 1, Weak1)," & "189 (BC_1, *, control, 1)," & "190 (BC_6, TXD, bidir, X, 189, 1, Z)," & "191 (BC_1, *, control, 1)," & "192 (BC_6, SC21, bidir, X, 191, 1, Z)," & "193 (BC_1, *, control, 1)," & "194 (BC_6, SC11, bidir, X, 193, 1, Z)," & "195 (BC_1, *, control, 1)," & "196 (BC_6, SC01, bidir, X, 195, 1, Z)," & "197 (BC_1, *, control, 1)," & "198 (BC_6, STD1, bidir, X, 197, 1, Z)," & "199 (BC_1, *, control, 1)," & -- num cell port func safe [ccell dis rslt] "200 (BC_6, SCK1, bidir, X, 199, 1, Z)," & "201 (BC_1, *, control, 1)," & "202 (BC_6, SRD1, bidir, X, 201, 1, Z)," & "203 (BC_1, *, control, 1)," & "204 (BC_6, SRD0, bidir, X, 203, 1, Z)," & "205 (BC_1, *, control, 1)," & "206 (BC_6, SCK0, bidir, X, 205, 1, Z)," & "207 (BC_1, *, control, 1)," & "208 (BC_6, STD0, bidir, X, 207, 1, Z)," & "209 (BC_1, *, control, 1)," & "210 (BC_6, SC00, bidir, X, 209, 1, Z)," & "211 (BC_1, *, control, 1)," & "212 (BC_6, SC10, bidir, X, 211, 1, Z)," & "213 (BC_1, *, control, 1)," & "214 (BC_6, SC20, bidir, X, 213, 1, Z)," & "215 (BC_1, *, control, 1)," & "216 (BC_6, DE_, bidir, X, 215, 1, Z)";

end DSP56305;

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JTAG BSDL

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MOTOROLA DSP56305 User’s Manual D-1

APPENDIX D

PROGRAMMING REFERENCE

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D-2 DSP56305 User’s Manual MOTOROLA


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D.1 INTRODUCTION

This section has been compiled as a reference for programmers. It contains a table showing the addresses of all the DSPs memory-mapped peripherals, an exception priority table, and programming sheets for the major programmable registers on the DSP. The programming sheets are grouped in the following order: central processor, Phase Lock Loop (PLL), Host Interface (HI08), Enhanced Synchronous Serial Interface (ESSI), Serial Communication Interface (SCI), Timer, and GPIO. Each sheet provides room to write in the value of each bit and the hexadecimal value for each register. The programmer can photocopy these sheets and reuse them for each application development project. For details on the instruction set of the DSP56300 family chips, see the DSP56300 Family Manual.

D.1.1 Peripheral Addresses

Table D-1 lists the memory addresses of all on-chip peripherals.

D.1.2 Interrupt Addresses

Table D-2 lists the interrupt starting addresses and sources.

D.1.3 Interrupt Priorities

Table D-3 lists the priorities of specific interrupts within interrupt priority levels.

D.1.4 DMA Requests

Table D-4 lists the DMA requests.

D.1.5 Programming Sheets

Figures describing the major programmable registers on the DSP56305.

D.1.6 HI32 Registers — Quick Reference Tables

Table D-5 provides a handy reference tool for the HI32 Registers.

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D.2 INTERNAL I/O MEMORY MAP

Table D-1 Internal I/O Memory Map

Peripheral 16-Bit Address

24-Bit Address Register Name

IPR $FFFF $FFFFFF Interrupt Priority Register Core (IPR-C)

$FFFE $FFFFFE Interrupt Priority Register Peripheral (IPR-P)

PLL $FFFD $FFFFFD PLL Control Register (PCTL)

OnCE $FFFC $FFFFFC OnCE GDB Register (OGDB)

BIU $FFFB $FFFFFB Bus Control Register (BCR)

$FFFA $FFFFFA DRAM Control Register (DCR)

$FFF9 $FFFFF9 Address Attribute Register 0 (AAR0)




$FFF5 $FFFFF5 ID Register (IDR)

DMA $FFF4 $FFFFF4 DMA Status Register (DSTR)

$FFF3 $FFFFF3 DMA Offset Register 0 (DOR0)




DMA0 $FFEF $FFFFEF DMA Source Address Register (DSR0)

$FFEE $FFFFEE DMA Destination Address Register (DDR0)

$FFED $FFFFED DMA Counter (DCO0)

$FFEC $FFFFEC DMA Control Register (DCR0)

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DMA1 $FFEB $FFFFEB DMA Source Address Register (DSR1)

$FFEA $FFFFEA DMA Destination Address Register (DDR1)

$FFE9 $FFFFE9 DMA Counter (DCO1)

$FFE8 $FFFFE8 DMA Control Register (DCR1)

DMA2 $FFE7 $FFFFE7 DMA Source Address Register (DSR2)

$FFE6 $FFFFE6 DMA Destination Address Register (DDR2)



DMA3 $FFE3 $FFFFE3 DMA Source Address Register (DSR3)

$FFE2 $FFFFE2 DMA Destination Address Register (DDR3)



DMA4 $FFDF $FFFFDF DMA Source Address Register (DSR4)

$FFDE $FFFFDE DMA Destination Address Register (DDR4)

$FFDD $FFFFDD DMA Counter (DCO4)

$FFDC $FFFFDC DMA Control Register (DCR4)

DMA5 $FFDB $FFFFDB DMA Source Address Register (DSR5)

$FFDA $FFFFDA DMA Destination Address Register (DDR5)

$FFD9 $FFFFD9 DMA Counter (DCO5)

$FFD8 $FFFFD8 DMA Control Register (DCR5)

Table D-1 Internal I/O Memory Map (Continued)



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$FFD7 $FFFFD7 Reserved








$FFCF $FFFFCF Reserved

$FFCE $FFFFCE Reserved

$FFCD $FFFFCD Reserved

$FFCC $FFFFCC Reserved

$FFCB $FFFFCB Reserved

$FFCA $FFFFCA Reserved

PORT B $FFC9 $FFFFC9 Host Port GPIO Data Register (HDR)

$FFC8 $FFFFC8 Host Port GPIO Direction Register (HDDR)

HI08 $FFC7 $FFFFC7 Host Transmit Register (HTX)

$FFC6 $FFFFC6 Host Receive Register (HRX)

$FFC5 $FFFFC5 Host Base Address Register (HBAR)

$FFC4 $FFFFC4 Host Polarity Control Register (HPCR)

$FFC3 $FFFFC3 Host Status Register (HSR)

$FFC2 $FFFFC2 Host Control Register (HCR)

$FFC1 $FFFFC1 Reserved

$FFC0 $FFFFC0 Reserved




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PORT C $FFBF $FFFFBF Port C Control Register (PCRC)

$FFBE $FFFFBE Port C Direction Register (PRRC)

$FFBD $FFFFBD Port C GPIO Data Register (PDRC)

ESSI 0 $FFBC $FFFFBC ESSI 0 Transmit Data Register 0 (TX00)

$FFBB $FFFFBB ESSI 0 Transmit Data Register 1 (TX01)

$FFBA $FFFFBA ESSI 0 Transmit Data Register 2 (TX02)

$FFB9 $FFFFB9 ESSI 0 Time Slot Register (TSR0)

$FFB8 $FFFFB8 ESSI 0 Receive Data Register (RX0)

$FFB7 $FFFFB7 ESSI 0 Status Register (SSISR0)

$FFB6 $FFFFB6 ESSI 0 Control Register B (CRB0)

$FFB5 $FFFFB5 ESSI 0 Control Register A (CRA0)

$FFB4 $FFFFB4 ESSI 0 Transmit Slot Mask Register A (TSMA0)

$FFB3 $FFFFB3 ESSI 0 Transmit Slot Mask Register B (TSMB0)

$FFB2 $FFFFB2 ESSI 0 Receive Slot Mask Register A (RSMA0)

$FFB1 $FFFFB1 ESSI 0 Receive Slot Mask Register B (RSMB0)

$FFB0 $FFFFB0 Reserved

PORT D $FFAF $FFFFAF Port D Control Register (PCRD)

$FFAE $FFFFAE Port D Direction Register (PRRD)

$FFAD $FFFFAD Port C GPIO Data Register (PDRD)




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ESSI 1 $FFAC $FFFFAC ESSI 1 Transmit Data Register 0 (TX10)

$FFAB $FFFFAB ESSI 1 Transmit Data Register 1 (TX11)

$FFAA $FFFFAA ESSI 1 Transmit Data Register 2 (TX12)

$FFA9 $FFFFA9 ESSI 1 Time Slot Register (TSR1)

$FFA8 $FFFFA8 ESSI 1 Receive Data Register (RX1)

$FFA7 $FFFFA7 ESSI 1 Status Register (SSISR1)

$FFA6 $FFFFA6 ESSI 1 Control Register B (CRB1)

$FFA5 $FFFFA5 ESSI 1 Control Register A (CRA1)

$FFA4 $FFFFA4 ESSI 1 Transmit Slot Mask Register A (TSMA1)

$FFA3 $FFFFA3 ESSI 1 Transmit Slot Mask Register B (TSMB1)

$FFA2 $FFFFA2 ESSI 1 Receive Slot Mask Register A (RSMA1)

$FFA1 $FFFFA1 ESSI 1 Receive Slot Mask Register B (RSMB1)

$FFA0 $FFFFA0 Reserved

PORT E $FF9F $FFFF9F Port E Control Register (PCRE)

$FF9E $FFFF9E Port E Direction Register (PRRE)

$FF9D $FFFF9D Port E GPIO Data Register (PDRE)




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SCI $FF9C $FFFF9C SCI Control Register (SCR)

$FF9B $FFFF9B SCI Clock Control Register (SCCR)

$FF9A $FFFF9A SCI Receive Data Register - High (SRXH)

$FF99 $FFFF99 SCI Receive Data Register - Middle (SRXM)

$FF98 $FFFF98 SCI Recieve Data Register - Low (SRXL)

$FF97 $FFFF97 SCI Transmit Data Register - High (STXH)

$FF96 $FFFF96 SCI Transmit Data Register - Middle (STXM)

$FF95 $FFFF95 SCI Transmit Data Register - Low (STXL)

$FF94 $FFFF94 SCI Transmit Address Register (STXA)

$FF93 $FFFF93 SCI Status Register (SSR)

$FF92 $FFFF92 Reserved






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TRIPLE TIMER

$FF8F $FFFF8F Timer 0 Control/Status Register (TCSR0)

$FF8E $FFFF8E Timer 0 Load Register (TLR0)

$FF8D $FFFF8D Timer 0 Compare Register (TCPR0)

$FF8C $FFFF8C Timer 0 Count Register (TCR0)

$FF8B $FFFF8B Timer 1 Control/Status Register (TCSR1)

$FF8A $FFFF8A Timer 1 Load Register (TLR1)

$FF89 $FFFF89 Timer 1 Compare Register (TCPR1)

$FF88 $FFFF88 Timer 1 Count Register (TCR1)

$FF87 $FFFF87 Timer 2 Control/Status Register (TCSR2)

$FF86 $FFFF86 Timer 2 Load Register (TLR2)

$FF85 $FFFF85 Timer 2 Compare Register (TCPR2)

$FF84 $FFFF84 Timer 2 Count Register (TCR2)

$FF83 $FFFF83 Timer Prescaler Load Register (TPLR)

$FF82 $FFFF82 Timer Prescaler Count Register (TPCR)






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D.3 INTERRUPT ADDRESSES AND SOURCES

Table D-2 Interrupt Sources

InterruptStarting Address

Interrupt Priority

Level Range

Interrupt Source

VBA:$00 3 Hardware RESET

VBA:$02 3 Stack Error

VBA:$04 3 Illegal Instruction

VBA:$06 3 Debug Request Interrupt

VBA:$08 3 Trap

VBA:$0A 3 Non-Maskable Interrupt (NMI)

VBA:$0C 3 Reserved

VBA:$0E 3 Reserved

VBA:$10 0–2 IRQA

VBA:$12 0–2 IRQB

VBA:$14 0–2 IRQC

VBA:$16 0–2 IRQD


VBA:$1A 0–2 DMA Channel 1

VBA:$1C 0–2 DMA Channel 2

VBA:$1E 0–2 DMA Channel 3




VBA:$26 0–2 TIMER 0 Overflow


VBA:$2A 0–2 TIMER 1 Overflow

VBA:$2C 0–2 TIMER 2 Compare

VBA:$2E 0–2 TIMER 2 Overflow



VBA:$34 0–2 ESSI0 Receive Last Slot


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VBA:$38 0–2 ESSI0 Transmit Data With Exception Status

VBA:$3A 0–2 ESSI0 Transmit Last Slot





VBA:$44 0–2 ESSI1 Receive Last Slot


VBA:$48 0–2 ESSI1 Transmit Data With Exception Status

VBA:$4A 0–2 ESSI1 Transmit Last Slot



VBA:$50 0–2 SCI Receive Data

VBA:$52 0–2 SCI Receive Data With Exception Status

VBA:$54 0–2 SCI Transmit Data

VBA:$56 0–2 SCI Idle Line

VBA:$58 0–2 SCI Timer




VBA:$60 0–2 Host Receive Data Full

VBA:$62 0–2 Host Transmit Data Empty

VBA:$64 0–2 Host Command (Default)


: : :

VBA:$FE 0–2 Reserved

Table D-2 Interrupt Sources (Continued)

InterruptStarting Address

Interrupt Priority

Level Range

Interrupt Source

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D.4 INTERRUPT PRIORITIES

Table D-3 Interrupt Source Priorities within an IPL


Level 3 (Nonmaskable)

Highest Hardware RESET

Stack Error

Illegal Instruction

Debug Request Interrupt

Trap

Lowest Non-Maskable Interrupt

Levels 0, 1, 2 (Maskable)

Highest IRQA (External Interrupt)

IRQB (External Interrupt)

IRQC (External Interrupt)

IRQD (External Interrupt)







Host Command Interrupt

Host Transmit Data Empty

Host Receive Data Full


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ESSI0 TX Data With Exception Interrupt



ESSI1 RX Data With Exception Interrupt



ESSI1 TX Data With Exception Interrupt



SCI Receive Data With Exception Interrupt

SCI Receive Data

SCI Transmit Data

SCI Idle Line

SCI Timer






Lowest TIMER2 Compare Interrupt

Table D-3 Interrupt Source Priorities within an IPL (Continued)


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D.5 DMA REQUEST SOURCES

Table D-4 DMA Request Sources


00000 External (IRQA pin)

00001 External (IRQB pin)

00010 External (IRQC pin)

00011 External (IRQD pin)











01110 SCI Receive Data (RDRF=1)

01111 SCI Transmit Data (TDRE=1)

10000 Timer0 (TCF0=1)

10001 Timer1 (TCF1=1)

10010 Timer2 (TCF2=1)

10011 FCOP Data Input Buffer Empty (FDIBE=1)

10100 FCOP Data Output Buffer Full (FDOBF=1)

10101 VCOP Input Data (DREQ=1)

10110 VCOP Output Buffer Full (DOBF=1)

10111 VCOP Output Data (DRDY=1)

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D.6 PROGRAMMING REFERENCE SHEETS

On the following pages, Figure D-1, Status Register (SR) through Figure D-25, Port E Registers provide a set of programming reference sheets for the DSP56305 registers.

11000 VCOP Processing Done (DONE=1)

11001 CCOP Input FIFO Empty (INFE=1)

11010 CCOP Cipher Processing Done (CIDN=1)

11011 Reserved

11100 Host Slave Receive Data (SRRQ=1)

11101 Host Master Receive Data (MRRQ=1)

11110 Host Slave Transmit Data (STRQ=1)

11111 Host Master Transmit Data (MTRQ=1)


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Figure D-1 Status Register (SR)

Application: Date:

Programmer:Sheet 1 of 5

Central Processor

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0U Z V C

19 18 17 1623 22 21 20LLF S1SM I1 I0CE SA FV S0 N

Scaling ModeS(1:0) Scaling Mode

00011011

No scalingScale downScale upReserved

*0 *0

Interrupt MaskI(1:0) Exceptions Masked

00011011

NoneIPL 0IPL 0, 1IPL 0, 1, 2

Carry Overflow Zero Negative

Unnormalized ( U = Acc(47) xnor Acc(46) ) Extension Limit FFT Scaling ( S = Acc(46) xor Acc(45) )

ReservedSixteen-Bit CompatibilitityDouble Precision Multiply ModeLoop FlagDO-Forever FlagSixteenth-Bit ArithmeticReservedInstruction Cache EnableArithmetic SaturationRounding Mode

Core PriorityCP(1:0) Core Priority

00011011

0 (lowest)123 (highest)

* = Reserved, Program as 0

Mode Register (MR) Condition Code Register (CCR)Extended Mode Register (MR)

Status Register (SR)Read/WriteReset = $C00300

CP1 CP0 RM DM SC S E

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Figure D-2 Operating Mode Register (OMR)

Chip Operating ModesMOD(D:A) Reset Vector Description

0000X001X010X011X100X101X110X1111000

$C00000$FF0000$FF0000

—$FF0000$FF0000$FF0000$FF0000$008000

Expanded modeBootstrap from byte wide memoryBootstrap through SCIReservedHost Bootstrap PCI mode (32-bit wide)Host Bootstrap 16-bit wide UB mode (ISA)Host Bootstrap 8-bit wide UB mode (dbl strb)Host Bootstrap 8-bit wide UB mode (sgl strb)Expanded mode

Application: Date:


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0EBD MC MB MA

19 18 17 1623 22 21 20SDBRT TASSEN CDP1 CDP0WRP EOV EUN XYS BE MD

Core-DMA PriorityCDP(1:0) Core-DMA Priority

00011011

Core vs DMA PriorityDMA accesses > CoreDMA accesses = CoreDMA accesses < Core

*0 *0 *0 *0

Chip Operating Mode Register (COM)

System Stack ControlStatus Register (SCS)

Extended Chip OperatingMode Register (COM)

X = Latched from levels on Mode pins

Operating Mode Register (OMR)Read/WriteReset = $00030X

Central Processor


Burst Mode EnableTA Synchronize SelectBus Release Timing

Stack Extension Space SelectExtended Stack Underflow FlagExtended Stack Overflow FlagExtended Stack Wrap FlagStack Extension Enable

Memory Switch Mode

MS

External Bus DisableStop Delay

Patch Enable

PEN ATE APD

Address Priority DisableAddress Tracing Enable

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56305 User’s M

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-19

Figure D

-3 Interrupt Priority Register–C

ore (IPR–C

)

Application:

Date:

Program

mer:

Sheet 3 of 5

CENTRAL PROCESSOR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0D1L0 IDL2 IDL1 IBL2 IBL1 IBL0 IAL2 IAL1 IAL0

Interrupt Priority

X:$FFFF Read/Write

D0L1 D0L0

Reset = $000000

Register (IPR–C)

23 22 21 20 19 18 1617D1L1

IAL2 Trigger0 Level1 Neg. Edge

IRQA ModeIAL1 IAL0 Enabled IPL

0 0 No —0 1 Yes 01 0 Yes 11 1 Yes 2

IBL2 Trigger0 Level1 Neg. Edge

IRQB ModeIBL1 IBL0 Enabled IPL

0 0 No —0 1 Yes 01 0 Yes 11 1 Yes 2

ICL0ICL1ICL2IDL0D2L0D2L1D3L0D3L1D4L0D4L1D5L0D5L1

ICL2 Trigger0 Level1 Neg. Edge

IRQC ModeICL1 ICL0 Enabled IPL

0 0 No —0 1 Yes 01 0 Yes 11 1 Yes 2

IDL2 Trigger0 Level1 Neg. Edge

IRQD ModeIDL1 IDL0 Enabled IPL

0 0 No —0 1 Yes 01 0 Yes 11 1 Yes 2

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D-20

DS

P56305 U

ser’s Manual

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Figure D

-4 Interrupt Priority Register – Peripherals (IPR

–P)

Application:

Date:

Program

mer:

Sheet 4 of 5

CENTRAL PROCESSOR


Interrupt Priority

X:$FFFF Read/WriteReset = $000000

Register (IPR–P)

HPL1 HPL0 Enabled IPL0 0 No —0 1 Yes 01 0 Yes 11 1 Yes 2

Host IPL

S0L1 S0L0 Enabled IPL0 0 No —0 1 Yes 01 0 Yes 11 1 Yes 2

ESSI0 IPL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0S1L1 S1L0 SOL1 S0L0 HPL1 HPL0

23 22 21 20 19 18 1617SCL0SCL1T0L0T0L1*0 *0 *0 *0 *0 *0

$0

*0 *0 *0 *0$0

*0 *0 *0 *0$0

S1L1 S1L0 Enabled IPL0 0 No —0 1 Yes 01 0 Yes 11 1 Yes 2

ESSI1 IPL

SCL1 SCL0 Enabled IPL0 0 No —0 1 Yes 01 0 Yes 11 1 Yes 2

SCI IPLTOL1 TOL0 Enabled IPL

0 0 No —0 1 Yes 01 0 Yes 11 1 Yes 2

Timer IPL

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Figure D

-5 Phase Lock L

oop Control R

egister (PCT

L)

Application:

Date:

Program

mer:

Sheet 5 of 5

PLL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0MF7 MF5 MF4 MF3 MF2 MF1 MF0

19 18 17 1623 22 21 20PENCODPD1PD3 MF6PD2 XTLD XTLR DF2 DF1 DF0 MF11PD0 PSTP MF10 MF9 MF8PLL Control

Register (PCTL)X:$FFFFFD Read/Write

Reset = $000000

XTAL Disable Bit (XTLD)

0 = Enable Xtal Oscillator

1 = EXTAL Driven FromAn External Source

Clock Output Disable (COD)

0 = 50% Duty Cycle Clock

1 = Pin Held In High State Crystal Range Bit (XTLR)0 = External Xtal Freq < 200KHz

1 = External Xtal Freq > 200KHz

Predivision Factor Bits (PD0 – PD3)PD3 – PD0 Predivision Factor PDF

$0$1$2•••

$F

123•••

16

Multiplication Factor Bits MF0 – MF11MF11 – MF0 Multiplication Factor MF

$000$001$002

•••

$FFE$FFF

123•••

40954096

Division Factor Bits (DF0 – DF2)DF2 – DF0 Division Factor DF

$0$1$2•••

$7

20

21

22

•••

27

PSTP and PEN Relationship

PSTP PENOperation During STOP Recovery Time

for STOPPower Consumption

during STOPPLL Oscillator0 x Disabled Disabled Long Minimal1 0 Disabled Enabled Short Lower1 1 Enabled Enabled Short Higher

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Figure D-6 Host Receive and Host Transmit Data Registers

Application: Date:


HOST (HI08)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 019 18 17 1623 22 21 20Receive High Byte Receive Middle Byte Receive Low Byte

Host Receive Data Register (HRX)X:$FFEC6 Read OnlyReset = empty

Host Receive Data (usually Read by program)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 019 18 17 1623 22 21 20Transmit High Byte Transmit Middle Byte Transmit Low Byte

Host Transmit Data (usually Loaded by program)

Host Transmit Data Register (HTX)X:$FFEC7 Write OnlyReset = empty

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Figure D-7 Host Control and Host Status Registers

Application: Date:


HOST

7 6 5 4 3 2 1 015


*0 *0 *0

DSP Side

Host Receive Data Full1 = ÷ Read0 = ÷ Wait

HCP HRDFHF1 HTDEHF0

Host FlagsRead Only

Host Command Pending1 = ÷ Ready0 = ÷ Wait

Host Transmit Data Empty1 = ÷ Write0 = ÷ Wait

*0Host Staus Register (HSR)X:$FFFFC3 Read Only

Reset = $2

7 6 5 4 3 2 1 015

*0 *0 *0

Host Receive Interrupt Enable1 = Enable0 = Disable

HCIE HRIEHF3 HTIEHF2

Host Flag 2

Host Command Interrupt Enable

Host Transmit Interrupt Enable1 = Enable0 = Disable

*0Host Control Register (HCR)X:$FFFFC2 Read /Write

Reset = $0

if HRDF = 1

if HTDE = 1

1 = Enable0 = Disable if HCP = 1

Host Flag 3

(HI08)

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Figure D-8 Host Base Address and Host Port Control Registers

Application: Date:


HOST (HI08)7 6 5 4 3 2 1 015

BA5 BA3BA7 BA4BA6*0Host Base Address Register (HBAR)X:$FFFFC5Reset = $80

8BA8BA9BA10*0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0HAEN HREN HCSEN HA9EN HA8EN HGEN


HEN*0HAP HRP HCSP HDDS HRODHMUX HDSPHASPHost Port Control

X:$FFFFC4

Reset = $0

Host Acknowledge Enable0 → HACK = GPIO

Host Request Enable0 → HREQ/HACK = GPIO,1 → HREQ = HREQ, if HDRQ = 0

Host Chip Select Enable0 → HCS/HAI0 = GPIO,1 → HCS/HA10 = HC8, if HMUX = 01 → HCS/HA10 = HC10, if HMUX = 1

Host Address Line 9 Enable0 → HA9 = GPIO, 1 → HA9 = HA9

Host Address Line 8 Enable0 → HA8 = GPIO, 1 → HA8 = HA8

Host GPIO Port Enable0 = GPIO Pins Disable, 1 = GPIO Pin Enable

Host Acknowledge Priority0 = HACK Active Low, 1 = HACK Active High

Host Chip Select Polarity0 = HCS Active Low

Host Dual Data Strobe0 = Singles Stroke, 1 = Dual Stoke

Host Multiplexed Bus0 = Nonmultiplexed, 1 = Multiplexed

Host Address Strobe Polarity0 = Strobe Active Low, 1 = Strobe Active High

Host Data Strobe Polarity0 = Strobe Active Low, 1 = Strobe Active High

Host Enable0 → HI08 Disable

1 → HI08 Enable

Pins = GPIO

Register (HPCR)

Read/Write

If HDRQ & HREN = 1,HACK = HACK

Host Request Open DrainHDRQ HROD HREN/HEW

0011

0101

1111

HTRQ & HRRQ Enable1 = HCS Active High

Host Request PriorityHDRQ HRP

0011

0101

HREQ Active LowHREQ Active HighHTRQ,HRRQ Active LowHTRQ,HRRQ Active High

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Figure D-9 Interrupt Control and Interrupt Status Registers

Application: Date:


HOST (HI08)

7 6 5 4 3 2 1 0

Processor Side

RREQHF1 TREQHF0INIT HLEND

Interrupt Control Register (ICR)X:$

Read/Write

Transmit Request EnableDMA Off 0 = ∏ Interrupts Disabled 1 = Interrupts EnabledDMA On 0 = DSP → Host 1 = Host → DSP

Host FlagsWrite Only

Initialize (Write Only)

Host Little Endian

Receive Request EnableDMA Off 0 = ÷ Interrupts Disabled 1 = Interrupts EnabledDMA On 0 = Host → DSP 1 = DSP → Host

0 = ÷ No Action 1 = ÷ Initialize DMA

HDRQ*0

HDRQ HREQ/HTRQ HACK/HRRQ0 HREQ HACK1 HTRQ HRRQ

Reset = $0

7 6 5 4 3 2 1 0


*0RXDFHF3 TXDEHF2HREQ DMA TRDY

Interrupt Status Register (ISR)$2 Read/Write

Reset = $06

Transmit Data Register Empty0 = Wait 1 = Write

Transmitter Ready0 = Data in HI 1 = Data Not in HI

DMA Status0 = ÷ DMA Disabled 1 = ÷ DMA Enabled

Host FlagsRead Only

Receive Data Register Full0 = Wait 1 = Read

Host Request0 = ÷ HREQ Deasserted 1 = ÷ HREQ Asserted

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Figure D-10 Interrupt Vector and Command Vector Registers

Application: Date:


HOST (HI08)

7 6 5 4 3 2 1 0IV0IV4 IV1IV3IV7 IV5

Interrupt Vector Register (IVR)

IV2

Reset = $0F

Contains the interrupt vector or number

IV6

7 6 5 4 3 2 1 0HC0HC4 HC1HC3HC7 HC5

Command Vector Register (CVR)

HC2

Reset = $2A

Contains the host command interrupt address

HC6

Host VectorContains Host Command Interrupt Address ÷ 2

Host CommandHandshakes Executing Host Command Interrupts

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Figure D-11 Host Receive and Host Transmit Data Registers

Application: Date:


HOST (HI08) Processor Side

7 0 7 007

Host Receive Data (usually Read by program)

Receive Byte Registers$7, $6, $5, $4 Read OnlyReset = $00

Transmit Byte Registers$7, $6, $5, $4 Write OnlyReset = $00

Receive Byte Registers

$6 $5 $4

00 0 0 0 0 0 0

07

$7

Receive Middle Byte Receive High Byte Not UsedReceive Low Byte

7 0 7 007

Host Transmit Data (usually loaded by program)

$6 $5 $4

00 0 0 0 0 0 0

07

$7

Transmit Middle Byte Transmit High Byte Not UsedTransmit Low Byte

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D-28

DS

P56305 U

ser’s Manual

MO

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Figure D

-12 ESSI C

ontrol Register A

(CR

A)

Application:

Date:

Program

mer:

Sheet 1 of 4

ESSI

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0PM7 PM5 PM4 PM3 PM2 PM1 PM0

19 18 17 1623 22 21 20ALCWL0WL1SSC1


PM6*0*0*0*0

Word Length ControlWL2 WL1 WL0 Number of bits/word

0 0 0 80 0 1 120 1 0 160 1 1 241 0 0 32 (data in first 24 bits)1 0 1 32 (data in last 24 bits)1 1 0 Reserved1 1 1 Reserved

ESSI Control Register A (CRAx)ESSI0:$FFFFB5 Read/WriteESSI1:$FFFFA5 Read/WriteReset = $000000

Select SC1 as Tx#0 drive enable0 = SC1 functions as serial I/O flag1 = functions as driver enable of Tx#0 external buffer

Frame Rate Divider ControlDC4:0 = $00-$1F (1 to 32)Divide ratio for Normal mode# of time slots for Network

Prescaler Range0 = ÷8 1 = ÷1

Prescale Modulus SelectPM7:0 = $00-$FF (÷1 to ÷256)

PSR = 1 & PM[7:0] = $00 is

*0WL2 DC4 DC3 DC2 DC1 DC0 PSR

Alignment Control0 = 16-bit data left aligned to bit 231 = 16-bit data left aligned to bit 15

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56305 User’s M

anualD

-29

Figure D

-13 ESSI C

ontrol Register B

(CR

B)

Application:

Date:

Program

mer:

Sheet 2 of 4

ESSI

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0FSL0 SCKD SCD2 SCD1 SCD0 OF1 OF0

19 18 17 1623 22 21 20TIERIERLIEREIE SHFD

Serial Control Direction BitsSCDx = 0 (Input) SCDx = 1(Output)

SC0 Pin Rx Clk Flag 0SC1 Pin Rx Frame Sync Flag 1SC2 Pin Tx Frame Sync Tx, Rx Frame Sync

TEIE TE0 TE1 TE2 MOD SYN CKP

Transmit 2 Enable (SYN=1 only) 0 = Disable 1 = Enable

Shift Direction 0 = MSB First 1 = LSB First

Frame Sync Relative Timing (WL Frame Sync only)0 = with 1st data bit 1 = 1 clock cycle earlier than 1st data bit

Mode Select0 = Normal 1 = Network

Clock Polarity (clk edge data & Frame Sync clocked out/in)0 = out on rising / in on falling 1 = in on rising / out on falling

Sync/Async Control (Tx & Rx transfer together or not)0 = Asynchronous 1 = Synchronous

ESSI Control Register B (CRBx)

ESSI0 :$FFFFB6 Read/WriteESSI1 :$FFFFA6 Read/Write

Reset = $000000

Transmit 1 Enable (SYN=1 only) 0 = Disable 1 = Enable

Transmit Interrupt Enable 0 = Disable 1 = Enable

Receive Interrupt Enable 0 = Disable 1 = Enable

Transmit Last Slot Interrupt Enable 0 = Disable 1 = Enable

Receive Last Slot Interrupt Enable 0 = Disable 1 = Enable

Transmit Exception Interrupt Enable 0 = Disable 1 = Enable

Receive Exception Interrupt Enable 0 = Disable 1 = Enable

Frame Sync Polarity0 = high level (positive) 1 = low level (negative)

TLIE RE FSP FSR FSL1

Output Flag xIf SYN = 1 and SCD1 = 1OFx → SCx Pin

Clock Source Direction 0 = External Clock 1 = Internal Clock

Transmit 0 Enable 0 = Disable 1 = Enable

Receiver Enable 0 = Disable 1 = Enable

FSL1 FSL0Frame Sync Length

TX RX0 0 Word Word0 1 Bit Word1 0 Bit Bit1 1 Word Bit

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Figure D-14 ESSI Status Register (SSISR)

Application: Date:


ESSI

7 6 5 4 3 2 1 0IF0IF1RFSTUEROERDF TDE

* = Reserved, program as 0

23

*0TFS

Receive Frame Sync0 = ÷ Wait 1 = ÷ Frame Sync Occurred

Transmitter Underrun Error Flag0 = ÷ OK 1 = ÷ Error

Receiver Overrun Error Flag0 = ÷ OK 1 = ÷ Error

Transmit Data Register Empty0 = ÷ Wait 1 = ÷ Write

Transmit Frame Sync0 = ÷ Sync Inactive 1 = ÷ Sync Active

Receive Data Register Full1 = ÷ Read

Serial Input Flag 0If SCD0 = 0, SYN = 1, & TE1 = 0latch SC0 on FS

Serial Input Flag 1If SCD1 = 0, SYN = 1, & TE2 = 0latch SC0 on FS

0 = ÷ Wait

SSI Status Bits

SSI Status Register (SSISRx)ESSI0: $FFFFB7 (Read)ESSI1: $FFFFA7 (Read)

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Figure D-15 ESSR Transmit and Receive Slot Mask Registers (TSM, RSM)

Application: Date:


ESSI

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RS23 RS21 RS20 RS19 RS18 RS17 RS16

1623


RS22*0RS31 RS30 RS29 RS28 RS27

SSI Receive Slot Mask ARSMAx

ESSI0: $FFFFB2 Read/WriteESSI1: $FFFFA2 Read/Write

Reset = $FFFF

SSI Receive Slot Mask BRSMBx


Reset = $FFFF

ESSI Transmit Slot Mask ATSMAx


Reset = $FFFF

ESSI Transmit Slot Mask BTSMBx


Reset = $FFFF

ESSI Receive Slot Mask A

ESSI Receive Slot Mask B

ESSI Transmit Slot Mask A

ESSI Transmit Slot Mask B

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RS7 RS5 RS4 RS3 RS2 RS1 RS0

1623


RS6*0RS15 RS14 RS13 RS12 RS11

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0TS23 TS21 TS20 TS19 TS18 TS17 TS16

1623


TS22*0TS31 TS30 TS29 TS28 TS27

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0TS7 TS5 TS4 TS3 TS2 TS1 TS0

1623


TS6*0TS15 TS14 TS13 TS12 TS11

SSI Receive Slot Mask 0 = Ignore Time Slot 1 = Active Time Slot

SSI Receive Slot Mask0 = Ignore Time Slot1 = Active Time Slot

SSI Transmit Slot Mask0 = Ignore Time Slot1 = Active Time Slot

*0TS10 TS9 TS8

SSI Transmit Slot Mask0 = Ignore Time Slot1 = Active Time Slot

TS26 TS25 TS24*0

RS10 RS9 RS8

RS26 RS25 RS24

*0

*0

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Figure D-16 SCI Control Register (SCR)

Application: Date:


SCI

Port E Control Register (PCRE)

SCI Control Register (SCR)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0WOMS WAKE SBK SSFTD WDS2 WDS1 WDS0

23


RWU*0SCKP STIR TMIE TIE RIE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0PC1 PC0


ILIE TE RE

*0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0PC2

$0$0$0

Port E Pin Control0 = General Purpose I/O Pin1 = SCI pin

SCI Shift Direction0 = LSB First1 = MSB First

Send Break0 = Send break, then revert1 = Continually send breaks

Receiver Wakeup Enable0 = receiver has awakened1 = Wakeup function enabled

Receiver Enable0 = Receiver Disabled1 = Receiver Enabled

Wired-Or Mode Select1 = Multidrop0 = Point to Point

Wakeup Mode Select0 = Idle Line Wakeup1 = Address Bit Wakeup

Word Select Bits0 0 0 = 8-bit Synchronous Data (Shift Register Mode)0 0 1 = Reserved0 1 0 = 10-bit Asynchronous (1 Start, 8 Data, 1 Stop)0 1 1 = Reserved1 0 0 = 11-bit Asynchronous (1 Start, 8 Data, Even Parity, 1 Stop)1 0 1 = 11-bit Asynchronous (1 Start, 8 Data, Odd Parity, 1 Stop)1 1 0 = 11-bit Multidrop (1 Start, 8 Data, Data Type, 1 Stop)1 1 1 = Reserved

Port EControl Register (PCRE)

X:$FFFF9F Read/WriteReset = $000000

Transmitter Enable0 = Transmitter Disable1 = Transmitter Enable

Transmit Interrupt Enable0 = Transmit Interrupts Disabled1 = Transmit Interrupts Enabled

Idle Line Interrupt Enable0 = Idle Line Interrupt Disabled1 = Idle Line Interrupt Enabled

Receive Interrupt Enable

SCI Clock Polarity0 = Clock Polarity is Positive1 = Clock Polarity is Negative

SCI Timer Interrupt Rate0 = ÷ 32, 1 = ÷ 1

Timer Interrupt Enable0 = Timer Interrupts Disabled1 = Timer Interrupts Enabled

0 = Receive Interrupt Disabled1 = Idle Line Interrupt Enabled

Register (SCR)Address X:$FFFF9C

Read/Write

SCI Control REIE

16

SCI Receive Exception Inerrupt0 = Receive Interrupt Disable1 = Receive Interrupt Enable

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Figure D-17 SCI Status and Clock Control Registers (SSR, SCCR)

Application: Date:


SCI

SCI Clock Control Register (SCCR)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0CD7 CD5 CD4 CD3 CD2 CD1 CD0

23


CD6*0TCM RCM SCP COD CD11

23 7 6 5 4 3 2 1 0TDRE TRNE


CD10 CD9 CD8

*0RDRF

$0

IDLEORPEFER8SCI Status Register (SSR)

Address X:$FFFF93Read Only

Reset = $000003

Received Bit 80 = Data1 = Address

Framing Error Flag0 = No error1 = No Stop Bit detected

Parity Error Flag0 = No error1 = Incorrect Parity detected

Overrun Error Flag0 = No error1 = Overrun detected

Idle Line Flag0 = Idle not detected1 = Idle State

Receive Data Register Full0 = Receive Data Register Full1 = Receive Data Register Empty

Transmitter Data Register Empty0 = Transmitter Data Register full1 = Transmitter Data Register empty

Transmitter Empty0 = Transmitter full1 = Transmitter empty

Clock Divider Bits CD11 – CD0)CD11 – CD0 Icyc Rate

$000 Icyc/1$001 Icyc/2$002 Icyc/3

• •• •• •

$FFE Icyc/4095$FFF Icyc/4096

SCI Clock Prescaler 0 = ÷1 1 = ÷ 8

SCI Status Register (SSR)

Clock Out Divider0 = Divide clock by 16 before feed to SCLK1 = Feed clock to directly to SCLK

Clock Divider Bits CD11 – CD0)TCM RCM TX Clock RX Clock SCLK Pin Mode

0 0 Internal Internal Output Synchronous/Asynchronous0 1 Internal External Input Asynchronous only1 0 External Internal Input Asynchronous only1 1 External External Input Synchronous/Asynchronous

Receiver Clock Mode/Source0 = Internal clock for Receiver1 = External clock from SCLK

Transmitter Clock Mode/Source0 = Internal clock for Transmitter1 = External clock from SCLK

$3

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Figure D-18 SCI Receive and Transmit Data Registers (SRX, TRX)

Application: Date:


SCI

23 16 15 8 7 0

X:$FFFF97

X:$FFFF96

X:$FFFF95

STX

STX

STX

X0 “A” “B” “C”

SCI Transmit Data RegistersAddress X:$FFFF95 – X:$FFFF97

WriteReset = xxxxxx

Unpacking

TXDSCI Transmit SR

SCI Transmit Data Registers

SCI Receive Data Registers

X:$FFFF94 STXA

23 16 15 8 7 0

SRX

SRX

SRX

“A” “B” “C”

Packing

RXD SCI Receive SR

SCI Receive Data RegistersAddress X:$FFFF98 – X:$FFFF9A

ReadReset = xxxxxx

X:$FFFF9A

X:$FFFF99

X:$FFFF98

Note: STX is the same register decoded at four different addresses

Note: STX is the same register decoded at three different addresses

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Figure D-19 Timer Prescaler Load/Count Register (TPLR, TPCR)

Application: Date:


Timers

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 019 18 17 1623 22 21 20PS0PS1*0 Prescaler Preload Value (PL [0:20])


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 019 18 17 1623 22 21 20

*0 Current Value of Prescaler Counter (PC [0:20])

Timer Prescaler Load RegisterTPLR:$FFFF83 Read/WriteReset = $000000

Timer Prescaler Count RegisterTPCR:$FFFF82 Read OnlyReset = $000000


PS (1:0) Prescaler Clock Source00 Internal CLK/201 TIO010 TIO111 TIO2

*0 *0

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Figure D-20 Timer Control/Status Register (TCSR)

Application: Date:


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0TC3 TC1 TC0 TCIE TQIE TE

19 18 17 1623 22 21 20TCF TC2PCE DO DI DIRTOF TRM INV

Timers

*0 *0*0 *0*0 *0 *0 *0 *0

Timer Enable Bit 00 = Timer Disabled1 = Timer Enabled

Timer Overflow Interrupt Enable Bit 10 = Overflow Interrupts Disabled1 = Overflow Interrupts Enabled

Inverter Bit 80 = 0- to-1 transitions on TIO input increment the counter,or high pulse width measured, or high pulse output on TIO

1 = 1-to-0 transitions on TIO input increment the counter,or low pulse width measured, or low pulse output on TIO

Timer Compare Interrupt Enable Bit 20 = Compare Interrupts Disabled1 = Compare Interrupts Enabled

Timer Control/Status RegisterTCSR0:$FFFF8F Read/WriteTCSR1:$FFFF8B Read/WriteTCSR2:$FFFF87 Read/WriteReset = $000000


Timer Control Bits 4 – 7 (TC0 – TC3)TC (3:0) TIO Clock Mode

0000000100100011010001010110011110001001101010111100110111101111

GPIOOutputOutputInputInputInputInput

Output–

OutputOutput

–––––

InternalInternalInternalExternalInternalInternalInternalInternal

–InternalInternal

–––––

TimerTimer PulseTimer ToggleEvent CounterInput WidthInput PeriodCapturePulse Width ModulationReservedWatchdog PulseWatchdog ToggleReservedReservedReservedReservedReserved

Timer Reload Mode Bit 9

1 = Timer is reloaded whenselected condition occurs

0 = Timer operates as a freerunning counter

Timer Overflow Flag Bit 200 = “1” has been written to TCSR(TOF),or timer Overflow interrupt serviced

1 = Counter wraparound has occurred

Direction Bit 110 = TIO pin is input1 = TIO pin is output

Data Output Bit 130 = Zero written to TIO pin 1 = One written to TIO pin

Data Input Bit 120 = Zero read on TIO pin 1 = One read on TIO pin

Timer Compare Flag Bit 210 = “1” has been written to TCSR(TCF),or timer compare interrupt serviced

1 = Timer Compare has occurred

Prescaled Clock Enable Bit 150 = Clock source is CLK/2 or TIO1 = Clock source is prescaler output

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Figure D-21 Timer Load, Compare, Count Registers (TLR, TCPR, TCR)

Application: Date:


Timers

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 019 18 17 1623 22 21 20

Timer Reload Value

Timer Load RegisterTLR0:$FFFF8E Write Only

Reset = $000000

TLR1:$FFFF8A Write OnlyTLR2:$FFFF86 Write Only

Timer Compare RegisterTCPR0:$FFFF8D Read/Write

Reset = $000000

TCPR1:$FFFF89 Read/WriteTCPR2:$FFFF85 Read/Write

Timer Count RegisterTCR0:$FFFF8C Read OnlyTCR1:$FFFF88 Read OnlyTCR2:$FFFF84 Read Only

Reset = $000000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 019 18 17 1623 22 21 20

Value Compared to Counter Value

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 019 18 17 1623 22 21 20

Timer Count Value

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Figure D-22 Host Data Direction and Host Data Registers (HDDR, HDR)

Application: Date:


GPIO

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0DR5 DR4 DR3 DR2 DR1 DR0DR6DR15 DR14 DR13 DR12 DR8DR11 DR9DR10Direction Register

X:$FFFFC8

Reset = $0

(HDDR)

Write

Host Data

DRx = 0 → HIx is InputDRx = 1 → HIx is Output

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0D5 D4 D3 D2 D1 D0D6D15 D14 D13 D12 D8D11 D9D10Register

X:$FFFFC9

Reset = Undefined

(HDR)

Write

Host Data

DRx holds value of corresponding HI08 GPIO pin.

DR7

D7

Function depends on HDDR.

Port B (HI08)

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Figure D-23 Port C Registers (PCRC, PRRC, PDRC)

Application: Date:


GPIO

23 6 5 4 3 2 1 0PC5 PC4 PC3 PC2 PC1 PC0Port C Control Register

X:$FFFFBF

Reset = $0

(PCRC)

ReadWrite

*0


*0

PCn = 1 → Port Pin configured as ESSIPCn = 0 → Port Pin configured as GPIO

Port C (ESSI0)

23 6 5 4 3 2 1 0PDC5 PDC4 PDC3 PDC2 PDC1 PDC0Port C Direction Register

X:$FFFFBE

Reset = $0

(PRRC)

ReadWrite

*0*0

PDCn = 1 → Port Pin is OutputPDCn = 0 → Port Pin is Input

23 6 5 4 3 2 1 0PD5 PD4 PD3 PD2 PD1 PD0Port C GPIO Data Register

X:$FFFFBD

Reset = $0

(PDRC)

ReadWrite

*0*0

port pin n is GPIO input, then PDn reflects the value on port pin n

if port pin n is GPIO output, then value written to PDn is reflected on port pin n

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Figure D-24 Port D Registers (PCRD, PRRD, PDRD)

Application: Date:


GPIO

23 6 5 4 3 2 1 0PC5 PC4 PC3 PC2 PC1 PC0Port D Control Register

X:$FFFFAF

Reset = $0

(PCRD)

ReadWrite

*0


*0

PCn = 1 → Port Pin configured as ESSIPCn = 0 → Port Pin configured as GPIO

Port D (ESSI1)

23 6 5 4 3 2 1 0PDC5 PDC4 PDC3 PDC2 PDC1 PDC0Port D Direction Register

X:$FFFFAE

Reset = $0

(PRRD)

ReadWrite

*0*0


23 6 5 4 3 2 1 0PD5 PD4 PD3 PD2 PD1 PD0Port D GPIO Data Register

X:$FFFFAD

Reset = $0

(PDRD)

ReadWrite

*0*0



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Figure D-25 Port E Registers

Application: Date:


GPIO

23 6 5 4 3 2 1 0PC2 PC1 PC0Port E Control Register

X:$FFFF9F

Reset = $0

(PCRE)

ReadWrite

*0


*0

PCn = 1 → Port Pin configured as SCIPCn = 0 → Port Pin configured as GPIO

Port E (SCI)

23 6 5 4 3 2 1 0PDC2 PDC1 PDC0Port E Direction Register

X:$FFFF9E

Reset = $0

(PRRE)

ReadWrite

*0*0


23 6 5 4 3 2 1 0PD2 PD1 PD0Port E GPIO Data Register

X:$FFFF9D

Reset = $0

(PDRE)

ReadWrite

*0*0



*0 *0 *0

*0 *0 *0

*0 *0 *0

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D.7 QUICK REFERENCE TABLES

(See Table D-5 HI32 Programming Model - Quick Reference on page D-43.)

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Table D-5 HI32 Programming Model - Quick Reference

HI32 Registers - Quick Reference (Sheet 1 of 8)

Reg Bit # Comments Reset Type

Mnemonic Name Val Function HS PH PS

DSP SIDE

DCTR HCIE Host Command Interrupt Enable

01

HCP interrupt disabledHCP interrupt enabled

0 - -

STIE Slave Transmit Interrupt Enable

01

STRQ interrupt disabledSTRQ interrupt enabled

0 - -

SRIE Slave Receive Interrupt Enable

01

SRRQ interrupt disabledSRRQ interrupt enabled

0 - -

HF5-HF3 Host Flags $0 - -

HINT Host Interrupt A 0

1

HINTA signal is high impedanceHINTA signal is driven low

0

HDSM Host Data Strobe Mode 0

1

HWR + HRD (double data strobe)HRW + HDS (single data strobe)

may be changed only in PS reset

0 - -

HRWP Host RD/WR Polarity 01

HRW (0 = WRITE, 1 = READ)HRW(0 = READ, 1 = WRITE)


0 - -

HTAP Host Transfer Acknowledge Polarity

01

HTAHTA


0 - -

HDRP Host DMA Request Polarity 01

HDRQHDRQ


0 - -

HRSP Host Reset Polarity 01

HRSTHRST


0 - -

HIRH Host Interrupt Request Handshake Mode

01

HIRQ pulsedHIRQ - full handshake

may be changed only in PS resetHIRQ pulse width is defined by CLAT

0 - -

HIRD Host Interrupt Request Drive Control

01

HIRQ - open drainHIRQ - driven


0 - -

22-20

HM2-HM0 HI32 Mode 00000101001110010111x

Terminate and ResetPCIGenBusEnhanced GenBusGPIOSelf ConfigurationReserved

may be changed to non-zero value only in PS reset

$0 - -

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DPCR MTIE Master Transmit Interrupt Enable

01

MTRQ interrupt disabledMTRQ interrupt enabled

0 - -

MRIE Master Receive Interrupt Enable

01

MRRQ interrupt disabledMRRQ interrupt enabled

0 - -

MAIE Master Address Interrupt Enable

01

A/DPER interrupt disabledA/DPER interrupt enabled

0 - -

PEIE Parity Error Interrupt Enable 01

MARQ interrupt disabledMARQ interrupt enabled

0 - -

TAIE Transaction Abort Interrupt Enable

01

M/TAB interrupt disabledM/TAB interrupt enabled

0 - -

TTIE Transaction Termination Int. En.

01

TO/DIS/RTY interrupt disabledTO/DIS/RTY interrupt enabled

0 - -

TCIE Transfer Complete Interrupt Enable

01

HDTC interrupt disabledHDTC interrupt enabled

0 - -

CLRT Clear Transmitter 01

inactiveempty master transmitter path

may be set only if MARQ = 1cleared by hardware

0 - -

MTT Master Transfer Terminate 01

inactiveterminate current PCI transaction

may be set only if MWS = 1 cleared by hardware

0 - -

SERF HSERR Force 01

inactivegenerate a PCI system error

cleared by hardware

0 - -

18 MACE Master Access Counter Enable

01

unlimited burst lengthburst length is limited by the BL value

0 - -

MWSD Master Wait State Disable 01

HI32 master inserts wait statesHI32 master releases bus

may be set only if MARQ = 1

0 - -

RBLE Receive Buffer Lock Enable 0

1

HI32 responds to new accessesHI32 retries accesses after write accesses


0 - -

IAE Insert Address Enable 01

HI32 does not insert addressHI32 inserts address in incoming data


0 - -




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DPMC 15-0

AR31-AR16 DSP PCI Transaction Address (High)

may be written only if MARQ = 1

$0000 - -

21-16

BL5-BL0 PCI Data Burst Length may be written only if MARQ = 1

$0 - -

23-22

FC1-FC0 Data Transfer Format Control 00

011011

Transmit Receive32 bit mode32 bit mode3 Right, zero ext.3 LSBs3 Right, sign ext.3 LSBs3 Left, zero filled3 MSBs


$0 - -

DPAR 15-0

AR15-AR0 DSP PCI TransactionAddress (Low)


$0000 - -

19-16

C3-C0 PCI Bus Command may be written only if MARQ = 1

$0 - -

23-20

BE3-BE0 PCI Byte Enables may be written only if MARQ = 1

$0 - -

DSR HCP Host Command Pending 01

no host command pendinghost command pending

cleared when the HC interrupt request is serviced

- - 0

STRQ Slave Transmit Data Request

10

slave transmit FIFO is not fullslave transmit FIFO is full

cleared if the DTXS is filled by core writes

1a - 1(a)

SRRQ Slave Receive Data Request 01

slave receive FIFO is emptyslave receive FIFO is not empty

cleared if the DRXR is emptied by core reads; or the data to be read from the DRXR is master data.

0 - 0

HF2-HF0 Host Flags - $0 -

HACT HI32 Active 01

HI32 is in personal reset (PS)HI32 is active

0 - 0




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DPSR MWS PCI Master Wait States 01

HI32 is asserting HIRDYHI32 is negating HIRDY

0 - 0

MTRQ PCI Master Transmit Data Req.

10

master transmit FIFO is not fullmaster transmit FIFO is full

cleared if the DTXM is filled by core writes

1(a) - 1(a)

MRRQ PCI MasterReceive Data Req.

01

master receive FIFO is emptymaster receive FIFO is not empty

cleared if the DRXR is emptied by core reads; or the data to be read from the DRXR is slave data.

0 - 0

MARQ PCI Master Address Request 1

0

core may initiate new transactioncore may not initiate new transaction

0 0 0

APER PCI Address Parity Error 0

1

HI32 target has not detected an address parity errorHI32 target has detected an address parity error

cleared by writing 1

0 - -

DPER PCI Data Parity Error 01

a data parity error has not occurreda data parity error has occurred


0 - -

MAB PCI Master Abort 01

a master abort has not occurreda master abort has occurred


0 - -

TAB PCI Target Abort 01

a target abort has not occurreda target abort has occurred


0 - -

TDIS PCI Target Disconnect 01

a target disconnect has not occurreda target disconnect has occurred


0 - -

TRTY PCI Target Retry 01

a target retry has not occurreda target retry has occurred


0 - -

TO PCI Time Out Termination 0

1

a time-out termination has not occurreda time-out termination has occurred


0 - -

HDTC PCI Host Data Transfer Complete

0

1

HI32 is transferring data to the core HI32 has completed transfer of data to the core, and will disconnect write accesses to the HTXR

cleared by writing 1may be written 1 only if HDTC = 1

0 - 0

21-16 RDC5-RDC0

Remaining Data Count - - -




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DRXR 23-0

DSP Receive Data FIFO empty

DTXM 23-0

DSP Master Transmit Data FIFO

empty

DTXS 23-0

DSP SlaveTransmit Data FIFO

empty

DATH 23-0

DAT23-DAT0

GPIO Signal Data $000000 - -

DIRH 23-0

DIR23-DIR0 GPIO Signal Direction [0][1]

InputOutput

$000000 - -

Host Side

HCTR TREQ Transmit Request Enable

01

HTRQ interrupt disabledHTRQ interrupt enabled

- 0 -

RREQ Receive Request Enable 01

HRRQ interrupt disabledHRRQ interrupt enabled

- 0 -

HF2-HF0 Host Flags - 0 -

DMAE DMA Enable (ISA/EISA) 01

HI32 does not support DMA transfersHI32 supports ISA-DMA type transfers

- 0 -

7 SFT Slave Fetch Type 01

Pre-fetchFetch

- 0 -

9-8

HTF1-HTF0 Host Transmit Data Transfer Format 00

011011

PCI UB32 bit mode24 bit mode3 LSBs2 Right, zero ext.3 LSBs2 Right, sign ext.3 MSbs2 Left, zero filled

- $0 -

12-11

HRF1-HRF0

Host Receive Data Transfer Format 00

011011

PCI UB32 bit mode24 bit mode3 Right, zero ext.2 LSBs3 Right, sign ext.2 LSBs3 Left, zero filled2 middle bytes

- $0 -

16-14

HS2-HS0 Host Semaphores - 0 -

19 TWSD Target Wait State Disable 01

HI32 target will insert up to 8 w.s.HI32 target will not insert wait states

- 0 -




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HSTR TRDY Transmitter Ready 10

transmit FIF O (6 deep) is emptytransmit FIFO is not empty

1 - 1

HTRQ Host Transmit Data Request 10

host transmit FIFO is not fullhost transmit FIFO is full

1 - 1

HRRQ Host Receive Data Request 01

host receive FIFO is emptyhost receive FIFO is not empty

0 - 0

HF5-HF3 Host Flags 0 - -

HINT Host Interrupt A 0

1

HINTA signal is high impedanceHINTA signal is driven low

0 - -

HREQ Host Request 01

HIRQ signal is deassertedHIRQ signal is asserted (if enabled)

- 0 -

HCVR 0 HC Host Command 01

no host command pendinghost command pending

cleared when the HC interrupt request is serviced

- - 0

7-1

HV6-HV0 Host Command Vector default vector via programmable (Section 6.10)

- default vector

-

15 HNMI Host Non Maskable Int. Req. 01

a maskable interrupt requesta non-maskable interrupt request

- 0 -

HRXM 31-0

Host Master Receive Data FIFO

empty

HRXS 31-0

Host Slave Receive Data FIFO

empty

HTXR 31-0

Host Transmit Data FIFO empty

CVIDCDID

15-0

VID15-VID0 Vendor ID $1057

hardwired $1057

- - -

31-16

DID15-DID0 Device ID via programmable (Section 6.10)

- - -




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CCMRCSTR

1 MSE Memory Space Enable 01

memory space response is disabledmemory space response is enabled

- 0 -

2 BM Bus Master Enable 01

HI32 PCI bus master disabled HI32 PCI bus master enabled

- 0 -

6 PERR Parity Error Response 01

HI32 does not drive HPERRHI32 drives HPERR if a parity error is detected

- 0 -

7 WCC Wait Cycle Control 0 HI32 never executes address stepping

hardwired 0 - - -

8 SERE System Error Enable 01

HI32 does not drive HSERRHI32 may drive HSERR

- 0 -

23 FBBC Fast Back-to-Back Capable 1 HI32 supports fast back-to-back transactions as a target

hardwired 1 - - -

24 DPR Data Parity Reported 01

no parity error detectedHI32 master parity error detected or HPERR asserted


- 0 -

26-25

DST1-DST0 DEVSEL Timing 01 medium DEVSEL timing hardwired 01 - - -

27 STA Signaled Target Abort 01

HI32 has not generated a target-abort event HI32 target, generated a target-abort event


- 0 -

28 RTA Received Target Abort 01

HI32 has not received a target-abort event HI32 master, received a target-abort event


- 0 -

29 RMA Received Master Abort 01

HI32 has not received a master-abort event HI32 master, terminates a transaction with master-abort


- 0 -

30 SSE Signaled System Error 01

HI32 not asserted HSERRHI32 asserted HSERR


- 0 -

31 DPE Detected Parity Error 01

no parity error detectedparity error detected


- 0 -

CRIDCCCR

7-0

RID7-RID0 Revision ID via programmable (Section 6.10)

- - -

15-8

PI7-PI0 PCI Device Program Interface

- - -

23-16

SC7-SC0 PCI Device Sub-Class - - -

31-24

BC7-BC0 PCI Device Base Class - - -




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CLATCHTY

15-8

LT7-LT0 Latency Timer - $00 -

23-16

HT7-HT0 Header Type $0 hardwired $0 - - -

CBMA 0 MSI Memory Space Indicator 0 HI32 is a memory mapped agent

hardwired 0 - - -

2-1

MS1-MS0 Memory Space $0 32 bits wide and mapping can be done anywhere

hardwired $0 - - -

3 PF Prefetch 0 HI32 data is not pre-fetchable (in the PCI sense)

hardwired 0 - - -

15-4

PM15-PM4 Memory Base Address Low $00 64Kbytes occupancy of PCI memory space

hardwired $00

- - -

31-16

PM31-PM16

Memory Base Address High - $0000 -

23-15

GB10-GB3 Genbus Base Address - $00 -

CILP 7-0

IP-7-IP0 Interrupt Signal PCI interrupt line routing information

15-8

IL7-IL0 Interrupt Line $01 INTA is supported hardwired $01

23-16

MG7-MG0 MAX_GNT $00 Min Grant hardwired $00

31-24

ML7-ML0 MAX_LAT $00 Max Latency hardwired $00

a. STRQ. MTRQ are zero in the personal software reset state.




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MOTOROLA DSP56305 User’s Manual Index-1

INDEX

A

addermodulo 1-9offset 1-9reverse-carry 1-9

Address Generation Unit 1-9Address Tracing Enable bit (ATE) 4-21addressing modes 1-10AGU 1-9ALC bit 7-18Alignment Control bit (ALC) 7-18Asynchronous/Synchronous bit (SYN) 7-24ATE 4-21ATE bit 4-21

B

barrel shifter 1-8bootstrap 4-5bootstrap from byte-wide external memory 4-7bootstrap program options

invoking 4-5bootstrap ROM 3-4bootstrap through SCI 4-8Boundary Scan Register (BSR) 11-7break 8-10Breakpoint 0 and 1 Event bits (BT0–BT1) 10-14Breakpoint 0 Condition Code Select bits

(CC00–CC01) 10-13Breakpoint 0 Read/Write Select bits

(RW00–RW01) 10-12Breakpoint 1 Condition Code Select bits

(CC10–CC11) 10-14Breakpoint 1 Read/Write Select bits

(RW10–RW11) 10-13BSR register 11-7BT0–BT1 bits 10-14bus

external address 2-9external data 2-9

busesinternal 1-13

BYPASS instruction 11-12

C

CC00–CC01 bits 10-13CC10–CC11 bits 10-14CD0–CD11 bits 8-18Central Processing Unit (CPU) 1-3

CKP bit 7-24CLAMP instruction 11-10CLKGEN 1-11Clock 2-8clock 1-7Clock Divider bits (CD0–CD11) 8-18Clock Generator (CLKGEN) 1-11Clock Out Divider bit (COD) 8-18Clock Polarity bit (CKP) 7-24Clock Source Direction bit (SCKD) 7-22CMOS 1-7COD bit 8-18code

compatible 1-7Core Status bits (OS0–OS1) 10-9CRA register 7-15

bits 0–7—Prescale Modulus Select bits (PM0–PM7) 7-15

bits 8–10—reserved bits 7-15bit 11—Prescaler Range bit (PSR) 7-15bit 17—reserved bit 7-18bit 18—Alignment Control bit (ALC) 7-18bits 19–21—Word Length Control bits

(WL0–WL1) 7-19bit 22—Select SC1 as Transmitter 0 Drive

Enable bit (SSC1) 7-19bit 23—reserved bit 7-19reserved bits—bit 17 7-18reserved bits—bit 23 7-19reserved bits—bits 8–10 7-15

CRB registerbits 0–1—Serial Output Flag bits

(OF0–OF1) 7-20bit 2—Serial Control 0 Direction bit

(SCD0) 7-21bit 3—Serial Control 1 Direction bit

(SCD1) 7-22bit 4—Serial Control 2 Direction bit

(SCD2) 7-22bit 5—Clock Source Direction bit (SCKD) 7-22bit 6—Shift Direction bit (SHFD) 7-22bits 7–8—Frame Sync Length bits

(FSL1–FSL0) 7-22bit 9—Frame Sync Relative Timing bit

(FSR) 7-23bit 10—Frame Sync Polarity bit (FSP) 7-23bit 11—Clock Polarity bit (CKP) 7-24bit 12—Asynchronous/Synchronous bit

(SYN) 7-24bit 13—ESSI Mode Select bit (MOD) 7-26bit 14—ESSI Transmit 2 Enable bit (TE2) 7-28

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D

Index-2 DSP56305 User’s Manual MOTOROLA

bit 15—ESSI Transmit 1 Enable bit (TE1) 7-29bit 16—ESSI Transmit 0 Enable bit (TE0) 7-30bit 17—ESSI Receive Enable bit (RE) 7-32bit 18—ESSI Transmit Interrupt Enable bit

(TIE) 7-33bit 19—ESSI Receive Interrupt Enable bit

(RIE) 7-33bit 20—ESSI Transmit Last Slot Interrupt

Enable bit (TLIE) 7-33bit 21—ESSI Receive Last Slot Interrupt Enable

bit (RLIE) 7-33bit 22—ESSI Transmit Exception Interrupt

Enable bit (TEIE) 7-34bit 23—ESSI Receive Exception Interrupt

Enable bit (REIE) 7-34

D

data ALU 1-8registers 1-8

Data Input bit (DI) 9-15Data Output bit (DO) 9-15DE signal 10-4Debug Event signal (DE signal) 10-4Debug mode

in OnCE module 10-16DEBUG_REQUEST instruction 11-11

executing during Stop state 10-17executing during Wait state 10-17executing in OnCE module 10-17

DI bit 9-15DIR bit 9-15Direct Memory Access (DMA) 1-15Direction bit (DIR) 9-15Divide Factor (DF) 1-11DMA 1-15

triggered by timer 9-29DO bit 9-15DO loop 1-10DRAM 1-13DSP56300 core 1-3, 1-6DSP56300 Family Manual 1-3, 1-7DSP56303 Technical Data 1-3

E

ENABLE_ONCE instruction 11-11Enhanced Synchronous Serial Interface 2-3, 2-29,

2-32Enhanced Synchronous Serial Interface (ESSI) 1-16

ESSI 2-3, 2-4, 2-29, 2-32after reset 7-42asynchronous operating mode 7-49frame sync length 7-50frame sync polarity 7-51frame sync selection 7-50frame sync word length 7-50GPIO functionality 7-52initialization 7-42interrupts 7-44Network mode 7-47Normal mode 7-47operating mode 7-42operating modes 7-47Port Control Register (PCR) 7-53Port Data Register (PDR) 7-55Port Direction Register (PRR) 7-54programming model 7-13synchronous operating mode 7-49

ESSI Control Register A (CRA) 7-15ESSI Mode Select bit (MOD) 7-26ESSI Receive Data Register (RX) 7-39ESSI Receive Enable bit (RE) 7-32ESSI Receive Exception Interrupt Enable bit

(REIE) 7-34ESSI Receive Interrupt Enable bit (RIE) 7-33ESSI Receive Last Slot Interrupt Enable bit

(RLIE) 7-33ESSI Receive Shift Register 7-39ESSI Receive Slot Mask Registers (RSMA,

RSMB) 7-41ESSI Status Register (SSISR) 7-34ESSI Time Slot Register (TSR) 7-40ESSI Transmit 0 Enable bit (TE0) 7-30ESSI Transmit 1 Enable bit (TE1) 7-29ESSI Transmit 2 Enable bit (TE2) 7-28ESSI Transmit Data registers (TX2, TX1, TX0) 7-40ESSI Transmit Exception Interrupt Enable bit

(TEIE) 7-34ESSI Transmit Interrupt Enable bit (TIE) 7-33ESSI Transmit Last Slot Interrupt Enable bit

(TLIE) 7-33ESSI Transmit Shift Registers 7-39ESSI Transmit Slot Mask Registers (TSMA,

TSMB) 7-40ESSI0 (GPIO) 5-3ESSI1 (GPIO) 5-4EX bit 10-6Exit Command bit (EX) 10-6

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F


expanded mode 4-6external address bus 2-9external bus control 2-9, 2-12, 2-13external data bus 2-9external memory expansion port 2-9EXTEST instruction 11-9

F

FE bit 8-16Frame Sync Length bits (FSL1–FSL0) 7-22Frame Sync Polarity bit (FSP) 7-23Frame Sync Relative Timing bit (FSR) 7-23frame sync selection

ESSI 7-50Framing Error Flag bit (FE) 8-16frequency

operation 1-7FSL1–FSL0 bits 7-22FSP bit 7-23FSR bit 7-23functional groups 2-4functional signal groups 2-3

G

Global Data Bus 1-13GO Command bit (GO) 10-6GPIO 1-15, 2-37

Timers 2-4GPIO (ESSI0, Port C) 5-3GPIO (ESSI1, Port D) 5-4GPIO (HI08, Port B) 5-3GPIO (SCI, Port E) 5-4GPIO (Timer) 5-4GPIO functionality

on ESSI 7-52Ground 2-7

PLL 2-7

H

hardware stack 1-10HI08 1-16, 2-3

(GPIO) 5-3HI32 2-4, 2-5, 2-18, 2-19HI-Z instruction 11-11Host Inteface 2-3Host Interface 1-16, 2-4, 2-18, 2-19

PCI 2-4PCI bus 2-5

universal bus 2-5host port

configuration 2-18usage considerations 2-18

I

IDCODE instruction 11-9IDLE bit 8-15Idle Line Flag bit (IDLE) 8-15Idle Line Interrupt Enable bit (ILIE) 8-12IF0 bit 7-34IF1 bit 7-35ILIE bit 8-12IME bit 10-8instruction cache 3-3

location 3-10instruction set 1-7internal buses 1-13interrupt 1-10

ESSI 7-44sources 4-10, 4-11

interrupt and mode control 2-15, 2-17interrupt control 2-15, 2-17Interrupt Mode Enable bit (IME) 10-8Interrupt Priority Register P (IPR—P) 4-16INV bit 9-13Inverter bit (INV) 9-13IPR—P 4-16

J

Joint Test Action Group (JTAG) 11-3JTAG 1-7, 1-11, 2-38JTAG instructions

BYPASS instruction 11-12CLAMP instruction 11-10DEBUG_REQUEST instruction 11-11ENABLE_ONCE instruction 11-11EXTEST instruction 11-9HI-Z instruction 11-11IDCODE instruction 11-9SAMPLE/PRELOAD instruction 11-9

JTAG/OnCE Interface signalsDebug Event signal (DE signal) 10-4

L

LA register 1-10LC register 1-10logic 1-7

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M


Loop Address register (LA) 1-10Loop Counter register (LC) 1-10

M

MAC 1-9Manual Conventions 1-5MBO bit 10-9MBS0–MBS1 bits 10-12memory

bootstrap ROM 3-4enabling breakpoints 10-18expansion 1-13external expansion port 1-13off-chip 1-13on-chip 1-12program RAM 3-4X data RAM 3-5Y data RAM 3-6

Memory Breakpoint Occurrence bit (MBO) 10-9Memory Breakpoint Select bits

(MBS0–MBS1) 10-12memory configuration 3-10

memory spaces 3-10RAM 3-10

MF bits 4-22MIPS 1-7MOD bit 7-26mode control 2-15, 2-17Mode Select bit (MOD) 7-26modulo adder 1-9Multiplication Factor bits (MF) 4-22multiplier-accumulator (MAC) 1-8, 1-9

O

OBCR register 10-12bits 0–1—Memory Breakpoint Select bits

(MBS0–MBS1) 10-12bits 2–3—Breakpoint 0 Read/Write Select bits

(RW00–RW01) 10-12bits 4–5—Breakpoint 0 Condition Code Select

bits (CC00–CC01) 10-13bits 6–7—Breakpoint 1 Read/Write Select bits

(RW10–RW11) 10-13bits 8–9—Breakpoint 1 Condition Code Select

bits (CC10–CC11) 10-14bits 10–11—Breakpoint 0 and 1 Event Select

bits (BT0–BT1) 10-14reserved bits—bits 12–15 10-15

OCR registerbits 0–4—Register Select bits (RS0–RS4) 10-6bit 5—Exit Command bit (EX) 10-6bit 6—GO Command bit (GO) 10-6bit 7—Read/Write Command bit (R/W) 10-6

ODEC 10-8OF0–OF1 bits 7-20offset adder 1-9OGDBR register 10-20OMAC0 comparator 10-11OMAC1 comparator 10-11OMAL register 10-11OMBC counter 10-14OMLR0 register 10-11OMLR1 register 10-11OMR

bit 15-Address Tracing Enable bit (ATE) 4-21OMR register 1-11OnCE 1-4, 1-7

commands 10-23controller 10-5trace logic 10-15

OnCE Breakpoint Control Register (OBCR) 10-12OnCE Command Register (OCR) 10-5OnCE Decoder (ODEC) 10-8OnCE GDB Register (OGDBR) 10-20OnCE Memory Address Comparator 0

(OMAC0) 10-11OnCE Memory Address Comparator 1

(OMAC1) 10-11OnCE Memory Address Latch register

(OMAL) 10-11OnCE Memory Breakpoint Counter (OMBC) 10-14OnCE Memory Limit Register 0 (OMLR0) 10-11OnCE Memory Limit Register 1 (OMLR1) 10-11OnCE module 1-12, 2-38, 10-3

checking for Debug mode 10-24displaying a specified register 10-26displaying X data memory 10-27interaction with JTAG port 10-29polling the JTAG Instruction Shift

register 10-24reading the Trace buffer 10-25returning to Normal mode 10-28saving pipeline information 10-25

OnCE PAB Register for Decode Register (OPABDR) 10-20

OnCE PAB Register for Execute (OPABEX) 10-21

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P


OnCE PAB Register for Fetch Register (OPABFR) 10-20

OnCE PIL Register (OPILR) 10-19OnCE Program Data Bus Register (OPDBR) 10-19OnCE Status and Control Register (OSCR) 10-8OnCE Trace Counter (OTC) 10-16OnCE/JTAG 2-4OnCE/JTAG port 2-3On-Chip Emulation (OnCE) module 1-12On-Chip Emulation module 10-3on-chip memory 1-12

program 3-4X data RAM 3-5Y data RAM 3-6

OPABDR register 10-20OPABEX register 10-21OPABFR register 10-20OPDBR register 10-19Operating 4-3operating mode 4-3

bootstrap from byte-wide external memory 4-7bootstrap through SCI 4-8ESSI 7-42, 7-47expanded 4-6expanded mode 4-7

Operating Mode Register (OMR) 1-11operating modes 4-3OPILR register 10-19OR bit 8-15OS0–OS1 bits 10-9OSCR register 10-8

bit 0—Trace Mode Enable bit (TME) 10-8bit 1—Interrupt Mode Enable bit (IME) 10-8bit 2—Software Debug Occurrence bit

(SWO) 10-9bit 3—Memory Breakpoint Occurrence bit

(MBO) 10-9bit 4—Trace Occurrence bit (TO) 10-9bit 5—reserved bit 10-9bits 6–7—Core Status bits (OS0–OS1) 10-9reserved bits—bits 8–23 10-10

OTC counter 10-16Overrun Error Flag bit (OR) 8-15

P

PAB 1-13PAG 1-10Parity Error bit (PE) 8-16Patch Mode

PEN bit 4-22

PC register 1-10PC0-PC20 bits 9-7PCE bit 9-16PCRC register 7-53PCRD register 7-53PCRE register 8-29PCTL register

bits 0–11—Multiplication Factor bits (MF0–MF11) 4-22

bit 16—XTAL Disable bit (XTLD) 4-23bits 20–23—PreDivider Factor bits

(PD0–PD3) 4-23PCU 1-10PD bits 4-23PDB 1-13PDC 1-10PDRC register 7-55PDRD register 7-55PDRE register 8-31PE bit 8-16Peripheral I/O Expansion Bus 1-13PIC 1-10pin configuration, SCKn 7-6pin configuration, SCn0 7-8pin configuration, SCn1 7-11pin configuration, SCn2 7-8, 7-12PL0-PL20 bits 9-6PL21-PL22 bits 9-6PLL 1-11, 2-8PM0–PM7 bits 7-15Port A 2-9Port B 5-3

GPIO 2-5Port C 2-4, 2-29, 5-3Port C Control Register (PCRC) 7-53Port C Data Register (PDRC) 7-55Port C Direction Register (PRRC) 7-54Port D 2-4, 2-32, 5-4Port D Control Register (PCRD) 7-53Port D Data Register (PDRD) 7-55Port D Direction Register (PRRD) 7-54Port E 2-35, 5-4Port E Control Register (PCRE) 8-29Port E Data Register (PDRE) 8-31Port E Direction Register (PRRE) 8-30Power 2-6power

low 1-7management 1-7standby modes 1-7

PreDivider Factor bits (PD) 4-23

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R


Prescale Modulus Select bits (PM0–PM7) 7-15Prescaler Clock Enable bit (PCE) 9-16Prescaler Counter 9-5Prescaler Counter Value bits (PC0-PC20) 9-7Prescaler Load Value bits (PL0-PL20) 9-6Prescaler Range bit (PSR) 7-15Prescaler Source bits (PL21-PL22) 9-6Program Address Bus (PAB) 1-13Program Address Generator (PAG) 1-10Program Control Unit (PCU) 1-10Program Counter register (PC) 1-10Program Data Bus (PDB) 1-13Program Decode Controller (PDC) 1-10Program Interrupt Controller (PIC) 1-10Program Memory Expansion Bus 1-13program RAM 3-4Programming Sheets — See Appendix BPRRC register 7-54PRRD register 7-54PRRE register 8-30PSR bit 7-15

R

R/W bit 10-6R8 bit 8-16RCM bit 8-19RDF bit 7-36RDRF bit 8-15RE bit 7-32, 8-11Read/Write Command bit (R/W) 10-6Receive Clock Mode Source bit (RCM) 8-19Receive Data Register (RX) 7-39Receive Data Register Full bit (RDF) 7-36Receive Data Register Full bit (RDRF) 8-15Receive Data signal (RXD) 8-4Receive Exception Interrupt Enable bit (REIE) 7-34Receive Frame Sync Flag bit (RFS) 7-35Receive Interrupt Enable bit (RIE) 7-33, 8-13Receive Last Slot Interrupt Enable bit (RLIE) 7-33Receive Shift Register 7-39Receive Slot Mask Registers (RSMA, RSMB) 7-41Received Bit 8 Address bit (R8) 8-16Receiver Enable bit (RE) 8-11Receiver Overrun Error Flag bit (ROE) 7-36Receiver Wakeup Enable bit (SBK) 8-11Register Select bits (RS0–RS4) 10-6REIE bit 7-34, 8-14reserved bits

in CRA register 7-15, 7-18, 7-19in OBCR register

bits 12–15 10-15in OSCR register

bit 5, bits 8–23 10-9in TCSR register

bits 3, 10, 14, 16–19, 22, 23 9-16in TPCR 9-7in TPLR 9-6

RESET 2-16reverse-carry adder 1-9RFS bit 7-35RIE bit 7-33, 8-13RLIE bit 7-33ROE bit 7-36ROM

bootstrap 3-4RS0–RS4 bits 10-6RSMA, RSMB registers 7-41RW00–RW01 bits 10-12RW10–RW11 bits 10-13RWU bit 8-11RX register 7-39RXD signal 8-4

S

SAMPLE/PRELOAD instruction 11-9SBK bit 8-10SC register 1-11SC0 signal 7-8, 7-12SC1 signal 7-10SCCR register 8-17

bits 0–11—Clock Divider bits (CD0–CD11) 8-18

bit 12—Clock Out Divider bit (COD) 8-18bit 13—SCI Clock Prescaler bit (SCP) 8-18bit 14—Receive Clock Mode Source bit

(RCM) 8-19bit 15—Transmit Clock Source bit (TCM) 8-20

SCD0 bit 7-21SCD1 bit 7-22SCD2 bit 7-22SCI 1-17, 2-4, 2-35

exceptions 8-29Idle Line 8-29Receive Data 8-29Receive Data with Exception Status 8-29Timer 8-29

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S


Transmit Data 8-29GPIO functionality 8-29initialization 8-27

example 8-27operating mode

Asynchronous 8-23Synchronous 8-23

operating modesAsynchronous 8-23

programming model 8-5reset 8-24

state after reset 8-25transmission priority

preamble, break, and data 8-28SCI (GPIO) 5-4SCI Clock Control Register (SCCR) 8-17SCI Clock Polarity bit (SCKP) 8-14SCI Clock Prescaler bit (SCP) 8-18SCI Control Register (SCR) 8-9SCI exceptions

Receive Data 8-29SCI pins

RXD, TXD, SCLK 8-3SCI Receive Register (SRX) 8-21SCI Receive with Exception Interrupt bit

(REIE) 8-14SCI Serial Clock signal (SCLK) 8-4SCI Shift Direction bit (SSFTD) 8-10SCI Status Register (SSR) 8-14SCI Transmit Register (STX)

STX register 8-21SCK signal 7-6SCKD bit 7-22SCKn pin configuration 7-6SCKP bit 8-14SCLK signal 8-4SCn0 pin configuration 7-8SCn1 pin configuration 7-11SCn2 pin configuration 7-8, 7-12SCP bit 8-18SCR register 8-9

bits 0-2—Word Select bits (WDS0-WDS2) 8-9bit 3—SCI Shift Direction bit (SSFTD) 8-10bit 4—Send Break bit (SBK) 8-10bit 5—Wakeup Mode Select bit (WAKE) 8-10bit 6—Receiver Wakeup Enable bit

(RWU) 8-11bit 7—Wired-OR Mode Select bit

(WOMS) 8-11bit 8—Receiver Enable bit (RE) 8-11bit 9—Transmitter Enable bit (TE) 8-12

bit 10—Idle Line Interrupt Enable bit (ILIE) 8-12

bit 11—Receive Interrupt Enable bit (RIE) 8-13bit 12—Transmit Interrupt Enable bit

(TIE) 8-13bit 13—Timer Interrupt Enable bit (TMIE) 8-13bit 14—Timer Interrupt Rate bit (STIR) 8-13bit 15—SCI Clock Polarity bit (SCKP) 8-14bit 16—SCI Receive with Exception Interrupt

Enable bit (REIE) 8-14Select SC1 as Transmitter 0 Drive Enable bit

(SSC1) 7-19Send Break bit (SBK) 8-10Serial Clock signal (SCK) 7-6Serial Communications Interface 2-35Serial Communications Interface (SCI) 1-17, 2-3,

8-3Serial Control 0 Direction bit (SCD0) 7-21serial control 0 signal (SC0) 7-8, 7-12Serial Control 1 Direction bit (SCD1) 7-22serial control 1 signal (SC1) 7-10Serial Control 2 Direction bit (SCD2) 7-22Serial Input Flag 0 bit (IF0) 7-34Serial Input Flag 1 bit (IF1) 7-35Serial Output Flag bits (OF0–OF1) 7-20serial protocol

in OnCE module 10-23Serial Receive Data signal (SRD) 7-5Serial Transmit Data signal (STD) 7-4SHFD bit 7-22Shift Direction bit (SHFD) 7-22signal groupings 2-3signals 2-3

functional grouping 2-4Sixteen-bit Compatibility 3-3Size register (SZ) 1-11Software Debug Occurrence bit (SWO) 10-9SP 1-11SR register 1-10SRAM

interfacing 1-13SRD signal 7-5SRX

read as SRXL, SRXM, SRXH 8-21SRX register 8-21SS 1-11SSC1 bit 7-19SSFTD bit 8-10SSISR register 7-34

bit 0—Serial Input Flag 0 bit (IF0) 7-34bit 1—Serial Input Flag 1 bit (IF1) 7-35

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bit 2—Transmit Frame Sync Flag bit (TFS) 7-35bit 3—Receive Frame Sync Flag bit (RFS) 7-35bit 4—Transmitter Underrun Error Flag bit

(TUE) 7-36bit 5—Receiver Overrun Error Flag bit

(ROE) 7-36bit 6—Transmit Data Register Empty bit

(TDE) 7-36bit 7—Receive Data Register Full bit

(RDF) 7-36SSR register 8-14

bit 1—Transmitter Empty bit (TRNE) 8-14bit 2—Receive Data Register Full bit

(RDRF) 8-15bit 2—Transmit Data Register Empty bit

(TDRE) 8-14bit 3—Idle Line Flag bit (IDLE) 8-15bit 4—Overrun Error Flag bit (OR) 8-15bit 5—Parity Error bit (PE) 8-16bit 6—Framing Error Flag bit (FE) 8-16bit 7—Received Bit 8 Address bit (R8) 8-16

Stack Counter register (SC) 1-11Stack Pointer (SP) 1-11standby

modeStop 1-7Wait 1-7

Status Register (SR) 1-10STD signal 7-4STIR bit 8-13stop

standby mode 1-7STX register

read as STXL, STXM. STXH, and STXA 8-21SWO bit 10-9SYN bit 7-24System Stack (SS) 1-11SZ register 1-11

T

TAP 1-11TAP controller 11-6TC0–TC3 bits 9-11TCF bit 9-16TCIE bit 9-11TCK pin 11-5TCM bit 8-20TCPR register 9-17

TCR register 9-17TCSR register 9-10

bit 0—Timer Enable bit (TE) 9-10bit 1—Timer Overflow Interrupt Enable bit

(TOIE) 9-11bit 2—Timer Compare Interrupt Enable bit

(TCIE) 9-11bits 4–7—Timer Control bits (TC0–TC3) 9-11bit 8—Inverter bit (INV) 9-13bit 9—Timer Reload Mode bit (TRM) 9-14bit 11—Direction bit (DIR) 9-15bit 12—Data Input bit (DI) 9-15bit 13—Data Output bit (DO) 9-15bit 15—Prescaler Clock Enable bit (PCE) 9-16bit 20—Timer Overflow Flag bit (TOF) 9-16bit 21—Timer Compare Flag bit (TCF) 9-16reserved bits—bits 3, 10, 14, 16–19, 22, 23 9-16

TDE bit 7-36TDI pin 11-5TDO pin 11-5TDRE bit 8-14TE bit 8-12, 9-10TE0 bit 7-30TE1 bit 7-29TE2 bit 7-28TEIE bit 7-34Test Access Port (TAP) 1-11, 11-3Test Clock Input pin (TCK) 11-5Test Data Input pin (TDI) 11-5Test Data Output pin (TDO) 11-5Test Mode Select Input pin (TMS) 11-5Test Reset Input pin (TRST) 11-5TFS bit 7-35TIE bit 7-33, 8-13Time Slot Register (TSR) 7-40timer 1-17

special cases 9-29Timer (GPIO) 5-4Timer Compare Flag bit (TCF) 9-16Timer Compare Interrupt Enable bit (TCIE) 9-11Timer Compare Register (TCPR) 9-17Timer Control bits (TC0–TC3) 9-11Timer Control/Status Register (TCSR) 9-10Timer Count Register (TCR) 9-17Timer Enable bit (TE) 9-10Timer Interrupt Enable bit (TMIE) 8-13Timer Interrupt Rate bit (STIR) 8-13Timer Load Register (TLR) 9-17timer mode

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mode 0—GPIO 9-19mode 1—timer pulse 9-20mode 2—timer toggle 9-21mode 3—timer event counter 9-22mode 4—measurement input width 9-23mode 5—measurement input period 9-24mode 6—measurement capture 9-25mode 7—pulse width modulation 9-26mode 8—reserved 9-27mode 9—watchdog pulse 9-27mode 10—measurement toggle 9-28modes 11–15—reserved 9-29

Timer modulearchitecture 9-3timer block diagram 9-3

Timer Overflow Flag bit (TOF) 9-16Timer Overflow Interrupt Enable bit (TOIE) 9-11Timer Prescaler Count Register (TPCR) 9-7Timer Prescaler Load Register (TPLR) 9-5Timer Reload Mode bit (TRM) 9-14Timer/Event Counter 1-17Timer/Event Counter module 1-17Timers 2-3, 2-4, 2-37TLIE bit 7-33TLR register 9-17TME bit 10-8TMIE bit 8-13TMS pin 11-5TO bit 10-9TOF bit 9-16TOIE bit 9-11TPCR register 9-7

bits 0-20—Prescaler Counter Value bits (PC0-PC20) 9-7

bit 21-23—reserved bits 9-7reserved bits—bits 21-23 9-7

TPLR register 9-5bits 0-20—Prescaler Load Value bits

(PL0-PL20) 9-6bits 21-22—Prescaler Source bits

(PL0-PL20) 9-6bit 23—reserved bit 9-6reserved bit—bit 23 9-6

Trace buffer 10-21Trace mode

enabling 10-18in OnCE module 10-15

Trace Mode Enable bit (TME) 10-8Trace Occurrence bit (TO) 10-9Transmit 0 Enable bit (TE0) 7-30Transmit 1 Enable bit (TE1) 7-29

Transmit 2 Enable bit (TE2) 7-28Transmit Clock Source bit (TCM) 8-20Transmit Data Register Empty bit (TDE) 7-36Transmit Data Register Empty bit (TDRE) 8-14Transmit Data signal (TXD) 8-4Transmit Exception Interrupt Enable bit

(TEIE) 7-34Transmit Frame Sync Flag bit (TFS) 7-35Transmit Interrupt Enable bit (TIE) 7-33, 8-13Transmit Last Slot Interrupt Enable bit (TLIE) 7-33Transmit Shift Registers 7-39Transmit Slot Mask Registers (TSMA, TSMB) 7-40Transmitter Empty bit (TRNE) 8-14Transmitter Enable bit (TE) 8-12Transmitter Underrun Error Flag bit (TUE) 7-36triple timer module 1-17TRM bit 9-14TRNE bit 8-14TRST pin 11-5TSMA, TSMB registers 7-40TSR register 7-40TUE bit 7-36TX2, TX1, TX0 registers 7-40TXD signal 8-4

V

VBA register 1-11Vector Base Address register (VBA) 1-11

W

waitstandby mode 1-7

WAKE bit 8-10Wakeup Mode Select bit (WAKE) 8-10WDS0-WDS2 bits 8-9Wired-OR Select bit (WOMS) 8-11WL0–WL1 bits 7-19WOMS bit 8-11Word Length Control bits (WL0–WL1) 7-19Word Select bits (WDS0-WDS2) 8-9

X

X data RAM 3-5X Memory Address Bus (XAB) 1-13X Memory Data Bus (XDB) 1-13X Memory Expansion Bus 1-13XAB 1-13XDB 1-13

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XTAL Disable bit (XTLD) 4-23XTLD bit 4-23

Y

Y data RAM 3-6Y Memory Address Bus (YAB) 1-13Y Memory Data Bus (YDB) 1-13Y Memory Expansion Bus 1-13YAB 1-13YDB 1-13

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abcelectroniquenotes-application.abcelectronique.com/314/314-67976.pdf · 2009. 2. 8. · this...

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