addizione tra numeri binari - uniroma2.it · type conversions • type conversion function:...
TRANSCRIPT
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si=a
i ⨁ b
i ⨁ c
in
Addizione tra numeri binari
FAa1 b1
cincout
s1
FAa0 b0
cincout
s0
FAan1 bn1
cincout
sn1
FAan2 bn2
cincout
sn2carryout
FAai bi
cincout
si
cout
=aib
i + a
ic
in + b
ic
in
A=an-1
an-2
...ai...a
0
B=bn-1
bn-2
...bi...b
0
S=sns
n-1s
n-2...s
i...s
0
sn
A,B ∈ [0,2n-1]S ∈ [0,2n+1-1]
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Numeri con il segno (complemento a 2)
A=an-1
an-2
...ai...a
0 con
a
i ∈ {0,1} rappresenta un numero tra 0 e 2n-1
def.: B=-A è un numero tale che A+B=0 (A - A = 0)
Al posto della definizione di sopra utilizziamo la seguente
def.: B=-A è un numero tale che A+B=2n
dove 2n in binario viene rappresentato da S=sns
n-1s
n-2...s
i...s
0 con s
n=1 , s
i=0 ∀ i ∈[0,n-1].
th.: B=-A, B=bn-1
bn-2
...bi...b
0 => B=( a
n-1a
n-2...a
i...a
0)
+1
Dim.: (an-1
an-2
...ai...a
0)+ (a
n-1a
n-2...a
i...a
0)= 11...1...1 (11...1...1=2n-1)
(an-1
an-2
...ai...a
0)+ (a
n-1a
n-2...a
i...a
0+1) = 2n
-ATrascurando l'ultimo bit del sommatore possiamo quindi utilizzare la stessa struttura vista prima per fare le addizioni tra numeri con il segno.
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Numeri con il segno (complemento a 2)
Quindi un vettore di n bits puo rappresentare:
un numero senza segno compreso tra 0 e 2n-1
un numero con il segno compreso tra -2n-1 e 2n-1-1
N.B.: tutti i numeri negativi hanno il bit più significativo ad 1, tutti quelli positivi hanno il bit più significativo a 0
N.M.B.: questo non vuol dire che cambiando l'ultimo bit passo da A a -A
Per la somma di due vettori di bit si usa il sommatore descritto in precedenza. E' l'”utilizzatore” del sommatore che sa se i vettori rappresentano numeri con il segno o senza.
BIT SIGNED UNSIGNED
A B S=A+B A B S=A+B A B S=A+B
1001 0100 1101 -7 4 -3 9 4 13
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Aritmetica in VHDL
package std_logic_1164 is
type std_logic_vector is array ( NATURAL range <>) of STD_LOGIC;
[...]Il package std_logic_1164 definisce il tipo di dato std_logic_vector
package std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
[...]
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: SIGNED) return SIGNED;
Il package std_logic_arith definisce due tipi corrispondenti ai numeri interi con il segno e senza il segno. Inoltre il VHDL contiene tra i tipi predefiniti il tipo INTEGER
Su questi quattro tipi di dato si possono effettuare le operazioni aritmetiche
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Operazioni Aritmetiche sintetizzabili in VHDL
Addizione, +
Sottrazione, -
Confronti, >, >=, <, <=
Moltiplicazione, *
Divisione per una potenza di 2(equivale a un right shift)
Shift per una costante, (SHL, SHR)
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Operazioni aritmetiche utilizzando std_logic_arith ...
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
[...]
Signal A, B: UNSIGNED(7 DOWNTO 0) ;
Signal S: UNSIGNED(7 DOWNTO 0) ;
[...]
S <= A+B;
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
[...]
Signal A, B: SIGNED(7 DOWNTO 0) ;
Signal S: SIGNED(7 DOWNTO 0) ;
[...]
S <= A+B;
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... utilizzando std_logic_unsigned e std_logic_signed ...
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
[...]
Signal A, B: STD_LOGIC_VECTOR (7 DOWNTO 0) ;
Signal S: STD_LOGIC_VECTOR (7 DOWNTO 0) ;
[...]
S <= A+B;
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
[...]
Signal A, B: STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Signal S: STD_LOGIC_VECTOR(7 DOWNTO 0) ;
[...]
S <= A+B;
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... e utilizzando gli integer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
[...]
Signal A, B,C: INTEGER;
Signal S: UNSIGNED (7 downto 0);
[...]
C<=A+B;
S <= CONV_UNSIGNED(C,8);
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
[...]
Signal A, B,C: INTEGER;
Signal S: SIGNED (7 downto 0);
[...]
C<=A+B;
S <= CONV_SIGNED(C,8);
library ieee;use ieee.std_logic_arith.all;use ieee.std_logc_1164.all;entity signed_resize_larger is
port(a : in signed(7 downto 0); z : out signed(15 downto 0) );
end;
architecture behavior of signed_resize_larger is begin
z <= conv_signed(a, 16);end;
msb lsb
library ieee;use ieee.std_logic_arith.all;use ieee.std_logc_1164.all;entity signed_resize_larger is
port(a : in signed(7 downto 0); z : out signed(15 downto 0) );
end;
architecture behavior of signed_resize_larger is begin
z <= conv_signed(a, z’length);end;
msb lsb
library ieee;use ieee.std_logic_arith.all;use ieee.std_logc_1164.all;entity unsigned_resize_larger is
port(a : in unsigned(7 downto 0); z : out unsigned(15 downto 0) );
end;
architecture behavior of unsigned_resize_larger is begin
z <= conv_unsigned(a, 16);end; msb lsb0 0 0 00 0 0 0
library ieee;use ieee.std_logic_arith.all;use ieee.std_logc_1164.all;entity signed_resize_smaller is
port(a : in signed(15 downto 0); z : out signed(7 downto 0) );
end;
architecture behavior of signed_resize_smaller is begin
z <= conv_signed(a, 8);end; lsbmsb
Library iee;use ieee.std_logic_arith.all;use ieee.std_logc_1164.all;entity unsigned_resize_smaller is
port(a : in unsigned(15 downto 0); z : out unsigned(7 downto 0) );
end;
architecture behavior of unsigned_resize_smaller is begin
z <= conv_unsigned(a, 8);end; lsbmsb
Library iee;use ieee.std_logic_arith.all;use ieee.std_logc_1164.all;entity unsigned_slice is
port(a : in unsigned(15 downto 0); z : out unsigned(7 downto 0) );
end;
architecture behavior of unsigned_slice is begin
z <= a(7 downto 0);end; lsbmsb
Type Conversions
• Type conversion function: conv_type type:integer, signed, unsigned, std_logic_vector aSig:integer, signed, unsigned, std_logic_vector
conv_integer(aSig): convert aSig to integerconv_integer(aInt, n): convert aInt to nbit integer conv_unsigned(aSig,n): convert aSig to nbit unsignedconv_signed(aSig,n): convert aSig to nbit signedconv_std_logic_vector(aSig,n):convert aSig to nbit
std_logic_vector
Type Conversions
library iee;use ieee.std_logic_arith.all;use ieee.std_logc_1164.all;entity conversion_demo is
port(value : in natural range 0 to 255; result : out unsigned(7 downto 0) );
end;
architecture behavior of conversion_demo is begin
result <= conv_signed(value,result’length);end;
Type Conversions
• std_logic_vector ==> signed or unsignedlibrary iee;use ieee.std_logic_arith.all;use ieee.std_logc_1164.all;entity conversion_demo is
port(value : in std_logic_vector(7 downto 0); result : out unsigned(7 downto 0) );
end;
architecture behavior of conversion_demo is begin
result <= unsigned(value);end;
std_logic_arith
u, v, w: unsigned( n DOWTO 0);s, r, t: signed( n DOWTO 0);i, j, k: integer;
u <= v + w;s <= r + t;s <= u + r;s <= r + u;u <= v + j;u <= j + v;s <= r + j;[...]
library IEEE;use IEEE.std_logic_1164.ALL;
PACKAGE std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; type SIGNED is array (NATURAL range <>) of STD_LOGIC; subtype SMALL_INT is INTEGER range 0 to 1;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; function "+"(L: SIGNED; R: SIGNED) return SIGNED; function "+"(L: UNSIGNED; R: SIGNED) return SIGNED; function "+"(L: SIGNED; R: UNSIGNED) return SIGNED; function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED; function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED; function "+"(L: SIGNED; R: INTEGER) return SIGNED; function "+"(L: INTEGER; R: SIGNED) return SIGNED; function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED; function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED; function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED; function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED;