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•VLSI Design I; A. Milenkovic •1
Aleksandar Milenkovic ( www.ece.uah.edu/~milenka )www.ece.uah.edu/~milenka/cpe527-05F
CPE/EE 427, CPE 527 VLSI Design I
L01: Introduction, Design Metrics
8/31/2005 VLSI Design I; A. Milenkovic 2
What is this course all about?
• Introduction to digital integrated circuits.– CMOS devices and manufacturing technology. CMOS
inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Design methodologies.
• What will you learn?– Understanding, designing, and optimizing digital circuits
with respect to different quality metrics: cost, speed, power dissipation, and reliability
•VLSI Design I; A. Milenkovic •2
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Digital Integrated Circuits
• Introduction: Issues in digital design• The CMOS inverter• Combinational logic structures• Sequential logic gates• Design methodologies• Interconnect: R, L and C• Timing• Arithmetic building blocks• Memories and array structures
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Why does it matter?
•VLSI Design I; A. Milenkovic •3
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A Brief History
• 1947: First Transistor at Bell Lab [John Bardeen and Walter Brattain]
• 1958: First Integrated circuit at Texas Instruments[Jack Kilby]
• 1965: Moore’s Law, Intel[Gordon Moore]
• 1994: Integrated circuits became $100B/year business
• 2003: Industry manufactured 1018
(one quintillion) transistors (200M per human being)
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The First Computer
The BabbageDifference Engine(1832)25,000 partscost: £17,470
•VLSI Design I; A. Milenkovic •4
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ENIAC - The first electronic computer (1946)
• Vacuum tube based digital computer
• “The Giant Brain” as labeled by the press
• ENIAC facts– Occupied 1,800 sq. feet
– Weighted 30 tons
– 18000 vacuum tubes
• Application: calculate firing tables for World War II artillery guns
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The Transistor Revolution
First transistorBell Labs, 1948
•VLSI Design I; A. Milenkovic •5
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The First Integrated Circuits
Bipolar logic1960’s
ECL 3-input GateMotorola 1966
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IC Evolution
• SSI – Small Scale Integration (early 1970s)– contained 1 – 10 logic gates
• MSI – Medium Scale Integration – logic functions, counters
• LSI – Large Scale Integration– first microprocessors on the chip
• VLSI – Very Large Scale Integration– now offers 64-bit microprocessors,
complete with cache memory (L1 and often L2), floating-point arithmetic unit(s), etc.
•VLSI Design I; A. Milenkovic •6
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IC Evolution
• Bipolar technology– TTL (transistor-transistor logic), 1962; higher integration density– ECL (emitter-coupled logic), 1974; high-performance
• MOS (Metal-oxide-silicon)– although invented before bipolar transistor (1925, 1935),
was initially difficult to manufacture– nMOS (n-channel MOS) technology developed in late 1970s
required fewer masking steps, was denser, and consumed less power than equivalent bipolar ICs => an MOS IC was cheaper than a bipolar IC and led to investment and growth of the MOS IC market.
– aluminum gates for replaced by polysilicon by early 1980– CMOS (Complementary MOS): n-channel and p-channel MOS
transistors => lower power consumption, simplified fabrication process
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Intel 4004• Introduction date:
November 15, 1971• Clock speed: 108 KHz • Number of transistors: 2,300
(10 microns)• Bus width: 4 bits• Addressable memory: 640 bytes• Typical use:
calculator, first microcomputer chip, arithmetic manipulation
•VLSI Design I; A. Milenkovic •7
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Pentium 4• 0.18-micron process technology
(2, 1.9, 1.8, 1.7, 1.6, 1.5, and 1.4 GHz)
– Introduction date: August 27, 2001 (2, 1.9 GHz); ...; November 20, 2000 (1.5, 1.4 GHz)
– Level Two cache: 256 KB Advanced Transfer Cache (Integrated)
– System Bus Speed: 400 MHz– SSE2 SIMD Extensions– Transistors: 42 Million – Typical Use: Desktops and entry-
level workstations• 0.13-micron process technology
(2.53, 2.2, 2 GHz)– Introduction date: January 7, 2002– Level Two cache: 512 KB Advanced– Transistors: 55 Million
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Intel’s McKinley• Introduction date: Mid 2002• Caches: 32KB L1,
256 KB L2, 3MB L3 (on-chip)• Clock: 1GHz• Transistors: 221 Million • Area: 464mm2
• Typical Use: High-end servers
• Future versions:5GHz, 0.13-micron technology
•VLSI Design I; A. Milenkovic •8
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Moore’s Law
• In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
• He made a prediction that semiconductor technology will double its effectiveness every 18 months
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Moore’s Law
16151413121110
9876543210
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG
2 OF
THE
NU
MB
ER O
FC
OM
PON
ENTS
PER
INTE
GR
ATE
D F
UN
CTI
ON
Electronics, April 19, 1965.
•VLSI Design I; A. Milenkovic •9
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Evolution in Complexity
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Transistor Counts
1,000,000
100,000
10,000
1,000
10
100
11975 1980 1985 1990 1995 2000 2005 2010
808680286
i386i486
Pentium®Pentium® Pro
K 1 Billion 1 Billion TransistorsTransistors
Source: IntelSource: Intel
ProjectedProjected
Pentium® IIPentium® III
Courtesy, Intel
•VLSI Design I; A. Milenkovic •10
8/31/2005 VLSI Design I; A. Milenkovic 19
Moore’s law in Microprocessors
40048008
80808085 8086
286386
486Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010Year
Tran
sist
ors
(MT)
2X growth in 1.96 years!
Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 yearsCourtesy, Intel
8/31/2005 VLSI Design I; A. Milenkovic 20
Die Size Growth
40048008
80808085
8086286
386486 Pentium ® procP6
1
10
100
1970 1980 1990 2000 2010Year
Die
siz
e (m
m)
~7% growth per year~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s LawCourtesy, Intel
•VLSI Design I; A. Milenkovic •11
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Frequency
P6Pentium ® proc
48638628680868085
8080800840040.1
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Freq
uenc
y (M
hz)
Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years
Doubles every2 years
Courtesy, Intel
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Power Dissipation
P6Pentium ® proc
486386
2868086
808580808008
4004
0.1
1
10
100
1971 1974 1978 1985 1992 2000Year
Pow
er (W
atts
)
Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase
Courtesy, Intel
•VLSI Design I; A. Milenkovic •12
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Power will be a major problem
5KW 18KW
1.5KW 500W
400480088080
80858086
286386
486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008Year
Pow
er (W
atts
)
Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive
Courtesy, Intel
8/31/2005 VLSI Design I; A. Milenkovic 24
Power density
400480088080
8085
8086
286 386486
Pentium® procP6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Pow
er D
ensi
ty (W
/cm
2)
Hot Plate
NuclearReactor
RocketNozzle
Power density too high to keep junctions at low tempPower density too high to keep junctions at low tempCourtesy, Intel
•VLSI Design I; A. Milenkovic •13
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Technology Directions: SIA Roadmap
Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 100 70 50 35 Logic trans/cm2 6.2M 18M 39M 84M 180M 390M Cost/trans (mc) 1.735 .580 .255 .110 .049 .022 #pads/chip 1867 2553 3492 4776 6532 8935 Clock (MHz) 1250 2100 3500 6000 10000 16900 Chip size (mm2) 340 430 520 620 750 900 Wiring levels 6-7 7 7-8 8-9 9 10 Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5 High-perf pow (W) 90 130 160 170 175 183
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Not Only Microprocessors
Digital Cellular Market(Phones Shipped)
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M Analog Baseband
Digital Baseband(DSP + MCU)
PowerManagement
Small Signal RF
PowerRF
(data from Texas Instruments)(data from Texas Instruments)
CellPhone
•VLSI Design I; A. Milenkovic •14
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Why Scaling?
• Technology shrinks by 0.7/generation• With every generation can integrate 2x more
functions per chip; chip cost does not increase significantly
• Cost of a function decreases by 2x• But …
– How to design chips with more and more functions?– Design engineering population does not double every
two years…• Hence, a need for more efficient design methods
– Exploit different levels of abstraction
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Design Abstraction Levels
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
•VLSI Design I; A. Milenkovic •15
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Major Design Challenges• Microscopic issues
– ultra-high speeds– power dissipation and
supply rail drop– growing importance of
interconnect– noise, crosstalk– reliability,
manufacturability– clock distribution
• Macroscopic issues– time-to-market– design complexity
(millions of gates)– high levels of
abstractions– design for test– reuse and IP, portability– systems on a chip (SoC)– tool interoperability
$360 M800800 MHz130 M Tr.0.132002
$160 M360600 MHz32 M Tr.0.181999
$120 M270500 MHz20 M Tr.0.251998
$90 M210400 MHz13 M Tr.0.351997
Staff Costs3 Yr. Design Staff Size
FrequencyComplexityTech.Year
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Productivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000Logic Tr./ChipTr./Staff Month.
xxxx
xx
x21%/Yr. compound
Productivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Logi
c Tr
ansi
stor
per
Chi
p(M
)
0.01
0.1
1
10
100
1,000
10,000
100,000
Prod
uctiv
ity(K
) Tra
ns./S
taff
-Mo.
Source: Sematech
Complexity outpaces design productivity
Com
plex
ity
Courtesy, ITRS Roadmap
•VLSI Design I; A. Milenkovic •16
8/31/2005 VLSI Design I; A. Milenkovic 31
Fundamental Design Metrics• Functionality• Cost
– NRE (fixed) costs - design effort– RE (variable) costs - cost of parts, assembly, test
• Reliability, robustness– Noise margins– Noise immunity
• Performance– Speed (delay)– Power consumption; energy
• Time-to-market
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Cost of Integrated Circuits• NRE (non-recurring engineering) costs
– Fixed cost to produce the design• design effort• design verification effort• mask generation
– Influenced by the design complexity and designer productivity– More pronounced for small volume products
• Recurring costs – proportional to product volume– silicon processing
• also proportional to chip area– assembly (packaging)– test
VolumecostFixedICpercostVariableICperCost +=
•VLSI Design I; A. Milenkovic •17
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NRE Cost is Increasing
8/31/2005 VLSI Design I; A. Milenkovic 34
Cost per Transistor
0.00000010.0000001
0.0000010.000001
0.000010.00001
0.00010.0001
0.0010.001
0.010.01
0.10.111
19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012
cost: cost: ¢¢--perper--transistortransistor
Fabrication capital cost per transistor (Moore’s law)
•VLSI Design I; A. Milenkovic •18
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Silicon Wafer
Single die
Wafer
From http://www.amd.com
Going up to 12” (30cm)
8/31/2005 VLSI Design I; A. Milenkovic 36
Recurring Costs
yieldtestFinalcostPackagingcostTestingcostDiecostVariable ++
=
yieldDiewaferperDieswaferofCostdieofCost×
=
•VLSI Design I; A. Milenkovic •19
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Dies per Wafer
areaDie2diameterWaferπ
areaDie)diameter/2(WaferπwaferperDies
2
×
×−
×=
8/31/2005 VLSI Design I; A. Milenkovic 38
Yield
α
αareaDieareaunitperDefects1yieldWaferyieldDie
−
⎟⎠⎞
⎜⎝⎛ ×+×=
α is approximately 3
4area) (die cost die f=
•VLSI Design I; A. Milenkovic •20
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Examples of Cost Metrics (1994)
$4179%402961.5$15000.803Pentium
$27213%482561.6$17000.703Super SPARC
$14919%532341.2$15000.703DEC Alpha
$7327%661961.0$13000.803HP PA 7100
$5328%1151211.3$17000.804PowerPC 601
$1254%181811.0$12000.803486DX2$471%360431.0$9000.902386DX
Die cost
YieldDies/wafer
Area (mm2)
Defects/cm2
Wafer cost
Line width
Metal layers
Chip
8/31/2005 VLSI Design I; A. Milenkovic 40
Yield Example
• Example #1: – 20-cm wafer for a die that is 1.5 cm on a side.– Solution: Die area = 1.5x1.5 = 2.25cm2.
Dies per wafer = 3.14x(20/2)2/2.25 – 3.14x20/(2x2.5)0.5=110.
• Example #2– wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2,
α = 3 (measure of manufacturing process complexity)– 252 dies/wafer (remember, wafers round & dies square)– die yield of 16%– 252 x 16% = only 40 dies/wafer die yield !
• Die cost is strong function of die area– proportional to the third or fourth power of the die area
•VLSI Design I; A. Milenkovic •21
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Functionality and Robustness
• Prime requirement –IC performs the function it is designed for
• Normal behavior deviates due to – variations in the manufacturing process (dimensions and
device parameters vary between runs and even on a single wafer or die)
– presence of disturbing on- or off-chip noise sources• Noise: Unwanted variation of voltages or currents
at the logic nodes
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Reliability Noise in Digital Integrated Circuits
i(t)
Inductive coupling Capacitive coupling Power and groundnoise
v(t) VDD
• from two wires placed side by side– inductive coupling
• current change on one wire caninfluence signal on the neighboring wire
– capacitive coupling• voltage change on one wire can
influence signal on the neighboring wire• cross talk
• from noise on the power and ground supply rails– can influence signal levels
in the gate
•VLSI Design I; A. Milenkovic •22
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Example of Capacitive Coupling
• Signal wire glitches as large as 80% of the supply voltage will be common due to crosstalk between neighboring wires as feature sizes continue to scale Crosstalk vs. Technology
0.16m CMOS0.12m CMOS
0.35m CMOS
0.25m CMOS
Pulsed Signal
Black line quietRed lines pulsedGlitches strength vs technology
From Dunlop, Lucent, 2000
8/31/2005 VLSI Design I; A. Milenkovic 44
Static Gate Behavior• Steady-state parameters of a gate – static behavior –
tell how robust a circuit is with respect to both variations in the manufacturing process and to noise disturbances.
• Digital circuits perform operations on Boolean variables x ∈{0,1}
• A logical variable is associated with a nominal voltage level for each logic state
1 ⇔ VOH and 0 ⇔ VOL
• Difference between VOH and VOL is the logic or signal swing Vsw
V(y)V(x)VOH = ! (VOL)
VOL = ! (VOH)
•VLSI Design I; A. Milenkovic •23
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DC OperationVoltage Transfer Characteristic
VOH = f(VOL)VOL = f(VOH)VM = f(VM)
V(x)
V(y)
f
V(y)V(x)
VOH = f (VIL)
VIL VIH
V(y)=V(x)
Switching ThresholdVM
VOL = f (VIH)
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Mapping between analog and digital signals• The regions of acceptable high and low voltages are delimited by
VIH and VIL that represent the points on the VTC curve where thegain = -1 (dVout/dVin)
V IL V IH V in
Slope = -1
Slope = -1
V OL
V OH
Vout
“ 0” VOL
VIL
VIH
VOH
UndefinedRegion
“ 1”
•VLSI Design I; A. Milenkovic •24
8/31/2005 VLSI Design I; A. Milenkovic 47
Definition of Noise Margins
Gate Output Gate Input
Large noise margins are desirable, but not sufficient …
For robust circuits, want the “0” and “1” intervals to be as large as possible
Gnd
UndefinedRegion
"1"
"0"
VOH
VIL
VOL
VIHNoise Margin High
Noise Margin Low
NMH = VOH - VIH
NML = VIL - VOL
VDD VDD
GndGnd
8/31/2005 VLSI Design I; A. Milenkovic 48
The Regenerative Property• A gate with regenerative property ensure that a disturbed
signal converges back to a nominal voltage level
v0 v1 v2 v3 v4 v5 v6
-1
1
3
5
0 2 4 6 8 10
t (nsec)
V (v
olts
) v0
v2
v1
•VLSI Design I; A. Milenkovic •25
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Conditions for Regeneration
v1 = f(v0) ⇒ v1 = finv(v2)
v0 v1 v2 v3 v4 v5 v6
v0
v1
v2
v3 f(v)
finv(v)
Regenerative Gate
v0
v1
v2
v3
f(v)
finv(v)
Nonregenerative Gate
To be regenerative, the VTC must have a transient region with a gain greater than 1 (in absolute value) bordered by two valid zones where the gain is smaller than 1. Such a gate has two stable operating points.
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Noise Immunity
• Noise immunity expresses the ability of the system to process and transmit information correctly in the presence of noise
• For good noise immunity, the signal swing (i.e., the difference between VOH and VOL) and the noise margin have to be large enough to overpower the impact of fixed sources of noise
• Noise margin expresses the ability of a circuit to overpower a noise source– noise sources: supply noise, cross talk, interference, offset
• Absolute noise margin values are deceptive– a floating node is more easily disturbed than a node driven by a
low impedance (in terms of voltage)
•VLSI Design I; A. Milenkovic •26
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Directivity
• A gate must be undirectional: changes in an output level should not appear at any unchanging input of the same circuit– In real circuits full directivity is an illusion (e.g., due to capacitive
coupling between inputs and outputs)
• Key metrics: output impedance of the driver andinput impedance of the receiver– ideally, the output impedance of the driver should be zero– input impedance of the receiver should be infinity
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Fan-In and Fan-Out
Fan-out – number of load gates connected to the output of the driving gate
gates with large fan-out are slowerN
M
Fan-in – the number of inputs to the gate
gates with large fan-in are bigger and slower
•VLSI Design I; A. Milenkovic •27
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The Ideal Inverter• The ideal gate should have
– infinite gain in the transition region– a gate threshold located in the middle of the logic swing– high and low noise margins equal to half the swing– input and output impedances of infinity and zero, resp.
g = - ∞
Vout
Vin
Ri = ∞
Ro = 0
Fanout = ∞
NMH = NML = VDD/2
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An Old-time Inverter
NM H
V in (V)
V
o u t
( V )
NM L
V M
0.0
1.0
2.0
3.0
4.0
5.0
1.0 2.0 3.0 4.0 5.0
•VLSI Design I; A. Milenkovic •28
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Delay Definitions
t
Vout
Vin
inputwaveform
outputwaveform
t
Vin Vout
Propagation delay?
signal slopes?
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Delay Definitions
t
Vout
Vin
inputwaveform
outputwaveform
tp = (tpHL + tpLH)/2Propagation delay
t
50%
tpHL
50%
tpLH
tf
90%
10%tr
signal slopes
Vin Vout
•VLSI Design I; A. Milenkovic •29
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Modeling Propagation Delay
• Model circuit as first-order RC network
R
C
vin
vout
vout (t) = (1 – e–t/τ)V
where τ = RC
Time to reach 50% point ist = ln(2) τ = 0.69 τ
Time to reach 90% point ist = ln(9) τ = 2.2 τ
• Matches the delay of an inverter gate
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Power and Energy Dissipation• Power consumption: how much energy is consumed
per operation and how much heat the circuit dissipates– supply line sizing (determined by peak power)
Ppeak = Vddipeak– battery lifetime (determined by average power dissipation)
p(t) = v(t)i(t) = Vddi(t) Pavg= 1/T ∫ p(t) dt = Vdd/T ∫ idd(t) dt– packaging and cooling requirements
• Two important components: static and dynamic
E (joules) = CL Vdd2 P0→1 + tsc Vdd Ipeak P0→1 + Vdd Ileakage
P (watts) = CL Vdd2 f0→1 + tscVdd Ipeak f0→1 + Vdd Ileakage
f0→1 = P0→1 * fclock
•VLSI Design I; A. Milenkovic •30
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Power and Energy Dissipation• Propagation delay and the power consumption of a gate
are related • Propagation delay is (mostly) determined by the speed
at which a given amount of energy can be stored on the gate capacitors– the faster the energy transfer (higher power dissipation) the
faster the gate
• For a given technology and gate topology, the product of the power consumption and the propagation delay is a constant– Power-delay product (PDP) –
energy consumed by the gate per switching event• An ideal gate is one that is fast and consumes little energy, so the
ultimate quality metric is– Energy-delay product (EDP) = power-delay 2
8/31/2005 VLSI Design I; A. Milenkovic 60
• Digital integrated circuits have come a long way and still have quite some potential left for the coming decades
• Some interesting challenges ahead– Getting a clear perspective on the challenges and
potential solutions is the purpose of this course• Understanding the design metrics that govern
digital design is crucial– Cost, reliability, speed, power and energy
dissipation
Summary
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