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•VLSI Design I; A. Milenkovic •1
CPE/EE 427, CPE 527 VLSI Design I
CMOS Inverter
Department of Electrical and Computer Engineering University of Alabama in Huntsville
Aleksandar Milenkovic
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CMOS Inverter: A First Look
VDD
Vout
CL
Vin
•VLSI Design I; A. Milenkovic •2
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CMOS Inverter: Steady State Response
VDD
Rn
Vout = 0
Vin = V DD
VDD
Rp
Vout = 1
Vin = 0
VOL = 0VOH = VDD
VM = f(Rn, Rp)
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CMOS Properties• Full rail-to-rail swing ⇒ high noise margins
– Logic levels not dependent upon the relative device sizes ⇒transistors can be minimum size ⇒ ratioless
• Always a path to Vdd or GND in steady state ⇒ low output impedance (output resistance in kΩ range) ⇒large fan-out (albeit with degraded performance)
• Extremely high input resistance (gate of MOS transistor is near perfect insulator) ⇒ nearly zero steady-state input current
• No direct path steady-state between power and ground ⇒ no static power dissipation
• Propagation delay function of load capacitance and resistance of transistors
•VLSI Design I; A. Milenkovic •3
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Short Channel I-V Plot (NMOS)
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
I D( A
)
VDS (V)
X 10-4
VGS = 1.0V
VGS = 1.5V
VGS = 2.0V
VGS = 2.5V
Line
ar d
epen
denc
e
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
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Short Channel I-V Plot (PMOS)
-1
-0.8
-0.6
-0.4
-0.2
00-1-2
I D( A
)
VDS (V)
X 10-4
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
• All polarities of all voltages and currents are reversed
•VLSI Design I; A. Milenkovic •4
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nMOS Operation
Vgsn >
Vdsn >
Vgsn >
Vdsn <
Vgsn <SaturatedLinearCutoff
Idsn
Idsp Vout
VDD
Vin
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nMOS Operation
Vgsn > Vtn
Vdsn > Vgsn – Vtn
Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vgsn < Vtn
SaturatedLinearCutoff
Idsn
Idsp Vout
VDD
Vin
•VLSI Design I; A. Milenkovic •5
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nMOS Operation
Vgsn > Vtn
Vdsn > Vgsn – Vtn
Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vgsn < Vtn
SaturatedLinearCutoff
Idsn
Idsp Vout
VDD
Vin
Vgsn = Vin
Vdsn = Vout
9/11/2006 VLSI Design I; A. Milenkovic 10
nMOS Operation
Vgsn > Vtn
Vin > Vtn
Vdsn > Vgsn – Vtn
Vout > Vin - Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn < Vgsn – Vtn
Vout < Vin - Vtn
Vgsn < Vtn
Vin < Vtn
SaturatedLinearCutoff
Idsn
Idsp Vout
VDD
Vin
Vgsn = Vin
Vdsn = Vout
•VLSI Design I; A. Milenkovic •6
9/11/2006 VLSI Design I; A. Milenkovic 11
pMOS Operation
Vgsp <
Vdsp <
Vgsp <
Vdsp >
Vgsp >SaturatedLinearCutoff
Idsn
Idsp Vout
VDD
Vin
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pMOS Operation
Vgsp < Vtp
Vdsp < Vgsp – Vtp
Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vgsp > Vtp
SaturatedLinearCutoff
Idsn
Idsp Vout
VDD
Vin
•VLSI Design I; A. Milenkovic •7
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pMOS Operation
Vgsp < Vtp
Vdsp < Vgsp – Vtp
Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vgsp > Vtp
SaturatedLinearCutoff
Idsn
Idsp Vout
VDD
Vin
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0
9/11/2006 VLSI Design I; A. Milenkovic 14
pMOS Operation
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp < Vgsp – Vtp
Vout < Vin - Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp – Vtp
Vout > Vin - Vtp
Vgsp > Vtp
Vin > VDD + Vtp
SaturatedLinearCutoff
Idsn
Idsp Vout
VDD
Vin
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0
•VLSI Design I; A. Milenkovic •8
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I-V Characteristics
• Make pMOS is wider than nMOS such that βn = βp
Vgsn5
Vgsn4
Vgsn3
Vgsn2Vgsn1
Vgsp5
Vgsp4
Vgsp3
Vgsp2
Vgsp1
VDD
-VDD
Vdsn
-Vdsp
-Idsp
Idsn
0
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Current vs. Vout, Vin
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
•VLSI Design I; A. Milenkovic •9
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Load Line Analysis
Vin0
Vin0
Idsn, |Idsp|
VoutVDD
• Vin = 0
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Load Line Analysis
Vin1
Vin1Idsn, |Idsp|
VoutVDD
• Vin = 0.2VDD
•VLSI Design I; A. Milenkovic •10
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Load Line Analysis
Vin2
Vin2
Idsn, |Idsp|
VoutVDD
• Vin = 0.4VDD
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Load Line Analysis
Vin3
Vin3
Idsn, |Idsp|
VoutVDD
• Vin = 0.6VDD
•VLSI Design I; A. Milenkovic •11
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Load Line Analysis
Vin4
Vin4
Idsn, |Idsp|
VoutVDD
• Vin = 0.8VDD
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Load Line Analysis
Vin5Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
• Vin = VDD
•VLSI Design I; A. Milenkovic •12
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Load Line Summary
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
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DC Transfer Curve
• Transcribe points onto Vin vs. Vout plot
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
VoutVDD
CVout
0
Vin
VDD
VDD
A B
DE
Vtn VDD/2 VDD+Vtp
•VLSI Design I; A. Milenkovic •13
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CMOS Inverter Load Lines
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
I Dn
( A)
Vout (V)
X 10-4
Vin = 1.0V
Vin = 1.5V
Vin = 2.0V
Vin = 2.5V
0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V
Vin = 0V
Vin = 0.5V
Vin = 1.0V
Vin = 1.5VVin = 0.5VVin = 2.0V
Vin = 2.5V
Vin = 2VVin = 1.5V Vin = 1V
Vin = 0.5V
Vin = 0V
PMOS NMOS
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CMOS Inverter VTC
00.5
11.5
22.5
0 0.5 1 1.5 2 2.5Vin (V)
V out
(V)
•VLSI Design I; A. Milenkovic •14
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Operating Regions
• Revisit transistor operating regions
CVout
0
Vin
VDD
VDD
A B
DE
Vtn VDD/2 VDD+VtpEDCBA
pMOSnMOSRegion
9/11/2006 VLSI Design I; A. Milenkovic 28
CMOS Inverter VTC
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
Vin (V)
Vou
t(V
)
NMOS offPMOS res
NMOS satPMOS res
NMOS satPMOS sat
NMOS resPMOS sat NMOS res
PMOS off0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
Vin (V)
Vou
t(V
)
NMOS offPMOS res
NMOS satPMOS res
NMOS satPMOS sat
NMOS resPMOS sat NMOS res
PMOS off
•VLSI Design I; A. Milenkovic •15
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Beta Ratio
• If βp / βn ≠ 1, switching point will move from VDD/2• Called skewed gate• Other gates: collapse into equivalent inverter
Vout
0
Vin
VDD
VDD
0.51
2
10p
n
ββ
=
0.1p
n
ββ
=
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Noise Margins
• How much noise can a gate input see before it does not recognize the input?
IndeterminateRegion
NML
NMH
Input CharacteristicsOutput Characteristics
VOH
VDD
VOL
GND
VIH
VIL
Logical HighInput Range
Logical LowInput Range
Logical HighOutput Range
Logical LowOutput Range
•VLSI Design I; A. Milenkovic •16
9/11/2006 VLSI Design I; A. Milenkovic 31
Logic Levels
• To maximize noise margins, select logic levels at
VDD
Vin
Vout
VDD
βp/βn > 1
Vin Vout
0
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Logic Levels
• To maximize noise margins, select logic levels at – unity gain point of DC transfer characteristic
VDD
Vin
Vout
VOH
VDD
VOL
VIL VIHVtn
Unity Gain PointsSlope = -1
VDD-|Vtp|
βp/βn > 1
Vin Vout
0
•VLSI Design I; A. Milenkovic •17
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CMOS Inverter: Switch Model of Dynamic Behavior
VDD
Rn
Vout
CL
Vin = V DD
VDD
Rp
Vout
CL
Vin = 0
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CMOS Inverter: Switch Model of Dynamic Behavior
VDD
Rn
Vout
CL
Vin = V DD
VDD
Rp
Vout
CL
Vin = 0
Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn)
•VLSI Design I; A. Milenkovic •18
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Relative Transistor Sizing
• When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to– maximize the noise margins and– obtain symmetrical characteristics
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Switching Threshold• VM where Vin = Vout (both PMOS and NMOS in
saturation since VDS = VGS)VM ≈ rVDD/(1 + r) where r = kpVDSATp/knVDSATn
• Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors
• Want VM = VDD/2 (to have comparable high and low noise margins), so want r ≈ 1
(W/L)p kn’VDSATn(VM-VTn-VDSATn/2)(W/L)n kp’VDSATp(VDD-VM+VTp+VDSATp/2)
=
•VLSI Design I; A. Milenkovic •19
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Switch Threshold Example
• In our generic 0.25 micron CMOS process, using the process parameters from slide L03.25, a VDD = 2.5V, and a minimum size NMOS device ((W/L)n of 1.5)
-0.1-30 x 10-6-1-0.4-0.4PMOS0.06115 x 10-60.630.40.43NMOSλ(V-1)k’(A/V2)VDSAT(V)γ(V0.5)VT0(V)
(W/L)p
(W/L)n
=
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Switch Threshold Example
• In our generic 0.25 micron CMOS process, using the process parameters, a VDD = 2.5V, and a minimum size NMOS device ((W/L)n of 1.5)
-0.1-30 x 10-6-1-0.4-0.4PMOS0.06115 x 10-60.630.40.43NMOSλ(V-1)k’(A/V2)VDSAT(V)γ(V0.5)VT0(V)
(W/L)p 115 x 10-6 0.63 (1.25 – 0.43 – 0.63/2)
(W/L)n -30 x 10-6 -1.0 (1.25 – 0.4 – 1.0/2)= x x = 3.5
(W/L)p = 3.5 x 1.5 = 5.25 for a VM of 1.25V
•VLSI Design I; A. Milenkovic •20
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Simulated Inverter VM
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
0 1 10(W/L)p/(W/L)n
VM
(V)
VM is relatively insensitive to variations in device ratio
setting the ratio to 3, 2.5 and 2 gives VM’s of 1.22V, 1.18V, and 1.13V
Increasing the width of the PMOS moves VMtowards VDD
Increasing the width of the NMOS moves VMtoward GND
.1
Note: x-axis is semilog
~3.4
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Noise Margins Determining VIH and VIL
0
1
2
3
VIL VIHVin
V out
VOH = VDD
VM
By definition, VIH and VIL are where dVout/dVin = -1 (= gain)
VOL = GND
A piece-wise linear approximation of VTC
NMH = VDD - VIHNML = VIL - GND
Approximating: VIH = VM - VM /gVIL = VM + (VDD - VM )/g
So high gain in the transition region is very desirable
•VLSI Design I; A. Milenkovic •21
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CMOS Inverter VTC from Simulation
00.5
11.5
22.5
0 0.5 1 1.5 2 2.5Vin (V)
Vou
t(V
)0.25um, (W/L)p/(W/L)n = 3.4(W/L)n = 1.5 (min size)VDD = 2.5V
VM ≈ 1.25V, g = -27.5
VIL = 1.2V, VIH = 1.3VNML = NMH = 1.2(actual values are VIL = 1.03V, VIH = 1.45VNML = 1.03V & NMH = 1.05V)
Output resistance low-output = 2.4kΩhigh-output = 3.3kΩ
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Gain Determinates
-18-16-14-12-10-8-6-4-20
0 0.5 1 1.5 2Vin
gain
Gain is a strong function of the slopes of the currents in the saturation region, for Vin = VM
(1+r)g ≈ ----------------------------------
(VM-VTn-VDSATn/2)(λn - λp )
Determined by technology parameters, especially channel length modulation (λ). Only designer influence through supply voltage and VM (transistor sizing).
•VLSI Design I; A. Milenkovic •22
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Impact of Process Variation on VTC Curve
00.5
11.5
22.5
0 0.5 1 1.5 2 2.5Vin (V)
Vou
t(V
)
Nominal
Good PMOSBad NMOS
Bad PMOSGood NMOS
process variations (mostly) cause a shift in the switching threshold
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Scaling the Supply Voltage
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5Vin (V)
Vou
t(V
)
Device threshold voltages are kept (virtually) constant
0
0.05
0.1
0.15
0.2
0 0.05 0.1 0.15 0.2
Vin (V)
Vou
t(V
)
Gain=-1
Device threshold voltages are kept (virtually) constant