lecture 4 - cpe 690 introduction to vlsi design

8/13/2019 Lecture 4 - CpE 690 Introduction to VLSI Design

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CpE 690: Digital System DesignFall 2013

Lecture 4

VHDL part III

1

Bryan Ackland

Department of Electrical and Computer Engineering

Stevens Institute of Technology

Hoboken, NJ 07030


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2

VHDL Synthesis


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What is Synthesis?

Process of creating a RTL or gate level net-list from a

VHDL model Net-list can be used to create a physical (hardware)

implementation

3

VHDL

simulation

synthesis

PLD FPGACMOS

ASIC


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Synthesis Process

4

VHDL

Model

Synthesis

RTL/gate

Net-list

Technology

Mapping

Technology

Specific

Net-list

Logic

Optimizer

Optimized

Net-list

Place &

Route

Physical

Implementation(ASIC, FPGA etc.)

Area &

Timing

ConstraintsTarget

Tech.


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Limitations of Synthesis

VHDL can model a hardware system at different levelsof abstraction from gate level up algorithmic level

Synthesis tools cannot, in general, map arbitrary highlevel behavioral models into hardware.

Many VHDL constructs have no hardware equivalent:wait for 10 ns;

signala1: real;

y


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Inferring Signals

In VHDL, signals are used to represent timed

information flow between subsystems. When synthesizing from VHDL, the basic hardware

implementations of signals are:

Wires

Latches (level sensitive)

Flip-flops (edge triggered)

Signals generated by combinational circuits (whereoutput depends only on the current value of the inputs)can be implemented as wires

Signals generated by sequential circuits (where outputdepends on current and previous value of inputs) areimplemented as latches or flip-flops

6


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Flip-flop vs. Latch

7

D

Clk

Q

Flip-flop

stores data when

clock rises

Clk

D

Q

Latch

passes data when G is high

stores data when G is low

D

G

Q

Gate

D

Q


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Inference from Declarations

When a signal is declared, there needs to be sufficient

information to determine the correct number of bitssignalresult: std_logic_vector (12 downto0);signalcount: integer;signalindex: integer range 0 to18:= 0;

type state_type is (state0, state1, state2, state3);

signalnext state: state_type;

How many bits are required to represent count ?

Compilers are conservative: they will only perform transformationsthat are guaranteed not to produce incorrect answers

Initializations are usually ignored Need to include run-time initialization in hardware (e.g. reset)

How many bits are required to represent next_state?

8


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Inference from Simple CSAs

target_signal


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Example of operator grouping

entityabc isport(s,t,u,w: in std_logic;

v:out std_logic);end entity concurrent;

architecturedataflow of abcissignals1, s2: std_logic;beginL1: s1


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Inference from Conditional Signal Assignment

11

architecture cond_saof muxisbegin

z


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What happens if there are combinations of inputs thatdo not result in an assignment?

A latch is inferred to cover the case sel=0

This is now a sequential circuit is that what we intended?

We may not care what the result is when sel=0

Result is unnecessary, hazardous hardware

If we really wanted sequential operation, better to use flip-flop

If combinational circuit is intention, make sure output isalways assigned a value by using a final elseclause

Incomplete Assignment Implies Latch

12

architecture cond_saof muxisbegin

z


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This is great for priority encoder, but what aboutmultiplexer where all conditions are mutually exclusive?

Only red gates are needed to implement multiplexer

Bluegates are inferred to maintain priority coding

Not needed because the clauses are mutually exclusive

Conditional Maintains Priority Order

13

architecturebehaveof mux4isbegin

z


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SSA is better construct for building a muliplexer

No longer implied priority order Clauses are required to be mutually exclusive

No redundant gates

Selected Signal Assignment

14

architecture SSAof mux4isbegin

with selselectz


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Simple variable assignment statements generatecombinational logic

Sensitivity list is often ignored by synthesis compiler

Inferring Logic from Processes and Variables

15

entity syn_y isport ( x,y,z: in std_logic;

res: out std_logic);

end entity syn_v;

architecturebehavof syn_v isbegin

pr1: process (x,y)variable v1,v2: std_logic;begin

v1 := x andy;v2 := v1 xorz;res


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architecturebehavof syn_if isbegin

pr1: process (x,y,z,sel)variable v1: std_logic;begin

if sel=1 thenv1 := x xory;w


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Can ensure that a signal is always assigned in an if-then-else clause by including a final else clause that assigns adefault value to all output signals of the statement

Another alternative is to set a signal to a default valuebefore the if-then-else statement:

Avoiding latches by initialization

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architecturebehavof syn_if isbegin

pr1: process (x,y,z,sel)variable v1: std_logic;begin

w


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Case statement is ideally suited for implementingmultiplexers

all clauses must be mutually exclusive

no implied priority between clauses (unlike if-then-else)

no redundant logic

Need to obey same rules to avoid latches(a) One branch of the case statement must always be true AND

(b) All output signals are assigned values in each branch

Case Statement

18


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4 input multiplexer

architecturebehavof syn_mux isbegin

pr1: process (in0,in1,in2,in3,sel)begin

casesel iswhen00 => z z z z


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Sequential Circuits

Any moderately complex digital system requires the useof sequential circuits, e.g. to

identify and modify current state of system

store and hold data

identify sequences of inputs

generate sequences of outputs

If and case statements and conditional signalassignments can be used to infer latches

Latches are not preferred means of generating sequentialcircuits.

A latch is transparent when LE is high can lead to unintendedasynchronous sequential behavior when a result is fed back to aninput

Latches are prone to generate race conditions

Circuits with latches are difficult to verify timing

Circuits with latches are difficult to test 20


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Synchronous (Single Clock) Digital Design

Preferred design style is combinational circuit modulesconnected via positive (negative) edge-triggered flip-flopsthat all use a common clock.

21

comb.

block

A

comb.

block

B

comb.block

c

D Q

D Q D Q

D

D Q

D Q

clk

primary

input

primary

output


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Finite State Machine

Single clock synchronous system can be modeled as asingle combinational block and a multi-bit register

combinational

block

n-bit

clk

registern

n

k-bit

I/O

22


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Advantages of single clock synchronous

Edge triggered D flip-flops are never transparent

no unintended asynchronous sequential circuits Timing can be analyzed by:

determining all combinational delays

just add them up

checking flip-flop setup and hold times No race conditions

only time signal values matter is on clock edge

Easy to test

Most real systems cannot be designed using a singleclock

different timing constraints on various I/O interfaces

clock delays across chip

goal is to make the single clock modules as large as possible23


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D Flip-flop

Edge triggered D flip-flops are preferred sequentialcomponent

Within a process, positive edge triggered operation isinferred using:

if rising_edge (clk) then

if clkevent and clk=1 then

For example:

architecture RTLof FFSisbegin

p0: process (clk)beginif rising_edge (clk) then

z


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Inferring D Flip-flop with Asynchronous Reset

Asynchronous reset takes precedence over clock

Flip-flop can also include asynchronous set

architecture RTLof ARFFisbegin

p0: process (resn, clk)beginif resn=0 then

z


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Inferring D Flip-flop with Synchronous Reset

Synchronous reset waits for clock

Flip-flop can also include synchronous set


p0: process (clk)beginif rising_edge (clk) then

if resn=0 thenz


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Example: 4-bit synchronous counter

library IEEE;use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity count4 isport( clk, reset:in std_logic;

count: out std_logic_vector (3 downto0));end entity count4;

architecture RTLof count4isbegin

p0: process (clk, reset)variable vcount: std_logic_vector (3 downto0);begin

if rising_edge (clk) thenif reset=1 then

vcount := 0000;else

vcount := vcount+1;end if;

end if;count


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Example: 4-bit synchronous counter

D Q

D Q

D Q

D Q

reset

clk

count(3)

count(2)

count(1)

count(0)

0001

4-bit

adder

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Wait Statement

Only one wait statement permitted per process

Must be the first statement in the process

Must be of the wait until form

cannot use wait for or wait on constructs

Both of these will trigger execution on rising clock edge:

wait until clkevent and clk=1;

wait until rising_edge(clk); -- only with std_logic type

A D flip-flop will be inferred for all signals assigned in theprocess

all signals are synchronously assigned in process

29


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Wait Statement - Example


p0: processbegin

wait until clock;if resn=0 then

z


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Loop Statements

For loop is most commonly supported by synthesis

compilers Iteration range should be known at compile time

While statements are usually not supported becauseiteration range depends on a variable that may be datadependent.

Compiler will unroll the loop, e.g.:

fork in 1to 3loopshift_reg(n)


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Functions

Since:

functions are executed in zero time and

functions do not remember local variable values between calls

Functions will typically infer combinational logic

Function call is essentially replaced by in-line code

functionparity(data: std_logic_vector)return std_logicis

variablepar: std_logic:= 0;begin

fori in datarangelooppar := par xor data(i);

end loop;return (par);

end functionparity;

signal a: std_logic_vector (3 downto0);begin

z


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Procedures

Like functions, proceduresdo not remember localvariable values between calls

Procedures, however, do not necessarily execute in zerotime

And procedures may assign new events to signals inparameter list

Like function, think of procedure calls as substituting theprocedure as inline code in the calling process orarchitecture

Can include a waitstatement, but then cannot be calledfrom a process

Generally avoid wait statements in a procedure

Synchronous behavior can be inferred using if-then-else

If procedure is called from a process with wait statement,flip-flops will be inferred for all signals assigned in

procedure 33


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Tri-state Gates

A tri-state gate is inferred if the output value isconditionally set to high impedanceZ

en

din dout

din en dout

0 1 0

1 1 1

X 0 Z

34


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0

1

3

2

Examples of Tri-state Gates

architecture RTL of STATE3 is

begin

seq0 : process (DIN, EN)begin

if (EN = '1') then

DOUT(0)


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36

Finite State Machines

St t f T i l Di it l S t


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Structure of Typical Digital System

Provides necessary resources

& interconnect to performspecified task e.g.:

Adders, Multipliers, Shifters,

Registers, Memories, etc.

37

Execution

Unit

(Datapath)

Data Inputs

Data Outputs

Control

Unit

(Control)

Control Inputs

Control Outputs

ControlSignals

Controls data movement and

operation of execution unit.Usually follows some program

or sequence.

Often implemented as one or

more Finite State Machine(s)

Fi it St t M hi


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Finite State Machine

Single clock synchronous system can be modeled as asingle combinational block and a multi-bit register

Values stored in registers are stateof the system

Number of states is finite (2n)

Statemay change as a function of inputs

Outputs are function of state and inputs

combinational

block

n-bit

clk

registern

n

k-bit

I/O

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G l A hit t f FSM


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General Architecture of FSM

Next state (nx_state) is a function of present state(pr_state) and inputs

Output is a function of pr_state. May also be a function ofinputs

Reset allows system to be set to a known state

CombinationalLogic

Sequential

Logic

input output

nx_statepr_state

clockreset

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M l M hi


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Mealy Machine

Output is a function of pr_state andinputs Fast response (input -> output) no FFs in way

Leads to a fewer number of states

Propagates asynchronous behavior (e.g. glitches) from

input to output

Sequential

Logic

input output

nx_statepr_state

clockreset

Next State

Function

Output

Function

40

M M hi


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Moore Machine

Output is a function of pr_state only Slower response: (input -> output) requires clock

transition

Usually requires more states

Operation is fully synchronous

Sequential

Logic

input

output

nx_statepr_state

clockreset

Next State

Function

Output

Function

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E l T l M lti l


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Example: Toggle Multiplexer

Design a synchronous multiplexer that selects between

two 1-bit inputs a and b. The multiplexer switches fromone input to the other whenever a third input s is set to 1

This is a Mealy machine42

a

b

s

clk rst

z

StateA

StateB

s=0,

z=bs=0,

z=a

s=1, z=b

s=1, z=a

E l A M M hi


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Example: As a Moore Machine

This is a Moore machine

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State

A1

z=1

State

A0

z=0

s=0,

a=0

s=0,a=1

s=0,

a=0

s=0,

a=1

State

B1

z=1

State

B0

z=0

s=0,b=1

s=0,

b=0

s=0,

b=0

s=0,

b=1

s=1, b=0

s=1, a=0

s=1, a=1

s=1, b=1

Toggle M ltiple er as Meal Machine


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Toggle Multiplexer as Mealy Machine

General approach is to model FSM as two communicatingconcurrent processes

Combinational process

Edge triggered clock process

44

library ieee;use ieee.std_logic_1164.all;

entity tmpx isport(a,b,s,clk,rst: instd_logic;

z: outstd_logic);end entity tmpx;

architecturemealy oftmpx istypestateis (stateA, stateB);signalpr_state, nx_state : state;begin

Clock Process


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Clock Process

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p_clk: process (rst, clk)begin

if(rst = 1) then

pr_state


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Combinational Process uses Case Statement

Make sure all signals are assigned in all branches of

case statement to avoid inferring latches46

p_comb: process(a, b, s, pr_state)begin

casepr_state iswhenstateA =>

z


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Moore Machine Implementation

architecturemoore oftmpx istypestateis (A0, A1, B0, B1);

signalpr_state, nx_state: state;

begin

p0: process (rst, clk)if(rst = 1) then

pr_state := A0;

elsif (clkevent andclk = 1) thenpr_state


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Moore Machine Implementation (2)

p_comb: process(a, b, s, pr_state)begin

casepr_state iswhenA0 =>

z


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Moore Machine Implementation (3)

whenB0 =>z


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Example: Sequence Detection

Build a Mealy FSM that has looks for sequence 101 in

a serial input stream. When it detects the sequence, it

outputs a 1 and holds that value until the machine isreset.

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SD101reset

din

10100110

z

clk

A B C D

0/0

reset 1/0

1/0

0/0 1/1

0/1

1/10/0

Sequence Detection: Clock Process


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Sequence Detection: Clock Process

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SD101reset

dinz

clk

library ieee;use ieee.std_logic_1164.all;

entity SD101 isport(din, reset,clk: instd_logic;

z: outstd_logic);end entity SD101;

architecturemealy ofSD101 istypestateis (stateA, stateB, stateC, stateD);signalpr_state, nx_state : state;begin

p_clk: process (rst, clk)begin

if (reset = 1) thenpr_state


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Sequence Detection: Combinational Process

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p_comb: process(din, pr_state)

begin

casepr_state iswhenstateA =>

z


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Example: Read-Write Controller

Specifications: RWCNTL starts at state IDLE, waiting for input

signal STARTto go to 1 and then changes to either state

READINGor state WRITINGdepending on the value of RWinput.States READINGand WRITINGpersist until input signal LAST

goes to 1 which changes state to WAITING. After one clock cycle,

state WAITINGalways goes to state IDLE.

The FSM has three outputs RDSIG, WRSIG, and DONE. They are

1 when they are in state READING, WRITING, and WAITING,respectively, otherwise they are 0.

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RWCNTL

START

RW

DONE LAST

RDSIG

WRSIG

CLK

RWCNTL: Clock Process


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RWCNTL: Clock Process

54

RWCNTL

START

RW

DONE LAST

READING

WRITING

CLK

entityRWCNTL is

port(

CLK :in std_logic;START: in std_logic;

RW : in std_logic;

LAST : in std_logic;

RDSIG : out std_logic;

WRSIG: outstd_logic;DONE : out std_logic);

end entity RWCNTL;

architectureRTL ofRWCNTL is

typeSTATE is(IDLE, READING,

WRITING, WAITING);

signalPR_STATE, NX_STATE: STATE;

begin

seq : process

beginwait until CLK'event andCLOCK = '1';

PR_STATE


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RWCNTL: Combinational Process

55

comb : process(PR_STATE, START, RW, LAST)

begin

DONE


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RWCNTL: Combinational Process (2)

56

when WRITING=>WRSIG


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Simulation Waveforms

57

Synthesized RWCNTL


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Synthesized RWCNTL

58

RWCNTL: Add Asynchronous Reset


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RWCNTL: Add Asynchronous Reset

59

seq : processbegin

if(RESETn = '0') then

PR_STATE


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Synthesized RWCNTL with Asynch. Reset

60


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61

Test Bench Design

Testing Digital Circuits


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Testing Digital Circuits

In our class examples, circuits were limited to a

few input & outputs Easy to set up test bench with processes to explicitlydrive the inputs

Look at output waveforms to check correct operation

62

A

BY

But how do we

test this one?

Processor for

SONY PlayStation 3

Test Vectors


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Test Vectors

For large complex designs, designers will set up a suite

of test vectors

One or more files that contain a sequence of inputs and expected

outputs

Input vectors are typically applied to circuit under test at

some regular clock rate. Outputs are read at same rate

and compared to expected outputs

It can take many millions of vectors to adequately test a

complex chip e.g., a microprocessor 63

inputs expected outputs0010011100000110 11XX010110

1101001101100101 11X01110100100011010011010 1101101110

1110011111010100 0110001110

Design Verification vs. Product Testing


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Design Verification vs. Product Testing

During the design process, we develop functional test

vectors

Apply vectors similar to what might be expected in normal operation

of chip

Look for correct functionality across broad range of expected inputs

Purpose of these functional vectors is to debug the design

Each time design is refined, we reapply the functional vectors tocheck that no mistake has been made in moving from behavioral

modeling to implementation

Once design has been synthesized into gates, and

checked once more using the functional vectors, we

develop a new set of manufacturing test vectors Now checking for manufacturing defects

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Testing for Manufacturing Defects


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Testing for Manufacturing Defects

Popular approach is to assume that all manufacturing

faults can be modeled as a single node being stuck-at

either a 0 or a 1

Ideally, develop a set of test vectors that would show an

error if any node is stuck-at 0 or 1

Not practical as it would take too many vectors to exhaustively test

for all stuck at faults tradeoff between test time and cost ofsending bad chips into the field

Ratio of tested faults to all possible faults is known as fault

coverage 90% is considered good for a large, complex chip

Production chip tester:

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Developing a Test Bench


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p g

Develop a set of test benches using simple example:

full adder

Move towards fully automated model:

66

Device Under Test: Full-Adder


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67

AB

cin

cout

sum


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TB1: Visually Check Simulation Result


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y

69

Assert Statement (revisited)


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( )

The boolean-expressionis evaluated and if theexpression is false, the string-expressionspecified in

report statement is displayed in the simulator window

The severity statement then indicates to the simulator

what action should be taken in response to theassertion failure.

Severity: NOTE, WARNING, ERROR, FAILURE.

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assertboolean-expression

[reportstring-expression]

[severityexpression];

TB2: Using Assert Statement


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g

71

TB2: Using Assert no errors


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g

72

TB2: Using Assert Introduce error


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g

73

Use orinstead of xor

TB3: Using Test Vector Array


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g y

74

TB3: Using Test Vector Array no errors


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75

Reading and Writ ing Files TEXTIO Package


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A fileis a class of object in VHDL (like signal, variable

& constant). Each file has a type. The standard VHDL library contains the TEXTIO

package which provides a set of file types, data

types and I/O procedures for simple text I/O to and

from files To make the package visible:

use std.textio.all;

TEXTIO read and write procedures are available forpredefined types bit, bit_vector, character andstring

The ieee.std_logic_textiopackage overloads these

procedures to support std_logicand std_logic_vector76

Declaring and Opening Files


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New Types:

text -- a file of character stringsline a string (to or from a text file)

Example Declarations

filetestfile: text; -- testfile is file handle

variableL: line; -- L is a single line buffer

Procedure to open a file:

file_open(file_handle,filename, open_kind);

where open_kindis one of (read_mode, write_modeor

append_mode), for example:

file_open (testfile, my_file.txt, read_mode);

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Reading Files


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readline (file_handle, line_buffer);

Read one line from "text" file file_handle into line_buffer

read(line_buffer, value);

Read one item from line_bufferinto variable value.

Variable valuecan be bit, bit_vector, character or string

Variable can also be std_logic or std_logic vector if IEEE

std_logic_textiopackage is used.

endfile(file_handle); --returns boolean (TRUE if at EOF)

For example:variablebuf_in: line;

variablebit0: std_logic;

begin

readline(my_file, buf_in);

read(buf_in, bit0);78

Writing Files


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writeline (file_handle, line_buffer);

Write one line to "text" file file_handle from line_buffer

write(line_buffer, value);

Write variable value into line_buffer

Variable valuecan be bit, bit_vector, character or string

Variable can also be std_logic or std_logic vector if IEEE

std_logic_textiopackage is used.

For example:variablebuf_out: line;

variableabc : bit_vector (3 downto 0);

begin

write(buf_out, abc is);

write(buf_out, abc);

writeline(my_file, buf_in); 79

TB4: Reading Vectors from File


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80

TB5: Writing Results to File


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TB5: Writing Results to File (2)


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TB5: Writing Results to File (2)


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TB5: Writing Results with OR/XOR error


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lecture 4 - cpe 690 introduction to vlsi design

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